WO2021207916A1 - 存储单元结构及存储器阵列结构、电压偏置方法 - Google Patents
存储单元结构及存储器阵列结构、电压偏置方法 Download PDFInfo
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- WO2021207916A1 WO2021207916A1 PCT/CN2020/084621 CN2020084621W WO2021207916A1 WO 2021207916 A1 WO2021207916 A1 WO 2021207916A1 CN 2020084621 W CN2020084621 W CN 2020084621W WO 2021207916 A1 WO2021207916 A1 WO 2021207916A1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0023—Address circuits or decoders
- G11C13/0026—Bit-line or column circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0023—Address circuits or decoders
- G11C13/0028—Word-line or row circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/003—Cell access
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/79—Array wherein the access device being a transistor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/82—Array having, for accessing a cell, a word line, a bit line and a plate or source line receiving different potentials
Definitions
- the present disclosure relates to the field of memory technology, and in particular to a memory cell structure, a memory array structure, and a voltage bias method.
- One aspect of the present disclosure provides a memory cell structure, which includes: a substrate layer, a well layer and a transistor, the substrate layer is used to provide support for the memory cell structure; the well layer is embedded in the substrate layer, and the upper surface of the well layer is connected to The upper surface of the substrate layer is flat, and the transistors are arranged inside and on the surface of the well layer.
- the well layer includes: a first well layer and a second well layer, the first well layer is embedded in the substrate layer, and the upper surface of the first well layer is level with the upper surface of the substrate layer; second The well layer is arranged between the first well layer and the substrate layer, and the upper surface of the second well layer is flat with the upper surface of the substrate layer for separating the first well layer and the substrate layer; wherein, the transistor is arranged on the first well layer. Internal and surface.
- the substrate layer is a non-P-type or N-type doped structure layer
- the first well layer is a P-type doped structure layer for forming a P-type well layer
- the second well layer is an N-type
- the doped structure layer is used to form an N-type well layer as an isolation between the substrate layer and the P-type well layer.
- the transistor includes a gate, a source, and a drain, the gate is disposed on the upper surface of the first well layer; the source is embedded in the first well layer, and the upper surface of the source is exposed to The first well layer; the drain is embedded in the first well layer, and the upper surface of the drain is exposed to the first well layer.
- the drain electrode and the source electrode are separated by a certain distance; the gate electrode is arranged on the upper surface of the first well layer between the drain electrode and the source electrode.
- the memory cell structure further includes: a first resistive switching unit, a first interconnection layer, and a first connecting line, the first resistive switching unit is located above the drain or the source;
- the first interconnection layer includes A plurality of interconnection sub-layers, the first resistive switching unit is in contact with the upper surface of the drain or source electrode, and the plurality of interconnecting sub-layers are located above the first resistive switching unit;
- the first connection line is along the first interconnection layer and the first resistive switching The arrangement direction of the unit is set to connect the first interconnection layer and the first resistive switching unit with the source electrode or the drain electrode.
- the memory cell structure further includes: a second resistive switching unit, a second interconnection layer, and a second connecting line, the second resistive switching unit is located above the drain or the source;
- the second interconnection layer includes A plurality of interconnection sublayers, at least one interconnection sublayer of the plurality of interconnection sublayers is located between the second resistive switching unit and the drain or source, and the remaining interconnection sublayers are located above the second resistive switching unit;
- the second connecting line It is arranged along the arrangement direction of the second interconnection layer and the second resistance switching unit, and is used to connect the second resistance switching unit and the second interconnection layer with the source electrode or the drain electrode.
- the memory cell structure further includes: a first well electrode and a second well electrode, the first well electrode is embedded in the first well layer, and the upper surface of the first well electrode is exposed to the first well layer ;
- the second well electrode is embedded in the second well layer, and the upper surface of the second well electrode is exposed to the second well layer.
- a memory array structure which includes: a plurality of memory cell array groups, a plurality of bit lines and a plurality of word lines, the plurality of memory cell array groups are arranged parallel to each other in a first direction,
- Each memory cell array group includes: a plurality of memory cell arrays arranged in parallel to each other along the second direction, the memory cell array includes a plurality of the above-mentioned memory cell structures; a plurality of bit lines are arranged in parallel to each other along the first direction, and at least two bit lines are arranged in parallel to each other.
- the lines respectively connect the two ends of the multiple memory cell arrays along the second direction; and the multiple word lines are arranged parallel to each other along the first direction, and are parallel to the multiple bit lines, and each word line connects multiple memory cells along the second direction
- the gate of the memory cell structure at the corresponding position in the array.
- the first direction is perpendicular to the second direction.
- the memory cell array includes at least: a first memory cell structure and a second memory cell structure, the drain terminal of the first memory cell structure is connected to a bit line; the drain terminal of the second memory cell structure is connected to Another bit line is connected, and the source is connected with the source of the first memory cell structure to form a common terminal; wherein the drain terminal further includes a resistive switching unit connected to the drain of the first memory cell structure or the second memory cell structure.
- it further includes: a plurality of source lines arranged in parallel to each other along the second direction, and each source line is connected to the common terminal in the corresponding memory cell array along the first direction;
- the line and the word line are perpendicular to each other.
- Another aspect of the present disclosure provides a voltage bias method applied to the above-mentioned memory array structure, wherein the voltage bias method includes: applying a bias to the first well layer of the memory cell structure in the determined memory array structure Voltage; apply a source terminal voltage to the source line corresponding to the common terminal of the memory cell structure, while applying a drain terminal voltage to the bit line corresponding to the drain terminal of the memory cell structure; wherein the value of the bias voltage is a negative value less than zero , The value of the source terminal voltage and the drain terminal voltage is greater than or equal to the value of the bias voltage.
- 1A is a schematic cross-sectional view of the composition of a memory cell structure in an embodiment of the present disclosure
- 1B is a schematic cross-sectional view of the composition of a memory cell structure in another embodiment of the present disclosure.
- FIG. 2 is a schematic diagram of a corresponding equivalent circuit corresponding to the memory cell structure shown in FIG. 1A or FIG. 1B in an embodiment of the present disclosure
- FIG. 3 is a schematic diagram of the composition of a memory cell array structure in the prior art
- FIG. 4 is a schematic diagram of the composition of a memory cell array structure in an embodiment of the present disclosure.
- FIG. 5 is a schematic diagram of voltage bias corresponding to the memory cell array structure shown in FIG. 4 in an embodiment of the present disclosure
- FIG. 6 is a schematic flowchart of a voltage bias method for a memory cell array structure in an embodiment of the present disclosure.
- the present disclosure provides a memory Cell structure and memory array structure, voltage bias method.
- the memory of the present disclosure may be a new type of embedded memory, such as a resistive random access memory (RRAM), and further may be a resistive random access memory with a 1T1R basic structural unit.
- RRAM resistive random access memory
- 1T1R basic structural unit a resistive random access memory
- the programming of the new embedded memory may include multiple operations.
- the programming of the resistive random access memory (RRAM) is mainly divided into three types: forming operation, set operation, and reset operation.
- the resistive switching unit CELL is programmed from the initial ultra-high resistance state (above M ⁇ ) to a relatively low resistance state (approximately several hundred K ⁇ ).
- a relatively high resistance is applied to the drain terminal corresponding to the bit line BL.
- a gate voltage VG is applied to the gate terminal corresponding to the word line WL to turn on the gate transistor (that is, the gate tube, which is a type of transistor), and the source terminal corresponding to the source line SL is connected to a low level.
- the source terminal is connected to a high level and the drain terminal is connected to a low level.
- the voltage required for the set operation is less than the voltage required for the forming operation, the resistance of the resistive switching unit CELL is small, and the gate tube has a substrate. Bias effect, the voltage applied to the source terminal is relatively large. If a reasonable voltage bias method is not adopted, the voltage applied to the transistor will exceed its maximum limit, making the gate transistor easy to be broken down, resulting in reliable sexual issues.
- the set voltage is applied to the drain terminal, and the source terminal is connected to a low level. Because the memory cell is in a low resistance state, a large part of the voltage will fall on the strobe tube, so the strobe tube will also Face the same reliability problem.
- One aspect of the present disclosure provides a memory cell structure, which, as shown in FIG. 1A and FIG. 1B, includes a substrate layer 100, a well layer 200 and a transistor, and the substrate layer 100 is used to provide support for the memory cell structure.
- the well layer 200 is embedded in the substrate layer 100.
- the upper surface of the well layer 200 is level with the upper surface of the substrate layer 100.
- the substrate layer 100 is provided with a recess recessed from its upper surface.
- the well layer 200 can pass through the chemical vapor phase. The deposition process is formed in the groove.
- the transistor is arranged inside and on the surface of the well layer 200.
- the transistor may be a strobe tube, which is used to control data reading and writing and signal output in the memory cell, and to better isolate the interference of adjacent memory cells, and is more compatible with the CMOS process.
- the well layer 200 includes: a first well layer 210 and a second well layer 220, the first well layer 210 is embedded in the substrate layer 100, and the first well layer
- the upper surface of 210 is level with the upper surface of the substrate layer 100 and is used to form a transistor structure, wherein the transistor is disposed inside and on the surface of the first well layer.
- the second well layer 220 is disposed between the first well layer 210 and the substrate layer 100, and the upper surface of the second well layer 220 is level with the upper surface of the substrate layer 100 to separate the first well layer 210 and the substrate layer 100.
- the second well layer 220 is formed on the inner surface of the groove of the substrate layer 100.
- the second well layer 220 may be formed on the inner surface of the groove by a chemical vapor deposition process, and the inner surface of the groove direct contact.
- the first well layer 210 is formed on the second well layer 220, that is, the outer surface of the second well layer 220 and the inner surface of the first well layer 210 (that is, the side surface and the lower surface except the upper surface of the first well layer 210). Surface) to make contact. Therefore, the second well layer 220 may form an isolation layer between the first well layer 210 and the substrate layer 100 to prevent the first well layer 210 from contacting the substrate layer.
- the substrate layer 100 may be a non-P-type or N-type doped structure layer
- the first well layer 210 may be a P-type doped structure layer for forming a P-type well layer and forming a transistor accordingly
- the layer 220 may be an N-type doped structure layer, used to form an N-type well layer, and used to form an isolation between the substrate layer 100 and the P-type well layer. Therefore, it constitutes the deep well bias structure of the present disclosure.
- the first well layer 210 as the P-type well layer can be biased to the negative voltage VB
- the second well layer 220 as the N-type well layer can be biased to the power supply voltage.
- VCC the substrate layer 100 can be biased to the ground Vsub, as shown in FIG. 2, so that when a negative voltage is applied to the drain terminal and the source terminal, the problem of PN forward conduction does not occur.
- the present disclosure adopts the above-mentioned deep-well bias technology, selects deep-well process transistors, and biases the well potential in a negative voltage state, so that a negative voltage can be connected to the source or drain of the transistor, thereby reducing the application of the drain or
- the voltage value of the source terminal only needs to ensure that the voltage difference falling on the memory cell meets the requirements. At the same time, it is ensured that the voltage difference between different terminals of the transistor does not exceed its breakdown voltage, and the breakdown of the resistive switching unit CELL of the transistor is prevented from causing reliability problems.
- the transistor includes: a gate 310, a source 320, and a drain 330.
- the gate 310 is disposed on the upper surface of the first well layer 210, and The corresponding gate terminal is formed in connection with the word line WL, and the gate voltage VG is applied to turn on the transistor, as shown in FIG. 2.
- the source electrode 320 is embedded in the first well layer 210, and the upper surface of the source electrode 320 is exposed to the first well layer 210.
- the upper surface of the source electrode 320 may be level with the upper surface of the first well layer 210 for contact with the source line SL. Connect to form the corresponding source terminal, and apply the source terminal voltage VS, as shown in Figure 2.
- the drain 330 is embedded in the first well layer 210, and the upper surface of the drain 330 is exposed to the first well layer 210.
- the upper surface of the drain 330 may be level with the upper surface of the first well layer 210 for connection with the bit line BL
- the corresponding drain terminal is formed, and the drain terminal voltage VD is applied, as shown in FIG. 2.
- the gate 310, the source 320, the drain 330 and the first well layer 210 form a transistor of the memory cell structure. It should be noted that there may be multiple transistors disposed on the first well layer 210, and a transistor array is formed on the first well layer 210. Specifically, a gate may be correspondingly provided on the upper surface of the first well layer 210 on the other side of the source 320, and the gate and the above-mentioned transistor structure share the source 320. Correspondingly, multiple other gates can be provided on the upper surface of the first well layer 210 to form multiple transistor structures that can be turned on to ensure that the size and area of the memory cell structure are smaller and the transistor integration level is higher.
- the drain 330 and the source 320 are separated by a certain distance to prevent the contact short circuit of the structure; the gate 310 is provided on the drain 330 and The upper surface of the first well layer 210 between the source electrodes 320.
- a certain thickness of the first well layer 210 is spaced between the drain 330 and the source 320, and a corresponding portion of the first well layer 210 is provided with a gate 310 on the upper surface, and one end of the gate 310 corresponds to the drain 330 , The other end corresponds to the source 320, as shown in FIG. 1A and FIG. 1B.
- the memory cell structure further includes: a first resistive switching unit CELL1, a first interconnection layer 340, and a first connecting line L1, and the first resistive switching unit CELL1 is located at the drain 330 Or above the source 320;
- the first interconnection layer 340 includes a plurality of interconnection sublayers, the first resistive switching unit CELL1 is in contact with the upper surface of the drain 330 or the source 320, and the plurality of interconnection sublayers are located in the first resistive switching unit CELL1 Above;
- the first connecting line L1 is arranged along the first interconnection layer 340, the first resistive switching unit CELL1 arrangement direction, for connecting the first interconnection layer 340, the first resistive switching unit CELL1 and the source 320 or the drain 330 .
- the first interconnection layer 340 may include multiple interconnection sublayers, and each interconnection sublayer may be a metal layer for electrical connection between the constituent structures of the memory cell structure.
- the interconnection sublayer may form bit lines, Word line or source line, etc.
- the first resistive switching unit CELL1 is in contact with the upper surface of the drain 330 or the source 320, which can be understood as being directly connected to the drain 330 or the source 320, and there is no longer any connection between the two except the first connection line L1 The structure is connected. Therefore, the first interconnection layer 340 needs to be disposed above the first resistive switching unit CELL1. As shown in FIG.
- the multiple interconnection sublayers include at least a first interconnection sublayer 341, a second interconnection sublayer 342, and a third interconnection sublayer 343 that are arranged at intervals from bottom to top.
- the corresponding first resistive switching unit CELL1 which is connected to the drain 330.
- the first connecting line L1 sequentially connects the first resistive switching unit CELL1, the first interconnection sublayer 341, the second interconnection sublayer 342, and the third interconnection sublayer 343 from the vertical direction.
- the drain 330 and The first resistive switching units CELL1 can also be connected by a first connecting line L1. Therefore, the memory cell structure of the present disclosure can form a 1T1R type structure with resistive switching cells.
- the memory cell structure further includes: a second resistive switching unit CELL2, a second interconnection layer 350, and a second connecting line L2, and the second resistive switching unit CELL2 is located at the drain Above the electrode 330 or the source electrode 320;
- the second interconnection layer 350 includes a plurality of interconnection sublayers, and at least one interconnection sublayer of the plurality of interconnection sublayers is located between the second resistive switching unit CELL2 and the drain electrode 330 or the source electrode 320 ,
- the remaining interconnection sublayer is located above the second resistive switching unit CELL2;
- the second connecting line L2 is arranged along the arrangement direction of the second interconnection layer 350 and the second resistive switching unit CELL2, and is used to connect the second resistive switching unit CELL2 and the second resistive switching unit CELL2.
- the interconnection layer 350 is connected to the source 320 or the drain 330.
- the second interconnection layer 340 may include multiple interconnection sublayers, and each interconnection sublayer may be a metal layer for electrical connection between the constituent structures of the memory cell structure.
- the interconnection sublayer may form bit lines, Word line or source line, etc.
- the multiple interconnection sublayers include at least a first interconnection sublayer 351, a second interconnection sublayer 352, a third interconnection sublayer 353, and a fourth interconnection sublayer 354 that are arranged at intervals from bottom to top.
- At least the first interconnection sublayer 351 and the second interconnection sublayer 352 are located between the second resistive switching unit CELL2 and the drain 330 or the source 320, and the remaining interconnection sublayers are located between the third interconnection sublayer 353 and the fourth interconnection sublayer 354
- the second connecting line L2 sequentially connects the second interconnection sublayer 351, the second interconnection sublayer 352, the second resistive switching unit CELL2, the third interconnection sublayer 353, and the fourth interconnection sublayer 354 from the vertical direction. . Therefore, the memory cell structure of the present disclosure can form a 1T1R type structure with resistive switching cells.
- the resistive switching cell CELL of the memory cell structure of the present disclosure is located between the drain 330 or the source 320 and the bit line and the source line to form a drain terminal or a source terminal.
- the resistive switching cell CELL can meet the design requirements of different memory cell structures, the preparation requirements of different preparation processes, and the design of different positions relative to the source or drain, which is beneficial to the preparation of 1T1R-type memory cell structure devices.
- first and second are only qualifiers used to make the solution more clear, not used to refer to the two as different storage.
- the cell structure for example, the first resistive switching unit CELL1 and the second resistive switching unit CELL2 may be the same type of resistive switching unit, or different types of resistive switching units, the type of which is affected by the other constituent structures of the corresponding memory cell structure ( For example, transistor design) depends on the difference.
- the memory cell structure further includes: a first well electrode 410 and a second well electrode 420, the first well electrode 410 is embedded in the first well layer 210.
- the upper surface of the first well electrode 410 is exposed to the first well layer 210, and the upper surface of the first well electrode 410 may be level with the upper surface of the first well layer 210.
- the composition structure of the first well electrode 410 and the transistor has a certain distance, and the upper surface of the first well electrode 410 is also level with the upper surface of the substrate layer 100 at the same time.
- the second well electrode 420 is embedded in the second well layer 220, the upper surface of the second well electrode 420 is exposed to the second well layer 220, and the upper surface of the second well electrode 420 may be level with the upper surface of the second well layer 220, At the same time, it is flush with the upper surface of the substrate layer 100.
- the present disclosure adopts a deep-well bias process, as shown in FIGS. 1A, 1B, and 2 to form transistors (such as NMOS transistors) inside and on the surface of the first well layer 210 of the deep-well structure, so that the second A well layer 210 is provided with a separate bias voltage, that is, a negative voltage VB is applied, so that a negative voltage can be applied to the drain terminal or the source terminal, and the negative voltage VB is more negative than the negative voltage applied to the drain terminal or the source terminal.
- a separate bias voltage that is, a negative voltage VB is applied, so that a negative voltage can be applied to the drain terminal or the source terminal, and the negative voltage VB is more negative than the negative voltage applied to the drain terminal or the source terminal.
- the present disclosure is further described as follows:
- Forming operation process The direction of forming operation is from the sink to the source.
- the first well layer 210 is biased to a negative voltage, that is, a negative voltage VB
- the source terminal is biased to a negative voltage VS, in order to prevent the substrate layer 100 and the PN of the source terminal from being turned on , It is necessary to ensure that the negative voltage VB and the negative voltage VS are more negative than the latter.
- the voltage applied to the drain terminal is VD
- the voltage falling on the resistive switching unit CELL is VD-VS. Since VS is negative, this bias method reduces the voltage applied on the drain terminal to the size of the source terminal voltage, that is, the voltage VS.
- this directly reduces the difficulty of the peripheral circuit that needs to transmit the high voltage to the drain terminal, and at the same time ensures the need for the programming voltage on the resistive switching cell CELL.
- the voltage difference between the ports of the strobe tube is within its reliability voltage (generally transistors can meet the redundant voltage of 1 times its normal voltage).
- the direction of set operation is from source to drain.
- the first well layer 210 is biased to a negative voltage, that is, a negative voltage VB
- the drain terminal is biased to a negative voltage VD.
- VD negative voltage
- the voltage applied by the source terminal is VS
- the voltage VD falling on the resistive switching unit CELL VG-Vth
- Vth is the threshold voltage of the resistive switching unit CELL.
- this bias method reduces the voltage VG applied to the gate terminal to the magnitude of the drain terminal voltage VD, which directly reduces the difficulty of the peripheral circuit that needs to transmit high voltage to the gate of the transistor (that is, Gate) , which reduces the risk of grid breakdown by high voltage.
- the requirement of the programming voltage on the resistive switching cell CELL is ensured.
- the voltage difference between the ports of the strobe tube is within its reliability voltage (generally transistors can meet the redundant voltage of 1 times its normal voltage).
- Reset operation process Since the reset operation and forming operation are in the same direction and the required voltage is also the same, the reset operation method can be the same as that of forming, so I won’t repeat it here.
- the word line w1 and the source line sl of the general memory cell array are parallel and perpendicular to the bit line bl at the same time.
- the array structure has the problem that the gate tube of the semi-selected cell is subjected to a large voltage, which may cause breakdown.
- the semi-selected cell may be the resistive switching cell CELL of the memory cell structure 302 and the resistive switching cell CELL of the memory cell structure 303 as shown in FIG.
- the selected cell is the resistive switching cell of the memory cell structure 301.
- CELL after the memory cell structure 301 is selected, one of the word lines w1, bit lines bl, and source lines sl of the unselected memory cell structures 302 and 303 will also experience the selected voltage of the selected cell 301.
- the set operation is similar and will not be repeated), that is, the selected cell 301.
- the voltage vg1 applied to the gate terminal of the corresponding word line wl2 is larger than the source terminal negative voltage vs1 by a threshold voltage, and for the unselected memory cell structure 302, 303, such as the gate terminal of the word line wl1 corresponding to the memory cell structure 303, the applied gate terminal voltage vg3 needs to turn off the resistive switching cell CELL of the memory cell structure 303 in the first row, so it corresponds to the bias of the source line sl1
- the voltage can be selected to be equal to vs1, and the voltage applied to the drain terminal of the corresponding bit line bl2 is high voltage vd.
- the gate corresponding to 301 is turned on, due to the existence of the resistive switching cell CELL , There will be a considerable voltage falling on the resistive switching unit CELL, and the voltage on the transistor is much smaller than its drain voltage vd. Therefore, the voltage at the source and drain terminals and the gate and drain terminals of the transistor are relatively small, which will not cause the transistor Was broken down.
- the adjacent memory cell structures 302 and 303 in the same column as the selected memory cell structure 301 will have the drain terminal voltage equal to the aforementioned voltage vd because their transistors are not turned on.
- the corresponding source line sl1 will be applied as a relatively negative source terminal voltage, so that the memory cell structure 303 in the first row and the memory cell structure 303 in the second row
- the voltages at the source and drain terminals and the gate and drain terminals of the transistors in the cell structure 302 that are not turned on are very high, which may cause the breakdown of the transistors.
- FIG. 4 includes: A plurality of memory cell array groups, a plurality of bit lines and a plurality of word lines, and the plurality of memory cell array groups are arranged parallel to each other in the first direction.
- FIG. 4 it is a partial structure of a memory array structure, specifically a memory cell array structure with four rows and four columns, which includes two memory cell array groups 401 and 402.
- the memory cell array group 402 is relative to the memory cell
- the array group 401 is arranged in parallel in the first direction.
- each memory cell array group includes a plurality of memory cell arrays arranged in parallel to each other along the second direction, and each memory cell array includes a plurality of the foregoing memory cell structures.
- the memory cell array group 401 includes four memory cell arrays 510, 520, 530, and 540.
- the memory cell arrays 510, 520, 530, and 540 are arranged parallel to each other in the second direction, forming one or two rows. Column of memory cell array structure.
- the plurality of bit lines are arranged in parallel to each other along the first direction, and at least two bit lines are respectively connected to the two ends of the plurality of memory cell arrays along the second direction.
- bit lines BL1 and BL2 corresponding to the memory cell array group 401, there may be bit lines BL1 and BL2, where BL1 and BL2 are arranged parallel to each other along the first direction, and BL1 is connected to the memory cell arrays 510, 520, 530 along the second direction.
- bit lines BL1, BL2, BL3, and BL4 are arranged parallel to each other in the first direction.
- a plurality of word lines are arranged parallel to each other along the first direction, and are parallel to each other with the plurality of bit lines, and each word line is connected to the gates of the memory cell structures at corresponding positions in the plurality of memory cell arrays along the second direction.
- word lines WL1 and WL2 corresponding to the memory cell array group 401, there may be word lines WL1 and WL2, where WL1 and WL2 are arranged parallel to each other along the first direction, and WL1 is connected to the memory cell arrays 510, 520, 530 along the second direction.
- the gates (ie, gate ends) of the memory cell structures 511, 521, 531, and 541 at the corresponding positions of and 540, WL2 is connected to the memory cell structure 512 at the corresponding positions of the memory cell arrays 510, 520, 530, and 540 along the second direction , 522, 532 and 542 gates.
- the memory cell structure 511 of the memory cell array 510 is located in the first row and first column of the memory cell array group 401.
- the memory cell structure at the corresponding position is the memory cell array.
- word lines WL3 and WL4 there may be word lines WL3 and WL4, and the connection relationship of the word lines WL3 and WL4 can refer to the above-mentioned WL1 and WL2, which will not be repeated here. It should be noted that the word lines WL1, WL2, WL3, and WL4 are arranged parallel to each other in the first direction.
- the bit lines BL1, BL2, BL3, and BL4 and the word lines WL1, WL2, WL3, and WL4 are arranged parallel to each other in the first direction, that is, the bit lines and the word lines are arranged parallel to each other.
- the first direction is perpendicular to the second direction.
- the memory cell array includes at least: a first memory cell structure and a second memory cell structure, the drain terminal of the first memory cell structure is connected to a bit line; the second memory cell The drain of the structure is connected with another bit line, and the source is connected with the source of the first memory cell structure to form a common end.
- the memory cell array 510 may at least include a first memory cell structure 511 and a second memory cell structure 512, where the "first" and "second" are only used to make the solution clearer. The term is not used to indicate that the first memory cell structure 511 and the second memory cell structure 512 are different memory cell structures.
- first memory cell structure 511 and the second memory cell structure 512 may be the same type of deep well
- the bias structure may also be a different type of deep well bias structure, and its type is determined by the design of the first well layer 210, the second well layer 220, and the transistor.
- the drain terminal also includes a resistive switching unit connected to the drain of the first memory cell structure or the second memory cell structure.
- a resistive switching unit can be arranged between the drain and the bit line, and the drain is connected to the bit line through the resistive switching unit.
- the drain of the first memory cell structure 511 is connected to the resistive switching unit, and the resistive switching unit is connected to a bit line BL1 to form a drain terminal between the resistive switching unit and the bit line BL1;
- the drains of the two memory cell structures 512 are connected to the resistive switching unit, and the resistive switching unit is connected to another bit line BL2 to form a drain between the resistive switching unit and the bit line BL2.
- the source of the second memory cell structure 512 is connected to the source of the first memory cell structure 511 to form a common terminal a, which is used to connect with the source line SL1 to form a common source terminal.
- the memory cell array 520 may include the first memory cell structure 521 and the second memory cell structure 522 and the common end b of the two
- the memory cell array 530 may include the first memory cell structure 531 and the second memory cell structure. 532 and the common terminal c of the two
- the memory cell array 540 may include the first memory cell structure 541 and the second memory cell structure 542 and the common terminal d of the two, which will not be repeated here.
- FIG. 4 it further includes: a plurality of source lines arranged in parallel to each other along the second direction, and each source line is connected to a common terminal in the corresponding memory cell array along the first direction, wherein, The source line is perpendicular to the bit line and the word line at the same time.
- the source lines SL1, SL2, SL3, and SL4 are arranged in parallel to each other along the second direction, and the source line SL1 connects the common end a of the memory cell array 510 and the common end a of the corresponding memory cell array of the memory cell array group 402 along the first direction.
- the source line SL2 is connected in the first direction to the common terminal b of the memory cell array 520 and the common terminal of the corresponding memory cell array of the memory cell array group 402; the source line SL3 is connected in the first direction to the common terminal c of the memory cell array 530 and The common end of the corresponding memory cell array of the memory cell array group 402; the source line SL4 connects the common end d of the memory cell array 540 and the common end of the corresponding memory cell array of the memory cell array group 402 along the first direction.
- the source line is perpendicular to the bit line and the word line at the same time.
- the bit line and the word line are parallel to each other, and at the same time perpendicular to the source line, which completely subverts the traditional memory array structure in which the word line and the source line are parallel to each other.
- the array composition design that is perpendicular to the bit line forms a brand-new memory cell array composition structure, which can be said to be a pioneering design in the field of memory technology.
- Voltage bias methods include:
- the arrangement of the first well layer 210 is the arrangement position provided by the first well electrode 410, and the bias voltage VB applied to the first well electrode 410 will not affect other memory components except the selected memory cell structure. , which further provides high voltage bias pertinence and accuracy, and at the same time prevents the risk of large voltage breakdown for transistors of other memory cell structures other than the selected memory cell structure.
- S620 Apply a source terminal voltage VS to the source line corresponding to the common terminal of the memory cell structure, and simultaneously apply a drain terminal voltage VD to the bit line corresponding to the drain terminal of the memory cell structure, as shown in FIG. 1A or FIG. 1B.
- the value of the bias voltage VB is a negative value less than zero
- the values of the source voltage VS and the drain voltage VD are greater than or equal to the value of the bias voltage VB
- the voltage value here is a value that distinguishes between positive and negative values
- the voltages corresponding to both ends of the source and drain are also low, which not only ensures that the selected memory cell structure 522 will not have the PN junction forward conduction problem, but also prevents the unselected or half-selected memory cell structure from being affected by the voltage. If it is too large, the transistor breakdown problem will be caused, and the impact on the structure of other unselected memory cells will be minimized.
- the present disclosure further proposes a memory array structure in view of the large voltage faced by unselected transistors caused by the deep-well negative voltage bias structure, which leads to the problem that affects its reliability, as shown in FIGS. 4 and 5 above.
- the word line WL and the bit line BL are arranged in parallel and perpendicular to the source line SL. This lies in the memory cell structure of the deep well negative voltage bias structure, which can effectively avoid half-selected memory.
- the cell structure of the cell will experience high voltage problems. It should be noted that FIG. 4 and FIG. 5 show the arrangement of the same memory cell array structure.
- a Forming operation or a reset operation is performed on the storage unit structure in the second row and second column, which corresponds to the operation of the storage unit structure 522 in FIG. 4.
- the bias voltage of the source terminal is the negative voltage VSL
- the gate voltage VG applied to the gate terminal of the word line WL2 is larger than VSL by a threshold voltage, and the unselected row (such as the row corresponding to the word line WL1) is applied
- the gate voltage needs to turn off the resistive switching cell CELL of the memory cell structure 521 in the first row, so its bias voltage can be selected to be equal to VSL.
- the voltage applied to the drain terminal of the bit line BL2 is the high voltage VD, and the gate tube of the resistive switching cell CELL of the selected memory cell structure 522 is turned on. Due to the existence of the resistive switching cell CELL, there will be a considerable voltage drop. On the resistive switching unit CELL, the voltage falling on the strobe tube is much smaller than VD, so the source and drain terminals of the strobe tube have relatively small voltages, which will not cause tube breakdown.
- the present disclosure places the bit line BL in parallel with the word line WL, and the voltage applied by the bit line BL is only applied to the resistive switching cell CELL of the memory cell structure of the row selected by the word line WL.
- the upper corresponding to the word line WL2 shown in FIG. 5
- the resistive switching cells CELL of the memory cell structures 512, 532, and 542 in FIG. 4 are half-selected cells.
- the source terminal can be individually biased, it is only necessary to set the source terminal (that is, the common The terminal b) applies a relatively negative voltage to ensure the voltage difference requirement of the resistive switching unit CELL.
- a corresponding application of one can turn off the gate tube where the unselected resistive switching cell CELL is located.
- the negative voltage is sufficient.
- the same voltage can be applied to the source line SL1 of the first column (the memory cell array 510 in FIG. 4) as the word line WL1, so the source-drain terminal voltage and the gate-drain voltage of the transistor are smaller. The transistor will not be broken down by high voltage, and the reliability is guaranteed.
- the drain terminal voltage VD is connected to a high voltage
- the half-selected resistive switching unit CELL has a drain terminal voltage equal to VD because the transistor is turned off.
- the deep well bias structure will be configured as a negative voltage on the semi-selected resistive switching cell CELL, it will cause its drain terminal and the PN junction of the first well layer to experience a large reverse bias voltage, but the transistor is more sensitive to large voltages.
- the source-drain voltage is followed by the gate-source voltage and the gate-drain voltage.
- the reverse bias voltage of the PN junction is generally larger, which will not cause the breakdown of the transistor.
- a forming operation or a reset operation is performed on a black-filled memory cell structure (ie, the memory cell structure 522 in FIG. 4), assuming that the required operating voltage is greater than 2.5V, here it is assumed that the voltage required to fall on the resistive switching cell CELL is about 2.5V to complete the forming operation. If the traditional process (non-deep well negative voltage bias) is used, such a large voltage is not easy to pass into the memory cell Array, while the WL and BL of the traditional array structure are perpendicular to each other, the transistors of the unselected memory cell will be broken down by a large voltage.
- the upper and lower parts of the selected memory cell structure 301 are half-selected memory cells. Structures 303 and 302, because the transistor is not turned on at this time, the high voltage is completely biased on the transistor, which is likely to cause its transistor to be broken down, and the deep well negative voltage biased memory cell structure and word line of the present disclosure are adopted.
- the memory array structure in which the WL and the bit line BL are parallel to each other makes the voltage of all the transistors in the array within their reliable operating range.
- the selected cell corresponds to the memory cell structure 522 shown in FIG. It can also be biased to -0.8V, and the problem of forward conduction of the PN junction between the substrate layer and the source terminal will not occur at this time.
- the word line WL2 of the selected memory cell structure 522 is applied with a voltage of 0.3V, so that its gate-source voltage is 1.1V, so that the transistor can be completely turned on.
- half-selected memory cell structures with reliability risks correspond to the memory cell structures 512, 522, 532, and 542 in FIG. 4.
- you can A relatively high voltage is applied to the source line terminals SL1, SL3, and SL4, for example, 0.3V can be selected. It can be seen that, except for the substrate layer and the source terminal voltage of the half-selected risk memory cell structure, the voltages at any other terminals are relatively low.
- the reverse breakdown voltage that the PN junction structure can withstand is much greater than its applied operating voltage, which will not cause a transistor The PN junction is broken down.
- the present disclosure overturns the arrangement rules of the traditional memory array structure and redesigns the arrangement structure of the memory cell array.
- the memory array structure is performing forming operations, set operations, and reset operations.
- the voltage difference between any two ends of the strobe tube corresponding to the unselected resistive switching unit CELL that does not need to be operated will not exceed its breakdown voltage.
- the memory array structure is more stable and reliable, and the volume and area size are well controlled. It is a subversive design in the memory field, which makes the application and promotion of embedded memory reach a new height and has extremely high commercial value. And scientific research value.
- the present disclosure provides a memory cell structure, a memory array structure, and a voltage biasing method.
- the memory cell structure includes: a substrate layer, a well layer and a transistor, the substrate layer is used to support the memory cell structure; the well layer is embedded in the substrate layer On the upper surface, the upper surface of the well layer is level with the upper surface of the substrate layer, and the transistor is arranged on the well layer.
- the present disclosure applies deep well bias to the memory cell structure so that the well voltage of the memory cell can be individually biased to a specific voltage.
- the programming voltage of the memory cell is reduced, and at the same time, the strobe transistor can be prevented from being broken down due to excessive voltage, thereby ensuring better reliability of the device and higher area efficiency of the memory cell array structure.
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Abstract
本公开提供了一种存储单元结构及存储器阵列结构、电压偏置方法,其中,存储单元结构包括:衬底层、阱层和晶体管,衬底层用于支撑存储单元结构;阱层嵌设于衬底层上,阱层的上表面与衬底层的上表面持平,晶体管设置于阱层上。本公开通过对存储单元结构进行了深阱偏置,使得存储单元的阱电压可以单独偏置为特定的电压,结合重新设计的存储单元阵列结构,将施加的编程电压大部分落在存储单元结构上,实现了对存储单元的编程电压的降低,同时可以避免选通晶体管因承受过大电压而被击穿,从而确保器件更好的可靠性以及存储单元阵列结构的面积效率更高。
Description
本公开涉及存储器技术领域,具体涉及一种存储单元结构及存储器阵列结构、电压偏置方法。
随着半导体制备工艺的发展,传统的嵌入式存储器(以闪存为主)在28nm工艺节点以下面临工艺复杂度急剧增加、成本上升、性能下降等技术瓶颈,因此迫切需要一种新型的嵌入式存储技术。现有技术中,新型嵌入式存储器包括阻变存储器(RRAM)、相变存储器(PCRAM)、磁存储器(MRAM)等类型,其具有与CMOS工艺兼容、微缩性强、成本低等优点,近年来已得到了广泛的研究和关注。
在现有技术中,由于工艺、材料的限制,新型嵌入式存储器的编程电压虽然较传统嵌入式存储器低,但是仍然无法降低到和先进工艺节点(28nm及以下)CMOS晶体管的核心电压的水平。因为在嵌入式应用领域,新型存储器大都采用1T1R的结构,即一个选通晶体管配一个存储单元,如果无法降低存储单元的编程电压,就需要采用高耐压值的选通管,这无疑增加了存储单元的面积,导致成本的上升,阵列结构面积效率低。
发明内容
本公开的一个方面提供了一种存储单元结构,其中,包括:衬底层、阱层和晶体管,衬底层用于为存储单元结构提供支撑;阱层嵌设于衬底层,阱层的上表面与衬底层的上表面持平,晶体管设置于阱层内部及表面。
根据本公开的实施例,其中,阱层包括:第一阱层和第二阱层,第一阱层嵌设于衬底层,第一阱层的上表面与衬底层的上表面持平;第二阱层设置于第一阱层和衬底层之间,第二阱层的上表面与衬底层的上表面持平,用于间隔第一阱层和衬底层;其中,晶体管设置于第一阱层的内部及表面。
根据本公开的实施例,其中,衬底层是非P型或N型掺杂的结构层;第一阱层是P型掺杂结构层,用于形成P型阱层;第二阱层是N型掺杂结构层,用于形成N型阱层,作为衬底层与P型阱层之间的隔离。
根据本公开的实施例,其中,晶体管包括:栅极、源极和漏极,栅极设置于第一阱层的上表面;源极嵌设于第一阱层,源极的上表面暴露于第一阱层;漏极嵌设于第一阱层,漏极的上表面暴露于第一阱层。
根据本公开的实施例,其中,漏极与源极之间间隔一定距离;栅极设置于漏极与源极之间的第一阱层的上表面。
根据本公开的实施例,其中,存储单元结构还包括:第一阻变单元、第一互联层和第一连接线,第一阻变单元位于漏极或源极的上方;第一互联层包括多个互联子层,第一阻变单元与漏极或源极的上表面接触,多个互联子层位于第一阻变单元的上方;第一连接线沿第一互联层、第一阻变单元的设置方向设置,用于将第一互联层、第一阻变单元与源极或漏极连接。
根据本公开的实施例,其中,存储单元结构还包括:第二阻变单元、第二互联层和第二连接线,第二阻变单元位于漏极或源极的上方;第二互联层包括多个互联子层,多个互联子层中的至少一个互联子层位于第二阻变单元和漏极或源极之间,剩余互联子层位于第二阻变单元的上方;第二连接线沿第二互联层、第二阻变单元的设置方向设置,用于将第二阻变单元、第二互联层与源极或漏极连接。根据本公开的实施例,其中,存储单元结构还包括:第一阱电极和第二阱电极,第一阱电极嵌设于第一阱层,第一阱电极的上表面暴露于第一阱层;第二阱电极嵌设于第二阱层,第二阱电极的上表面暴露于第二阱层。
本公开的另一个方面提供了一种存储器阵列结构,其中,包括:多个存储单元阵列组、多条位线和多条字线,多个存储单元阵列组在第一方向上相互平行排列,每个存储单元阵列组包括:多个存储单元阵列,沿第二方向相互平行排列,存储单元阵列包括多个上述的存储单元结构;多条位线沿第一方向相互平行排列,至少两条位线沿第二方向分别连接多个存储单元阵列的两端;以及多条字线沿第一方向相互平行排列,与多条位线相互平行,每条字线沿第二方向连接多个存储单元阵列中对应位置的存储单元结构的栅极。
根据本公开的实施例,其中,第一方向垂直于第二方向。
根据本公开的实施例,其中,存储单元阵列至少包括:第一存储单元 结构和第二存储单元结构,第一存储单元结构的漏端与一条位线连接;第二存储单元结构的漏端与另一条位线连接,源极与第一存储单元结构的源极连接形成公共端;其中,漏端还包括与第一存储单元结构或第二存储单元结构的漏极相连接的阻变单元。
根据本公开的实施例,其中,还包括:多条源线,沿第二方向相互平行排列,每条源线沿第一方向连接对应存储单元阵列中的公共端;其中,源线同时与位线及字线相互垂直。
本公开的又一个方面提供了一种电压偏置方法,应用于上述的存储器阵列结构,其中,电压偏置方法包括:对确定的存储器阵列结构中的存储单元结构的第一阱层施加偏置电压;对与存储单元结构的公共端对应的源线施加源端电压,同时对与存储单元结构的漏端对应的位线施加漏端电压;其中,偏置电压的值为小于零的负值,源端电压和漏端电压的值为大于等于偏置电压的值。
图1A是本公开一实施例中存储单元结构的组成剖面示意图;
图1B是本公开另一实施例中存储单元结构的组成剖面示意图;
图2是本公开实施例中对应图1A或图1B所示的存储单元结构的对应等效电路示意图;
图3是现有技术中存储单元阵列结构的组成示意图;
图4是本公开实施例中存储单元阵列结构的组成示意图;
图5是本公开实施例中对应图4所示的存储单元阵列结构的电压偏置示意图;
图6是本公开实施例中存储单元阵列结构的电压偏置方法的流程示意图。
为使本公开的目的、技术方案和优点更加清楚明白,以下结合具体实施例,并参照附图,对本公开进一步详细说明。
为了解决现有先进工艺节点下,在控制存储器面积尺寸和成本的前提 下,新型嵌入式存储器的编程电压无法有效降低,造成新型嵌入式存储器结构可靠性差的技术问题,本公开提供了一种存储单元结构及存储器阵列结构、电压偏置方法。
为能够对本公开的技术方案作清楚的说明,本公开的存储器可以是新型嵌入式存储器,例如阻变存储器(RRAM),进一步地可以是具有1T1R基本结构单元的阻变存储器。但是,本领域技术人员应当理解,其并非是对本公开的权利要求书保护范围的限制。
新型嵌入式存储器的编程可以包括多种操作,例如对阻变存储器(RRAM)的编程主要分为三种:初始化(forming)操作,设定(set)操作,置位(reset)操作。
在forming操作时,将阻变单元CELL从初始的超高阻状态(为MΩ以上)编程至相对低的电阻状态(约为几百KΩ),这种情况下位线BL对应的漏端上施加较大的编程电压,字线WL对应的栅端上施加栅电压VG打开选通晶体管(即选通管,为晶体管的一种),源线SL对应的源端则接低电平。此时,因为电阻的初始值较大,所以大部分的电压落在了阻变单元CELL上,使得即使施加在漏端上的电压较大,实际落在选通晶体管的电压也会相对较小,而且不会对晶体管的可靠性产生影响。
在set操作时,源端接高电平,漏端接低电平,虽然set操作需要的电压小于forming操作需要的电压,但是由于阻变单元CELL的电阻较小,同时选通管存在衬底偏置效应,施加在源端上的电压较大,若不采取合理的电压偏置方式,施加在晶体管上的电压会超过它的最大限值,使得选通晶体管易被击穿,从而产生可靠性问题。
在reset操作的时,置位电压施加在漏端,源端接低电平,因为存储单元处于低阻状态,所以电压还会有很大部分落在选通管上,因此选通管也会面临同样的可靠性问题。
本公开的一个方面提供了一种存储单元结构,其中如图1A、图1B所示,包括:衬底层100、阱层200和晶体管,衬底层100用于为该存储单元结构提供支撑。
阱层200嵌设于衬底层100,阱层200的上表面与衬底层100的上表面持平,衬底层100设置有自其上表面向下内凹的一凹槽,阱层200可以 通过化学气相沉积工艺形成于该凹槽内。
晶体管设置于阱层200内部及表面,晶体管可以是选通管,用于控制存储单元中的数据读写与信号输出,以及更好的隔离相邻存储单元的干扰,与CMOS工艺也更易兼容。
根据本公开的实施例,其中如图1A、图1B所示,阱层200包括:第一阱层210和第二阱层220,第一阱层210嵌设于衬底层100,第一阱层210的上表面与衬底层100的上表面持平,用于形成晶体管结构,其中,晶体管设置于第一阱层的内部及表面。第二阱层220设置于第一阱层210和衬底层100之间,第二阱层220的上表面与衬底层100的上表面持平,用于间隔第一阱层210和衬底层100。
换言之,第二阱层220形成于上述衬底层100的凹槽的内表面,具体地,第二阱层220可以通过化学气相沉积工艺形成于该凹槽的内表面,与该凹槽的内表面直接接触。第一阱层210形成于第二阱层220之上,即第二阱层220的外表面与第一阱层210的内表面(即除第一阱层210上表面之外的侧表面和下表面)形成接触。因此,第二阱层220可以在第一阱层210和衬底层100之间形成隔离层,防止第一阱层210与衬底层接触。
进一步地,衬底层100可以是非P型或N型掺杂的结构层,第一阱层210可以是P型掺杂结构层,用于形成P型阱层,并据此形成晶体管;第二阱层220可以是N型掺杂结构层,用于形成N型阱层,用于形成衬底层100和P型阱层之间的隔离。因此,其构成了本公开的深阱偏置结构,作为P型阱层的第一阱层210可以偏置为负压VB,作为N型阱层的第二阱层220可以偏置为电源电压VCC,衬底层100可以偏置为接地Vsub,如图2所示,使得漏端和源端在施加负压时,不会发生PN正向导通的问题。
因此,本公开采用上述深阱偏置技术,选择深阱工艺晶体管,将阱电位偏置在负压状态,这样可以在晶体管的源端或者漏端接负电压,从而可以降低施加在漏端或者源端的电压值,只需保证落在存储单元的电压差满足要求即可。同时又保证了晶体管的不同端电压差不会超过其击穿电压,防止晶体管的阻变单元CELL的击穿造成可靠性问题。
根据本公开的实施例,其中如图1A、图1B和图2所示,晶体管包括: 栅极310、源极320和漏极330,栅极310设置于第一阱层210的上表面,用于与字线WL连接形成对应的栅端,并施加栅电压VG打开晶体管,如图2所示。
源极320嵌设于第一阱层210,且源极320的上表面暴露于第一阱层210,源极320上表面可以与第一阱层210的上表面持平,用于与源线SL连接形成对应的源端,并施加源端电压VS,如图2所示。
漏极330嵌设于第一阱层210,且漏极330上表面暴露于第一阱层210,漏极330上表面可以与第一阱层210的上表面持平,用于与位线BL连接形成对应的漏端,并施加漏端电压VD,如图2所示。
其中,栅极310、源极320、漏极330和第一阱层210形成该存储单元结构的晶体管。需要说明的是,设置于该第一阱层210的晶体管可以有多个,并在第一阱层210上形成晶体管阵列。具体地,可以在源极320的另一侧的第一阱层210上表面上对应设置一栅极,该栅极与上述晶体管结构共用该源极320。相应地,可以在第一阱层210上表面设置其他的多个栅极,形成多个可以导通的晶体管结构,以确保存储单元结构的尺寸和面积更小,晶体管集成度更高。
根据本公开的实施例,其中如图1A、图1B和图2所示,漏极330与源极320之间间隔一定距离,用以防止结构的接触短路;栅极310设置于漏极330与源极320之间的第一阱层210的上表面。换言之,漏极330和源极320之间间隔一定厚度的第一阱层210,对应该部分的第一阱层210的上表面上对应设置栅极310,栅极310的一端对应于漏极330,另一端对应于源极320,如图1A、图1B所示。
根据本公开的实施例,其中,如图1A所示,存储单元结构还包括:第一阻变单元CELL1、第一互联层340和第一连接线L1,第一阻变单元CELL1位于漏极330或源极320的上方;第一互联层340包括多个互联子层,第一阻变单元CELL1与漏极330或源极320的上表面接触,多个互联子层位于第一阻变单元CELL1的上方;第一连接线L1沿第一互联层340、第一阻变单元CELL1的设置方向设置,用于将第一互联层340、第一阻变单元CELL1与源极320或漏极330连接。
具体地,第一互联层340可以包括多个互联子层,每个互联子层可以 是金属层,用于存储单元结构的各组成结构之间的电连接,例如互联子层可以形成位线、字线或源线等。第一阻变单元CELL1与漏极330或源极320的上表面接触,可以理解为与漏极330或源极320直接相连,二者之间不再通过除第一连接线L1之外的其它结构进行连接。因此,第一互联层340需要设置于第一阻变单元CELL1的上方。如图1A所示,多个互联子层至少包括从下往上依次间隔设置的第一互联子层341、第二互联子层342、第三互联子层343,其中第一互联子层341的下方为对应设置的第一阻变单元CELL1,其与漏极330连接。另外,第一连接线L1自垂直方向上,依次将第一阻变单元CELL1、第一互联子层341、第二互联子层342、第三互联子层343连接起来,其中,漏极330和第一阻变单元CELL1之间也可以借助第一连接线L1相连。因此,本公开的存储单元结构可以形成具有阻变单元的1T1R型结构。
根据本公开的另一实施例,其中,如图1B所示,存储单元结构还包括:第二阻变单元CELL2、第二互联层350和第二连接线L2,第二阻变单元CELL2位于漏极330或源极320的上方;第二互联层350包括多个互联子层,多个互联子层中的至少一个互联子层位于第二阻变单元CELL2和漏极330或源极320之间,剩余互联子层位于第二阻变单元CELL2的上方;第二连接线L2沿第二互联层350、第二阻变单元CELL2的设置方向设置,用于将第二阻变单元CELL2、第二互联层350与源极320或漏极330连接。
具体地,第二互联层340可以包括多个互联子层,每个互联子层可以是金属层,用于存储单元结构的各组成结构之间的电连接,例如互联子层可以形成位线、字线或源线等。如图1B所示,多个互联子层至少包括从下往上依次间隔设置的第一互联子层351、第二互联子层352、第三互联子层353、第四互联子层354,其中至少第一互联子层351、第二互联子层352位于第二阻变单元CELL2和漏极330或源极320之间,剩余互联子层第三互联子层353、第四互联子层354位于第二阻变单元CELL2的上方,也即第三互联子层353的下方、第二互联子层352的上方为对应设置的第二阻变单元CELL2,其与漏极330不再直接连接。另外,第二连接线L2自垂直方向上,依次将第二互联子层351、第二互联子层352、第二阻变 单元CELL2、第三互联子层353、第四互联子层354连接起来。因此,本公开的存储单元结构可以形成具有阻变单元的1T1R型结构。
可见,本公开的存储单元结构的阻变单元CELL位于漏极330或源极320和位线、源线之间,用于形成漏端或源端。另外,该阻变单元CELL可以符合不同存储单元结构的设计要求、不同制备工艺的制备需要、相对源极或漏极进行不同位置的设计,有益于1T1R型结构的存储单元结构器件的制备。
需要说明的是,在本公开的实施例中,其中,“第一”和“第二”仅为使方案更加清楚的表达所采用的限定词,并非是用于指代两者为不同的存储单元结构,例如,第一阻变单元CELL1和第二阻变单元CELL2可以是相同类型的阻变单元,也可以是不同类型的阻变单元,其类型受到上述相应存储单元结构的其他组成结构(例如晶体管设计)的不同而决定。
根据本公开的实施例,其中如图1A、图1B和图2所示,存储单元结构还包括:第一阱电极410和第二阱电极420,第一阱电极410嵌设于第一阱层210,第一阱电极410的上表面暴露于第一阱层210,第一阱电极410的上表面可以与第一阱层210的上表面持平。第一阱电极410与晶体管的组成结构具有一定间距,第一阱电极410的上表面同时也与衬底层100的上表面持平。
第二阱电极420嵌设于第二阱层220,第二阱电极420的上表面暴露于第二阱层220,第二阱电极420的上表面可以与第二阱层220的上表面持平,同时与衬底层100的上表面持平。
因此,本公开采用深阱偏置工艺,如图1A、图1B和图2所示,将晶体管(例如NMOS晶体管)形成于深阱结构的第一阱层210内部及表面,借此可以对第一阱层210设置单独的偏置电压,即施加一个负电压VB,这样就可以在漏端或源端上施加负电压,在负电压VB比漏端或源端上施加的负电压更负的情况下,就不会出现PN正向导通问题。具体地,参照图1A、图1B和图2,依据上述存储单元结构的三种基本操作方法:初始化(forming)操作,设定(set)操作,置位操作(reset),本公开作进一步的说明如下:
Forming操作过程:forming操作方向为漏端到源端。如图1A、图1B 和图2所示,将第一阱层210偏置为负电压,即负电压VB,源端偏置为负电压VS,为了防止衬底层100和源端的PN正向导通,需要保证负电压VB和负电压VS相对于后者更负。此时漏端施加的电压为VD,落在阻变单元CELL上的电压为VD-VS。由于VS为负,所以该种偏置方法,是将漏端上施加的电压降低到了源端电压的大小,即电压VS。换言之,这直接降低了外围电路需要传输高压到漏端的难度,同时保证了阻变单元CELL上的编程电压的需要。而且选通管各个端口之间的压差在其可靠性电压之内(一般晶体管可以满足其正常电压1倍的冗余电压)。
Set操作过程:set操作方向为源端到漏端。如图1A、图1B和图2所示,第一阱层210偏置为负电压,即负电压VB,漏端偏置为负电压VD,此时为了防止衬底层100和漏端的PN正向导通,需要保证电压VB和电压VD相对于后者更负。此时源端施加的电压为VS,落在阻变单元CELL上的电压VD=VG-Vth,Vth为阻变单元CELL的阈值电压。由于VD为负值,所以该种偏置方法,使得栅端上施加的电压VG降低到了漏端电压VD的大小,这直接降低了外围电路需要传输高压到晶体管的栅极(即Gate)的难度,降低了栅极被高压击穿的风险。同时保证了阻变单元CELL上的编程电压的需要。而且选通管各个端口之间的压差在其可靠性电压之内(一般晶体管可以满足其正常电压1倍的冗余电压)。
Reset操作过程:由于reset操作和forming操作方向一致,需要的电压也一样,所以reset操作方法可以与forming一致,在此不作赘述。
需要进一步说明的是,基于传统的存储器结构,例如图3所示或非NOR存储器结构,一般存储单元阵列的字线wl和源线sl平行,同时与位线bl垂直。但是,当其中的存储单元结构采用本公开上述的深阱负压偏置结构的存储单元结构后,该阵列结构会存在半选中单元的选通管承受大电压从而造成被击穿的问题。在本公开的实施例中,半选中单元可以是如图3所示的存储单元结构302的阻变单元CELL和存储单元结构303的阻变单元CELL,选中单元为存储单元结构301的阻变单元CELL,在选中存储单元结构301后,未选中存储单元结构302、303的字线wl、位线bl和源线sl中的某一根也会经受选中单元301的选中电压。
如图3所示,假设要对第二行第二列的存储单元结构301进行Forming 操作或reset操作(set操作类似,不再赘述),即被选中单元301。此时因为其对应源线sl1的源端偏置为负电压vs1,所以其对应字线wl2的栅端施加的电压vg1比源端负电压vs1大一个阈值电压,而对于未选中的存储单元结构302、303,如存储单元结构303对应字线wl1的栅端,其施加的栅端电压vg3需要把第一行的存储单元结构303的阻变单元CELL关闭,所以其对应源线sl1偏置的电压可以选择等于vs1,而此时对应位线bl2的漏端施加的电压为高压vd,选中存储单元结构301的阻变单元CELL,对应301的选通管打开,由于该阻变单元CELL的存在,会有相当电压落在阻变单元CELL上,而落晶体管上的电压较其漏端电压vd减小很多,所以该晶体管的源漏端、栅漏端的电压都相对较小,不会导致晶体管被击穿。但是,与被选中的存储单元结构301同一列的相邻存储单元结构302和303,则会由于其晶体管没有被打开,造成其漏端电压和上述的电压vd相等。由于此电压较大,同时为了满足选中存储单元结构301的电压要求,对应源线sl1会被施加为一个较负的源端电压,这样第一行中存储单元结构303和第二行中的存储单元结构302未打开的晶体管的源漏端、栅漏端的电压非常大,极有可能会导致其晶体管被击穿。
为解决上述由于本公开所采用的深阱偏置结构所带来的存储单元阵列结构的可靠性问题,本公开的另一个方面提供了一种存储器阵列结构,其中如图4所示,包括:多个存储单元阵列组、多条位线和多条字线,多个存储单元阵列组在第一方向上相互平行排列。如图4所示,为一存储器阵列结构的部分组成结构,具体是一四行四列的存储单元阵列结构,其中包括两个存储单元阵列组401和402,存储单元阵列组402相对于存储单元阵列组401在第一方向上平行排列。其中,每个存储单元阵列组包括:多个存储单元阵列,沿第二方向相互平行排列,每个存储单元阵列包括多个上述的存储单元结构。如图4所示,存储单元阵列组401包括4个存储单元阵列510、520、530和540,该存储单元阵列510、520、530和540在第二方向上相互平行排列,构成一两行4列的存储单元阵列结构。
多条位线沿第一方向相互平行排列,至少两条位线沿第二方向分别连接多个存储单元阵列的两端。如图4所示,对应于存储单元阵列组401中,可以存在位线BL1和BL2,其中BL1与BL2沿第一方向相互平行排列, BL1沿第二方向连接于存储单元阵列510、520、530和540的上端,即连接于存储单元结构511、521、531和541的漏端;BL2沿第二方向连接于存储单元阵列510、520、530和540的下端,即连接于存储单元结构512、522、532和542的漏端。相应地,对应于存储单元阵列组402中,可以存在位线BL3和BL4,其连接关系参照上述BL1和BL2,在此不作赘述。需要说明的是,位线BL1、BL2、BL3和BL4在第一方向上相互平行设置。
多条字线沿第一方向相互平行排列,与多条位线相互平行,每条字线沿第二方向连接多个存储单元阵列中对应位置的存储单元结构的栅极。如图4所示,对应于存储单元阵列组401中,可以存在字线WL1和WL2,其中WL1与WL2沿第一方向相互平行排列,WL1沿第二方向连接于存储单元阵列510、520、530和540的对应位置的存储单元结构511、521、531和541的栅极(即栅端),WL2沿第二方向连接于存储单元阵列510、520、530和540的对应位置的存储单元结构512、522、532和542的栅极。在本公开实施例中,存储单元阵列510的存储单元结构511位于该存储单元阵列组401的第一行第一列,在该存储单元阵列组401中,与之对应位置的存储单元结构为存储单元阵列520的存储单元结构521、存储单元阵列530的存储单元结构531和存储单元阵列540的存储单元结构541。相应地,对应于存储单元阵列组402中,可以存在字线WL3和WL4,其连接关系参照上述WL1和WL2,在此不作赘述。需要说明的是,字线WL1、WL2、WL3和WL4在第一方向上相互平行设置。
因此,在本公开的存储器阵列结构中,位线BL1、BL2、BL3和BL4与字线WL1、WL2、WL3和WL4在第一方向上相互平行设置,即位线与字线相互平行设置。
根据本公开的实施例,其中如图4所示,第一方向垂直于第二方向。
根据本公开的实施例,其中如图4所示,存储单元阵列至少包括:第一存储单元结构和第二存储单元结构,第一存储单元结构的漏端与一条位线连接;第二存储单元结构的漏端与另一条位线连接,源极与第一存储单元结构的源极连接形成公共端。具体地,存储单元阵列510可以至少包括第一存储单元结构511和第二存储单元结构512,其中,该处的“第一”和“第二”仅为使方案更加清楚的表达所采用的限定词,并非是用于指代 第一存储单元结构511和第二存储单元结构512为不同的存储单元结构,换言之,第一存储单元结构511和第二存储单元结构512可以是相同类型的深阱偏置结构,也可以是不同类型的深阱偏置结构,其类型受到上述第一阱层210和第二阱层220以及晶体管等设计的不同而决定。
其中,漏端还包括第一存储单元结构或第二存储单元结构的漏极相连接的阻变单元。换言之,漏极与位线之间可以设置阻变单元,通过阻变单元将漏极与位线相连。如图4所示,第一存储单元结构511的漏极与阻变单元相连接,该阻变单元与一条位线BL1连接形成位于该阻变单元与该位线BL1之间的漏端;第二存储单元结构512的漏极与阻变单元相连接,该阻变单元与另一条位线BL2连接形成位于该阻变单元与该位线BL2之间的漏端。第二存储单元结构512的源极与第一存储单元结构511的源极连接形成公共端a,用于与源线SL1连接形成共同的源端。相应地,对于存储单元阵列520可以包括第一存储单元结构521和第二存储单元结构522以及两者的公共端b,对于存储单元阵列530可以包括第一存储单元结构531和第二存储单元结构532以及两者的公共端c,对于存储单元阵列540可以包括第一存储单元结构541和第二存储单元结构542以及两者的公共端d,此处不作赘述。
根据本公开的实施例,其中如图4所示,还包括:多条源线,沿第二方向相互平行排列,每条源线沿第一方向连接对应存储单元阵列中的公共端,其中,源线同时与位线及字线相互垂直。具体地,源线SL1、SL2、SL3和SL4沿第二方向相互平行排列,其中源线SL1沿第一方向连接存储单元阵列510的公共端a和存储单元阵列组402的相应存储单元阵列的公共端;源线SL2沿第一方向连接存储单元阵列520的公共端b和存储单元阵列组402的相应存储单元阵列的公共端;源线SL3沿第一方向连接存储单元阵列530的公共端c和存储单元阵列组402的相应存储单元阵列的公共端;源线SL4沿第一方向连接存储单元阵列540的公共端d和存储单元阵列组402的相应存储单元阵列的公共端。在本公开的实施例中,对应于第二方向垂直于第一方向,源线同时与位线及字线相互垂直。可见,在本公开采用深阱偏置存储单元结构的存储器阵列结构中,位线与字线相互平行,并同时与源线相互垂直,这完全颠覆了传统存储器阵列结构中字线与 源线相互平行,并同时与位线相互垂直的阵列组成设计,形成一个全新的存储器单元阵列组成结构,可以说是存储器技术领域中开创性的设计。
为更进一步体现上述存储器阵列结构的技术效果,参照图4和图5,本公开的又一个方面公开了一种电压偏置方法,应用于上述的存储器阵列结构,其中,如图6所示,电压偏置方法包括:
S610:对确定的存储器阵列结构中的存储单元结构的第一阱层施加偏置电压VB;本公开实施例中确定的存储单元结构对应于上述的具有深阱偏置结构的存储单元结构,其中的确定可以理解为“选中”,即选中该存储单元结构,如图4或图5所示的存储单元结构522。进一步地,其中,第一阱层210的第一阱电极410用于施加偏置电压VB,该偏置电压可以是一负电压,例如偏置电压VB=﹣0.8V,如图1A或图1B、图5所示。因此,该第一阱层210的设置为第一阱电极410提供的设置位置,第一阱电极410上施加的偏置电压VB不会对选中的存储单元结构之外的其它存储器组成结构造成影响,进一步提供高了电压偏置的针对性和精确性,同时也防止了对选中的存储单元结构之外的其它存储单元结构的晶体管产生大电压击穿的风险。
S620:对与存储单元结构的公共端对应的源线施加源端电压VS,同时对与存储单元结构的漏端对应的位线施加漏端电压VD,如图1A或图1B所示,该公共端可以为如图4所示存储单元结构522的公共端b,其对应的源线SL2可以施加如图5所示源端电压VS=-0.8V或大于该值的电压值,该漏端可以为如图4所示存储单元结构522的漏端,其对应的位线BL2可以施加如图5所示的漏端电压VD=1.7V。
其中,偏置电压VB的值为小于零的负值,源端电压VS和漏端电压VD的值为大于等于偏置电压VB的值,此处的电压值为区分正负值的数值,而非是正负值的绝对值,其中的负值还可以表示该对应负电压为反向电压,例如偏置电压VB=﹣0.8V为反向电压为0.8V的偏置电压。在源端电压VS和漏端电压VD的值为大于等于偏置电压VB的值时,例如源端电压VS=-0.6V,漏端电压VD=1.7V时,源端电压VS和漏端电压VD的值均大于偏置电压VB=-0.8V,使得对应源线和位线上的电压值均较低,也即未选中的存储单元结构(例如图5所示的存储单元结构512、532、542 等)源漏两端对应的电压也较低,既保证了选中的存储单元结构522不会出现PN结的正向导通问题,也防止了未选中或半选中的存储单元结构会因电压过大,造成的晶体管击穿问题,将对其他未选中的存储单元结构的影响降低到最小。
为对上述存储单元阵列结构的电压偏置方法作更清楚的解释,本公开作进一步的说明如下:
本公开针对深阱负压偏置结构所带来的未选中晶体管面临的大电压,导致影响其可靠性的问题,进一步提出了一种存储器阵列结构,如上图4和图5所示。在该存储器阵列结构种,将字线WL和位线BL平行设置,同时与源线SL垂直,在于上述的深阱负压偏置结构的存储单元结构,该存储器阵列结构可以有效避免半选中存储单元结构的CELL会经受的高电压问题。需要说明的是,图4和图5为相同的存储单元阵列结构的排列。
如图5所示,在对第二行第二列的存储单元结构进行Forming操作或reset操作,即对应于图4中的存储单元结构522进行操作。此时因为其源端的偏置电压为负电压VSL,所以对应字线WL2的栅端施加的栅电压VG比VSL大一个阈值电压,而未被选中的行(如字线WL1对应行),施加栅电压需要把第一行的存储单元结构521的阻变单元CELL关闭,所以其偏置电压可以选择等于VSL。此时位线BL2对应的漏端施加的电压为高压VD,被选中的存储单元结构522的阻变单元CELL的选通管打开,由于其阻变单元CELL的存在,会有相当可观的电压落在阻变单元CELL上,而落在选通管上的电压较VD减小很多,所以选通管的源漏端、栅漏端的电压都相对较小,不会导致管子击穿。
因此,与传统存储器阵列结构不同的是,本公开将位线BL与字线WL平行放置,位线BL施加的电压只会施加到字线WL选中的那一行的存储单元结构的阻变单元CELL上(对应于图5所示字线WL2),即图4中存储单元结构512、532和542的阻变单元CELL为半选中单元。此时,由于源端可以单独偏置电压,因此只要在需要被操作的存储单元结构522的阻变单元CELL所在的那一列(即存储单元阵列520)的源端(即图4所示的公共端b)施加较负的电压,以保证该阻变单元CELL的电压差要求。而对于不需要编程操作的单元,即图4中存储单元结构512、532和 542所在的存储单元阵列510、530和540,相应施加一个可以使未选中阻变单元CELL所在的选通管被关闭的负电压即可。在本公开的实施例中,在第一列(图4中存储单元阵列510)的源线SL1上可以施加和字线WL1相同的电压,所以晶体管的源漏端电压、栅漏电压较小,晶体管不会被高压击穿,可靠性得到保障。
在此种存储器阵列结构中,在发生forming操作的时,大电压可能,半选中单元(即图4中存储单元结构512、532和542)漏端与深阱偏置的负压之间,forming操作的时候漏端电压VD接高电压,半选中阻变单元CELL因为晶体管被关闭,其漏端电压等于VD。因为深阱偏置结构会在半选中阻变单元CELL上配置为负压,会导致其漏端与其第一阱层的PN结经受较大的反偏电压,但是晶体管对大电压比较敏感的是源漏电压,其次是栅源电压和栅漏电压,而PN结的反偏电压一般较大,不会导致晶体管的击穿。
参照图4,如图5所示,在本公开的实施例中,是对黑色填充的存储单元结构(即图4中存储单元结构522)进行forming操作或者reset操作,假设该需要的操作电压大于2.5V,此处假设要求落在其阻变单元CELL上的电压大约为2.5V才能完成forming操作,如果采用传统工艺(非深阱负压偏置),如此大的电压不容易传进存储单元阵列,同时传统阵列结构的WL和BL相互垂直的设计,会使得未选中存储单元的晶体管被大电压击穿,如图3所示,选中存储单元结构301的上方和下方为半选中的存储单元结构303、302,由于此时晶体管没有打开,使得高压完全偏置在了晶体管上,从而很可能导致其晶体管被击穿,而采用本公开的深阱负压偏置的存储单元结构和字线WL与位线BL相互平行的存储器阵列结构,使得阵列中所有晶体管的电压都在其可靠操作范围之内。如图5所示,选中单元为对应图4所示的存储单元结构522,该存储单元结构522采用上述深阱偏置结构,阱偏置为-0.8V,因此存储单元结构522的源线SL2也可以偏置为-0.8V,此时不会发生衬底层和源端的PN结正向导通的问题。选中存储单元结构522的字线WL2施加0.3V的电压,从而其栅源电压1.1V,使得晶体管可以完全被打开。为了实现forming操作,在该存储单元结构522的位线BL2端施加1.7V的电压,由于存储单元结构522的阻变单元CELL 的电阻值较大,从而电压基本落在存储单元结构522的两端,约为2.5V(即1.7V+0.8V=2.5V),完成forming操作。同时,晶体管任意两端的压差都比较低,最大限度的减小了可靠性问题。而针对未选中的存储单元结构,存在可靠性风险的半选中存储单元结构,例如如图5所示对应于图4中的存储单元结构512、522、532、542,为了不对其进行操作,可以在其源线端SL1和SL3、SL4施加一个相对较高的电压,例如可以选择为0.3V。可见,把该半选中的风险存储单元结构除了衬底层和源端电压较高,其他任意两端电压均较低。由于衬底层和源端形成的是存在深阱偏置结构的存储单元结构的PN结结构,此时PN结结构能承受的反向击穿电压远大于其被施加的操作电压,不会导致晶体管的PN结被击穿。
因此,本公开颠覆了传统存储器阵列结构的排列规则,重新设计了存储单元阵列的排列结构,通过重新组合WL、BL、SL的方向,使得该存储器阵列结构在执行forming操作、set操作和reset操作的时候,不需要操作的未选中阻变单元CELL对应的选通管任意两端的电压差值不会超过其击穿电压。该存储器阵列结构更加稳定可靠,体积和面积尺寸都得到了很好的控制,是存储器领域中颠覆性的方案设计,使得嵌入式存储器的应用和推广达到一个全新的高度,具有极高的商业价值和科研价值。
本公开提供了一种存储单元结构及存储器阵列结构、电压偏置方法,其中,存储单元结构包括:衬底层、阱层和晶体管,衬底层用于支撑存储单元结构;阱层嵌设于衬底层上,阱层的上表面与衬底层的上表面持平,晶体管设置于阱层上。本公开通过对存储单元结构进行了深阱偏置,使得存储单元的阱电压可以单独偏置为特定的电压,结合重新设计的存储单元阵列结构,将施加的编程电压大部分落在存储单元结构上,实现了对存储单元的编程电压的降低,同时可以避免选通晶体管因承受过大电压而被击穿,从而确保器件更好的可靠性以及存储单元阵列结构的面积效率更高。
以上所述的具体实施例,对本公开的目的、技术方案和有益效果进行了进一步详细说明,应理解的是,以上所述仅为本公开的具体实施例而已,并不用于限制本公开,凡在本公开的精神和原则之内,所做的任何修改、等同替换、改进等,均应包含在本公开的保护范围之内。
Claims (13)
- 一种存储单元结构,其中,包括:衬底层,用于为所述存储单元结构提供支撑;阱层,嵌设于所述衬底层,所述阱层的上表面与所述衬底层的上表面持平;以及晶体管,设置于所述阱层内部及表面。
- 根据权利要求1所述的存储单元结构,其中,所述阱层包括:第一阱层,嵌设于所述衬底层,所述第一阱层的上表面与所述衬底层的上表面持平;第二阱层,设置于所述第一阱层和所述衬底层之间,所述第二阱层的上表面与所述衬底层的上表面持平,用于间隔所述第一阱层和所述衬底层;其中,所述晶体管设置于所述第一阱层的内部及表面。
- 根据权利要求2所述的存储单元结构,其中,所述衬底层是非P型或N型掺杂的结构层;所述第一阱层是P型掺杂结构层,用于形成P型阱层;所述第二阱层是N型掺杂结构层,用于形成N型阱层,作为所述衬底层与所述P型阱层之间的隔离。
- 根据权利要求2所述的存储单元结构,其中,所述晶体管包括:栅极,设置于所述第一阱层的上表面;源极,嵌设于所述第一阱层,所述源极上表面暴露于所述第一阱层;漏极,嵌设于所述第一阱层,所述漏极上表面暴露于所述第一阱层。
- 根据权利要求4所述的存储单元结构,其中,所述漏极与所述源极之间间隔一定距离;所述栅极设置于所述漏极与所述源极之间的所述第一阱层的上表面。
- 根据权利要求5所述的存储单元结构,其中,存储单元结构还包括:第一阻变单元,位于所述漏极或所述源极的上方;第一互联层,包括多个互联子层,所述第一阻变单元与所述漏极或源极的上表面接触,所述多个互联子层位于所述第一阻变单元的上方;第一连接线,沿第一互联层、第一阻变单元的设置方向设置,用于将所述第一互联层、第一阻变单元与所述源极或漏极连接。
- 根据权利要求5所述的存储单元结构,其中,存储单元结构还包括:第二阻变单元,位于所述漏极或所述源极的上方;第二互联层,包括多个互联子层,所述多个互联子层中的至少一个互联子层位于所述第二阻变单元和所述漏极或源极之间,剩余互联子层位于所述第二阻变单元的上方;第二连接线,沿第二互联层、第二阻变单元的设置方向设置,用于将所述第二阻变单元、第二互联层与所述源极或漏极连接。
- 根据权利要求2所述的存储单元结构,其中,还包括:第一阱电极,嵌设于所述第一阱层,所述第一阱电极的上表面暴露于所述第一阱层;第二阱电极,嵌设于所述第二阱层,所述第二阱电极的上表面暴露于所述第二阱层。
- 一种存储器阵列结构,其中,包括:多个存储单元阵列组,在第一方向上相互平行排列,每个存储单元阵列组包括多个存储单元阵列,沿第二方向相互平行排列;每个存储单元阵列包括多个权利要求1-8中任一项所述的存储单元结构;多条位线,沿第一方向相互平行排列,至少两条位线沿第二方向分别连接所述多个存储单元阵列的两端;以及多条字线,沿第一方向相互平行排列,与所述多条位线相互平行,每条字线沿第二方向连接所述多个存储单元阵列中对应位置的存储单元结构的栅极。
- 根据权利要求9所述的存储器阵列结构,其中,所述第一方向垂直于所述第二方向。
- 根据权利要求9所述的存储器阵列结构,其中,所述存储单元阵列至少包括:第一存储单元结构,其漏端与一条位线连接;第二存储单元结构,其漏端与另一条位线连接,源极与所述第一存储 单元结构的源极连接形成公共端;其中,所述漏端还包括与所述第一存储单元结构或第二存储单元结构的漏极相连接的阻变单元。
- 根据权利要求11所述的存储器阵列结构,其中,还包括:多条源线,沿第二方向相互平行排列,每条源线沿第一方向连接对应存储单元阵列中的公共端;其中,所述源线同时与位线及字线相互垂直。
- 一种电压偏置方法,应用于权利要求9-12中任一项所述的存储器阵列结构,其中,所述电压偏置方法包括:对确定的所述存储器阵列结构中的存储单元结构的第一阱层施加偏置电压;对与所述存储单元结构的公共端对应的源线施加源端电压,同时对与所述存储单元结构的漏端对应的位线施加漏端电压;其中,所述偏置电压的值为小于零的负值,所述源端电压和漏端电压的值为大于等于偏置电压的值。
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