WO2021207916A1

WO2021207916A1 - Memory cell structure, memory array structure, and voltage bias method

Info

Publication number: WO2021207916A1
Application number: PCT/CN2020/084621
Authority: WO
Inventors: 吕杭炳; 杨建国; 许晓欣; 刘明
Original assignee: 中国科学院微电子研究所
Priority date: 2020-04-14
Filing date: 2020-04-14
Publication date: 2021-10-21
Also published as: US20230197152A1

Abstract

The present disclosure provides a memory cell structure, a memory array structure, and a voltage bias method. The memory cell structure comprises: a substrate layer, a well layer, and a transistor. The substrate layer is used for supporting the memory cell structure; the well layer is embedded in the substrate layer, the upper surface of the well layer is flush with the upper surface of the substrate layer, and the transistor is arranged on the well layer. In the present disclosure, deep well bias is performed on the memory cell structure so that a trap voltage of a memory cell can be independently biased into a specific voltage; in conjunction with a redesigned memory cell array structure, most of an applied programming voltage falls on the memory cell structure, thereby reducing the programming voltage of the memory cell, avoiding a gating transistor from being broken down due to an overhigh voltage, and ensuring better reliability of a device and higher area efficiency of the memory cell array structure.

Description

Memory cell structure, memory array structure and voltage bias method

Technical field

The present disclosure relates to the field of memory technology, and in particular to a memory cell structure, a memory array structure, and a voltage bias method.

Background technique

With the development of semiconductor manufacturing technology, traditional embedded memory (mainly flash memory) is facing technical bottlenecks such as a sharp increase in process complexity, rising costs, and performance degradation below the 28nm process node. Therefore, a new type of embedded memory is urgently needed. technology. In the prior art, new types of embedded memory include resistive random access memory (RRAM), phase change memory (PCRAM), magnetic memory (MRAM) and other types, which have the advantages of compatibility with CMOS technology, strong miniaturization, and low cost. In recent years, It has received extensive research and attention.

In the prior art, due to process and material limitations, although the programming voltage of a new type of embedded memory is lower than that of a traditional embedded memory, it still cannot be reduced to the level of the core voltage of CMOS transistors at advanced process nodes (28nm and below). Because in the field of embedded applications, most of the new memory uses the 1T1R structure, that is, a strobe transistor is equipped with a memory cell. If the programming voltage of the memory cell cannot be reduced, a high withstand voltage strobe tube is required, which undoubtedly increases The area of the memory cell leads to an increase in cost, and the area efficiency of the array structure is low.

Summary of the invention

One aspect of the present disclosure provides a memory cell structure, which includes: a substrate layer, a well layer and a transistor, the substrate layer is used to provide support for the memory cell structure; the well layer is embedded in the substrate layer, and the upper surface of the well layer is connected to The upper surface of the substrate layer is flat, and the transistors are arranged inside and on the surface of the well layer.

According to an embodiment of the present disclosure, wherein the well layer includes: a first well layer and a second well layer, the first well layer is embedded in the substrate layer, and the upper surface of the first well layer is level with the upper surface of the substrate layer; second The well layer is arranged between the first well layer and the substrate layer, and the upper surface of the second well layer is flat with the upper surface of the substrate layer for separating the first well layer and the substrate layer; wherein, the transistor is arranged on the first well layer. Internal and surface.

According to an embodiment of the present disclosure, wherein the substrate layer is a non-P-type or N-type doped structure layer; the first well layer is a P-type doped structure layer for forming a P-type well layer; and the second well layer is an N-type The doped structure layer is used to form an N-type well layer as an isolation between the substrate layer and the P-type well layer.

According to an embodiment of the present disclosure, the transistor includes a gate, a source, and a drain, the gate is disposed on the upper surface of the first well layer; the source is embedded in the first well layer, and the upper surface of the source is exposed to The first well layer; the drain is embedded in the first well layer, and the upper surface of the drain is exposed to the first well layer.

According to an embodiment of the present disclosure, wherein the drain electrode and the source electrode are separated by a certain distance; the gate electrode is arranged on the upper surface of the first well layer between the drain electrode and the source electrode.

According to an embodiment of the present disclosure, the memory cell structure further includes: a first resistive switching unit, a first interconnection layer, and a first connecting line, the first resistive switching unit is located above the drain or the source; the first interconnection layer includes A plurality of interconnection sub-layers, the first resistive switching unit is in contact with the upper surface of the drain or source electrode, and the plurality of interconnecting sub-layers are located above the first resistive switching unit; the first connection line is along the first interconnection layer and the first resistive switching The arrangement direction of the unit is set to connect the first interconnection layer and the first resistive switching unit with the source electrode or the drain electrode.

According to an embodiment of the present disclosure, the memory cell structure further includes: a second resistive switching unit, a second interconnection layer, and a second connecting line, the second resistive switching unit is located above the drain or the source; the second interconnection layer includes A plurality of interconnection sublayers, at least one interconnection sublayer of the plurality of interconnection sublayers is located between the second resistive switching unit and the drain or source, and the remaining interconnection sublayers are located above the second resistive switching unit; the second connecting line It is arranged along the arrangement direction of the second interconnection layer and the second resistance switching unit, and is used to connect the second resistance switching unit and the second interconnection layer with the source electrode or the drain electrode. According to an embodiment of the present disclosure, the memory cell structure further includes: a first well electrode and a second well electrode, the first well electrode is embedded in the first well layer, and the upper surface of the first well electrode is exposed to the first well layer ; The second well electrode is embedded in the second well layer, and the upper surface of the second well electrode is exposed to the second well layer.

Another aspect of the present disclosure provides a memory array structure, which includes: a plurality of memory cell array groups, a plurality of bit lines and a plurality of word lines, the plurality of memory cell array groups are arranged parallel to each other in a first direction, Each memory cell array group includes: a plurality of memory cell arrays arranged in parallel to each other along the second direction, the memory cell array includes a plurality of the above-mentioned memory cell structures; a plurality of bit lines are arranged in parallel to each other along the first direction, and at least two bit lines are arranged in parallel to each other. The lines respectively connect the two ends of the multiple memory cell arrays along the second direction; and the multiple word lines are arranged parallel to each other along the first direction, and are parallel to the multiple bit lines, and each word line connects multiple memory cells along the second direction The gate of the memory cell structure at the corresponding position in the array.

According to an embodiment of the present disclosure, wherein the first direction is perpendicular to the second direction.

According to an embodiment of the present disclosure, the memory cell array includes at least: a first memory cell structure and a second memory cell structure, the drain terminal of the first memory cell structure is connected to a bit line; the drain terminal of the second memory cell structure is connected to Another bit line is connected, and the source is connected with the source of the first memory cell structure to form a common terminal; wherein the drain terminal further includes a resistive switching unit connected to the drain of the first memory cell structure or the second memory cell structure.

According to an embodiment of the present disclosure, it further includes: a plurality of source lines arranged in parallel to each other along the second direction, and each source line is connected to the common terminal in the corresponding memory cell array along the first direction; The line and the word line are perpendicular to each other.

Another aspect of the present disclosure provides a voltage bias method applied to the above-mentioned memory array structure, wherein the voltage bias method includes: applying a bias to the first well layer of the memory cell structure in the determined memory array structure Voltage; apply a source terminal voltage to the source line corresponding to the common terminal of the memory cell structure, while applying a drain terminal voltage to the bit line corresponding to the drain terminal of the memory cell structure; wherein the value of the bias voltage is a negative value less than zero , The value of the source terminal voltage and the drain terminal voltage is greater than or equal to the value of the bias voltage.

Description of the drawings

1A is a schematic cross-sectional view of the composition of a memory cell structure in an embodiment of the present disclosure;

1B is a schematic cross-sectional view of the composition of a memory cell structure in another embodiment of the present disclosure;

FIG. 2 is a schematic diagram of a corresponding equivalent circuit corresponding to the memory cell structure shown in FIG. 1A or FIG. 1B in an embodiment of the present disclosure;

FIG. 3 is a schematic diagram of the composition of a memory cell array structure in the prior art;

4 is a schematic diagram of the composition of a memory cell array structure in an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of voltage bias corresponding to the memory cell array structure shown in FIG. 4 in an embodiment of the present disclosure;

FIG. 6 is a schematic flowchart of a voltage bias method for a memory cell array structure in an embodiment of the present disclosure.

Detailed ways

In order to make the objectives, technical solutions, and advantages of the present disclosure clearer, the following further describes the present disclosure in detail in conjunction with specific embodiments and with reference to the accompanying drawings.

In order to solve the technical problem that the programming voltage of the new embedded memory cannot be effectively reduced under the premise of controlling the area size and cost of the memory under the existing advanced process nodes, resulting in poor reliability of the new embedded memory structure, the present disclosure provides a memory Cell structure and memory array structure, voltage bias method.

In order to make a clear description of the technical solutions of the present disclosure, the memory of the present disclosure may be a new type of embedded memory, such as a resistive random access memory (RRAM), and further may be a resistive random access memory with a 1T1R basic structural unit. However, those skilled in the art should understand that it is not a limitation on the protection scope of the claims of the present disclosure.

The programming of the new embedded memory may include multiple operations. For example, the programming of the resistive random access memory (RRAM) is mainly divided into three types: forming operation, set operation, and reset operation.

During the forming operation, the resistive switching unit CELL is programmed from the initial ultra-high resistance state (above MΩ) to a relatively low resistance state (approximately several hundred KΩ). In this case, a relatively high resistance is applied to the drain terminal corresponding to the bit line BL. For a large programming voltage, a gate voltage VG is applied to the gate terminal corresponding to the word line WL to turn on the gate transistor (that is, the gate tube, which is a type of transistor), and the source terminal corresponding to the source line SL is connected to a low level. At this time, because the initial value of the resistance is large, most of the voltage falls on the resistive switching unit CELL, so that even if the voltage applied to the drain terminal is large, the voltage actually falling on the gate transistor will be relatively small. , And will not affect the reliability of the transistor.

During the set operation, the source terminal is connected to a high level and the drain terminal is connected to a low level. Although the voltage required for the set operation is less than the voltage required for the forming operation, the resistance of the resistive switching unit CELL is small, and the gate tube has a substrate. Bias effect, the voltage applied to the source terminal is relatively large. If a reasonable voltage bias method is not adopted, the voltage applied to the transistor will exceed its maximum limit, making the gate transistor easy to be broken down, resulting in reliable Sexual issues.

During the reset operation, the set voltage is applied to the drain terminal, and the source terminal is connected to a low level. Because the memory cell is in a low resistance state, a large part of the voltage will fall on the strobe tube, so the strobe tube will also Face the same reliability problem.

One aspect of the present disclosure provides a memory cell structure, which, as shown in FIG. 1A and FIG. 1B, includes a substrate layer 100, a well layer 200 and a transistor, and the substrate layer 100 is used to provide support for the memory cell structure.

The well layer 200 is embedded in the substrate layer 100. The upper surface of the well layer 200 is level with the upper surface of the substrate layer 100. The substrate layer 100 is provided with a recess recessed from its upper surface. The well layer 200 can pass through the chemical vapor phase. The deposition process is formed in the groove.

The transistor is arranged inside and on the surface of the well layer 200. The transistor may be a strobe tube, which is used to control data reading and writing and signal output in the memory cell, and to better isolate the interference of adjacent memory cells, and is more compatible with the CMOS process.

According to an embodiment of the present disclosure, as shown in FIGS. 1A and 1B, the well layer 200 includes: a first well layer 210 and a second well layer 220, the first well layer 210 is embedded in the substrate layer 100, and the first well layer The upper surface of 210 is level with the upper surface of the substrate layer 100 and is used to form a transistor structure, wherein the transistor is disposed inside and on the surface of the first well layer. The second well layer 220 is disposed between the first well layer 210 and the substrate layer 100, and the upper surface of the second well layer 220 is level with the upper surface of the substrate layer 100 to separate the first well layer 210 and the substrate layer 100.

In other words, the second well layer 220 is formed on the inner surface of the groove of the substrate layer 100. Specifically, the second well layer 220 may be formed on the inner surface of the groove by a chemical vapor deposition process, and the inner surface of the groove direct contact. The first well layer 210 is formed on the second well layer 220, that is, the outer surface of the second well layer 220 and the inner surface of the first well layer 210 (that is, the side surface and the lower surface except the upper surface of the first well layer 210). Surface) to make contact. Therefore, the second well layer 220 may form an isolation layer between the first well layer 210 and the substrate layer 100 to prevent the first well layer 210 from contacting the substrate layer.

Further, the substrate layer 100 may be a non-P-type or N-type doped structure layer, and the first well layer 210 may be a P-type doped structure layer for forming a P-type well layer and forming a transistor accordingly; The layer 220 may be an N-type doped structure layer, used to form an N-type well layer, and used to form an isolation between the substrate layer 100 and the P-type well layer. Therefore, it constitutes the deep well bias structure of the present disclosure. The first well layer 210 as the P-type well layer can be biased to the negative voltage VB, and the second well layer 220 as the N-type well layer can be biased to the power supply voltage. VCC, the substrate layer 100 can be biased to the ground Vsub, as shown in FIG. 2, so that when a negative voltage is applied to the drain terminal and the source terminal, the problem of PN forward conduction does not occur.

Therefore, the present disclosure adopts the above-mentioned deep-well bias technology, selects deep-well process transistors, and biases the well potential in a negative voltage state, so that a negative voltage can be connected to the source or drain of the transistor, thereby reducing the application of the drain or The voltage value of the source terminal only needs to ensure that the voltage difference falling on the memory cell meets the requirements. At the same time, it is ensured that the voltage difference between different terminals of the transistor does not exceed its breakdown voltage, and the breakdown of the resistive switching unit CELL of the transistor is prevented from causing reliability problems.

According to an embodiment of the present disclosure, as shown in FIGS. 1A, 1B, and 2, the transistor includes: a gate 310, a source 320, and a drain 330. The gate 310 is disposed on the upper surface of the first well layer 210, and The corresponding gate terminal is formed in connection with the word line WL, and the gate voltage VG is applied to turn on the transistor, as shown in FIG. 2.

The source electrode 320 is embedded in the first well layer 210, and the upper surface of the source electrode 320 is exposed to the first well layer 210. The upper surface of the source electrode 320 may be level with the upper surface of the first well layer 210 for contact with the source line SL. Connect to form the corresponding source terminal, and apply the source terminal voltage VS, as shown in Figure 2.

The drain 330 is embedded in the first well layer 210, and the upper surface of the drain 330 is exposed to the first well layer 210. The upper surface of the drain 330 may be level with the upper surface of the first well layer 210 for connection with the bit line BL The corresponding drain terminal is formed, and the drain terminal voltage VD is applied, as shown in FIG. 2.

Wherein, the gate 310, the source 320, the drain 330 and the first well layer 210 form a transistor of the memory cell structure. It should be noted that there may be multiple transistors disposed on the first well layer 210, and a transistor array is formed on the first well layer 210. Specifically, a gate may be correspondingly provided on the upper surface of the first well layer 210 on the other side of the source 320, and the gate and the above-mentioned transistor structure share the source 320. Correspondingly, multiple other gates can be provided on the upper surface of the first well layer 210 to form multiple transistor structures that can be turned on to ensure that the size and area of the memory cell structure are smaller and the transistor integration level is higher.

According to an embodiment of the present disclosure, as shown in FIG. 1A, FIG. 1B and FIG. 2, the drain 330 and the source 320 are separated by a certain distance to prevent the contact short circuit of the structure; the gate 310 is provided on the drain 330 and The upper surface of the first well layer 210 between the source electrodes 320. In other words, a certain thickness of the first well layer 210 is spaced between the drain 330 and the source 320, and a corresponding portion of the first well layer 210 is provided with a gate 310 on the upper surface, and one end of the gate 310 corresponds to the drain 330 , The other end corresponds to the source 320, as shown in FIG. 1A and FIG. 1B.

According to an embodiment of the present disclosure, as shown in FIG. 1A, the memory cell structure further includes: a first resistive switching unit CELL1, a first interconnection layer 340, and a first connecting line L1, and the first resistive switching unit CELL1 is located at the drain 330 Or above the source 320; the first interconnection layer 340 includes a plurality of interconnection sublayers, the first resistive switching unit CELL1 is in contact with the upper surface of the drain 330 or the source 320, and the plurality of interconnection sublayers are located in the first resistive switching unit CELL1 Above; the first connecting line L1 is arranged along the first interconnection layer 340, the first resistive switching unit CELL1 arrangement direction, for connecting the first interconnection layer 340, the first resistive switching unit CELL1 and the source 320 or the drain 330 .

Specifically, the first interconnection layer 340 may include multiple interconnection sublayers, and each interconnection sublayer may be a metal layer for electrical connection between the constituent structures of the memory cell structure. For example, the interconnection sublayer may form bit lines, Word line or source line, etc. The first resistive switching unit CELL1 is in contact with the upper surface of the drain 330 or the source 320, which can be understood as being directly connected to the drain 330 or the source 320, and there is no longer any connection between the two except the first connection line L1 The structure is connected. Therefore, the first interconnection layer 340 needs to be disposed above the first resistive switching unit CELL1. As shown in FIG. 1A, the multiple interconnection sublayers include at least a first interconnection sublayer 341, a second interconnection sublayer 342, and a third interconnection sublayer 343 that are arranged at intervals from bottom to top. Below is the corresponding first resistive switching unit CELL1, which is connected to the drain 330. In addition, the first connecting line L1 sequentially connects the first resistive switching unit CELL1, the first interconnection sublayer 341, the second interconnection sublayer 342, and the third interconnection sublayer 343 from the vertical direction. Among them, the drain 330 and The first resistive switching units CELL1 can also be connected by a first connecting line L1. Therefore, the memory cell structure of the present disclosure can form a 1T1R type structure with resistive switching cells.

According to another embodiment of the present disclosure, as shown in FIG. 1B, the memory cell structure further includes: a second resistive switching unit CELL2, a second interconnection layer 350, and a second connecting line L2, and the second resistive switching unit CELL2 is located at the drain Above the electrode 330 or the source electrode 320; the second interconnection layer 350 includes a plurality of interconnection sublayers, and at least one interconnection sublayer of the plurality of interconnection sublayers is located between the second resistive switching unit CELL2 and the drain electrode 330 or the source electrode 320 , The remaining interconnection sublayer is located above the second resistive switching unit CELL2; the second connecting line L2 is arranged along the arrangement direction of the second interconnection layer 350 and the second resistive switching unit CELL2, and is used to connect the second resistive switching unit CELL2 and the second resistive switching unit CELL2. The interconnection layer 350 is connected to the source 320 or the drain 330.

Specifically, the second interconnection layer 340 may include multiple interconnection sublayers, and each interconnection sublayer may be a metal layer for electrical connection between the constituent structures of the memory cell structure. For example, the interconnection sublayer may form bit lines, Word line or source line, etc. As shown in FIG. 1B, the multiple interconnection sublayers include at least a first interconnection sublayer 351, a second interconnection sublayer 352, a third interconnection sublayer 353, and a fourth interconnection sublayer 354 that are arranged at intervals from bottom to top. At least the first interconnection sublayer 351 and the second interconnection sublayer 352 are located between the second resistive switching unit CELL2 and the drain 330 or the source 320, and the remaining interconnection sublayers are located between the third interconnection sublayer 353 and the fourth interconnection sublayer 354 Above the second resistance switching unit CELL2, that is, below the third interconnection sublayer 353 and above the second interconnection sublayer 352, is a corresponding second resistance switching unit CELL2, which is no longer directly connected to the drain 330. In addition, the second connecting line L2 sequentially connects the second interconnection sublayer 351, the second interconnection sublayer 352, the second resistive switching unit CELL2, the third interconnection sublayer 353, and the fourth interconnection sublayer 354 from the vertical direction. . Therefore, the memory cell structure of the present disclosure can form a 1T1R type structure with resistive switching cells.

It can be seen that the resistive switching cell CELL of the memory cell structure of the present disclosure is located between the drain 330 or the source 320 and the bit line and the source line to form a drain terminal or a source terminal. In addition, the resistive switching cell CELL can meet the design requirements of different memory cell structures, the preparation requirements of different preparation processes, and the design of different positions relative to the source or drain, which is beneficial to the preparation of 1T1R-type memory cell structure devices.

It should be noted that, in the embodiments of the present disclosure, “first” and “second” are only qualifiers used to make the solution more clear, not used to refer to the two as different storage. The cell structure, for example, the first resistive switching unit CELL1 and the second resistive switching unit CELL2 may be the same type of resistive switching unit, or different types of resistive switching units, the type of which is affected by the other constituent structures of the corresponding memory cell structure ( For example, transistor design) depends on the difference.

According to an embodiment of the present disclosure, as shown in FIGS. 1A, 1B, and 2, the memory cell structure further includes: a first well electrode 410 and a second well electrode 420, the first well electrode 410 is embedded in the first well layer 210. The upper surface of the first well electrode 410 is exposed to the first well layer 210, and the upper surface of the first well electrode 410 may be level with the upper surface of the first well layer 210. The composition structure of the first well electrode 410 and the transistor has a certain distance, and the upper surface of the first well electrode 410 is also level with the upper surface of the substrate layer 100 at the same time.

The second well electrode 420 is embedded in the second well layer 220, the upper surface of the second well electrode 420 is exposed to the second well layer 220, and the upper surface of the second well electrode 420 may be level with the upper surface of the second well layer 220, At the same time, it is flush with the upper surface of the substrate layer 100.

Therefore, the present disclosure adopts a deep-well bias process, as shown in FIGS. 1A, 1B, and 2 to form transistors (such as NMOS transistors) inside and on the surface of the first well layer 210 of the deep-well structure, so that the second A well layer 210 is provided with a separate bias voltage, that is, a negative voltage VB is applied, so that a negative voltage can be applied to the drain terminal or the source terminal, and the negative voltage VB is more negative than the negative voltage applied to the drain terminal or the source terminal. In this case, there will be no PN forward conduction problem. Specifically, referring to FIG. 1A, FIG. 1B and FIG. 2, according to the three basic operation methods of the above-mentioned storage unit structure: initialization (forming) operation, setting (set) operation, and setting operation (reset), the present disclosure is further described as follows:

Forming operation process: The direction of forming operation is from the sink to the source. As shown in FIG. 1A, FIG. 1B and FIG. 2, the first well layer 210 is biased to a negative voltage, that is, a negative voltage VB, and the source terminal is biased to a negative voltage VS, in order to prevent the substrate layer 100 and the PN of the source terminal from being turned on , It is necessary to ensure that the negative voltage VB and the negative voltage VS are more negative than the latter. At this time, the voltage applied to the drain terminal is VD, and the voltage falling on the resistive switching unit CELL is VD-VS. Since VS is negative, this bias method reduces the voltage applied on the drain terminal to the size of the source terminal voltage, that is, the voltage VS. In other words, this directly reduces the difficulty of the peripheral circuit that needs to transmit the high voltage to the drain terminal, and at the same time ensures the need for the programming voltage on the resistive switching cell CELL. Moreover, the voltage difference between the ports of the strobe tube is within its reliability voltage (generally transistors can meet the redundant voltage of 1 times its normal voltage).

Set operation process: The direction of set operation is from source to drain. As shown in FIGS. 1A, 1B, and 2, the first well layer 210 is biased to a negative voltage, that is, a negative voltage VB, and the drain terminal is biased to a negative voltage VD. At this time, in order to prevent the substrate layer 100 and the drain terminal from PN forward conduction It is necessary to ensure that the voltage VB and the voltage VD are more negative than the latter. At this time, the voltage applied by the source terminal is VS, the voltage VD falling on the resistive switching unit CELL=VG-Vth, and Vth is the threshold voltage of the resistive switching unit CELL. Since VD is a negative value, this bias method reduces the voltage VG applied to the gate terminal to the magnitude of the drain terminal voltage VD, which directly reduces the difficulty of the peripheral circuit that needs to transmit high voltage to the gate of the transistor (that is, Gate) , Which reduces the risk of grid breakdown by high voltage. At the same time, the requirement of the programming voltage on the resistive switching cell CELL is ensured. Moreover, the voltage difference between the ports of the strobe tube is within its reliability voltage (generally transistors can meet the redundant voltage of 1 times its normal voltage).

Reset operation process: Since the reset operation and forming operation are in the same direction and the required voltage is also the same, the reset operation method can be the same as that of forming, so I won’t repeat it here.

It should be further explained that, based on the traditional memory structure, such as the non-NOR memory structure shown in FIG. 3, the word line w1 and the source line sl of the general memory cell array are parallel and perpendicular to the bit line bl at the same time. However, when the memory cell structure adopts the memory cell structure of the deep-well negative voltage bias structure described in the present disclosure, the array structure has the problem that the gate tube of the semi-selected cell is subjected to a large voltage, which may cause breakdown. In the embodiment of the present disclosure, the semi-selected cell may be the resistive switching cell CELL of the memory cell structure 302 and the resistive switching cell CELL of the memory cell structure 303 as shown in FIG. 3, and the selected cell is the resistive switching cell of the memory cell structure 301. CELL, after the memory cell structure 301 is selected, one of the word lines w1, bit lines bl, and source lines sl of the unselected

memory cell structures

302 and 303 will also experience the selected voltage of the selected cell 301.

As shown in FIG. 3, it is assumed that a Forming operation or a reset operation is to be performed on the storage unit structure 301 in the second row and the second column (the set operation is similar and will not be repeated), that is, the selected cell 301. At this time, because the source terminal of the corresponding source line sl1 is biased to a negative voltage vs1, the voltage vg1 applied to the gate terminal of the corresponding word line wl2 is larger than the source terminal negative voltage vs1 by a threshold voltage, and for the unselected

memory cell structure

302, 303, such as the gate terminal of the word line wl1 corresponding to the memory cell structure 303, the applied gate terminal voltage vg3 needs to turn off the resistive switching cell CELL of the memory cell structure 303 in the first row, so it corresponds to the bias of the source line sl1 The voltage can be selected to be equal to vs1, and the voltage applied to the drain terminal of the corresponding bit line bl2 is high voltage vd. When the resistive switching cell CELL of the memory cell structure 301 is selected, the gate corresponding to 301 is turned on, due to the existence of the resistive switching cell CELL , There will be a considerable voltage falling on the resistive switching unit CELL, and the voltage on the transistor is much smaller than its drain voltage vd. Therefore, the voltage at the source and drain terminals and the gate and drain terminals of the transistor are relatively small, which will not cause the transistor Was broken down. However, the adjacent

memory cell structures

302 and 303 in the same column as the selected memory cell structure 301 will have the drain terminal voltage equal to the aforementioned voltage vd because their transistors are not turned on. Because this voltage is relatively large, and in order to meet the voltage requirements of the selected memory cell structure 301, the corresponding source line sl1 will be applied as a relatively negative source terminal voltage, so that the memory cell structure 303 in the first row and the memory cell structure 303 in the second row The voltages at the source and drain terminals and the gate and drain terminals of the transistors in the cell structure 302 that are not turned on are very high, which may cause the breakdown of the transistors.

In order to solve the above-mentioned reliability problem of the memory cell array structure caused by the deep well bias structure adopted in the present disclosure, another aspect of the present disclosure provides a memory array structure, which, as shown in FIG. 4, includes: A plurality of memory cell array groups, a plurality of bit lines and a plurality of word lines, and the plurality of memory cell array groups are arranged parallel to each other in the first direction. As shown in FIG. 4, it is a partial structure of a memory array structure, specifically a memory cell array structure with four rows and four columns, which includes two memory

cell array groups

401 and 402. The memory cell array group 402 is relative to the memory cell The array group 401 is arranged in parallel in the first direction. Wherein, each memory cell array group includes a plurality of memory cell arrays arranged in parallel to each other along the second direction, and each memory cell array includes a plurality of the foregoing memory cell structures. As shown in FIG. 4, the memory cell array group 401 includes four

memory cell arrays

510, 520, 530, and 540. The

memory cell arrays

510, 520, 530, and 540 are arranged parallel to each other in the second direction, forming one or two rows. Column of memory cell array structure.

The plurality of bit lines are arranged in parallel to each other along the first direction, and at least two bit lines are respectively connected to the two ends of the plurality of memory cell arrays along the second direction. As shown in FIG. 4, corresponding to the memory cell array group 401, there may be bit lines BL1 and BL2, where BL1 and BL2 are arranged parallel to each other along the first direction, and BL1 is connected to the

memory cell arrays

510, 520, 530 along the second direction. The upper ends of and 540 are connected to the drain ends of the

memory cell structures

511, 521, 531, and 541; BL2 is connected to the lower ends of the

memory cell arrays

510, 520, 530, and 540 in the second direction, that is, connected to the memory cell structures 512, Drain terminals of 522, 532, and 542. Correspondingly, corresponding to the memory cell array group 402, there may be bit lines BL3 and BL4, and the connection relationship of the bit lines BL3 and BL4 can be referred to the above-mentioned BL1 and BL2, which will not be repeated here. It should be noted that the bit lines BL1, BL2, BL3, and BL4 are arranged parallel to each other in the first direction.

A plurality of word lines are arranged parallel to each other along the first direction, and are parallel to each other with the plurality of bit lines, and each word line is connected to the gates of the memory cell structures at corresponding positions in the plurality of memory cell arrays along the second direction. As shown in FIG. 4, corresponding to the memory cell array group 401, there may be word lines WL1 and WL2, where WL1 and WL2 are arranged parallel to each other along the first direction, and WL1 is connected to the

memory cell arrays

510, 520, 530 along the second direction. The gates (ie, gate ends) of the

memory cell structures

511, 521, 531, and 541 at the corresponding positions of and 540, WL2 is connected to the memory cell structure 512 at the corresponding positions of the

memory cell arrays

510, 520, 530, and 540 along the second direction , 522, 532 and 542 gates. In the embodiment of the present disclosure, the memory cell structure 511 of the memory cell array 510 is located in the first row and first column of the memory cell array group 401. In the memory cell array group 401, the memory cell structure at the corresponding position is the memory cell array. The memory cell structure 521 of the cell array 520, the memory cell structure 531 of the memory cell array 530, and the memory cell structure 541 of the memory cell array 540. Correspondingly, corresponding to the memory cell array group 402, there may be word lines WL3 and WL4, and the connection relationship of the word lines WL3 and WL4 can refer to the above-mentioned WL1 and WL2, which will not be repeated here. It should be noted that the word lines WL1, WL2, WL3, and WL4 are arranged parallel to each other in the first direction.

Therefore, in the memory array structure of the present disclosure, the bit lines BL1, BL2, BL3, and BL4 and the word lines WL1, WL2, WL3, and WL4 are arranged parallel to each other in the first direction, that is, the bit lines and the word lines are arranged parallel to each other.

According to an embodiment of the present disclosure, as shown in FIG. 4, the first direction is perpendicular to the second direction.

According to an embodiment of the present disclosure, as shown in FIG. 4, the memory cell array includes at least: a first memory cell structure and a second memory cell structure, the drain terminal of the first memory cell structure is connected to a bit line; the second memory cell The drain of the structure is connected with another bit line, and the source is connected with the source of the first memory cell structure to form a common end. Specifically, the memory cell array 510 may at least include a first memory cell structure 511 and a second memory cell structure 512, where the "first" and "second" are only used to make the solution clearer. The term is not used to indicate that the first memory cell structure 511 and the second memory cell structure 512 are different memory cell structures. In other words, the first memory cell structure 511 and the second memory cell structure 512 may be the same type of deep well The bias structure may also be a different type of deep well bias structure, and its type is determined by the design of the first well layer 210, the second well layer 220, and the transistor.

Wherein, the drain terminal also includes a resistive switching unit connected to the drain of the first memory cell structure or the second memory cell structure. In other words, a resistive switching unit can be arranged between the drain and the bit line, and the drain is connected to the bit line through the resistive switching unit. As shown in FIG. 4, the drain of the first memory cell structure 511 is connected to the resistive switching unit, and the resistive switching unit is connected to a bit line BL1 to form a drain terminal between the resistive switching unit and the bit line BL1; The drains of the two memory cell structures 512 are connected to the resistive switching unit, and the resistive switching unit is connected to another bit line BL2 to form a drain between the resistive switching unit and the bit line BL2. The source of the second memory cell structure 512 is connected to the source of the first memory cell structure 511 to form a common terminal a, which is used to connect with the source line SL1 to form a common source terminal. Correspondingly, the memory cell array 520 may include the first memory cell structure 521 and the second memory cell structure 522 and the common end b of the two, and the memory cell array 530 may include the first memory cell structure 531 and the second memory cell structure. 532 and the common terminal c of the two, the memory cell array 540 may include the first memory cell structure 541 and the second memory cell structure 542 and the common terminal d of the two, which will not be repeated here.

According to an embodiment of the present disclosure, as shown in FIG. 4, it further includes: a plurality of source lines arranged in parallel to each other along the second direction, and each source line is connected to a common terminal in the corresponding memory cell array along the first direction, wherein, The source line is perpendicular to the bit line and the word line at the same time. Specifically, the source lines SL1, SL2, SL3, and SL4 are arranged in parallel to each other along the second direction, and the source line SL1 connects the common end a of the memory cell array 510 and the common end a of the corresponding memory cell array of the memory cell array group 402 along the first direction. The source line SL2 is connected in the first direction to the common terminal b of the memory cell array 520 and the common terminal of the corresponding memory cell array of the memory cell array group 402; the source line SL3 is connected in the first direction to the common terminal c of the memory cell array 530 and The common end of the corresponding memory cell array of the memory cell array group 402; the source line SL4 connects the common end d of the memory cell array 540 and the common end of the corresponding memory cell array of the memory cell array group 402 along the first direction. In the embodiment of the present disclosure, corresponding to the second direction being perpendicular to the first direction, the source line is perpendicular to the bit line and the word line at the same time. It can be seen that in the memory array structure of the present disclosure adopting the deep well biased memory cell structure, the bit line and the word line are parallel to each other, and at the same time perpendicular to the source line, which completely subverts the traditional memory array structure in which the word line and the source line are parallel to each other. , And at the same time, the array composition design that is perpendicular to the bit line forms a brand-new memory cell array composition structure, which can be said to be a pioneering design in the field of memory technology.

In order to further reflect the technical effects of the above-mentioned memory array structure, referring to FIGS. 4 and 5, another aspect of the present disclosure discloses a voltage bias method applied to the above-mentioned memory array structure, wherein, as shown in FIG. 6, Voltage bias methods include:

S610: Apply a bias voltage VB to the first well layer of the memory cell structure in the determined memory array structure; the memory cell structure determined in the embodiment of the present disclosure corresponds to the above-mentioned memory cell structure with a deep well bias structure, wherein The determination of can be understood as “selected”, that is, the storage unit structure is selected, such as the storage unit structure 522 shown in FIG. 4 or FIG. 5. Further, the first well electrode 410 of the first well layer 210 is used to apply a bias voltage VB, and the bias voltage may be a negative voltage, for example, the bias voltage VB=-0.8V, as shown in FIG. 1A or FIG. 1B , As shown in Figure 5. Therefore, the arrangement of the first well layer 210 is the arrangement position provided by the first well electrode 410, and the bias voltage VB applied to the first well electrode 410 will not affect other memory components except the selected memory cell structure. , Which further provides high voltage bias pertinence and accuracy, and at the same time prevents the risk of large voltage breakdown for transistors of other memory cell structures other than the selected memory cell structure.

S620: Apply a source terminal voltage VS to the source line corresponding to the common terminal of the memory cell structure, and simultaneously apply a drain terminal voltage VD to the bit line corresponding to the drain terminal of the memory cell structure, as shown in FIG. 1A or FIG. 1B. The terminal may be the common terminal b of the memory cell structure 522 shown in FIG. 4, and its corresponding source line SL2 may be applied with the source terminal voltage VS=-0.8V or a voltage value greater than this value as shown in FIG. 5. The drain terminal may As the drain terminal of the memory cell structure 522 shown in FIG. 4, the corresponding bit line BL2 can be applied with the drain terminal voltage VD=1.7V as shown in FIG. 5.

Among them, the value of the bias voltage VB is a negative value less than zero, the values of the source voltage VS and the drain voltage VD are greater than or equal to the value of the bias voltage VB, the voltage value here is a value that distinguishes between positive and negative values, and It is not an absolute value of positive and negative values, where the negative value can also indicate that the corresponding negative voltage is a reverse voltage, for example, the bias voltage VB=-0.8V is a bias voltage with a reverse voltage of 0.8V. When the values of the source terminal voltage VS and the drain terminal voltage VD are greater than or equal to the value of the bias voltage VB, for example, when the source terminal voltage VS=-0.6V and the drain terminal voltage VD=1.7V, the source terminal voltage VS and the drain terminal voltage The value of VD is greater than the bias voltage VB=-0.8V, so that the voltage values on the corresponding source line and bit line are both lower, that is, the unselected memory cell structure (for example, the

memory cell structures

512, 532 shown in FIG. 5) , 542, etc.) The voltages corresponding to both ends of the source and drain are also low, which not only ensures that the selected memory cell structure 522 will not have the PN junction forward conduction problem, but also prevents the unselected or half-selected memory cell structure from being affected by the voltage. If it is too large, the transistor breakdown problem will be caused, and the impact on the structure of other unselected memory cells will be minimized.

In order to explain the voltage bias method of the above-mentioned memory cell array structure more clearly, the present disclosure will further explain as follows:

The present disclosure further proposes a memory array structure in view of the large voltage faced by unselected transistors caused by the deep-well negative voltage bias structure, which leads to the problem that affects its reliability, as shown in FIGS. 4 and 5 above. In this memory array structure, the word line WL and the bit line BL are arranged in parallel and perpendicular to the source line SL. This lies in the memory cell structure of the deep well negative voltage bias structure, which can effectively avoid half-selected memory. The cell structure of the cell will experience high voltage problems. It should be noted that FIG. 4 and FIG. 5 show the arrangement of the same memory cell array structure.

As shown in FIG. 5, a Forming operation or a reset operation is performed on the storage unit structure in the second row and second column, which corresponds to the operation of the storage unit structure 522 in FIG. 4. At this time, because the bias voltage of the source terminal is the negative voltage VSL, the gate voltage VG applied to the gate terminal of the word line WL2 is larger than VSL by a threshold voltage, and the unselected row (such as the row corresponding to the word line WL1) is applied The gate voltage needs to turn off the resistive switching cell CELL of the memory cell structure 521 in the first row, so its bias voltage can be selected to be equal to VSL. At this time, the voltage applied to the drain terminal of the bit line BL2 is the high voltage VD, and the gate tube of the resistive switching cell CELL of the selected memory cell structure 522 is turned on. Due to the existence of the resistive switching cell CELL, there will be a considerable voltage drop. On the resistive switching unit CELL, the voltage falling on the strobe tube is much smaller than VD, so the source and drain terminals of the strobe tube have relatively small voltages, which will not cause tube breakdown.

Therefore, unlike the traditional memory array structure, the present disclosure places the bit line BL in parallel with the word line WL, and the voltage applied by the bit line BL is only applied to the resistive switching cell CELL of the memory cell structure of the row selected by the word line WL. The upper (corresponding to the word line WL2 shown in FIG. 5), that is, the resistive switching cells CELL of the

memory cell structures

512, 532, and 542 in FIG. 4 are half-selected cells. At this time, since the source terminal can be individually biased, it is only necessary to set the source terminal (that is, the common The terminal b) applies a relatively negative voltage to ensure the voltage difference requirement of the resistive switching unit CELL. For cells that do not require programming operations, that is, the

memory cell arrays

510, 530, and 540 where the

memory cell structures

512, 532, and 542 in FIG. 4 are located, a corresponding application of one can turn off the gate tube where the unselected resistive switching cell CELL is located. The negative voltage is sufficient. In the embodiment of the present disclosure, the same voltage can be applied to the source line SL1 of the first column (the memory cell array 510 in FIG. 4) as the word line WL1, so the source-drain terminal voltage and the gate-drain voltage of the transistor are smaller. The transistor will not be broken down by high voltage, and the reliability is guaranteed.

In this type of memory array structure, when the forming operation occurs, a large voltage may occur. Between the drain terminals of the half-selected cells (that is, the

memory cell structures

512, 532, and 542 in FIG. 4) and the negative pressure of the deep well bias, forming During operation, the drain terminal voltage VD is connected to a high voltage, and the half-selected resistive switching unit CELL has a drain terminal voltage equal to VD because the transistor is turned off. Because the deep well bias structure will be configured as a negative voltage on the semi-selected resistive switching cell CELL, it will cause its drain terminal and the PN junction of the first well layer to experience a large reverse bias voltage, but the transistor is more sensitive to large voltages. The source-drain voltage is followed by the gate-source voltage and the gate-drain voltage. The reverse bias voltage of the PN junction is generally larger, which will not cause the breakdown of the transistor.

Referring to FIG. 4, as shown in FIG. 5, in the embodiment of the present disclosure, a forming operation or a reset operation is performed on a black-filled memory cell structure (ie, the memory cell structure 522 in FIG. 4), assuming that the required operating voltage is greater than 2.5V, here it is assumed that the voltage required to fall on the resistive switching cell CELL is about 2.5V to complete the forming operation. If the traditional process (non-deep well negative voltage bias) is used, such a large voltage is not easy to pass into the memory cell Array, while the WL and BL of the traditional array structure are perpendicular to each other, the transistors of the unselected memory cell will be broken down by a large voltage. As shown in Figure 3, the upper and lower parts of the selected memory cell structure 301 are half-selected memory cells.

Structures

303 and 302, because the transistor is not turned on at this time, the high voltage is completely biased on the transistor, which is likely to cause its transistor to be broken down, and the deep well negative voltage biased memory cell structure and word line of the present disclosure are adopted. The memory array structure in which the WL and the bit line BL are parallel to each other makes the voltage of all the transistors in the array within their reliable operating range. As shown in FIG. 5, the selected cell corresponds to the memory cell structure 522 shown in FIG. It can also be biased to -0.8V, and the problem of forward conduction of the PN junction between the substrate layer and the source terminal will not occur at this time. The word line WL2 of the selected memory cell structure 522 is applied with a voltage of 0.3V, so that its gate-source voltage is 1.1V, so that the transistor can be completely turned on. In order to realize the forming operation, a voltage of 1.7V is applied to the bit line BL2 of the memory cell structure 522. Since the resistance value of the resistive switching cell CELL of the memory cell structure 522 is relatively large, the voltage basically falls on both ends of the memory cell structure 522. , About 2.5V (that is, 1.7V+0.8V=2.5V), and the forming operation is completed. At the same time, the voltage difference between any two ends of the transistor is relatively low, which minimizes reliability problems. For unselected memory cell structures, half-selected memory cell structures with reliability risks, for example, as shown in FIG. 5, correspond to the

memory cell structures

512, 522, 532, and 542 in FIG. 4. In order not to operate on them, you can A relatively high voltage is applied to the source line terminals SL1, SL3, and SL4, for example, 0.3V can be selected. It can be seen that, except for the substrate layer and the source terminal voltage of the half-selected risk memory cell structure, the voltages at any other terminals are relatively low. Since the substrate layer and the source terminal form a PN junction structure of a memory cell structure with a deep well bias structure, the reverse breakdown voltage that the PN junction structure can withstand is much greater than its applied operating voltage, which will not cause a transistor The PN junction is broken down.

Therefore, the present disclosure overturns the arrangement rules of the traditional memory array structure and redesigns the arrangement structure of the memory cell array. By recombining the directions of WL, BL, and SL, the memory array structure is performing forming operations, set operations, and reset operations. At this time, the voltage difference between any two ends of the strobe tube corresponding to the unselected resistive switching unit CELL that does not need to be operated will not exceed its breakdown voltage. The memory array structure is more stable and reliable, and the volume and area size are well controlled. It is a subversive design in the memory field, which makes the application and promotion of embedded memory reach a new height and has extremely high commercial value. And scientific research value.

The present disclosure provides a memory cell structure, a memory array structure, and a voltage biasing method. The memory cell structure includes: a substrate layer, a well layer and a transistor, the substrate layer is used to support the memory cell structure; the well layer is embedded in the substrate layer On the upper surface, the upper surface of the well layer is level with the upper surface of the substrate layer, and the transistor is arranged on the well layer. The present disclosure applies deep well bias to the memory cell structure so that the well voltage of the memory cell can be individually biased to a specific voltage. Combined with the redesigned memory cell array structure, most of the applied programming voltage falls on the memory cell structure In the above, the programming voltage of the memory cell is reduced, and at the same time, the strobe transistor can be prevented from being broken down due to excessive voltage, thereby ensuring better reliability of the device and higher area efficiency of the memory cell array structure.

The specific embodiments described above further describe the purpose, technical solutions and beneficial effects of the present disclosure in further detail. It should be understood that the above are only specific embodiments of the present disclosure and are not intended to limit the present disclosure. Within the spirit and principle of the present disclosure, any modification, equivalent replacement, improvement, etc., shall be included in the protection scope of the present disclosure.

Claims

A storage unit structure, which includes:

The substrate layer is used to provide support for the memory cell structure;

A well layer embedded in the substrate layer, and the upper surface of the well layer is level with the upper surface of the substrate layer; and

The transistor is arranged inside and on the surface of the well layer.
The memory cell structure according to claim 1, wherein the well layer comprises:

The first well layer is embedded in the substrate layer, and the upper surface of the first well layer is level with the upper surface of the substrate layer;

The second well layer is arranged between the first well layer and the substrate layer, and the upper surface of the second well layer is level with the upper surface of the substrate layer, and is used to separate the first well layer and the substrate layer. The substrate layer;

Wherein, the transistor is arranged inside and on the surface of the first well layer.
The memory cell structure according to claim 2, wherein:

The substrate layer is a non-P-type or N-type doped structure layer;

The first well layer is a P-type doped structure layer for forming a P-type well layer;

The second well layer is an N-type doped structure layer, and is used to form an N-type well layer as an isolation between the substrate layer and the P-type well layer.
The memory cell structure according to claim 2, wherein the transistor comprises:

The gate is arranged on the upper surface of the first well layer;

The source electrode is embedded in the first well layer, and the upper surface of the source electrode is exposed to the first well layer;

The drain is embedded in the first well layer, and the upper surface of the drain is exposed to the first well layer.
The memory cell structure according to claim 4, wherein:

A certain distance between the drain and the source;

The gate is disposed on the upper surface of the first well layer between the drain and the source.
The memory cell structure according to claim 5, wherein the memory cell structure further comprises:

The first resistive switching unit is located above the drain or the source;

The first interconnection layer includes a plurality of interconnection sublayers, the first resistive switching unit is in contact with the upper surface of the drain or the source electrode, and the plurality of interconnection sublayers are located above the first resistive switching unit;

The first connection line is arranged along the arrangement direction of the first interconnection layer and the first resistance switching unit, and is used to connect the first interconnection layer and the first resistance switching unit with the source electrode or the drain electrode.
The memory cell structure according to claim 5, wherein the memory cell structure further comprises:

The second resistive switching unit is located above the drain or the source;

The second interconnection layer includes a plurality of interconnection sublayers, at least one interconnection sublayer of the plurality of interconnection sublayers is located between the second resistive switching unit and the drain or source, and the remaining interconnection sublayers are located Above the second resistive switching unit;

The second connecting line is arranged along the arrangement direction of the second interconnection layer and the second resistive switching unit, and is used to connect the second resistive switching unit and the second interconnection layer with the source or drain.
The storage unit structure according to claim 2, further comprising:

A first well electrode embedded in the first well layer, and an upper surface of the first well electrode is exposed to the first well layer;

The second well electrode is embedded in the second well layer, and the upper surface of the second well electrode is exposed to the second well layer.
A memory array structure, which includes:

A plurality of memory cell array groups are arranged in parallel with each other in the first direction, each memory cell array group includes a plurality of memory cell arrays arranged in parallel with each other along the second direction; each memory cell array includes a plurality of claims 1-8 Any one of the storage unit structure;

A plurality of bit lines are arranged in parallel to each other along a first direction, and at least two bit lines are respectively connected to two ends of the plurality of memory cell arrays along a second direction; and

A plurality of word lines are arranged in parallel to each other along the first direction, and are parallel to the plurality of bit lines, and each word line is connected to the gate of the memory cell structure at a corresponding position in the plurality of memory cell arrays in the second direction.
The memory array structure of claim 9, wherein:

The first direction is perpendicular to the second direction.
The memory array structure according to claim 9, wherein the memory cell array at least comprises:

The first memory cell structure, the drain terminal of which is connected to a bit line;

The drain of the second memory cell structure is connected to another bit line, and the source is connected to the source of the first memory cell structure to form a common terminal;

Wherein, the drain terminal further includes a resistive switching unit connected to the drain of the first memory cell structure or the second memory cell structure.
The memory array structure according to claim 11, further comprising:

A plurality of source lines are arranged in parallel to each other along the second direction, and each source line is connected to a common terminal in the corresponding memory cell array along the first direction;

Wherein, the source line is perpendicular to the bit line and the word line at the same time.
A voltage bias method applied to the memory array structure of any one of claims 9-12, wherein the voltage bias method comprises:

Applying a bias voltage to the determined first well layer of the memory cell structure in the memory array structure;

Applying a source terminal voltage to the source line corresponding to the common terminal of the memory cell structure, and simultaneously applying a drain terminal voltage to the bit line corresponding to the drain terminal of the memory cell structure;

Wherein, the value of the bias voltage is a negative value less than zero, and the values of the source terminal voltage and the drain terminal voltage are greater than or equal to the value of the bias voltage.