CN101777572A - Semiconductor memory structure and control method thereof - Google Patents
Semiconductor memory structure and control method thereof Download PDFInfo
- Publication number
- CN101777572A CN101777572A CN201010023061A CN201010023061A CN101777572A CN 101777572 A CN101777572 A CN 101777572A CN 201010023061 A CN201010023061 A CN 201010023061A CN 201010023061 A CN201010023061 A CN 201010023061A CN 101777572 A CN101777572 A CN 101777572A
- Authority
- CN
- China
- Prior art keywords
- semiconductor memory
- voltage
- links
- scope
- control method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Semiconductor Memories (AREA)
Abstract
The invention belongs to the technical field of semiconductor non-volatile memory, in particular disclosing a semiconductor memory structure and a control method thereof. The semiconductor memory structure comprises at least one semiconductor substrate, one tunnel transistor structure for controlling the semiconductor memory, one storage unit for storing information and one coping electrode for connecting the storage unit, wherein the tunnel transistor is manufactured by a self alignment technique and is used for controlling the operation of the semiconductor memory like toerase operation and read operation. A plurality of semiconductor memories can form a semiconductor memory array. The invention also discloses a control method of the above semiconductor memory array, comprising the steps of resetting, setting and reading.
Description
Technical field
The invention belongs to technical field of semiconductor non-volatile memory, be specifically related to a kind of organization of semiconductor memory and control method thereof that adopts self-registered technology.
Background technology
Continuous development along with microelectric technique, Moore's Law is followed in the development of integrated circuit (IC) chip basically, the integrated level that is semiconductor chip is with per speed increment of doubling in 18 months, this makes the design of integrated circuit develop towards the direction of SOC (system on a chip) integrated (SOC), and a key technology that the realizes SOC on-chip memory that to be exactly low-power consumption, high density, access speed fast is integrated.Integrated circuit (IC)-components technology of today has been in about 30 nanometers, but traditional floating boom (Flash) memory since coupling ratio and voltage than problems such as height, be difficult to narrow down to below 30 nanometers, therefore novel non-volatility memorizer be developed to focus for current research.Phase transition storage and resistance-variable storing device can be as novel memories.
Phase transition storage (phase change memory) is to utilize the huge conductivity difference of chalcogenide when crystalline state and amorphous state to store data.The phase transformation chalcogenide can show reversible phase transition phenomena when turning to crystalline phase by amorphous phase, when amorphous phase, material is highly unordered state, does not have the network of crystalline solid.Under this kind state, material has high impedance and high reflectance.On the contrary, in crystalline phase, material has the crystal structure of rule, has Low ESR and antiradar reflectivity.The phase transition storage utilization be exactly two alternate impedance contrasts.The violent heat that inject to produce by electric current can atarting material phase transformation.Material character after the phase transformation is by the electric current that injects, voltage and operating time decision.Fig. 1 a is the profile of a typical phase-changing memory unit, and as shown in Figure 1a, one deck chalcogenide layer 100 is clipped between apex electrode 105 and the bottom electrode 101, bottom electrode 101 extended heating resistor 102 contact chalcogenide layers 100.Electric current injects the Joule heat that produces behind the tie point of heating resistor 102 and chalcogenide layer 100 and causes phase transformation, in crystal structure chalcogenide layer 100, produced the zone 103 of amorphous phase, the zone 104 for crystallization to the zone, because the difference of reflectivity, amorphous phase zone 103 present the shape as the mushroom cap.Fig. 1 b is the summary equivalent circuit diagram of a phase-changing memory unit, shown in Fig. 1 b, phase-changing memory unit 106 comprises 1 transistor 107 and a phase-change element 108, a source/drain (S/D) ground connection of transistor 107, and another S/D of transistor 107 is connected with an end of phase-change element 108.The grid of transistor 107 and grid voltage V
GConnect.The other end of phase-change element 108 and bit-line voltage V
BLConnect.When wanting the data of the storage in the access phase-change element 108, voltage V
GPut on transistor 107, and turn-on transistor 107, and bit-line voltage V
BLPut on phase-change element 108, make one to read electric current through phase-change element 108 and transistor 107.Based on the size of output current, the data that are stored in phase-change element 120 are read.Compare with traditional Flash floating-gate memory, phase transition storage has and writes faster and erasing speed and better scaling.
The Card read/write of resistance-variable storing device is to rely on the resistance read or to change the resistive material to realize.Fig. 1 c is the basic structure schematic diagram of a resistance-variable storing device.Shown in Fig. 1 b, between top electrode 109 and bottom electrode 111, be provided with electric resistance converting storage layer 110.Top electrode 109 and bottom electrode 111 use the more stable metal materials of chemical property such as Pt and Ti usually, and electric resistance converting storage layer 110 is generally TiO
2, ZrO, Cu
2O and SrTiO
3Etc. binary or ternary metal oxide.The resistance value of electric resistance converting storage layer 110 can have two kinds of no states under the applied voltage effect, i.e. high-impedance state and low resistance state, and it can be used for characterizing " 0 " and " 1 " two states respectively.Under the effect of different applied voltages, but the resistance value of resistance-variable storing device can realize inverse conversion between high-impedance state and low resistance state, realizes the function of information stores with this.In the read-write operation of resistance-variable storing device, binary message 0 of General Definition high-impedance state storage, binary message 1 of low resistance state storage.Because the initial resistance state of resistive material is a high-impedance state, therefore will write 1 operation (corresponding resistive material transfers low resistance state to by high-impedance state) to information bit and be defined as write operation, be defined as erase operation and write 0 operation (corresponding resistive material transfers high-impedance state to by low resistance state) to information bit.The device write operation, generally need between top electrode and hearth electrode, apply the short potential pulse of about 1-5V, and suitable maximum current limit is set, owing to increasing several magnitudes suddenly, electric current causes component failure to avoid the resistive material to turn to by high-impedance state in the process of low resistance state.The erase operation of device generally need apply and write voltage in the same way or the short potential pulse of reverse about 0.5-1V.The voltage pulse width that is used to write and wipe is decided on concrete resistive material behavior from not waiting to microseconds up to a hundred tens of nanoseconds.The erasing voltage width is generally greater than writing pulse duration.Reading of device stores information can be by applying the small voltage about 0.2V and detecting corresponding size of current and realize.Because the resistivity of material itself and the yardstick of material are irrelevant, therefore the memory property of resistance-variable storing device can't be degenerated along with dwindling of device size in theory.This has just determined the potential integration capability of resistance-variable storing device to be higher than the Flash floating-gate memory of current main-stream far away.On the other hand, the device architecture of resistance-variable storing device is simple, can realize integrated with existing C MOS production technology easily.
But phase transition storage and resistance-variable storing device all need bigger erasable electric current, therefore need special array access device to carry out erasable to it.
Summary of the invention
The objective of the invention is to propose the big organization of semiconductor memory of a kind of erasable electric current, and the control method of the operation of this semiconductor memory reading and writing etc.
For reaching above-mentioned purpose of the present invention, the present invention proposes a kind of organization of semiconductor memory that adopts self-registered technology, has proposed the control method of this semiconductor memory simultaneously.
A kind of control method of semiconductor memory comprise reset, set, read step.
Reset process to described semiconductor memory is: the reference voltage wiring that links to each other with described semiconductor memory is applied first voltage; The word line that links to each other with described semiconductor memory is applied second voltage; The bit line that links to each other with described semiconductor memory is applied the 3rd voltage; The p-n junction diode that makes tunneling transistor in the described semiconductor memory thus is by forward bias, and this semiconductor memory is reset, and it is big that its resistance becomes.
The scope of described first voltage is that 0.1V is to 4V; The scope of described second voltage is-1V is to 1V; The scope of described the 3rd voltage is that 0V is to 3V.
Further, the set step to described semiconductor memory is: the reference voltage wiring that links to each other with described semiconductor memory is applied the 4th voltage; The word line that links to each other with described semiconductor memory is applied the 5th voltage; The bit line that links to each other with described semiconductor memory is applied the 6th voltage; Described semiconductor memory is set, and its resistance diminishes.
The scope of described the 4th voltage is that 0V arrives-3V; The scope of described the 5th voltage is that 0V is to 10V; The scope of described the 6th voltage is that 0.1V is to 3V.
Further, the read step to described semiconductor memory is: the reference voltage wiring that links to each other with described semiconductor memory is applied the 7th voltage; The word line that links to each other with described semiconductor memory is applied the 8th voltage; The bit line that links to each other with described semiconductor memory is applied the 9th voltage; Thus, based on the size of output current, be stored in selected the reading of data in the semiconductor memory.
The scope of described the 7th voltage is that 0V arrives-3V; The scope of described the 8th voltage is that 0V is to 10V; The scope of described the 9th voltage is that 0.1V is to 2V.
Further, described semiconductor memory comprises at least one Semiconductor substrate, a tunneling transistor arrangement, a memory cell and a top electrodes.Described Semiconductor substrate is the silicon (SOI) on monocrystalline silicon, polysilicon or the insulator.Described tunneling transistor arrangement comprises at least one source electrode, a drain electrode and a grid, and the raceway groove of grid covering device and described raceway groove are vertical with the residing substrate surface of this tunneling transistor.Described grid structure comprises at least one conductive layer and the insulating barrier with described conductive layer and the isolation of described Semiconductor substrate.Described conductive layer is polysilicon, amorphous silicon, tungsten metal, titanium nitride, tantalum nitride or metal silicide.Described grid conducting layer forms the abutment wall structure around being looped around vertical raceway groove.Described insulating barrier is SiO
2, HfO
2, HfSiO, HfSiON, SiON, Al
2O
3Perhaps several mixture among them.
Among the present invention, described memory cell is made of phase-change material or is made of the resistive material; Described top electrodes is metal Pt, TiN, Ti, Ta or TaN, and links to each other with described memory cell; Described memory cell is used for stored charge and links to each other with the source electrode or the drain electrode of described tunneling transistor, and the grid control of described tunneling transistor is by the electric current of described memory cell; Any one in described top electrodes and the multiple bit lines is connected, and any one in the grid of described tunneling transistor and many word lines is connected, and any one in the source electrode of described tunneling transistor or drain electrode and many reference voltages wirings is connected.
Semiconductor memory of the present invention adopts the tunneling transistor of self-registered technology to carry out erasable to semiconductor memory, read to wait the control of operation, vertical gate control diode structure not only can satisfy the big current requirements that resistance-variable storing device and phase transition storage are write in the tunneling transistor, promptly form a semicondctor storage array by aforesaid semiconductor memory, any one in the multiple bit lines in described top electrodes and the array is connected, any one in many word lines in the grid of described tunneling transistor and the array is connected, and any one in many reference voltages wirings in the source electrode of described tunneling transistor or drain electrode and the array is connected.And can improve the density of memory device array, be highly suitable for the manufacturing of semiconductor memory chips, and its control method and control circuit are also comparatively simple.
Can also constitute a semicondctor storage array by a plurality of semiconductor memories of the present invention, promptly form a semicondctor storage array by aforesaid semiconductor memory, any one in the multiple bit lines in described top electrodes and the array is connected, any one in many word lines in the grid of described tunneling transistor and the array is connected, and any one in many reference voltages wirings in the source electrode of described tunneling transistor or drain electrode and the array is connected.And its control method can be carried out set to individual memory wherein again for earlier a plurality of memories in the semicondctor storage array being resetted.
Description of drawings
Fig. 1 a is the profile of a typical phase-changing memory unit.
Fig. 1 b is the summary equivalent circuit diagram of a phase-changing memory unit.
Fig. 1 c is the profile of a typical resistance-variable storing device unit.
Fig. 2 a is the vertical view of a kind of organization of semiconductor memory embodiment provided by the invention.
Fig. 2 b is the sectional view of a kind of organization of semiconductor memory embodiment provided by the invention.
Fig. 2 c is the equivalent circuit diagram of a kind of organization of semiconductor memory embodiment provided by the invention.
Fig. 3 a is an equivalent circuit diagram that semicondctor storage array embodiment resets provided by the invention.
Fig. 3 b is an equivalent circuit diagram that semicondctor storage array embodiment carries out set provided by the invention.
Fig. 3 c is an equivalent circuit diagram that semicondctor storage array embodiment reads provided by the invention.
Embodiment
Below with reference to accompanying drawings an exemplary embodiment of the present invention is elaborated.In the drawings, for convenience of description, amplified or dwindled the thickness in layer and zone, shown in size do not represent actual size.Reference diagram is the schematic diagram of idealized embodiment of the present invention, and embodiment shown in the present should not be considered to only limit to the given shape in zone shown in the figure, but comprises resulting shape, the deviation that causes such as manufacturing.For example the curve that obtains of etching has crooked or mellow and full characteristics usually, but in embodiments of the present invention, all represents with rectangle, and the expression among the figure is schematically, but this should not be considered to limit the scope of the invention.Simultaneously in the following description, employed term wafer and substrate can be understood as and comprise the just semiconductor wafer in processes, may comprise other prepared thin layer thereon.
As Fig. 2 a is the vertical view of a kind of organization of semiconductor memory provided by the present invention, and Fig. 2 b is the sectional view of a kind of organization of semiconductor memory provided by the present invention.As Fig. 2 a and Fig. 2 b, shown in 200 Semiconductor substrate for providing; Shown in 201 be n type ion doping zone; Shown in 202 be SiO
2Gate medium; Shown in 203 be high k material gate medium; Shown in 204 be grid conducting layer such as being TiN or TaN, grid conducting layer 204 forms the abutment wall structure around being looped around vertical raceway groove; Shown in 205 be polysilicon; Shown in 202,203,204 and 205 grids that constitute tunneling transistors, and the raceway groove of this grid covering device and described raceway groove are vertical with the residing substrate surface of this tunneling transistor; Shown in 206 be p type ion doping zone; Shown in 208 be by SiO
2, Si
3N
4The insulating barrier of the insulating material formation of perhaps mixing mutually between them; Shown in 208 memory cell that are used for stored charge for constituting by phase-change material or resistive material; Shown in 209 be the metal electrode that links to each other with memory cell 208, can be TiN, Ti, Ta or TaN.The grid of tunneling transistor can be controlled the electric current by memory cell 208, and realizes the read-write operation to memory cell 208.
Fig. 2 c is the equivalent circuit diagram of a kind of organization of semiconductor memory provided by the invention.Shown in Fig. 2 c, bit line BL is connected with metal electrode 209, and word line WL is connected with the grid of described tunneling transistor, and reference voltage wiring SL is connected with the source electrode or the drain electrode of described tunneling transistor.
Can constitute a semicondctor storage array by a plurality of semiconductor memories shown in Fig. 2 b, as Fig. 3 a, 3b and 3c be respectively to a semicondctor storage array reset, set and the equivalent circuit diagram that reads.
Specifically, step such as Fig. 3 a that semicondctor storage array is resetted:
Reference voltage wiring SL1 and SL2 are all applied voltage 2V;
Word line WL1, WL2, WL3 and WL4 are all applied voltage 0V;
Pairs of bit line BL1 applies voltage 0V, and pairs of bit line BL2 applies voltage 2V.
Because SL2=BL2=2V, therefore with in the memory that BL2 links to each other there is not the electric current process, and BL1=0V＜SL1=0V, therefore the p-n of the tunneling transistor that links to each other with BL1 is by forward bias, the electric current process is arranged, and the memory that links to each other with BL1 is selected to be resetted, and it is big that its resistance becomes.
Semicondctor storage array is carried out step such as Fig. 3 b of set:
Reference voltage wiring SL1 and SL2 are all applied voltage 0V;
Word line WL1, WL3 and WL4 are all applied voltage 0V, word line WL2 is applied voltage 3V;
Pairs of bit line BL1 applies voltage 1V, and pairs of bit line BL2 applies voltage 0V.
Because WL2=3V＞SL1=0V, the p-n of the tunneling transistor shown in 301 is reverse biased among Fig. 3 b, the selected set of the memory shown in 301, and its resistance diminishes.
Step such as Fig. 3 c that semicondctor storage array is read:
Reference voltage wiring SL1 and SL2 are all applied voltage 0V;
Word line WL1, WL3 and WL4 are all applied voltage 0V, word line WL2 is applied voltage 3V;
Pairs of bit line BL1 and bit line BL2 apply voltage 0.5V.
Based on the size of electric current, the data that store in the memory cell shown in 302 among Fig. 3 c are read.For preventing set operation, the voltage that is applied to bit line WL in the read step should be lower than the voltage that is applied to bit line WL in the set step.
As mentioned above, under the situation that does not depart from spirit and scope of the invention, can also constitute many very embodiment of big difference that have.Should be appreciated that except as defined by the appended claims, the invention is not restricted at the instantiation described in the specification.
Claims (12)
1. a semiconductor memory is characterized in that, described semiconductor memory comprises at least one Semiconductor substrate, a tunneling transistor arrangement, a memory cell and a top electrodes; Described memory cell is made of phase-change material or is made of the resistive material; Described top electrodes links to each other with described memory cell; Described memory cell is used for stored charge and links to each other with the source electrode or the drain electrode of described tunneling transistor, and the grid control of described tunneling transistor is by the electric current of described memory cell; Any one in described top electrodes and the multiple bit lines is connected, and any one in the grid of described tunneling transistor and many word lines is connected, and any one in the source electrode of described tunneling transistor or drain electrode and many reference voltages wirings is connected.
2. semiconductor memory according to claim 1, it is characterized in that, described tunneling transistor arrangement comprises at least one source electrode, a drain electrode and a grid, and the raceway groove of grid covering device and described raceway groove are vertical with the residing semiconductor substrate surface of this transistor.
3. semiconductor memory according to claim 2 is characterized in that, described gate stack comprises at least one conductive layer and the insulating barrier with described conductive layer and the isolation of described Semiconductor substrate.
4. semiconductor memory according to claim 3 is characterized in that, described conductive layer is polysilicon, amorphous silicon, tungsten metal, titanium nitride, tantalum nitride or metal silicide.
5. semiconductor memory according to claim 3 is characterized in that, described insulating barrier is SiO
2, HfO
2, HfSiO, HfSiON, SiON, Al
2O
3The perhaps mixture between them.
6. semiconductor memory according to claim 3 is characterized in that, described grid conducting layer forms the abutment wall structure around being looped around vertical raceway groove.
7. semicondctor storage array, it is characterized in that, form a semicondctor storage array by the described semiconductor memory of a plurality of claims 1, any one in the multiple bit lines in described top electrodes and the array is connected, any one in many word lines in the grid of described tunneling transistor and the array is connected, and any one in many reference voltages wirings in the source electrode of described tunneling transistor or drain electrode and the array is connected.
8. the control method of semiconductor memory according to claim 1 is characterized in that, control method comprise reset, set and read operation; Wherein:
Reset process is as follows:
The reference voltage wiring that links to each other with described semiconductor memory is applied first voltage;
The word line that links to each other with described semiconductor memory is applied second voltage;
The bit line that links to each other with described semiconductor memory is applied the 3rd voltage;
The p-n junction diode that makes tunneling transistor in the described semiconductor memory thus is by forward bias, and this semiconductor memory is reset, and it is big that its resistance becomes;
The set step is as follows:
The reference voltage wiring that links to each other with described semiconductor memory is applied the 4th voltage;
The word line that links to each other with described semiconductor memory is applied the 5th voltage;
The bit line that links to each other with described semiconductor memory is applied the 6th voltage;
Described semiconductor memory is set, and its resistance diminishes;
Read step is as follows:
The reference voltage wiring that links to each other with described semiconductor memory is applied the 7th voltage;
The word line that links to each other with described semiconductor memory is applied the 8th voltage;
The bit line that links to each other with described semiconductor memory is applied the 9th voltage;
Thus, based on the size of output current, the data that are stored in the described semiconductor memory are read.
9. control method according to claim 8 is characterized in that, the scope of described first voltage is that 0.1V is to 4V; The scope of described second voltage is-1V is to 1V; The scope of described the 3rd voltage is that 0V arrives-3V;
10. control method according to claim 8 is characterized in that, the scope of described the 4th voltage is that 0V arrives-3V; The scope of described the 5th voltage is that 0V is to 10V; The scope of described the 6th voltage is that 0.1V is to 3V.
11. control method according to claim 10 is characterized in that, the scope of described the 7th voltage is that 0V arrives-3V; The scope of described the 8th voltage is that 0V is to 10V; The scope of described the 9th voltage is that 0.1V is to 2V.
12. the control method of a semicondctor storage array according to claim 7 is characterized in that, earlier a plurality of memories in the semicondctor storage array is resetted, and again individual memory is wherein carried out set.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010023061A CN101777572A (en) | 2010-01-21 | 2010-01-21 | Semiconductor memory structure and control method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010023061A CN101777572A (en) | 2010-01-21 | 2010-01-21 | Semiconductor memory structure and control method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101777572A true CN101777572A (en) | 2010-07-14 |
Family
ID=42513965
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201010023061A Pending CN101777572A (en) | 2010-01-21 | 2010-01-21 | Semiconductor memory structure and control method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101777572A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102185105A (en) * | 2011-04-22 | 2011-09-14 | 复旦大学 | Semiconductor memory structure and manufacturing method thereof |
| CN102185108A (en) * | 2011-05-10 | 2011-09-14 | 复旦大学 | Semiconductor memory structure and control method thereof |
| CN101800236B (en) * | 2010-02-04 | 2012-07-04 | 复旦大学 | Semiconductor memory structure and manufacturing method thereof |
| CN102768850A (en) * | 2011-05-04 | 2012-11-07 | 中国科学院微电子研究所 | Semiconductor device and semiconductor memory device |
| US9013918B2 (en) | 2011-05-04 | 2015-04-21 | Institute of Microelectronics, Chinese Academy of Sciences | Two-terminal memory cell and semiconductor memory device based on different states of stable current |
| WO2023087804A1 (en) * | 2021-11-17 | 2023-05-25 | 北京大学 | Embedded semiconductor random access memory structure and control method therefor |
-
2010
- 2010-01-21 CN CN201010023061A patent/CN101777572A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101800236B (en) * | 2010-02-04 | 2012-07-04 | 复旦大学 | Semiconductor memory structure and manufacturing method thereof |
| CN102185105A (en) * | 2011-04-22 | 2011-09-14 | 复旦大学 | Semiconductor memory structure and manufacturing method thereof |
| CN102768850A (en) * | 2011-05-04 | 2012-11-07 | 中国科学院微电子研究所 | Semiconductor device and semiconductor memory device |
| WO2012149703A1 (en) * | 2011-05-04 | 2012-11-08 | 中国科学院微电子研究所 | Semiconductor device and semiconductor storage apparatus |
| US9013918B2 (en) | 2011-05-04 | 2015-04-21 | Institute of Microelectronics, Chinese Academy of Sciences | Two-terminal memory cell and semiconductor memory device based on different states of stable current |
| CN102768850B (en) * | 2011-05-04 | 2015-07-08 | 中国科学院微电子研究所 | Semiconductor device and semiconductor memory device |
| CN102185108A (en) * | 2011-05-10 | 2011-09-14 | 复旦大学 | Semiconductor memory structure and control method thereof |
| WO2012151725A1 (en) * | 2011-05-10 | 2012-11-15 | 复旦大学 | Semiconductor memory structure and control method thereof |
| WO2023087804A1 (en) * | 2021-11-17 | 2023-05-25 | 北京大学 | Embedded semiconductor random access memory structure and control method therefor |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10109679B2 (en) | Wordline sidewall recess for integrating planar selector device | |
| JP4684297B2 (en) | Writing method for nonvolatile semiconductor memory device | |
| US10276792B2 (en) | Low power barrier modulated cell for storage class memory | |
| US9530824B2 (en) | Monolithic three dimensional memory arrays with staggered vertical bit line select transistors and methods therfor | |
| US7106618B2 (en) | Method of driving a non-volatile memory | |
| CN100454439C (en) | Non-volatile semiconductor memory device | |
| CN109427969B (en) | Phase change memory electrode with multiple thermal interfaces | |
| US7382647B1 (en) | Rectifying element for a crosspoint based memory array architecture | |
| KR100738070B1 (en) | Nonvolitile Memory Device Comprising One Resistance Material and One Transistor | |
| CN102185105A (en) | Semiconductor memory structure and manufacturing method thereof | |
| JP2006140224A (en) | Semiconductor memory element and semiconductor storage device | |
| KR20060042734A (en) | Nonvolitile memory device comprising one resistance material and one diode | |
| US10355129B2 (en) | Vertical transistors with sidewall gate air gaps and methods therefor | |
| CN101777572A (en) | Semiconductor memory structure and control method thereof | |
| US9646880B1 (en) | Monolithic three dimensional memory arrays formed using sacrificial polysilicon pillars | |
| US10153430B1 (en) | Germanium-based barrier modulated cell | |
| US10541273B2 (en) | Vertical thin film transistors with isolation | |
| US9748479B2 (en) | Memory cells including vertically oriented adjustable resistance structures | |
| CN101777570A (en) | Semiconductor memory structure utilizing self-aligning process and manufacturing method thereof | |
| CN102185108A (en) | Semiconductor memory structure and control method thereof | |
| CN101807596A (en) | Autoregistration semiconductor memory structure and manufacturing method thereof | |
| US20140003122A1 (en) | Semiconductor memory structure and control method thereof | |
| US10468459B2 (en) | Multiple vertical TFT structures for a vertical bit line architecture | |
| US9754999B1 (en) | Vertical thin film transistors with surround gates | |
| CN101800236B (en) | Semiconductor memory structure and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20100714 |