CN102185108A - Semiconductor memory structure and control method thereof - Google Patents

Semiconductor memory structure and control method thereof Download PDF

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CN102185108A
CN102185108A CN2011101198590A CN201110119859A CN102185108A CN 102185108 A CN102185108 A CN 102185108A CN 2011101198590 A CN2011101198590 A CN 2011101198590A CN 201110119859 A CN201110119859 A CN 201110119859A CN 102185108 A CN102185108 A CN 102185108A
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semiconductor memory
organization
voltage
links
effect transistor
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王鹏飞
孙清清
张卫
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Fudan University
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Fudan University
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Priority to CN2011101198590A priority Critical patent/CN102185108A/en
Priority to PCT/CN2011/001353 priority patent/WO2012151725A1/en
Publication of CN102185108A publication Critical patent/CN102185108A/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
    • H10B63/34—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors of the vertical channel field-effect transistor type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8833—Binary metal oxides, e.g. TaOx
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8836—Complex metal oxides, e.g. perovskites, spinels

Abstract

The invention belongs to the technical field of semiconductor nonvolatile memories, and particularly discloses a semiconductor memory structure and a control method thereof. The semiconductor memory structure provided by the invention comprises a memory cell used for storing information and a tunneling field effect transistor connected with the memory cell, wherein the tunneling field effect transistor is used for controlling the semiconductor memory, for example, performing rewriting operations and reading operations. A plurality of semiconductor memory structures form a semiconductor memory array. The control method provided by the invention comprises resetting, setting and reading steps. A vertical grid-controlled diode structure in the tunneling field effect transistor can meet requirements on high current in the writing of a resistive random access memory and a phase change memory and increase the density of the memory array, and is suitable for manufacturing a semiconductor memory chip. Moreover, the control method and a control circuit are relatively simpler.

Description

A kind of organization of semiconductor memory and control method thereof
Technical field
The invention belongs to technical field of semiconductor non-volatile memory, be specifically related to a kind of organization of semiconductor memory and control method thereof, particularly a kind of organization of semiconductor memory and control method thereof that adopts self-registered technology.
Background technology
Continuous development along with microelectric technique, Moore's Law is followed in the development of integrated circuit (IC) chip basically, the integrated level that is semiconductor chip is with per speed increment of doubling in 18 months, this makes the design of integrated circuit develop towards the direction of SOC (system on a chip) integrated (SOC), and a key technology that the realizes SOC on-chip memory that to be exactly low-power consumption, high density, access speed fast is integrated.Integrated circuit (IC)-components technology of today has been in about 30 nanometers, but traditional floating boom (Flash) memory since coupling ratio and voltage than problems such as height, be difficult to narrow down to below 30 nanometers, therefore novel non-volatility memorizer be developed to focus for current research.Phase transition storage and resistance-variable storing device can be as novel memories.
Phase transition storage (phase change memory) is to utilize the huge conductivity difference of chalcogenide when crystalline state and amorphous state to store data.The phase transformation chalcogenide can show reversible phase transition phenomena when turning to crystalline phase by amorphous phase, when amorphous phase, material is highly unordered state, does not have the network of crystalline solid.Under this kind state, material has high impedance and high reflectance.On the contrary, in crystalline phase, material has the crystal structure of rule, has Low ESR and antiradar reflectivity.The phase transition storage utilization be exactly two alternate impedance contrasts.The violent heat that inject to produce by electric current can atarting material phase transformation.Material character after the phase transformation is by the electric current that injects, voltage and operating time decision.Fig. 1 is the profile of a typical phase-changing memory unit, and as shown in Figure 1, one deck chalcogenide layer 100 is clipped between apex electrode 105 and the bottom electrode 101, bottom electrode 101 extended heating resistor 102 contact chalcogenide layers 100.Electric current injects the Joule heat that produces behind the tie point of heating resistor 102 and chalcogenide layer 100 and causes phase transformation, in crystal structure chalcogenide layer 100, produced the zone 103 of amorphous phase, the zone 104 for crystallization to the zone, because the difference of reflectivity, amorphous phase zone 103 present the shape as the mushroom cap.Fig. 2 is the summary equivalent circuit diagram of a phase-changing memory unit, as shown in Figure 2, phase-changing memory unit 106 comprises 1 transistor 107 and a phase-change element 108, a source/drain (S/D) ground connection of transistor 107, and another S/D of transistor 107 is connected with an end of phase-change element 108.The grid of transistor 107 and grid voltage V GConnect.The other end of phase-change element 108 and bit-line voltage V BLConnect.When wanting the data of the storage in the access phase-change element 108, voltage V GPut on transistor 107, and turn-on transistor 107, and bit-line voltage V BLPut on phase-change element 108, make one to read electric current through phase-change element 108 and transistor 107.Based on the size of output current, the data that are stored in phase-change element 120 are read.Compare with traditional Flash floating-gate memory, phase transition storage has and writes faster and erasing speed and better scaling.
The Card read/write of resistance-variable storing device is to rely on the resistance read or to change the resistive material to realize.Fig. 3 is the basic structure schematic diagram of a resistance-variable storing device.As shown in Figure 3, between top electrode 109 and bottom electrode 111, be provided with electric resistance converting storage layer 110.Top electrode 109 and bottom electrode 111 use the more stable metal materials of chemical property such as Pt and Ti usually, and electric resistance converting storage layer 110 is generally TiO 2, ZrO, Cu 2O and SrTiO 3Etc. binary or ternary metal oxide.The resistance value of electric resistance converting storage layer 110 can have two kinds of no states under the applied voltage effect, i.e. high-impedance state and low resistance state, and it can be used for characterizing " 0 " and " 1 " two states respectively.Under the effect of different applied voltages, but the resistance value of resistance-variable storing device can realize inverse conversion between high-impedance state and low resistance state, realizes the function of information stores with this.In the read-write operation of resistance-variable storing device, binary message 0 of General Definition high-impedance state storage, binary message 1 of low resistance state storage.Because the initial resistance state of resistive material is a high-impedance state, therefore will write 1 operation (corresponding resistive material transfers low resistance state to by high-impedance state) to information bit and be defined as write operation, be defined as erase operation and write 0 operation (corresponding resistive material transfers high-impedance state to by low resistance state) to information bit.The device write operation, generally need between top electrode and hearth electrode, apply the short potential pulse of about 1-5V, and suitable maximum current limit is set, owing to increasing several magnitudes suddenly, electric current causes component failure to avoid the resistive material to turn to by high-impedance state in the process of low resistance state.The erase operation of device generally need apply and write voltage in the same way or the short potential pulse of reverse about 0.5-1V.The voltage pulse width that is used to write and wipe is decided on concrete resistive material behavior from not waiting to microseconds up to a hundred tens of nanoseconds.The erasing voltage width is generally greater than writing pulse duration.Reading of device stores information can be by applying the small voltage about 0.2V and detecting corresponding size of current and realize.Because the resistivity of material itself and the yardstick of material are irrelevant, therefore the memory property of resistance-variable storing device can't be degenerated along with dwindling of device size in theory.This has just determined the potential integration capability of resistance-variable storing device to be higher than the Flash floating-gate memory of current main-stream far away.On the other hand, the device architecture of resistance-variable storing device is simple, can realize integrated with existing C MOS production technology easily.
But phase transition storage and resistance-variable storing device all need bigger erasable electric current, therefore need special array access device to carry out erasable to it.
Summary of the invention
The objective of the invention is to propose a kind of organization of semiconductor memory, this organization of semiconductor memory can adopt special array access device to carry out operation to semiconductor memory reading and writing etc.
For reaching above-mentioned purpose of the present invention, the present invention proposes a kind of organization of semiconductor memory, described organization of semiconductor memory comprises that the memory cell of a resistance-variable and one are used for the tunneling field-effect transistor structure that semiconductor memory is operated; Wherein, described tunneling field-effect transistor comprises a source electrode, a drain electrode, a low-doped channel region and a grid; Any one in the grid of described tunneling field-effect transistor and many word lines is connected, and any one in its source electrode and the many source lines is connected, and its variable-resistance two ends are connected to the drain electrode of bit line and described tunneling field-effect transistor respectively.
The method of controlling of this organization of semiconductor memory comprised reset, set, read three steps.
Reset process to described organization of semiconductor memory is: the source line that links to each other with described semiconductor memory is applied first voltage; The word line that links to each other with described organization of semiconductor memory is applied second voltage; The bit line that links to each other with described organization of semiconductor memory is applied the 3rd voltage; The p-n junction diode that makes tunneling field-effect transistor in the described organization of semiconductor memory thus is by forward bias, and this organization of semiconductor memory is reset, and it is big that its resistance becomes.
Further, the scope of described first voltage is that 0.1 V is to 4 V; The scope of described second voltage is that-1 V is to 1 V; The scope of described the 3rd voltage is that 0 V is to 3 V.
Set step to described organization of semiconductor memory is: the source line that links to each other with described organization of semiconductor memory is applied the 4th voltage; The word line that links to each other with described organization of semiconductor memory is applied the 5th voltage; The bit line that links to each other with described organization of semiconductor memory is applied the 6th voltage; Described organization of semiconductor memory is set, and its resistance diminishes.
Further, the scope of described the 4th voltage is that 0 V is to-3 V; The scope of described the 5th voltage is that 0 V is to 10 V; The scope of described the 6th voltage is that 0.1 V is to 3 V.
Read step to described organization of semiconductor memory is: the source line that links to each other with described organization of semiconductor memory is applied the 7th voltage; The word line that links to each other with described organization of semiconductor memory is applied the 8th voltage; The bit line that links to each other with described organization of semiconductor memory is applied the 9th voltage; Thus, based on the size of output current, be stored in selected the reading of data in the organization of semiconductor memory.
Further, the scope of described the 7th voltage is that 0 V is to-3 V; The scope of described the 8th voltage is that 0 V is to 10 V; The scope of described the 9th voltage is that 0.1 V is to 2 V.
Further, the drain region of the tunneling field-effect transistor in the organization of semiconductor memory that the present invention proposes is in a top perpendicular to the platform structure of horizontal surface, what this platform structure adopted is semiconductor substrate materials, described source electrode is in the outward extending substrate in described platform structure bottom, described low-doped channel region is between described drain electrode and the source electrode, and the described grid position that the doped regions of this platform structure is following covers with control by the source electrode of channel region and the size of current between the drain electrode.Described Semiconductor substrate is the silicon (SOI) on monocrystalline silicon, polysilicon or the insulator.Described gate stack comprises at least one conductive layer and the insulating barrier with described conductive layer and the isolation of described Semiconductor substrate, described conductive layer is polysilicon, amorphous silicon, tungsten metal, titanium nitride, tantalum nitride or metal silicide, and described insulating barrier is SiO 2, HfO 2, HfSiO, HfSiON, SiON or Al 2O 3, perhaps several mixture among them.
Described grid conducting layer forms the abutment wall structure around being looped around vertical low-doped channel region, and the memory cell of resistance-variable is made of phase-change material or the resistive material constitutes.
By device architecture proposed by the invention, can also form a kind of array of organization of semiconductor memory.The control method of the array of this organization of semiconductor memory can reset to a plurality of memories in the semicondctor storage array earlier, again individual memory is wherein carried out set.
The control method of organization of semiconductor memory of the present invention adopt tunneling field-effect transistor carry out to organization of semiconductor memory erasable, operation such as read, vertical gate control diode structure not only can satisfy the big current requirements that resistance-variable storing device and phase transition storage are write in the tunneling field-effect transistor, and can improve the density of memory device array, be highly suitable for the manufacturing of semiconductor memory chips, and its control method and control circuit are also comparatively simple.
Description of drawings
Fig. 1 is the profile of a typical phase-changing memory unit.
Fig. 2 is the summary equivalent circuit diagram of a phase-changing memory unit.
Fig. 3 is the profile of a typical resistance-variable storing device unit.
Fig. 4 is the vertical view of a kind of organization of semiconductor memory embodiment provided by the invention.
Fig. 5 is the sectional view of a kind of organization of semiconductor memory embodiment provided by the invention.
Fig. 6 is the equivalent circuit diagram of a kind of organization of semiconductor memory embodiment provided by the invention.
Fig. 7 is an equivalent circuit diagram that organization of semiconductor memory array control method embodiment resets provided by the invention.
Fig. 8 is an equivalent circuit diagram that semicondctor storage array control method embodiment carries out set provided by the invention.
Fig. 9 is an equivalent circuit diagram that semicondctor storage array control method embodiment reads provided by the invention.
Embodiment
Below with reference to accompanying drawings an exemplary embodiment of the present invention is elaborated.In the drawings, for convenience of description, amplified or dwindled the thickness in layer and zone, shown in size do not represent actual size.Reference diagram is the schematic diagram of idealized embodiment of the present invention, and embodiment shown in the present should not be considered to only limit to the given shape in zone shown in the figure, but comprises resulting shape, the deviation that causes such as manufacturing.For example the curve that obtains of etching has crooked or mellow and full characteristics usually, but in embodiments of the present invention, all represents with rectangle, and the expression among the figure is schematically, but this should not be considered to limit the scope of the invention.Simultaneously in the following description, employed term wafer and substrate can be understood as and comprise the just semiconductor wafer in processes, may comprise other prepared thin layer thereon.
As Fig. 4 is the vertical view of the control method of a kind of organization of semiconductor memory provided by the present invention, and Fig. 5 is the sectional view of a kind of organization of semiconductor memory provided by the present invention.As Fig. 4 and Fig. 5, shown in 200 Semiconductor substrate for providing; Shown in 201 be n type ion doping zone; Shown in 202 be SiO 2Gate medium; Shown in 203 be high k material gate medium; Shown in 204 be grid conducting layer such as being TiN or TaN, grid conducting layer 204 forms the abutment wall structure around being looped around vertical raceway groove; Shown in 205 be polysilicon; Shown in 202,203,204 and 205 grids that constitute tunneling field-effect transistors, and the raceway groove of this grid covering device and described raceway groove are vertical with the residing substrate surface of this tunneling field-effect transistor; Shown in 206 be p type ion doping zone; Shown in 208 be by SiO 2, Si 3N 4The insulating barrier of the insulating material formation of perhaps mixing mutually between them; Shown in 208 memory cell that are used for stored charge for constituting by phase-change material or resistive material; Shown in 209 be the metal electrode that links to each other with memory cell 208, can be TiN, Ti, Ta or TaN.The grid of tunneling field-effect transistor can be controlled the electric current by memory cell 208, and realizes the read-write operation to memory cell 208.
Fig. 6 is the equivalent circuit diagram of a kind of organization of semiconductor memory control method provided by the invention.As shown in Figure 6, bit line BL is connected with metal electrode 209, and word line WL is connected with the grid of described tunneling field-effect transistor, and source line SL is connected with the source electrode or the drain electrode of described tunneling field-effect transistor.
Can constitute a semicondctor storage array by a plurality of semiconductor memories as shown in Figure 5, as Fig. 7, Fig. 8 and Fig. 9 be respectively to a semicondctor storage array reset, set and the equivalent circuit diagram that reads.
Specifically, step such as Fig. 7 that semicondctor storage array is resetted:
Source line SL1 and SL2 are all applied voltage 2V;
Word line WL1, WL2, WL3 and WL4 are all applied voltage 0V;
Pairs of bit line BL1 applies voltage 0V, and pairs of bit line BL2 applies voltage 2V.
Because SL2=BL2=2V, therefore with in the memory that BL2 links to each other there is not the electric current process, and BL1=0V＜SL1=0V, therefore the p-n of the tunneling field-effect transistor that links to each other with BL1 is by forward bias, the electric current process is arranged, and the memory that links to each other with BL1 is selected to be resetted, and it is big that its resistance becomes.
Semicondctor storage array is carried out step such as Fig. 8 of set:
Source line SL1 and SL2 are all applied voltage 0V;
Word line WL1, WL3 and WL4 are all applied voltage 0V, word line WL2 is applied voltage 3V;
Pairs of bit line BL1 applies voltage 1V, and pairs of bit line BL2 applies voltage 0V.
Because WL2=3V〉SL1=0V, the p-n of the tunneling field-effect transistor among Fig. 8 shown in 301 is reverse biased, the selected set of the memory shown in 301, its resistance diminishes.
Step such as Fig. 9 that semicondctor storage array is read:
Source line SL1 and SL2 are all applied voltage 0V;
Word line WL1, WL3 and WL4 are all applied voltage 0V, word line WL2 is applied voltage 3V;
Pairs of bit line BL1 and bit line BL2 apply voltage 0.5V.
Based on the size of electric current, the data that store in the memory cell among Fig. 9 shown in 302 are read.For preventing set operation, the voltage that is applied to bit line WL in the read step should be lower than the voltage that is applied to bit line WL in the set step.
As mentioned above, under the situation that does not depart from spirit and scope of the invention, can also constitute many very embodiment of big difference that have.Should be appreciated that except as defined by the appended claims, the invention is not restricted at the instantiation described in the specification.

Claims (10)

1. organization of semiconductor memory is characterized in that: comprise that the memory cell of a resistance-variable and one are used for the tunneling field-effect transistor structure that semiconductor memory is operated;
Wherein, described tunneling field-effect transistor comprises a source electrode, a drain electrode, a low-doped channel region and a grid;
Any one in the grid of described tunneling field-effect transistor and many word lines is connected, and any one in its source electrode and the many source lines is connected, and its variable-resistance two ends are connected to the drain electrode of bit line and described tunneling field-effect transistor respectively.
2. organization of semiconductor memory according to claim 1, it is characterized in that: the drain region of described tunneling field-effect transistor is in a top perpendicular to the platform structure of horizontal surface, what this platform structure adopted is semiconductor substrate materials, described source electrode is in the outward extending substrate in described platform structure bottom, described low-doped channel region is between described drain electrode and the source electrode, and the described grid position that the doped regions of this platform structure is following covers with control by the source electrode of channel region and the size of current between the drain electrode.
3. organization of semiconductor memory according to claim 1 and 2 is characterized in that: described Semiconductor substrate is the silicon on monocrystalline silicon, polysilicon or the insulator; Described gate stack comprises at least one conductive layer and the insulating barrier with described conductive layer and the isolation of described Semiconductor substrate, described conductive layer is polysilicon, amorphous silicon, tungsten metal, titanium nitride, tantalum nitride or metal silicide, and described insulating barrier is SiO 2, HfO 2, HfSiO, HfSiON, SiON or Al 2O 3, perhaps several mixture among them.
4. organization of semiconductor memory according to claim 1 and 2 is characterized in that: described grid conducting layer forms the abutment wall structure around being looped around vertical low-doped channel region; The memory cell of described resistance-variable is made of phase-change material or the resistive material constitutes.
5. as the control method of the described organization of semiconductor memory of one of claim 1-4, comprise reset, set, read operation; It is characterized in that:
As follows to described reset operation step:
The source line that links to each other with described organization of semiconductor memory is applied first voltage;
The word line that links to each other with described organization of semiconductor memory is applied second voltage;
The bit line that links to each other with described organization of semiconductor memory is applied the 3rd voltage;
The p-n junction diode that makes tunneling field-effect transistor in the described organization of semiconductor memory thus is by forward bias, and this organization of semiconductor memory is reset, and it is big that its resistance becomes;
As follows to described set operation step:
The source line that links to each other with described organization of semiconductor memory is applied the 4th voltage;
The word line that links to each other with described organization of semiconductor memory is applied the 5th voltage;
The bit line that links to each other with described organization of semiconductor memory is applied the 6th voltage;
Described organization of semiconductor memory is set, and its resistance diminishes;
As follows to described read operation step:
The source line that links to each other with described organization of semiconductor memory is applied the 7th voltage;
The word line that links to each other with described organization of semiconductor memory is applied the 8th voltage;
The bit line that links to each other with described organization of semiconductor memory is applied the 9th voltage;
Thus, based on the size of output current, the data that are stored in the described semiconductor memory are read.
6. control method according to claim 5 is characterized in that, the scope of described first voltage is that 0.1 V is to 4 V; The scope of described second voltage is that-1 V is to 1 V; The scope of described the 3rd voltage is that 0 V is to-3 V.
7. control method according to claim 5 is characterized in that, the scope of described the 4th voltage is that 0 V is to-3 V; The scope of described the 5th voltage is that 0 V is to 10 V; The scope of described the 6th voltage is that 0.1 V is to 3 V.
8. control method according to claim 5 is characterized in that, the scope of described the 7th voltage is that 0 V is to-3 V; The scope of described the 8th voltage is that 0 V is to 10 V; The scope of described the 9th voltage is that 0.1 V is to 2 V.
9. the array of an organization of semiconductor memory is characterized in that being made up of the described organization of semiconductor memory of one of claim 1-4.
10. the control method of the array of organization of semiconductor memory as claimed in claim 9 is characterized in that, earlier a plurality of memories in the semicondctor storage array is resetted, and again individual memory is wherein carried out set.
CN2011101198590A 2011-05-10 2011-05-10 Semiconductor memory structure and control method thereof Pending CN102185108A (en)

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Cited By (3)

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Publication number Priority date Publication date Assignee Title
CN104037322A (en) * 2013-03-07 2014-09-10 华邦电子股份有限公司 Resistive memory and memory cell thereof
WO2023087804A1 (en) * 2021-11-17 2023-05-25 北京大学 Embedded semiconductor random access memory structure and control method therefor
WO2024041049A1 (en) * 2022-08-23 2024-02-29 International Business Machines Corporation Back side phase change memory

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US7880160B2 (en) * 2006-05-22 2011-02-01 Qimonda Ag Memory using tunneling field effect transistors
US20090034355A1 (en) * 2007-07-30 2009-02-05 Qimonda Ag Integrated circuit including memory cells with tunnel fet as selection transistor
CN101777570A (en) * 2009-12-30 2010-07-14 复旦大学 Semiconductor memory structure utilizing self-aligning process and manufacturing method thereof
CN101807596A (en) * 2010-01-21 2010-08-18 复旦大学 Autoregistration semiconductor memory structure and manufacturing method thereof

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104037322A (en) * 2013-03-07 2014-09-10 华邦电子股份有限公司 Resistive memory and memory cell thereof
WO2023087804A1 (en) * 2021-11-17 2023-05-25 北京大学 Embedded semiconductor random access memory structure and control method therefor
WO2024041049A1 (en) * 2022-08-23 2024-02-29 International Business Machines Corporation Back side phase change memory

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Application publication date: 20110914