JP2008021968A - Method of operating non-volatile memory element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multi-bit operation method of a non-volatile memory element operating at a low operating current and permitting high integration. <P>SOLUTION: A method of operating a non-volatile memory element comprises: a step of programming two-bit data into a first resistive layer 122 and a second resistive layer 124 by using a first embedded electrode 112 as a first bit line BL1, a second embedded electrode 114 as a second bit line BL2, and a gate electrode 132 as a word line; and a step of reading the two-bit data that is programmed in the first resistive layer 122 and the second resistive layer 124. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly, to a method for operating a nonvolatile memory device using a resistance node.

  A non-volatile memory device, for example, a phase-change memory device (PRAM) or a resistive memory device (Resistive Random Access Memory: RRAM) operates using a variable resistance state of a resistance node. Recently, with the increase in semiconductor products that require high-capacity data processing, improvement in the degree of integration of such nonvolatile memory elements or improvement in operation bits has been demanded. For example, there is an increasing need for non-volatile memory devices that can operate in multiple bits.

  On the other hand, as described above, the capacity of the nonvolatile memory element is increased at the same time as the capacity is increased. That is, in order to process high-capacity data, high-speed data processing is required. Therefore, an increase in the operation speed of the non-volatile memory device, for example, a block erase or flash erase characteristic like a flash memory device is required.

  In addition, efforts have been made to reduce the operating current by improving the degree of integration of nonvolatile memory elements. However, a nonvolatile memory element using a resistance node requires a relatively high operating current. The decrease in operating current can affect the state of the variable resistance of the resistance node. Therefore, the conventional nonvolatile memory device has a limit in reducing the operating current.

  For example, the PRAM stores data using a resistance change caused by a change in the crystal state of the phase transition resistor. However, in order to change the crystal state of the PRAM, a high current density is required, which increases the operating current. Such an increase in the operating current induces a short channel effect and may hinder the improvement of the integration degree of the PRAM device. Therefore, efforts are being made to obtain a high current density with a small operating current by reducing the change region of the crystalline state of the phase change resistor.

  The technical problem to be solved by the present invention is to overcome the above-mentioned problems, and provides a multi-bit operation method of a non-volatile memory device that operates at a low operating current and can be highly integrated. There is a place to do.

  A method for operating a nonvolatile memory device according to an aspect of the present invention for solving the technical problem is provided. The nonvolatile memory element is formed in the vicinity of a semiconductor substrate, a surface of the semiconductor substrate, and a first resistance layer and a second resistance layer that store a variable resistance state, and the lower side of the first resistance layer. A first embedded electrode formed on a portion of the semiconductor substrate and connected to the first resistance layer; and formed on a portion of the semiconductor substrate below the second resistance layer and connected to the second resistance layer. A second buried electrode; a gate electrode formed on the semiconductor substrate, extending across the first resistance layer and the second resistance layer; and a gate insulating film between the semiconductor substrate and the gate electrode. . The operation method of the nonvolatile memory device uses the first embedded electrode as a first bit line, the second embedded electrode as a second bit line, and the gate electrode as a word line. The non-volatile memory device may be operated by programming 2-bit data in the first resistance layer and the second resistance layer, and 2-bit data programmed in the first resistance layer and the second resistance layer. Reading data.

  According to one aspect of the present invention, the step of programming the 2-bit data can be performed by changing the resistances of the first resistance layer and the second resistance layer in two states.

  According to another aspect of the present invention, the step of reading the 2-bit data includes the first bit line and the second bit line according to changes in resistance values of the first resistance layer and the second resistance layer. This can be done by measuring the change in current during

  According to still another aspect of the present invention, the step of reading the 2-bit data forms a deep channel to connect one of the buried electrodes and one of the adjacent resistance layers, and the first bit. The method may include sequentially measuring a bidirectional current value between a line and the second bit line.

  According to another aspect of the present invention, the method of operating the nonvolatile memory device may further include simultaneously erasing data stored in the first resistance layer and the second resistance layer.

  A method for operating a nonvolatile memory device according to another aspect of the present invention for solving the technical problem is provided. The nonvolatile memory element is formed in the vicinity of a semiconductor substrate, a surface of the semiconductor substrate, a plurality of resistance layers for storing a variable resistance state, and a portion of the semiconductor substrate below the plurality of resistance layers. A plurality of buried electrodes respectively formed and connected to the plurality of resistance layers; a gate electrode extending across the plurality of resistance layers; and a gate insulating film between the semiconductor substrate and the gate electrode. Prepare. The operation method of the nonvolatile memory device uses the plurality of embedded electrodes as a plurality of bit lines and the gate electrode as a word line. The non-volatile memory device may be operated by programming 2-bit data in two adjacent resistance layers of the plurality of resistance layers, and 2-bit programmed in the two adjacent resistance layers. Reading the data.

  According to the operation method of the nonvolatile memory element according to the present invention, the operating current, for example, the program current can be lowered.

  In addition, according to the operation method of the nonvolatile memory device according to the present invention, 2-bit data can be processed in one unit cell.

  In addition, according to the operation method of the nonvolatile memory device according to the present invention, block erasure or flash erasure is possible, and thus the operation speed can be improved.

  Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and may be embodied in various different forms. The embodiments are merely a complete disclosure of the present invention and are disclosed to those skilled in the art. It is provided to fully inform the category. The components in the drawings are exaggerated in size for convenience of explanation.

  The nonvolatile memory device according to the embodiment of the present invention can store data using a resistance node or a resistance layer. Therefore, the nonvolatile memory device according to the embodiment of the present invention may be referred to by other names depending on the type of the resistance node or the resistance layer. For example, the nonvolatile memory device according to the embodiment of the present invention may include a PRAM or an RRAM, but the scope of the present invention is not limited to such names.

  FIG. 1 is a schematic perspective view illustrating a nonvolatile memory device according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line III-III of the nonvolatile memory device of FIG.

As shown in FIGS. 1 and 2, the nonvolatile memory element includes a semiconductor substrate 102. However, the semiconductor substrate 102 is not shown in FIG. 1 for convenience of explanation. The semiconductor substrate 102 may include a silicon (Si) wafer, a germanium (Ge) wafer, or a metal-insulator transition (MIT) material. For example, the MIT material can include a transition metal oxide, such as V ₂ O ₅ , TiO _x . Such an MIT material can change from an insulator to a metal when a voltage higher than a predetermined critical voltage is applied. Such an MIT material can be used to form a semiconductor device having a plurality of layers.

  The plurality of resistance layers 122, 124, 126, and 128 are formed near the surface of the semiconductor substrate 102, respectively. The plurality of buried electrodes 112, 114, 116, and 118 are formed on portions of the semiconductor substrate 102 below the resistance layers 122, 124, 126, and 128, respectively. The gate electrode 132 is formed on the semiconductor substrate 102 and may be disposed to extend across the resistance layers 122, 124, 126, and 128. The gate insulating layer 130 may be interposed between the semiconductor substrate 102 and the gate electrode 132. Optionally, bit lines BL 1, BL 2, BL 3, BL 4 may be further formed on the semiconductor substrate 102.

  For example, the embedded electrodes 112, 114, 116, and 118 may be provided in a form embedded in the semiconductor substrate 102. The embedded electrodes 112, 114, 116, and 118 are referred to as various forms depending on their functions or arrangements, and the scope of the present invention is not limited by their names. For example, the buried electrodes 112, 114, 116, and 118 may be sequentially referred to as a source S and a drain D, or the buried electrodes 112, 114, 116, and 118 are referred to as a lower electrode depending on the arrangement on the position. May be.

  For example, the buried electrodes 112, 114, 116, and 118 can be formed by doping the semiconductor substrate 102 with impurities. In this case, when the semiconductor substrate 102 is doped with the first conductivity type impurity, the buried electrodes 112, 114, 116, and 118 may be doped with the second conductivity type impurity opposite to the first conductivity type. Thereby, the buried electrodes 112, 114, 116, 118 and the semiconductor substrate 102 can form a diode junction. The first conductivity type and the second conductivity type may be any one selected from n-type and p-type, respectively.

  As another example, the buried electrodes 112, 114, 116, 118 can comprise a metal layer or a metal silicide layer. In this case, the embedded electrodes 112, 114, 116, and 118 can form a Schottky junction with the semiconductor substrate 102. With such a Schottky junction, the current flow between the buried electrodes 112, 114, 116, and 118 and the semiconductor substrate 102 can have a rectifying characteristic.

  The gate insulating film 130 can serve to insulate the gate electrode 132 from the semiconductor substrate 102. Further, since the gate insulating film 130 further extends on the resistance layers 122, 124, 126, and 128, the resistance layers 122, 124, 126, and 128 can be further insulated from the gate electrode 132. The thickness of the gate insulating film 130 is appropriately selected according to the operating voltage, and is not limited by the size shown in FIGS. For example, the gate electrode 132 may include a conductive material, such as a polysilicon layer or a metal layer.

  Bit lines BL1, BL2, BL3, and BL4 are formed on gate electrode 132 with interlayer insulating film 160 interposed. The bit lines BL1, BL2, BL3, and BL4 are connected to the buried electrodes 112, 114, 116, and 118 via plugs 135, respectively. For example, the bit lines BL 1, BL 2, BL 3, BL 4 may extend in a direction different from the extending direction of the gate electrode 132, for example, a direction parallel to the buried electrodes 112, 114, 116, 118. For example, the bit lines BL1, BL2, BL3, and BL4 may include a metal layer.

  The plurality of resistance layers 122, 124, 126, 128 store variable resistance states, and such variable resistance states can be stored as data bits. For example, the resistance layers 122, 124, 126, and 128 have a low resistance state and a high resistance state, and the low resistance state and the high resistance state may correspond to the data state “0” or “1”, respectively. . If two or more resistance layers 122, 124, 126, 128 are combined, a data state of 2 bits or more may be formed. For example, if two resistance layers are used, a 2-bit data state of (0, 0), (0, 1), (1, 0) and (1, 1) states can be formed.

For example, the resistance layers 122, 124, 126, and 128 include a material whose resistance state changes depending on a voltage applied to both ends, for example, SrTiO ₃ or ZrO _x doped with Nb ₂ O ₅ or chromium (Cr). _{, GST (GeSb x Te y)} , may include NiO, ZnO, selected from the group consisting of TiO ₂ and HfO the at least one, respectively. For example, GST can be used in a PRAM in that its resistance changes with changes in its crystalline state. As another example, SrTiO ₃ , NiO, or ZnO doped with Nb ₂ O ₅ , chromium (Cr) can be used for RRAM in that its resistance changes without changing its crystalline state.

  As shown in FIG. 3, the voltage-current characteristics of the resistance layer used in the RRAM element will be described in more detail by way of example. FIG. 3 is a graph illustrating NiO as an example of the resistance layer. Depending on the material of the resistance layer, graphs having other shapes can be formed. However, this is common in that the resistance can be changed depending on the applied voltage.

  As shown in FIG. 3, when an initial voltage is applied to the resistance layer (P10), in the case of a set voltage, for example, NiO, current hardly flows up to 4.5V. That is, the resistance layer exhibits a high resistance value (reset state). However, if the set voltage is exceeded, the current increases rapidly. Once a voltage equal to or higher than the set voltage is applied, if a voltage is applied again from 0 (P20), a high current flows. That is, the resistance layer exhibits a low resistance value (set state). However, if the voltage increases again above the reset voltage, the current rapidly decreases (P30). That is, the resistance of the resistance layer is reduced again to a high resistance value in the reset state. Thereafter, if the voltage is continuously raised before reaching the set voltage (P40), the same path as in the initial reset state is shown.

  That is, the resistivity of the resistive layer changes with a critical voltage, for example, a set voltage or a reset voltage as a boundary, and such a change in specific resistance is maintained within a voltage range of a certain range even after the applied voltage disappears. Is done. Therefore, the resistance layer can be used as a recording medium for a nonvolatile memory element.

  The description relating to the resistance layer in FIG. 3 is an example of what is used in the RRAM, and the resistance layer used in the PRAM can experience a resistance change in other ways. A resistance layer used in PRAM is called a phase change resistor, and such a phase change resistor can change its resistance state through a structural change, for example, a transition to an amorphous state and a crystalline state. . Such resistance change characteristics of the phase change resistor are well known to those skilled in the art, and a detailed description thereof will be omitted.

  On the other hand, in the above-described embodiment, a pair of adjacent ones of the resistance layers 122, 124, 126, and 128, for example, the first resistance layer 122 and the second resistance layer 124 may form a unit cell structure. In this case, the first buried electrode 112, the second buried electrode 114, the first bit line BL1, and the second bit line BL2 can be part of the structure of such a unit cell.

  The nonvolatile memory device according to the embodiment of the present invention is not limited to the arrangement shown in FIGS. Therefore, the nonvolatile memory device may include a single unit cell structure or a plurality of unit cell structures. That is, the resistance layers 122, 124, 126, 128, the buried electrodes 112, 114, 116, 118, and the bit lines BL1, BL2, BL3, BL4 are simply provided as pairs, and the number does not limit the scope of the present invention. .

  Hereinafter, operation characteristics of the nonvolatile memory device will be described.

  4 and 5 are cross-sectional views illustrating a program operation of the nonvolatile memory device according to the embodiment of the present invention.

  As shown in FIGS. 4 and 5, in this embodiment, the first resistance layer 122 and the second resistance layer 124 form one unit cell, and the third resistance layer 126 and the fourth resistance layer 128 form another unit cell. A cell is formed. Although FIG. 4 and FIG. 5 illustrate that two unit cells operate simultaneously, the two unit cells may operate separately. Further, the configuration of the unit cell may be provided in other forms, for example, the second resistance layer 124 and the third resistance layer 126 may be provided to form one unit cell. On the other hand, the gate electrode 132 can be used as a word line.

  As shown in FIG. 4, a program operation of one resistance layer selected from two unit cells, for example, the first resistance layer 122 and the third resistance layer 126 will be described as an example. With this program operation, data can be stored in the right portion of the first resistance layer 122 and the right portion of the third resistance layer 126. As described above, such a data program can be performed by changing the resistances of the first resistance layer 122 and the third resistance layer 126 in two states.

  For example, the program voltage is applied to the first bit line BL1, and the turn-on voltage is applied to the word line, that is, the gate electrode 132 so that the deep channel 104 connecting the second buried electrode 114 and the first resistance layer 122 is formed. Apply. The deep channel 104 is formed deeper in the vicinity of the second bit line BL2 than in the vicinity of the first bit line B1. For example, the depth of the deep channel 104 can be controlled by adjusting the turn-on voltage applied to the gate electrode 132 or the concentration of impurities in the semiconductor substrate 102.

Accordingly, the program current I _P1 flows from the first bit line BL1 through the first buried electrode 112, the first resistance layer 122, the deep channel 104, and the second buried electrode 114 in the direction of the second bit line BL2. Since the deep channel 104 connects the first resistance layer 122 and the second buried electrode 114, the amount of the program current I _P1 passing through the second resistance layer 124 having a relatively high resistance is negligible.

Similarly, a program voltage is applied to the third bit line BL3 to turn on the word line, that is, the gate electrode 132 so that the deep channel 104 connecting the fourth buried electrode 118 and the third resistance layer 126 is formed. Apply voltage. Accordingly, the program current I _P2 flows from the third bit line BL3 through the third buried electrode 116, the third resistance layer 126, the deep channel 104, and the fourth buried electrode 118 in the direction of the fourth bit line BL4.

  Therefore, a program current flows through the first resistance layer 122 and the third resistance layer 126, and the resistances of the first resistance layer 122 and the third resistance layer 126 may change. For example, if the state before programming is set to a low resistance state, for example, “0” state, the first resistance layer 122 and the third resistance layer 126 can be set to a high resistance state, for example, “1” state by programming. For example, the program voltage may be a voltage for bringing the phase change resistor into an amorphous state. However, the data states “0” and “1” may be displayed in reverse.

  As a result, the two unit cells can be converted from the (0, 0) state to the (1, 0) state by the program operation of FIG. For example, in the (0, 0) state, two resistance layers in the unit cell, for example, the first resistance layer 122 and the second resistance layer 124 or the third resistance layer 126 and the fourth resistance layer 128 are both in a low resistance state. Represents the case. In the (1, 0) state, the left resistance layer in the unit cell, for example, the first resistance layer 122 or the third resistance layer 126 is in a high resistance state, and the right resistance layer, for example, the second resistance layer 124 or the fourth resistance layer. This represents a case where the resistance layer 128 is in a low resistance state.

  As shown in FIG. 5, the program operation of different resistance layers selected from two unit cells, for example, the second resistance layer 124 and the fourth resistance layer 128 will be described as an example. With this program operation, data can be stored in the left part of the second resistance layer 124 and the left part of the fourth resistance layer 128. The program operation of FIG. 5 can be performed by reversing the current direction in the program operation of FIG.

  For example, a program voltage is applied to the second bit line BL2 and the fourth bit line BL4 to deeply connect the first buried electrode 112 and the second resistance layer 124, or the third buried electrode 116 and the fourth resistance layer 128, respectively. A turn-on voltage is applied to the word line, that is, the gate electrode 132 so that the channel 104 is formed.

Accordingly, the program current I ′ _P1 flows from the second bit line BL2 to the first bit line BL1, and the program current I ′ _P2 flows from the fourth bit line BL4 to the third bit line BL3. Accordingly, a program current flows through the second resistance layer 124 and the fourth resistance layer 128, and the resistances of the second resistance layer 124 and the fourth resistance layer 128 can be changed.

  As a result, the two unit cells can be converted from the (0, 0) state to the (0, 1) state by the program operation of FIG. In the (0, 1) state, the right resistance layer in the unit cell, for example, the second resistance layer 124 or the fourth resistance layer 128 is in a high resistance state, and the left resistance layer, for example, the first resistance layer 122 or the third resistance layer. This represents a case where the resistance layer 126 is in a low resistance state.

  On the other hand, if the program operation of FIG. 4 and FIG. 5 is sequentially performed on the two unit cells, the two unit cells change from the (0,0) state to the (1,1) state via the (1,0) state, respectively. Can be converted to In the (1, 1) state, two resistance layers in the unit cell, for example, the first resistance layer 122 and the second resistance layer 124, or the third resistance layer 126 and the fourth resistance layer 128 are both in a high resistance state. Represents a case. Therefore, if the program operation of FIG. 4 and / or FIG. 5 is used, the unit cell has four states, that is, (0, 0), (1, 0), (0, 1) and (1, 1), respectively. Therefore, 2-bit data can be stored.

With the above-described program operation, the resistance change region of the resistance layer becomes a local portion in contact with the deep channel 104. Therefore, the program operation can be performed with only the low program currents I _P1 , I _P2 , I ′ _P1 , I ′ _P2 .

  6 and 7 are cross-sectional views illustrating a reading operation according to an embodiment of the present invention.

  As shown in FIG. 6, a read voltage is applied to the first bit line BL1 and the third bit line BL3, respectively, and the second embedded electrode 114 and the first resistance layer 122 or the fourth embedded electrode 118 and the third resistance layer 126 are applied. And a turn-on voltage is applied to the word line, that is, the gate electrode 132 so that the deep channels 104 are connected to each other. The read voltage may be a low voltage so as not to cause a resistance change of the resistance layers 122, 124, 126, and 128, and thus may be lower than the program voltage.

Thus, the read current _{I R1,} the first buried electrode 112 from the first bit line BL1, the first resistance layer 122, through a deep channel 104 and the second buried electrode 114, flows in the direction of the second bit line BL2. Read current _{I R2} is the third buried electrode 116 from the third bit line BL3, the third resistance layer 126, through a deep channel 104 and the fourth buried electrode 118, flows in the direction of the fourth bit line BL4.

Therefore, the resistance levels of the first resistance layer 122 and the third resistance layer 126 can be obtained from the levels of the read currents I _R1 and I _R2 , respectively. As described above, since the read currents I _R1 and I _R2 hardly flow through the second resistance layer 124 and the fourth resistance layer 128, the resistance levels of the first resistance layer 122 and the third resistance layer 126 can be obtained, respectively. . Accordingly, the data states of the first resistance layer 122 and the third resistance layer 126, that is, the “0” or “1” state can be read.

  As shown in FIG. 7, read voltages are applied to the second bit line BL2 and the fourth bit line BL4, respectively, and the first embedded electrode 112 and the second resistance layer 124, or the third embedded electrode 116 and the fourth resistance layer 128 are applied. And a turn-on voltage is applied to the word line, that is, the gate electrode 132 so that the deep channels 104 are connected to each other.

Accordingly, the read current I ′ _R1 flows in the direction of the first bit line BL1 from the second bit line BL2 through the second embedded electrode 114, the second resistance layer 124, the deep channel 104, and the first embedded electrode 112. The read current I ′ _R2 flows from the fourth bit line BL4 through the fourth buried electrode 118, the fourth resistance layer 128, the deep channel 104, and the third buried electrode 116 in the direction of the third bit line BL3. Therefore, the resistance levels of the second resistance layer 124 and the fourth resistance layer 128 can be obtained from the levels of the read currents I ′ _R1 and I ′ _R2 , respectively. Accordingly, the data states of the second resistance layer 124 and the fourth resistance layer 128, that is, the “0” or “1” state can be read.

Accordingly, as shown in FIGS. 6 and 7, the deep cell 104 is formed, and the unit cell is measured by measuring the bidirectional currents I _R1 and I ′ _R1 between the first bit line BL1 and the second bit line BL2. The 2-bit data programmed in the first resistance layer 122 and the second resistance layer 124 can be read. Similarly, by forming the deep channel 104 and measuring the bidirectional currents I _R2 and I ′ _R2 between the third bit line BL3 and the fourth bit line BL4, the third resistance layer 126 and the fourth of the unit cell are measured. The 2-bit data programmed in the resistance layer 128 can be read.

  FIG. 8 is a cross-sectional view illustrating a read operation of a nonvolatile memory device according to another embodiment of the present invention.

As shown in FIG. 8, a read voltage is applied to the first bit line BL1, and a shallow channel 104 ′ is formed in the semiconductor substrate 102 so as to connect the first resistance layer 122 and the second resistance layer. Accordingly, the read current I ″ _R1 is transmitted from the first bit line BL1 to the second bit through the first buried electrode 112, the first resistance layer 122, the shallow channel 104 ′, the second resistance layer 124, and the second buried electrode 114. The shallow channel 104 ′ is formed shallow so as to directly connect the resistance layers 122 and 124 and not directly connect the buried electrodes 112 and 114. For example, the shallow channel 104 ′ is added to the word line, that is, the gate electrode 132. By increasing the turn-on voltage, the shallow channel 104 ′ can be formed.

Similarly, a read voltage is applied to the third bit line BL3 to form a shallow channel 104 ′ in the semiconductor substrate 102 so as to connect the third resistance layer 126 and the fourth resistance layer 128. Accordingly, the read current I ″ _R2 is transferred from the third bit line BL3 to the fourth bit through the third buried electrode 116, the third resistance layer 126, the shallow channel 104 ′, the fourth resistance layer 128, and the fourth buried electrode 118. Flows to line BL4.

By measuring the read current I ″ _R1 , the resistance levels, that is, the data states of the first resistance layer 122 and the second resistance layer 124 are simultaneously obtained, and by measuring the read current I ″ _R2 , the third resistance layer The resistance level of 126 and the fourth resistance layer 128, that is, the data state can be obtained simultaneously. This is because the read current I ″ _R1 varies depending on the resistance levels of the first resistance layer 122 and the second resistance layer 124, and the read current I ″ varies depending on the resistance levels of the third resistance layer 126 and the fourth resistance layer 128. _This is because _R2 changes.

The difference between the read currents I ″ _R1 and I ″ _R2 is because the threshold voltage for forming the shallow channel 104 ′ depends on the source potential with respect to the semiconductor substrate 102. Here, the source may be the end of the second embedded electrode 114 and / or the second resistance layer 124 in contact with the shallow channel 104 ′, or the end of the fourth embedded electrode 118 and / or the fourth resistance layer 128. The source potential varies depending on the resistance levels of the first resistance layer 122 and the second resistance layer 124 or the resistance levels of the third resistance layer 126 and the fourth resistance layer 128.

  FIG. 10 is a graph showing a simulation result of the read operation of the nonvolatile memory element of FIG. In this simulation, the resistance of the resistance layer in the “0” state is 1 kΩ, and the resistance in the “1” state is 1 MΩ.

As shown in FIG. 10, when the read voltage was _Vb , the read current increased in the order of (1, 1), (1, 0), (0, 1), and (0, 0). However, in order to further partitioned reliably (1,0) and (1,1) state, can be further compares a read current _{V a.} For example, V _a can be about 0.6V and V _b can be about 1V. In this way, the data state of the resistance layer of the unit cell can be read by comparing one or two read currents. For example, the data state can be found by comparing the measured read current value with the read current of the already known data state.

  FIG. 9 is a cross-sectional view illustrating the erase operation of the nonvolatile memory device according to the embodiment.

  As shown in FIG. 9, data of a predetermined number of resistance layers, for example, the resistance layers 122, 124, 126, and 128 can be simultaneously erased. Such an erase operation is also called block erase or flash erase.

For example, the shallow channel 104 ′ is formed so as to connect the resistance layers 122, 124, 126, and 128, and the bit lines located at the edges of the resistance layers 122, 124, 126, and 128, that is, the first bit lines BL 1 and An erase voltage is applied between the fourth bit line BL4. As a result, the erase current _IE flows from the first bit line BL1 to the fourth bit line BL4 through the resistance layers 122, 124, 126, and 128.

The data of the resistance layers 122, 124, 126, and 128 can be erased simultaneously by the erase current _IE . For example, the resistance of the resistance layers 122, 124, 126, and 128 may be changed to a low level, and the data state may be “0”. The erase voltage can vary depending on the number of selected resistive layers 122, 124, 126, 128.

  In this embodiment, the data in the resistive layers 122, 124, 126, 128 is erased at a time and thus can have a very fast erase rate.

  The foregoing descriptions of specific embodiments of the present invention have been presented for purposes of illustration and description. The present invention is not limited to the above-described embodiments, and it goes without saying that various modifications and changes can be made by those skilled in the art, for example, by combining the embodiments within the scope of the technical idea of the present invention. .

  The present invention can be suitably used in technical fields related to nonvolatile memory elements.

1 is a schematic perspective view illustrating a nonvolatile memory device according to an embodiment of the present invention. FIG. 3 is a cross-sectional view of the nonvolatile memory element of FIG. 1 taken along line III-III. 3 is a graph illustrating exemplary voltage-current characteristics of a resistance layer of a nonvolatile memory device according to an embodiment of the present invention. FIG. 6 is a cross-sectional view showing a program operation of a nonvolatile memory element according to an embodiment of the present invention. FIG. 6 is a cross-sectional view showing a program operation of a nonvolatile memory element according to an embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a read operation of a nonvolatile memory element according to an embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a read operation of a nonvolatile memory element according to an embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a read operation of a nonvolatile memory element according to another embodiment of the present invention. FIG. 5 is a cross-sectional view showing an erase operation of a nonvolatile memory element according to an embodiment of the present invention. 9 is a graph showing a simulation result of a reading operation of the nonvolatile memory element of FIG.

Explanation of symbols

112, 114, 116, 118 Embedded electrode 122, 124, 126, 128 Resistance layer 130 Gate insulating film 132 Gate electrode 135 Plug BL1, BL2, BL3, BL4 Bit line

Claims (18)

A semiconductor substrate;
A first resistance layer and a second resistance layer, each formed near the surface of the semiconductor substrate and storing a variable resistance state;
A first embedded electrode formed on a portion of the semiconductor substrate below the first resistance layer and connected to the first resistance layer;
A second embedded electrode formed in a portion of the semiconductor substrate below the second resistance layer and connected to the second resistance layer;
A gate electrode formed on the semiconductor substrate and extending across the first resistance layer and the second resistance layer;
A non-volatile memory device operating method comprising: a gate insulating film between the semiconductor substrate and the gate electrode;
The first buried layer is used as a first bit line, the second buried electrode is used as a second bit line, and the gate electrode is used as a word line to form the first resistance layer and the second resistance layer. A method for operating a nonvolatile memory device, comprising: programming 2-bit data; and reading 2-bit data programmed in the first resistance layer and the second resistance layer.   The operation of the nonvolatile memory device according to claim 1, wherein the step of programming the 2-bit data is performed by changing resistances of the first resistance layer and the second resistance layer in two states. Method. In the programming step, the resistance change of the first resistance layer is:
A program voltage is applied to the first bit line, and a turn-on voltage is applied to the word line so that a deep channel connecting the second buried electrode and the first resistance layer is formed. The method of operating a nonvolatile memory device according to claim 2. In the programming step, the resistance change of the second resistance layer is:
A program voltage is applied to the second bit line, and a turn-on voltage is applied to the word line so as to form a deep channel connecting the first buried electrode and the second resistance layer. The method of operating a nonvolatile memory device according to claim 2. The step of reading the 2-bit data includes:
Forming a deep channel to connect one of the buried electrodes and one of the adjacent resistance layers, and sequentially measuring a bidirectional current value between the first bit line and the second bit line. The method of operating a non-volatile memory device according to claim 1. The step of reading the 2-bit data includes:
Forming a shallow channel to connect the first resistance layer and the second resistance layer, and measuring at least a one-way current value between the first bit line and the second bit line. The method of operating a non-volatile memory device according to claim 1.   7. The method of claim 6, wherein the step of measuring the one-way current value is repeated with at least two levels of read voltages.   The method of claim 1, further comprising: simultaneously erasing data stored in the first resistance layer and the second resistance layer. The step of simultaneously erasing the data comprises:
Forming a shallow channel to connect the first resistance layer and the second resistance layer, and applying an erase voltage between the first bit line and the second bit line. The method of operating a nonvolatile memory device according to claim 8. The first resistance layer and the second resistance layer may be selected from the group consisting of Nb ₂ O ₅ , chromium-doped SrTiO ₃ , ZrOx, GST (GeSb _x Te _y ), NiO, ZnO, TiO ₂ and HfO. The method of claim 1, further comprising at least one. A semiconductor substrate;
A plurality of resistance layers formed respectively near the surface of the semiconductor substrate and storing a variable resistance state;
A plurality of embedded electrodes respectively formed on portions of the semiconductor substrate below the plurality of resistance layers and connected to the plurality of resistance layers;
A gate electrode extending across the plurality of resistive layers;
A non-volatile memory device operating method comprising: a gate insulating film between the semiconductor substrate and the gate electrode;
Using the plurality of buried electrodes as a plurality of bit lines and using the gate electrode as a word line, and programming 2-bit data in two adjacent resistance layers of the plurality of resistance layers; And reading the 2-bit data programmed in the two adjacent resistance layers.   The method of claim 11, wherein the step of programming the 2-bit data is performed by changing resistances of the two adjacent resistance layers to two states. In the programming step, one resistance change of the two adjacent resistance layers is:
Forming a deep channel connecting one of the two resistance layers and one of the adjacent buried electrodes, and applying a program voltage to a bit line connected to one of the two resistance layers; The method according to claim 12, further comprising: The step of reading the 2-bit data includes:
A deep channel is formed to connect one of the two adjacent resistance layers and one of the adjacent buried electrodes, and a bidirectional current value between bit lines connected to the two adjacent resistance layers is obtained. The method of claim 12, further comprising a step of sequentially measuring. The step of reading the 2-bit data includes:
The method includes forming a shallow channel to connect the two adjacent resistance layers and measuring at least one-way current value between bit lines connected to the two adjacent resistance layers. Item 13. A method for operating a nonvolatile memory element according to Item 12.   The method of claim 15, wherein the step of measuring the one-way current value is performed with at least two levels of read voltages.   The method of claim 11, further comprising: simultaneously erasing data stored in a predetermined number of consecutive resistance layers among the plurality of resistance layers. The step of simultaneously erasing the data comprises:
Forming a shallow channel so as to connect the predetermined number of consecutive resistance layers, and applying an erase voltage to bit lines connected to the resistance layers at both ends of the predetermined number of consecutive resistance layers. 16. The method of operating a nonvolatile memory device according to claim 15, wherein:

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