WO2008041278A1 - Dispositif semi-conducteur - Google Patents

Dispositif semi-conducteur Download PDF

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Publication number
WO2008041278A1
WO2008041278A1 PCT/JP2006/319470 JP2006319470W WO2008041278A1 WO 2008041278 A1 WO2008041278 A1 WO 2008041278A1 JP 2006319470 W JP2006319470 W JP 2006319470W WO 2008041278 A1 WO2008041278 A1 WO 2008041278A1
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WO
WIPO (PCT)
Prior art keywords
voltage
circuit
semiconductor device
common data
switch
Prior art date
Application number
PCT/JP2006/319470
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English (en)
Japanese (ja)
Inventor
Akira Kotabe
Satoru Hanzawa
Original Assignee
Renesas Technology Corp.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp. filed Critical Renesas Technology Corp.
Priority to JP2008537336A priority Critical patent/JPWO2008041278A1/ja
Priority to PCT/JP2006/319470 priority patent/WO2008041278A1/fr
Priority to TW096124458A priority patent/TW200818213A/zh
Publication of WO2008041278A1 publication Critical patent/WO2008041278A1/fr

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G11C2013/0054—Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/79—Array wherein the access device being a transistor

Definitions

  • the present invention relates to a semiconductor device, and more particularly to a semiconductor device including a memory cell including an element that can vary in resistance according to stored information.
  • information is stored using a state change of a phase change material.
  • the present invention relates to a semiconductor device including a memory cell that detects a resistance difference and discriminates information.
  • Non-Patent Document 1 The document referred to in this specification is the following Non-Patent Document 1.
  • the memory element is made of a phase change material (or chalcogenide material) such as Ge—Sb—Te, Ag—In—Sb—Te, or the like containing at least antimony (Sb) and tellurium (Te). It is used as The characteristics of a memory element using a phase change material are described in, for example, [Non-Patent Document 1]. As shown in FIG. 32, when the memory information “0” is written to the memory element, a reset pulse is applied so that the memory element is heated to the melting point Ta or higher of the phase change material and rapidly cooled.
  • a reset pulse is applied so that the memory element is heated to the melting point Ta or higher of the phase change material and rapidly cooled.
  • the phase change material becomes a high resistance amorphous state (reset state).
  • the memory element is kept in a temperature region higher than the crystallization temperature Tx that is equal to or higher than the glass transition point lower than the melting point.
  • Such a set pulse is applied.
  • the phase change material becomes a low resistance polycrystalline state (set state).
  • the time t 2 required for crystallization is a force that varies depending on the composition of the phase change material, such as lus.
  • the temperature of the element shown in the figure depends on Joule heat generated by the memory element itself and thermal diffusion to the surroundings.
  • the amorphous state is associated with the stored information '0' and the crystalline state is associated with the stored information '1'.
  • the amorphous state is stored with the stored information '1', and the crystalline state is stored with the stored information '. You may make it correspond to 0 '.
  • FIG. 33 shows typical IV characteristics of a memory element using a phase change material.
  • the read operation is performed by applying a read voltage VR lower than the threshold voltage Vth and discriminating the difference in the amount of current flowing through the memory element so that the state of the memory element does not change.
  • Reading The extraction voltage VR is, for example, 0.3 V. At this time, the amount of current flowing through the memory element varies depending on the composition of the phase change material.
  • a semiconductor memory using such a resistive memory element it is desirable to trim the chip internal voltage. This is because, for example, even if a plurality of memory cells composed of memory elements using a phase change material are set or reset under the same conditions (voltage and application time), they have different resistances due to manufacturing variations. Value. If the variation in the resistance value of the memory cell in the set and reset states becomes large, there is a risk of malfunction during reading. For this purpose, it is possible to measure the current flowing through the memory cell, inspect the resistance value variation from there, and adjust the resistance value in each state so that no malfunction occurs during reading. It is desirable to be able to trim etc.
  • Non-Patent Document 1 I'I'I ', International' Electron 'Device' Meeting, Technical 'Digest, 803-806 (2001) (IEEE Alternation al Electron Devices meeting, TECHNICAL DIGEST, pp. 803-806, 2001) Disclosure of the Invention
  • the stored information is discriminated based on the magnitude of the current flowing through the memory cell, the stored information is subjected to current-voltage conversion by a sense amplifier or the like and output as voltage information. Therefore, the current flowing through the memory cell cannot be observed directly.
  • a plurality of circuits through which leakage current flows are connected in series or in parallel to the path to the memory cell power input / output pad.
  • the leakage current includes a current that flows to the non-selected memory cell with a bit line force, and a current that flows from the common data line to the non-selected bit line.
  • the memory cell current is as small as several hundred nA or less, it cannot be accurately measured if it is added to such a leak current and the memory cell current.
  • An object of the present invention is to provide a semiconductor device capable of accurately detecting a current flowing in a memory cell having a memory element force using a phase change material.
  • One representative means of the present invention is as follows. That is, a first switch circuit is provided for connecting the nod and the pad to the common data line at the time of current detection.
  • a second switch circuit is provided for holding the non-selected bit line at the first voltage equal to or lower than the read voltage VR at the time of current detection.
  • the non-selected bit line is held at the first voltage by the second switch circuit, it is possible to separate the non-selected bit line and the common data line and to bias the CMOS switch as follows. It can. That is, the voltage between the source and drain of the CMOS switch can be relaxed by the first voltage. In addition, the first voltage can be reverse-biased between the gate source and the bulk source of the NMOS transistor constituting the CMOS switch. As described above, the leakage current flowing to the common data line force non-selected bit line can be reduced. As a result, even if the memory cell is in a high resistance state, the current can be detected with high accuracy.
  • FIG. 1 is a diagram showing a block of a memory array and its peripheral circuits in the first embodiment.
  • FIG. 2 is a diagram showing a configuration example of a memory array and memory cells in the first embodiment.
  • FIG. 3 is a diagram illustrating a configuration example of a multiplexer according to the first embodiment.
  • FIG. 4 is a diagram showing a configuration example of a read circuit.
  • FIG. 5 is a diagram showing operation waveforms during a read operation.
  • FIG. 6 is a diagram showing a configuration example of a rewrite circuit.
  • FIG. 7 is a diagram showing operation waveforms when the rewriting operation is performed.
  • FIG. 8 is a diagram showing a configuration example of a switch for connecting a pad and a common data line in the first embodiment.
  • FIG. 9 is a diagram showing operation waveforms in the first embodiment.
  • FIG. 10 is a diagram illustrating a configuration example of a multiplexer according to the second embodiment.
  • FIG. 11 is a diagram showing operation waveforms in the second embodiment.
  • FIG. 12 is a diagram showing a configuration example of a memory array and memory cells in the third embodiment.
  • FIG. 13 is a diagram illustrating a configuration example of a multiplexer according to the third embodiment.
  • FIG. 14 is a diagram showing operation waveforms in the third embodiment.
  • FIG. 15 is a diagram showing a configuration example of a memory array and memory cells in the fourth embodiment.
  • FIG. 16 is a diagram showing operation waveforms in the fifth embodiment.
  • FIG. 17 is a diagram showing a configuration example of a memory array and memory cells in a sixth embodiment.
  • FIG. 18 is a diagram illustrating a configuration example of a multiplexer according to a sixth embodiment. [19] FIG. 19 is a diagram showing operation waveforms in the sixth embodiment.
  • FIG. 20 is a diagram illustrating a configuration example of a rewrite circuit according to the seventh embodiment.
  • FIG. 21 is a diagram showing blocks of a memory array and its peripheral circuits in an eighth embodiment.
  • FIG. 22 is a diagram showing a configuration example of a switch for connecting a node and a common data line in the eighth embodiment.
  • FIG. 23 shows a configuration of a switch for connecting a node and a common data line in the ninth embodiment. It is a figure which shows a composition example.
  • FIG. 24 is a diagram illustrating a configuration example of a shift register as the tenth embodiment.
  • FIG. 25 is a diagram showing operation waveforms of the shift register.
  • FIG. 26 is a diagram showing blocks of banks and their peripheral circuits in the eleventh embodiment.
  • FIG. 27 is a diagram showing blocks of a memory array and its peripheral circuits in a twelfth embodiment.
  • FIG. 28 is a diagram showing a configuration example of an output buffer in the twelfth embodiment.
  • FIG. 29 is a diagram showing a configuration example of a switch for connecting an input / output pad and a current detection dedicated wiring in a twelfth embodiment.
  • FIG. 30 is a diagram illustrating a configuration example of an output buffer according to a thirteenth embodiment.
  • FIG. 31 is a diagram showing blocks of a memory array and its peripheral circuits in a fourteenth embodiment.
  • FIG. 32 is a diagram showing the relationship between the pulse width and temperature required for the phase change of the memory element using the phase change material.
  • FIG. 33 is a diagram showing current-voltage characteristics of a memory element using a phase change material. Explanation of symbols
  • each block of the embodiment are not particularly limited, but typically one semiconductor crystal circuit such as a single-crystal silicon by a semiconductor integrated circuit technology such as a known CMOS complementary MOS transistor). It is formed on a semiconductor substrate.
  • phase change materials that exhibit phase change are hybridized to integrated circuit fabrication technology.
  • FIG. 1 shows various circuits necessary for rewriting, reading, and current detection of data in one memory cell in each of the memory arrays MCAl to MCAk, and the same number of memory arrays MCAl to MCAk as the number of bits k to be read and written simultaneously. Is shown.
  • a word driver row WDA for driving a word line, a plurality of bit lines BL force, a multiplexer MUXl to MUXk that selects one and connects to the corresponding common data lines CDLl to CDLk, and a memory cell array MCA force
  • Read circuit PRGMl to PRGMk that amplifies the read signal and outputs it as output data D01 to DOk and receives rewrite voltage to memory cell array MCA in response to input data DIl to RDk and input data DIl to DIk
  • the pads PADl to PADk for detecting the current from the memory cell MC included in the memory array MCA to be detected, the switches SDCl to SDCk connected between the pad PAD and the common data line CDL, and the control logic circuit CL GC are shown.
  • Each of the memory arrays MCAl to MCAk is simplified, and a plurality of bit lines BL are connected to each of the force multiplexers MUX in which one memory cell MC is shown as a representative.
  • the force input data DI omitted for the sake of simplicity is input from the common input / output pad different from the pad PAD through the input buffer (not shown), and the output data DO through the output buffer (not shown). Is input and output.
  • the control logic circuit CLGC receives the command signal group CMD and generates signals for controlling the switches SDC1 to SDCk, the read circuits RDl to RDk, and the rewrite circuits PRGMl to PRGMk.
  • the semiconductor device of the present invention can be in at least three operation modes: a data read operation, a data write operation, and a memory cell current detection operation.
  • FIG. 2 shows a configuration example of the memory array and the memory cell.
  • a configuration example of MCA1 is shown as an example.
  • the memory array MCA1 includes word lines WLl to WLm, bit lines BLl to BLn, and m ⁇ n bits of memory cells MCl 1 to MCmn arranged at each intersection of the word line and the bit line.
  • the memory cell also includes a memory element PCR force using a selection transistor CT and a phase change material. These elements are connected in series in the order of the select transistor CT and the storage element PCR in the direction of the power supply line of the ground voltage VSS.
  • the selection transistor CT and the storage element PC The connection order of R cannot be reversed.
  • Word lines WLl to WLm are driven by corresponding word drivers WDl to WDm in word driver column WDA.
  • one of the bit lines BLl to BLn is selected by a multiplexer, which will be described later, and is connected to the common data line CDL1.
  • FIG. 3 shows a configuration example of the multiplexer.
  • the multiplexer MUX1 is composed of a column selection switch string CSWA and a discharge circuit DCCKT.
  • the column selection switch row CSWA is composed of CMOS switches CSW1 l to CSWln inserted between the bit lines BLl to BLn and the common data line CDL1.
  • Each of the CMOS switches CSW1 l to CSWln is omitted in the figure, and is activated and selected according to the column selection signal pairs (YS1T, YSlB) to (YSnT, YSnB) generated by the column decoder.
  • CMOS switch CSW11 Connects the bit line to the common data line CDL1.
  • CMOS switch CSW11 when CMOS switch CSW11 is inactive, YS1T is held at negative voltage VNN, YS1B is held at power supply voltage VDD, and when activated, YS1T is driven to power supply voltage VDD, and YS1B is driven to ground voltage VSS Is done.
  • the negative voltage VNN is generated by a negative voltage generation circuit and is a voltage lower than the ground voltage VSS.
  • the voltage of the column selection signal YS1T when the CMOS switch CSW11 is activated is preferably a voltage VPP higher than the power supply voltage VDD. This is to ensure that the read voltage VR is applied to the selected bit line even if the threshold voltage of the NMOS transistor constituting the CMOS switch CSW11 becomes high due to a temperature change or manufacturing variation.
  • the discharge circuit DCCKT is composed of NMOS transistors ⁇ 11 to ⁇ 1 ⁇ inserted between each of the bit lines BLl to BLn and the power supply line of the ground voltage VSS, and is not selected by the column selection signals YSlB to YSnB described above. Bit lines BLl to BLn are held at ground voltage VSS.
  • FIG. 4 shows a configuration example of the reading circuit.
  • the readout circuit RD1 is composed of a transmission gate TG, a precharge circuit PCKT, and a sense amplifier SA.
  • the transmission gate TG includes an NMOS transistor MN26 inserted between the common data line CDL1 and the node NT, and an NMOS transistor MN27 inserted between the power supply line of the reference voltage VREF and the node NB.
  • the reference voltage VREF is a voltage between the power supply voltage VDD and the ground voltage VSS.
  • the reference voltage VREF is generated from the power supply voltage VDD and the ground voltage VSS by using a step-down circuit that is omitted in FIG.
  • the transmission gate TG is activated by the transmission gate control signal RS, connects the node NT to the common data line CDL1, and drives the node NB to the reference voltage VREF.
  • the precharge circuit PCKT is composed of an NMOS transistor MN24 inserted between the feed line of the read voltage VR and the node NT, and an NMOS transistor MN25 inserted between the feed line of the reference voltage VREF and the node NB.
  • the read voltage VR is generated from, for example, the power supply voltage V DD and the ground voltage VSS using a step-down circuit not shown in the figure, and is a voltage between the power supply voltage VDD and the reference voltage VREF.
  • the precharge circuit PCKT is activated by the precharge signal PCE, and drives the node NT to the read voltage VR and the node NB to the reference voltage VREF. When the aforementioned transmission gate TG is activated, the precharge circuit PCKT simultaneously drives the common data line CDL1 and the bit line to the read voltage VR.
  • the sense amplifier SA includes a PMOS transistor MP23, a latch and a ground voltage VSS inserted between a latch composed of NMOS transistors MN21 and MN22, a PMOS transistor MP21 and MP22, and a power supply line of the latch and the power supply voltage VDD.
  • NMOS transistor MN23 inserted between the power supply lines, and the notch circuits BUF21 and BUF22.
  • the sense amplifier SA is activated by the sense amplifier control signal pair (SAC, SACB), amplifies a small voltage difference between the nodes NT and NB, and the notifier circuit BUF21 corresponds to the read data DOl according to the read stored information. Output voltage.
  • FIG. 5 shows operation waveforms during the read operation.
  • the transmission gate TG is activated by the transmission gate control signal RS
  • the node NT is connected to the common data line CDL1
  • the node NB is held at the reference voltage VREF.
  • the selected bit line BL1 is connected to the common data line CDL1 by the multiplexer MUX1.
  • the common data line CDL1 and the selected bit line BL1 are driven to the read voltage VR by the precharge circuit PCKT.
  • the precharge circuit PCKT is deactivated by the precharge control signal PCE, and the word line WL1 to which the selected memory cell MC11 is connected is By being driven, the voltages of the selected bit line BL1, the common data line CDL1, and the node NT change according to the storage information of the selected memory cell MCI1.
  • the transmission gate TG is deactivated by the transmission gate control signal RS, and the sense amplifier SA is activated by the sense amplifier control signal pair (SAC, SACB), whereby the data of the selected memory cell MCI 1 is read.
  • FIG. 6 shows a configuration example of the rewrite circuit.
  • PRGM1 is composed of a rewrite control circuit PCCKT, a reset circuit RCKT, and a set circuit SCKT.
  • the rewrite control circuit PCCKT generates a set signal SETB and a reset signal RSTB based on the rewrite signals WES and WER and the input data DI1.
  • the reset circuit RCKT is composed of a PMOS transistor MP25 inserted between the power supply line of the reset voltage VRST and the common data line CDL1.
  • the reset voltage VRST is a voltage between the power supply voltage VDD and the ground voltage VSS.
  • the reset voltage VRST is generated from the power supply voltage VDD and the ground voltage VSS by using a step-down circuit that is omitted in FIG.
  • the reset signal RSTB is connected to the gate of the PMOS transistor MP25.
  • Figure 7 shows the operating waveforms during the rewrite operation.
  • the reset operation is performed, the rewrite signal WER is driven to the power supply voltage V DD with the ground voltage VSS, and the reset signal RSTB that is at the power supply voltage VDD is driven to the ground voltage VSS.
  • the PMOS transistor MP25 becomes conductive, and a current is applied to the storage element PCR in the selected memory cell MC11. Since this current is set so as to realize the temperature waveform shown in FIG. 32, the storage element PCR is reset.
  • the set circuit SCKT includes a PMOS transistor MP24 inserted between a power supply line of a set voltage VSET and a common data line CDL1.
  • the set voltage VSET is a voltage between the power supply voltage VDD and the ground voltage VSS.
  • the set voltage VSET is generated from the power supply voltage VDD and the ground voltage VSS using a step-down circuit that is omitted in the figure.
  • the set signal SETB is connected to the gate of the PMOS transistor MP24.
  • Figure 7 shows the operating waveforms during the rewrite operation.
  • an operation when performing a set operation on memory cell MC11 in memory array MCA1 will be described.
  • ground voltage VSS ground voltage VSS
  • the rewrite signal WES is driven to the power supply voltage VDD
  • the reset signal SETB at the power supply voltage VDD is driven to the ground voltage VSS.
  • the PMOS transistor MP24 becomes conductive, and a current is applied to the memory element PCR in the selected memory cell MCI1. Since this current is set so as to realize the temperature waveform shown in FIG. 32, the memory element PCR is set.
  • FIG. 8 shows a configuration example of a switch that connects the pad and the common data line.
  • the switch SDC 1 is composed of a CMOS switch CSW31 inserted between the common data line CDL 1 and the pad PAD 1.
  • the switch SDC1 is activated by the test signal pair (TDC, TDCB) and connects the common data line CDL1 and the pad PAD1.
  • the voltage of the test signal TDC when the switch SDC 1 is activated is preferably higher than the power supply voltage VDD, for example, and the voltage VPP. This is to ensure that the read voltage VR is applied to the selected bit line even if the threshold voltage force of the NMOS transistor constituting the switch SDC1 becomes high due to temperature change or manufacturing variation.
  • FIG. 9 shows an operation waveform at the time of current detection in the present embodiment.
  • the transmission gate control signal RS is held at the ground voltage VSS
  • the precharge signal PCE is held at the power supply voltage VDD
  • the read circuit RD1 is separated from the common data line CDL1
  • the node NT is set at the read voltage VR. Is retained.
  • the rewrite signals WER and WES are held at the ground voltage VSS, and the reset circuit RCKT and the set circuit SCKT are deactivated.
  • the switch SDC1 is activated by the test signal pair (TDC, TDCB), so that the pad PAD1 and the common data line CDL1 do not pass through the output buffer. Connected to.
  • the CMOS switch CSW11 is activated by the column selection signal pair (YS1T, YS1B), the bit line BL1 and the common data line CDL1 are connected.
  • the word line WL1 is driven to the ground voltage VSS, and the CMOS switch CSW11 and switch SDC1 are deactivated by the column selection signal pair (YS1T, YS1B) and the test signal pair (TCD, TCDB). To return to the standby state. Note that the sense amplifier SA is not activated during current detection.
  • CMOS switches that are inactive CSW11 ⁇ Negative voltage VNN at the gate of the NMOS transistor that makes up Ln, and ground voltage VSS at the source
  • VNN negative voltage
  • VSS ground voltage
  • the gate and source of the NMOS transistor are reverse-biased, so that the leakage current flowing from the common data line CDL1 to the unselected bit line can be reduced.
  • the common data line CDL1 is set to a read voltage VR lower than the power supply voltage VDD, so that the gate-to-source of the PMOS transistor is reverse-biased, so that the leakage current is similarly reduced. be able to.
  • the node NT in the readout circuit RD1 is held at the same voltage VR as in standby, thereby reverse biasing between the gate source and the bulk source of the NMOS transistor MN26 that constitutes the transmission gate TG. It can be in a state. Therefore, the leakage current flowing from the common data line CDL1 to the node NT can be reduced. With the above effects, it is possible to realize a semiconductor device capable of accurately detecting the current flowing through the memory cell.
  • FIG. 10 shows a configuration example of the multiplexer in this embodiment.
  • the multiplexer MUX1 is composed of a column selection switch row CSWA and a discharge circuit DCCKT.
  • the column selection switch row CSWA includes CMOS switches CSW41 to CSW4n inserted between the bit lines BL1 to BLn and the common data line CDL1.
  • Each of the CMOS switches CS W41 to CSW4n is activated and selected according to the force column selection signal pairs (YS1T, YSlB) to (YSnT, YSnB) generated by the column decoder not shown in the figure. Connect the bit line to the common data line CDL1.
  • CMOS switch CSW11 when CMOS switch CSW11 is inactive, YS1T is held at ground voltage VSS, YS1B is held at power supply voltage VDD, and when activated, YS1T is driven to power supply voltage VDD, and YS1B is driven to ground voltage VSS. It is done.
  • the discharge circuit DCCKT is composed of NMOS transistors MN41 to MN4n inserted between each of the bit lines BL1 to BLn and the node NS and a source control circuit SCCKT.
  • the NMOS transistors MN41 to MN4n are activated by the column selection signals YSlB to YSnB described above, and hold the unselected bit lines BLl to BLn at the same voltage as the voltage of the node NS.
  • the source control circuit SCCKT is composed of an NMOS transistor MN41 inserted between the power supply line of the voltage VDC and the node NS, and an NMOS transistor MN42 inserted between the power supply line of the ground voltage VSS and the node NS.
  • the voltage at node NS is controlled according to the test signal pair (TSC, TSCB) generated by the control logic circuit, which is not shown in the figure.
  • Node NS is held at ground voltage VSS during standby, read operation, and rewrite operation, and at voltage VDC during current detection.
  • the voltage VDC is generated from the power supply voltage VDD and the ground voltage VSS by using a step-down circuit not shown in the figure, and is the same as or lower than the read voltage VR.
  • FIG. 11 shows an operation waveform at the time of current detection in the present embodiment.
  • transmission gate control signal RS is held at ground voltage VSS
  • precharge signal PCE is held at power supply voltage VDD
  • read circuit RD1 is isolated from common data line CDL1
  • node NT is held at read voltage VR.
  • Rewrite signals WER and WES are each driven to ground voltage VSS and set with reset circuit RCKT.
  • the circuit SCKT is deactivated.
  • the test signal TSC is driven to the power supply voltage VDD and the test signal TSCB is driven to the ground voltage VSS, the unselected bit lines BLl to BLn are driven to the voltage VDC.
  • the switch SDC1 is activated by the test signal pair (TDC, TDCB), thereby connecting the pad PAD1 and the common data line CDL1.
  • the CMOS switch CSW41 is activated by the column selection signal pair (YS1T, YS1B)
  • the bit line BL1 and the common data line CDL1 are connected.
  • the node line WL1 is driven to the power supply voltage VDD, whereby a current flows from the pad PAD1 to the memory cell MC11.
  • the current flowing through the memory cell MC11 can be detected.
  • the word line WL1 is driven to the ground voltage VSS, and the CMOS switch CSW41 and the switch SDC1 are deactivated by the column selection signal pair (YS1T, YS1B) and the test signal pair (TCD, TCDB), and the test signal TSC Is driven to the ground voltage VSS and the test signal TSCB is driven to the power supply voltage V DD to return to the standby state.
  • the column selection switch example CSWA is in an inactive state.
  • the bias of the CMOS switch can be set as follows. That is, the voltage between the source and drain of the CMO switch CSW can be relaxed by VDC. Further, it is possible to reverse noise between the gate and source of the NMOS transistor constituting the CMOS switch and between the bulk source by a voltage VDC. From the above, it is possible to reduce the leakage current flowing to the common data line CDL1 power unselected bit line.
  • the voltage control range of the column selection signal pair can be changed from the ground voltage VSS to the power supply voltage VDD, so that the negative voltage generation circuit required in the first embodiment is not necessary.
  • the chip area can be reduced. Due to the above two effects, the same effects as those of the first embodiment can be obtained with an area smaller than that of the first embodiment.
  • the unselected bit line is driven with the voltage VDC when the current is detected, and is driven with the power read voltage VR.
  • the voltage between the source and drain of the CMOS switch CSW connected to the unselected bit line becomes equal, and subthreshold leakage current can be prevented.
  • a step-down circuit that generates voltage VDC is not required, a semiconductor device with a smaller chip area can be realized.
  • Embodiment 2 a modification of the second embodiment is shown.
  • bit lines and source lines are arranged in parallel, and memory cells connected to the same bit line are connected to the same source line.
  • Second, the unselected bit lines are always held at the voltage VDC.
  • the other points are basically the same as those in the first or second embodiment. Hereinafter, the configuration will be described by paying attention to these differences.
  • FIG. 12 shows a configuration of the memory array and the memory cell in the present embodiment.
  • the memory array MCA1 includes word lines WL1 to WLm, bit lines BL1 to: BLn, source lines SL1 to SLn, and m ⁇ n bit memory cells MCI 1 to MCmn arranged at the intersections of the node lines and the bit lines. Made.
  • the m memory cells connected to the same bit line are each connected to the corresponding source line.
  • the memory cell also includes a memory element PCR force using a select transistor CT and a phase change material.
  • Word lines WLl to WLm are driven by corresponding word drivers WDl to WDm in word driver column WDA.
  • the bit lines BLl to BLn and the source lines SLl to SLn corresponding to the bit lines are respectively selected by a multiplexer described later, the selected bit line is the common data line CDL1, and the selected source line is the ground voltage VSS. Connected to the feeder line.
  • FIG. 13 shows a configuration example of the multiplexer in the present embodiment.
  • the multiplexer MUX1 is composed of a column selection switch row CSWA and a discharge circuit DCCKT.
  • Column selection switch row CSWA is inserted between each of the bit lines BLl to BLn and the common data line CDL1 between the CMOS switches CSW51B to CSW5nB, the source lines SLl to SLn, and the ground voltage VSS power supply line.
  • CMOS switches CSW51S to CSW5nS Configured.
  • Each of the CMOS switches CSW51B to CSW5nB is activated and selected in accordance with column selection signal pairs (YS1T, YSlB) to (YSnT, YSnB) generated by a column decoder not shown in the figure. Connect the line to the common data line CDL1.
  • Each of the C MOS switches CSW51S to CSW5nS is activated according to the column selection signal pairs (YS1T, YS1B) to (YSnT, YSnB), and drives the source line corresponding to the selected bit line to the ground voltage VSS. .
  • CMOS switches CSW51B and CSW51S are inactive, YS1T is held at ground voltage VSS, YS1B is held at power supply voltage VDD, and when activated, YS1T is at power supply voltage VDD, and YS1B is at ground voltage VSS.
  • the discharge circuit DCCKT is inserted between the NMOS transistors MN51B to MN5nB inserted between each of the bit lines BLl to BLn and the voltage VDC power supply line, and between each of the source lines SLl to SLn and the voltage VDC power supply line.
  • the NMOS transistors MN51S to MN5nS are configured to hold the unselected bit lines and the unselected source lines at the voltage VDC according to the column selection signals YSlB to YSnB.
  • FIG. 14 shows operation waveforms at the time of current detection in the present embodiment.
  • transmission gate control signal RS is held at ground voltage VSS
  • precharge signal PCE is held at power supply voltage VDD
  • read circuit RD1 is isolated from common data line CDL1
  • node NT is read voltage VR. Retained.
  • the rewrite signals WER and WES are each driven to the ground voltage VSS, and the reset circuit RCKT and the set circuit SCKT are deactivated! /.
  • the switch SDC1 is activated by the test signal pair (TDC, TDCB), thereby connecting the pad PAD1 and the common data line CDL1.
  • the CMOS switches CSW 51 B and CSW 51 S are activated by the column selection signal pair (YS1T, YS1B)
  • the bit line BL1 and the common data line CDL1 are connected, and the source line SL1 is connected to the ground voltage VSS.
  • the word line WL1 is driven to the power supply voltage VDD, whereby a current flows from the pad PAD1 to the memory cell MCI1.
  • the current flowing through the memory cell MC11 can be detected.
  • word line WL1 Driven to the ground voltage VSS, the CMOS switch CSW51B, CSW51S, and switch SDC1 are deactivated by the column selection signal pair (YS1T, YS1B) and the test signal pair (TD C, TDCB). .
  • the source control circuit SCC KT shown in FIG. 10 is configured by individually controlling the selected bit line, the source line, the unselected bit line, and the source line using the multiplexer MUX1. Since the test signals TSC and TSCB are not required, the circuit configuration can be simplified. Second, also in this embodiment, since the non-selected bit line at the time of current detection is held at the voltage VDC, the same effect as in the second embodiment can be obtained.
  • FIG. 2 another configuration of the memory array and the memory cell shown in FIG. 2 is shown.
  • the difference is that a negative voltage is applied to the memory array substrate during current detection.
  • the configuration will be described focusing on this difference.
  • This embodiment can be implemented in combination with the first to third embodiments.
  • FIG. 15 shows a configuration example of a memory array and memory cells.
  • MCA1 an example configuration of MCA1 is shown as an example.
  • the substrate P W of the selection transistor CT is held at, for example, the ground voltage VSS during standby, read operation, and rewrite operation, and is driven to the negative voltage VBN when current is detected.
  • the negative voltage VBN is generated by a negative voltage generation circuit and is lower than the ground voltage VSS.
  • the effects of the configuration and operation described above are as follows.
  • a negative voltage VBN to the substrate PW of the selected transistor CT during current detection, the threshold voltage of the selected transistor increases, so that the leakage current that flows to the unselected memory cells connected to the selected bit line is reduced.
  • the negative voltage VBN may be the same voltage as the negative voltage VNN used in the first embodiment. In this case, it is possible to realize a semiconductor device with a small chip area that does not require a new negative voltage generation circuit.
  • Embodiment 1 In the present embodiment, another operation is shown in addition to reducing the leakage current flowing through the non-selected memory cell at the time of current detection.
  • the difference from Embodiment 1 is that a negative voltage VNN is applied to a non-selected word line. Note that this embodiment can be implemented in combination with the first to fourth embodiments.
  • FIG. 16 shows an operation waveform at the time of current detection in the present embodiment.
  • the drive voltage of the unselected node is the negative voltage VNN, and the other operations are the same as in Fig. 9.
  • the present embodiment another configuration of the memory array and the multiplexer is shown.
  • the first difference is that memory cells connected to the same word line are connected to the same source line by arranging the source line in parallel with the word line in the memory array.
  • the second difference is that the unselected bit line is always held at a voltage VDC equal to or lower than the read voltage VR due to the switch in the multiplexer. Only the components different from the second embodiment will be described below. This embodiment can be implemented in combination with Embodiments 1 and 4-5.
  • FIG. 17 shows the configuration of the memory array and the memory cell, and the source driver column SDA in the present embodiment.
  • the memory array MCA1 includes word lines WLl to WLm, bit lines BL1 to: BLn, source lines SL1 to SLm, and m ⁇ n bit memory cells MCl l to MCmn arranged at the intersections of the word lines and the bit lines.
  • the N memory cells connected to the same word line are respectively connected to corresponding source lines.
  • the memory cell is also configured with a select transistor CT and a memory element PCR force using a phase change material.
  • the word lines WL l to WLm are connected to the corresponding word drivers WDl to WDm in the word driver column WDA. Driven.
  • the bit lines BLl to BLn are selected by a multiplexer described later, and one of them is connected to the common data line CDL1.
  • the source lines SLl to SLm are driven by the corresponding source drivers SDl to SDm in the source driver column SDA, the source line corresponding to the selected word line is set to the ground voltage VSS, and the source line corresponding to the unselected word line is set to Driven to voltage VDC respectively.
  • FIG. 18 shows a configuration of the multiplexer in the present embodiment.
  • the multiplexer M UX1 is composed of a column selection switch row CSWA and a discharge circuit DCCKT.
  • the column selection switch row CSWA is composed of CMOS switches CSW61 to CSW6n inserted between each of the bit lines BL1 to BLn and the common data line CDL1.
  • Each of the CMOS switches CSW6 l to CSW6n is activated and selected in response to column selection signal pairs (YS1T, YSlB) to (YSnT, YSnB) generated by a column decoder not shown in the figure.
  • CMOS switch CSW61 When CMOS switch CSW61 is inactive, YS1T is held at ground voltage VSS, YS1B is held at power supply voltage VDD, and when activated, YS1T is driven to power supply voltage VDD, and YS1B is driven to ground voltage VSS. Is done.
  • the discharge circuit DCCKT is composed of NMOS transistors MN61 to MN6n inserted between each of the bit lines BLl to BLn and the power supply line of the voltage VDC, and the unselected bit lines are connected by the above-described column selection signals Y SlB to YSnB. Hold at voltage VDC.
  • FIG. 19 shows operation waveforms at the time of current detection in the present embodiment.
  • transmission gate control signal RS is held at ground voltage VSS
  • precharge signal PCE is held at power supply voltage VDD
  • read circuit RD1 is isolated from common data line CDL1
  • node NT is held at read voltage VR.
  • the rewrite signals WER and WES are each driven to the ground voltage VSS, and the reset circuit RCKT and the set circuit SCKT are deactivated.
  • the switch SDC1 is activated by the test signal pair (TDC, TDCB), thereby connecting the pad PAD1 and the common data line CDL1.
  • CMOS switch CSW by column select signal pair (YS1T, YS1B)
  • bit line BL1 and common data line CDL1 are connected.
  • the word line WL1 is driven to the power supply voltage VDD and the source line SL1 is driven to the ground voltage VSS, whereby a current flows from the pad PAD1 to the memory cell MC11.
  • word line WL1 is driven to ground voltage VSS and source line SL1 is driven to voltage VDC, and CMOS switch CSW61 and switch SDC1 are driven by column selection signal pair (YS1T, YS IB) and test signal pair (TDC, TDCB). Is brought into an inactive state to return to a standby state.
  • YS1T, YS IB column selection signal pair
  • TDC, TDCB test signal pair
  • the same effect can be obtained even when the source line of the non-selected memory cell is driven with the voltage VDC when the current is detected. This eliminates the need for a step-down circuit that generates the voltage VDC, thereby realizing a semiconductor device with a smaller chip area.
  • FIG. 6 another configuration of the rewrite circuit of FIG. 6 is shown. The difference is that a switch is inserted between the set and reset circuits and the common data line.
  • a switch is inserted between the set and reset circuits and the common data line.
  • FIG. 20 shows a configuration example of the rewrite circuit in the present embodiment.
  • Rewrite circuit PRG Ml is rewrite control circuit PCCKT, reset circuit RCKT, set circuit SCKT, switch S WW power is composed.
  • the reset circuit RCKT and the set circuit SCKT are connected to the node NW, and are connected to the common data line CDL1 via the switch SWW.
  • the switch SWW includes a CMOS switch CSW71 inserted between the node NW and the common data line CDL 1 and an NMOS transistor MN71 inserted between the node NW and the voltage VDC power supply line.
  • the voltage VDC is generated from, for example, the power supply voltage VDD and the ground voltage VSS by using a step-down circuit not shown in the figure, and is the same voltage or lower than the read voltage VR.
  • the rewrite signals WES and WER and the switch control signal pair (WS and WSB) for controlling the rewrite circuit PRGM1 are generated by the control logic circuit CLGC which is omitted in the figure.
  • the CMOS switch CSW71 is activated by the switch control signal pair (WS, WSB), and the node NW and the common data line CDL1 are connected. Thereafter, the rewrite circuit PRGM1 sets the storage element PCR in the memory cell to the reset state or the set state in accordance with the rewrite signals WER and WES and the data DI1.
  • the CMOS switch CSW71 is deactivated by the switch control signal pair (WS, WSB), the NMOS transistor MN71 is activated, and the node NW is voltageed by the NMOS transistor M N71. Held in VDC.
  • the bias of the CMOS switch CSW71 can be set as follows. In other words, the voltage between the source and drain of the CMOS switch CSW71 can be reduced by VDC. In addition, it is possible to reverse noise between the gate and source of the NMOS transistor constituting the CMOS switch CSW71 and between the Balta source by voltage VDC. From the above, since the leakage current flowing from the common data line CDL1 to the node NW can be reduced, it is possible to detect a minute current flowing in the memory cell in the high resistance state with higher accuracy than in the first embodiment.
  • the node NW is driven with the voltage VDC when the current is detected.
  • the same effect can be obtained even when the node NW is driven with the read voltage VR.
  • a step-down circuit that generates the voltage VDC is not required, and thus a semiconductor device with a smaller chip area can be realized.
  • the rewriting circuit shown in this embodiment can also be applied to the second embodiment. In that case, it is possible to realize a semiconductor device capable of detecting a minute current flowing through a memory cell in a high resistance state with higher accuracy than in the second embodiment. Further, since the voltage applied to the node NW and the voltage applied to the non-selected bit line can be generated by the same step-down circuit during current detection, the chip area can be reduced.
  • Embodiment 1 another configuration example of a semiconductor device to which the present invention is applied is shown.
  • the difference from Embodiment 1 is that one common pad is provided in a plurality of memory arrays, and a plurality of switches connecting the plurality of common data lines and pads are controlled by different test signal pairs. It is. Only the components different from the first embodiment will be described below. This embodiment can be implemented in combination with Embodiments 1 to 7.
  • FIG. 21 shows p memory arrays MCAl to MCAp and word driver strings WDA and multiplexers MUXl to MUXp necessary for rewriting, reading, and current detection of data in one memory cell in each of the memory arrays MCAl to MCAp.
  • Read circuits RDl to RDp, rewrite circuits PRGMl to PRGMp, switches SDCl to SDCp, control logic circuit CLGC, and shared pad PAD are shown.
  • the memory arrays MCAl to MCAp are simplified, and each memory cell MC is shown as a representative! /.
  • FIG. 22 shows a configuration example of the switch in the present embodiment.
  • SDC1 is composed of a CMOS switch CSW81 arranged between the common data line CDL1 and the common pad PAD.
  • the switch SDC1 is controlled by a test signal pair (TDC 1, TDCB1) generated by the control logic circuit CLGC.
  • test signal TDC1 is held at negative voltage VNN
  • test signal TDCBl is held at power supply voltage VDD
  • common data line CDL1 and shared pad PAD are separated.
  • test signal TDC1 is driven to the power supply voltage VDD
  • test signal TDCBl is driven to the ground voltage VSS
  • common data line CDL1 is connected to the common pad PAD, and the same operation as in the first embodiment is performed.
  • the current of the selected memory cell is detected.
  • the number of pads can be reduced as compared with the first embodiment by sharing one pad with a plurality of memory arrays.
  • a semiconductor device capable of detecting a memory cell current with high accuracy can be realized with a smaller number of pads than in the first embodiment, that is, with a small area.
  • FIG. 8 another configuration example of the switch shown in the eighth embodiment is shown.
  • the feature of this embodiment is that the voltage of the non-selected common data line is adjusted at the time of current detection to suppress the leakage current from the node force to the non-selected common data line, and the test for controlling the switch.
  • the voltage control range of the signal is different.
  • This embodiment can be implemented in combination with Embodiments 1 to 8.
  • FIG. 23 shows a configuration example of the switch in the present embodiment.
  • Switch SDC1 is a CMOS switch CSW91 inserted between common data line CDL1 and common pad PAD, and an NMOS transistor newly placed between common data line CDL1 and the voltage VDC power supply line. It is composed of MN91 and MN92.
  • the voltage VDC is generated from, for example, the power supply voltage VDD and the ground voltage VSS using a step-down circuit omitted in the figure, and is the same voltage or lower than the read voltage VR.
  • Test signal TCP is connected to the gate of NMOS transistor MN91, and test signal TDC1 is connected to NMOS transistor MN92.
  • test signal TDC1 generated by control logic circuit CLGC is held at ground voltage VSS
  • test signal TDCB1 is held at power supply voltage VDD
  • test signal TCP is held at ground voltage VSS. Therefore, the CMOS switch CSW91 and the NMOS transistor MN91 are deactivated. Therefore, the NMOS transistor MN92 and the power supply line of voltage VDC are separated from the common data line CDL1.
  • the test signal TCP is driven to the power supply voltage VDD and the NMOS transistor MN91 is activated, thereby connecting the NMOS transistor MN92 and the common data line CDL1.
  • the common data line CDL1 is not selected, that is, when the switch is inactivated, the test signal TDC1 is held at the ground voltage VSS and the test signal TDCB1 is held at the power supply voltage VDD. Therefore, the transistor MN92 is activated and the common data line CDL1 is driven to the voltage VDC.
  • CMOS switch CS via NMOS transistors NM91 and MN92
  • voltage VDC voltage between the drain and source of the CMOS switch CSW91
  • the gate source and bulk source of the NMOS transistor that constitutes the CMOS switch CSW91 It can be reverse biased by voltage VDC. Therefore, the leak current that flows into the non-selected common data line can also be reduced.
  • a semiconductor device capable of detecting a memory cell current with high accuracy can be realized with a smaller number of pads than in Embodiment 1, that is, with a small area.
  • the non-selected common data line is driven with the voltage VDC at the time of current detection.
  • the same effect can be obtained even when driven with the read voltage VR. By doing so, a step-down circuit for generating the voltage VDC is not required, and accordingly, a chip area can be reduced and a semiconductor device can be realized.
  • a configuration example of a shift register for generating test signal pairs (TDC1, TDCBl) to (TDCp, TDCBp) is shown as a main circuit block of the control logic circuit CLGC in the eighth embodiment.
  • the configuration and operation of the shift register will be described below using the symbols shown in FIG. FIG. 24 illustrates a configuration example of the shift register.
  • the shift register includes an AND circuit AD101, flip-flops FFl to FFp, and inverters INVl to INVp. This shift register receives input signal DSET, shift signal SHIFT, and shift enable signal SE, and outputs test signal pairs (TDC1, TDCBl) to (TDCp, TDCBp).
  • the AND circuit AD101 receives the shift signal SHIFT and the shift enable signal SE, and outputs the operation result to the input terminals CK of the flip-flops FFl to FFp.
  • the input signal DSET is input to the input terminal D of the flip-flop FF1, and the test signal TDC1 is output from the output terminal Q.
  • the test signal TDCB1 is output from the inverter INV1 that receives TDC1.
  • Test signal TDC1 is applied to input terminal D of flip-flop FF2. Is input, and test signal TDC2 is output from output terminal Q.
  • the test signal TDCB2 is output from the inverter INV2, which receives TDC2.
  • test signal TDC (p ⁇ l) is input to the input terminal D of the flip-flop FFp, and the test signal TDCp is output from the output terminal Q.
  • test signal TDCBp is output from the inverter INVp that receives TDCp.
  • the flip-flops FFl to FFp take in the data input to the input terminal D when the input terminal CK is driven to the power supply voltage VDD power ground voltage VSS. The captured data is held until the input terminal CK is driven from the power supply voltage VDD to the ground voltage VSS again.
  • FIG. 25 shows operating waveforms of the shift register shown in FIG.
  • the shift enable signal SE is at the ground voltage VSS
  • the input signal DS ET is at the ground voltage VSS
  • the test signals TDCl to TDCp are at the negative voltage VNN
  • the test signal T DCB 1 ⁇ TDCBp is held at the power supply voltage VDD.
  • the shift enable signal SE is held at the ground voltage VSS
  • the input terminals CK of the flip-flops FF1 to FFp are driven to the ground voltage VSS, so that the data of the flip-flops FFl to FFp is held.
  • the shift enable signal SE and the input signal DSET are driven to the ground voltage VSS power supply voltage VDD.
  • the input signal DSET is fetched into the flip-flop FF1
  • the test signal TDC1 has the negative voltage VNN power to the power supply voltage VDD
  • the test signal TDCB1 has the ground voltage VSS.
  • the input signal DSET is driven from the power supply voltage VDD to the ground voltage VSS until the shift signal SHIFT is driven from the power supply voltage VDD to the ground voltage VSS.
  • the flip-flop FF1 receives the input signal DSET, and the flip-flop FF2 receives the test signal TDC1.
  • the test signal TDC1 is driven from the power supply voltage VDD to the negative voltage VNN, and the test signal TDCB1 is driven from the ground voltage VSS to the power supply voltage VDD.
  • the test signal TDC2 is driven from the negative voltage VNN to the power supply voltage VDD, and the test signal TD CB2 is driven from the power supply voltage VDD to the ground voltage VSS.
  • the test signal pairs (TDC1, TDCBl) to (TDCp, TDCBp) are sequentially added. Activated.
  • the number of control signals required to generate the test signal pairs (TDC1, TDCBl) to (TDCp, TDCBp) can be reduced to three.
  • the number of test signals is greater than when the test signal pairs (TDC1, T DCB1) to (TDCp, TDCBp) are generated using a decoder.
  • the shift register shown in this embodiment can be applied to the ninth embodiment. Even in that case, the same effect as the present embodiment can be obtained.
  • FIG. 26 shows two banks BANK1, BANK2, a bank control circuit BC CKT that controls the banks, and pads PAD1 to PADk as many as the number of bits k that are simultaneously read and written.
  • the bank control circuit BCCKT receives the command signal group CMD and outputs the command signals CMD1 and CMD2 of the banks BANK1 and BANK2. When either one of the command signal group CMD1 or CMD2 is activated, the corresponding bank is selected.
  • Banks BANK1 and BANK2 are word driver columns WDA, multiplexers MUXl to MUXk, and read circuits required for rewriting, reading, and current detection of data in the memory arrays MCAl to MCAk and one memory cell in each memory array MCAl to MCAk.
  • RDl to RDk rewrite circuits PRG Ml to PRGMk, pads PADl to PADk, switches SDCl to SDCk, and control logic circuit C LGC.
  • the configuration of switches SDCl to SDCk is the same as Fig. 22 or Fig. 23.
  • the control logic circuit CLGC receives the command signal group generated by the bank control circuit BCCKT and generates control signals for the switches SDCl to SDCk, read circuits RDl to RDk, rewrite circuits PRGM1 to PRGMk, and multiplexers MUXl to MUXk.
  • Embodiments 1 to 7 and 11 a configuration example of a semiconductor device characterized by detecting a current of a memory cell from an input / output pad is shown. This embodiment can be combined with Embodiments 1 to 7 and 11.
  • FIG. 27 shows words necessary for rewriting, reading, and current detection of data in memory arrays MCAl to MCAk having the same number of bits k that are simultaneously read and written, and one memory cell MC in each memory array MCAl to MCAk.
  • Driver string WDA multiplexer MUXl to MUXk, read circuit RDl to RDk, rewrite circuit PRGMl to PRGMk, switch SDCl to SDCk, ST Rl to STRk, input buffer IBUFl to IBUFk, output buffer OBUFl to OBUFk, write buffer WBUFl to WBUFk ⁇ Read buffers RBUFl to RBUFk ⁇ I / O pads I OPl to IOPk and control logic circuit CLGC are shown.
  • Each of the memory arrays MCAl to MCAk is simplified, and one memory cell MC is shown as a representative. In the following, only the components different from those of the first embodiment in the blocks necessary for rewriting, reading, and current detection of data in one memory cell in the memory array MCA1 will be described.
  • the control logic circuit CLGC receives the command signal group CMD and generates control signals for the read circuit RD1, rewrite circuit PRGM1, switch SDC1, switch STR1, input buffer IBUF1, output buffer OBUFl, write buffer WBUF1, and read buffer RBUF1. To do.
  • the input canister IBUF1 is activated by the rewrite control signal pair (WE, WEB), and transmits the signal input to the input / output node IOP1 to the input / output line IOL1.
  • the write buffer WBUF1 is activated by the rewrite control signal pair (WE, WEB) and transmits the signal of the I / O line IOL1 to the rewrite circuit PRGM1.
  • the read buffer RBUF1 is activated by the read control signal pair (RE, RE B) and transmits the output signal of the read circuit RD1 to the input / output line IOL1.
  • FIG. 28 shows a configuration example of the output buffer OBUF1.
  • the output buffer OBUF1 includes PMOS transistors MP131, MP132, MP133, and NMOS transistors MN131, MN132, MN133.
  • the PMOS transistor MP133 is inserted between the power supply line of the power supply voltage VDD and the sources of the PMOS transistors MP131 and MP132, and the gate has a readout.
  • Control signal REB is input.
  • the NMOS transistor MN133 is inserted between the power supply line of the ground voltage VSS and the sources of the NMOS transistors MN131 and MN132, and the read control signal RE is input to the gate thereof.
  • the PMOS transistor MP133 and NMOS transistor MN133 are deactivated by the read control signal pair (RE, REB), and the PMOS transistors MP131 and MP132 are supplied with the power supply voltage V DD Therefore, the NMOS transistors MN131 and MN132 are separated from the power supply line of the ground voltage VSS.
  • the PMOS transistor MP133 and NMOS transistor MN133 are activated by the read control signal pair (RE, REB), the power supply voltage VDD is supplied to the sources of the PMOS transistors MP131 and MP132, and the sources of the NMOS transistors MN131 and MN132.
  • a ground voltage VSS is supplied.
  • the signal of the input / output line IOL1 is transmitted to the input / output pad IOP1 by the inverter composed of the PMOS transistor MP131 and the NMOS transistor MN131 and the inverter composed of the PMOS transistor MP132 and the NMOS transistor MN132.
  • FIG. 29 shows a configuration example of a switch connecting the input / output pad ⁇ 1 and the current detection dedicated wiring DCL1.
  • the switch SDC1 is composed of a CMOS switch CSW131 inserted between the input / output pad IOP1 and the current detection dedicated wiring DCL1.
  • Switch STR1 is activated by the test signal pair (TTR, TTRB) at the time of current detection, and connects input / output canopy IOP1 and current detection wiring DCL1. Thereafter, by performing the same operation as in the first embodiment, the current of the selected memory cell can be detected.
  • the number of pads can be reduced by using input / output pads as current detection nodes.
  • the leakage current flowing from the power supply to the IO pad can be reduced by cutting off the PMOS transistor MP133 and the NMOS transistor MN133 in the output buffer when the current is detected.
  • FIG. 30 shows a configuration example of the output buffer OBUF1 in the present embodiment.
  • Output buffer OBUF 1 includes a PMOS transistor MP141, NMOS transistors MN141 and MN142, a CMOS switch CSW141, a NAND circuit ND141, and a NOR circuit NR141.
  • the inputs of the NAND circuit ND141 are the input / output line IOL1 and the read control signal RE, and the calculation result is input to the gate of the PMOS transistor MP141.
  • the inputs of the NOR circuit ND141 are the input / output line IOL1 and the read control signal REB, and the calculation result is input to the gate of the NMOS transistor MN141.
  • the PMOS transistor MP141 is between the power supply line of the power supply voltage VDD and the node N14, the NMOS transistor MN141 is between the power supply line of the ground voltage VSS and the node N14, and the NMOS transistor MN142 is between the power supply line of the voltage VDC and the node N14.
  • the CMOS switch CSW141 is arranged between the node N14 and the input / output pad IOP1.
  • the NMOS transistor MN142 is activated by the read control signal REB and holds the node N14 at the voltage VDC.
  • the voltage VDC is generated from, for example, the power supply voltage VDD and the ground voltage VSS by using a step-down circuit not shown in the figure, and is the same voltage or lower than the read voltage VR.
  • the CMOS switch CSW141 is activated by the read control signal pair (RE, REB), and connects the node N14 and the input / output pad ⁇ 1.
  • the output buffer OBUF1 During standby, current detection, and rewrite operation, the output of the NAND circuit ND141 is set to the power supply voltage VDD and the output of the NOR circuit NR141 is set to the ground voltage VSS by the read control signal pair (RE, REB). As a result, the PMOS transistor MP141 and the NMOS transistor MN141 are deactivated. Also, the CMOS switch CSW141 is inactivated, and the node N14 and the input / output pad ⁇ 1 are separated. On the other hand, the NMOS transistor MN142 is activated and holds the node N14 at the voltage VDC.
  • the CMOS switch CSW141 is activated by the read control signal pair (RE, REB), the NMOS transistor MN142 is deactivated, and the NAND circuit ND141, NOR circuit NR141, PMOS transistor MP141, NMOS transistor MN141 The signal of the input / output line IOL1 is transmitted to the input / output pad IOP1.
  • the bias of the inactive CMOS switch CSW141 can be set as follows. In other words, the voltage between the source and drain of the C MOS switch CSW141 can be relaxed by VDC. The In addition, it is possible to reverse noise between the gate and the source of the NMOS transistor constituting the CMOS switch CSW141 and the voltage source by the voltage VDC. As described above, since the leakage current flowing from the input / output pad ⁇ 1 to the output buffer can be reduced, the same effect as that of the embodiment 12 can be obtained.
  • the node N14 is driven with the voltage VDC when the current is detected.
  • the same effect can be obtained even when the node N14 is driven with the read voltage VR.
  • the step-down circuit for generating the voltage VDC is not required, so that a semiconductor device with a smaller chip area can be realized.
  • FIG. 31 shows the number of memory arrays MCAl to MCAk as many as the number of bits k to be read and written simultaneously, and words necessary for rewriting, reading, and current detection of data in one memory cell MC in each memory array MCAl to MCAk.
  • Driver string WDA multiplexer MUXl to MUXk, read circuit RDl to RDk, rewrite circuit PRGMl to PRGMk, switch SDCl to SDCk, ST Rl to STRk, input buffer IBUFl to IBUFk, output buffer OBUFl to OBUFk, write buffer WBUFl to WBUFk ⁇ Read buffers RBUFl to RBUFk ⁇ I / O pads I OPl to IOPk and control logic circuit CLGC are shown.
  • Each of the memory arrays MCAl to MCAk is simplified, and one memory cell MC is shown as a representative. Only the components different from those in the twelfth embodiment in the blocks necessary for rewriting, reading, and current detection of data in one memory cell in the memory array MCA1 will be described below.
  • the configurations of the input buffer IBUF1 and the read buffer RBUF1 are the same as those in FIG. 28 or FIG.
  • the configuration of the switch STR1 is the same as FIG. Switch STR1 is activated by the test signal pair (TTR, TTRB) at the time of current detection, and connects I / O pad ⁇ 1 and I / O line IOL1. Thereafter, by performing the same operation as in the first embodiment, the current of the selected memory cell can be detected.
  • the current detection dedicated wiring DCL1 can be removed by detecting the memory cell current using the I / O line IOL1.
  • the number of lines can be reduced.
  • the leakage current flowing between the input buffer, the read buffer, and the input / output line can be reduced by the operation principle described in the twelfth and thirteenth embodiments.
  • a semiconductor device capable of accurately detecting the memory cell current can be realized with a smaller chip area than that of the twelfth embodiment.
  • the present invention can be widely applied to semiconductor devices such as a memory LSI having a memory cell having a memory element force using a phase change material and a data processing LSI such as a microphone computer.

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  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Semiconductor Memories (AREA)

Abstract

L'invention concerne une pastille et un premier circuit de commutation qui connecte la pastille à une ligne de données commune lors d'une détection de courant. L'invention concerne également un second circuit de commutation qui maintient les lignes de bit non sélectionnées à une première tension qui est égale ou inférieure à une tension de lecture (VR) lors de la détection de courant. Lors de la détection de courant, le premier circuit de commutation est utilisé pour connecter la pastille à la ligne de données commune, appliquant ainsi une tension de la pastille à une cellule mémoire qui est sectionnée par une rangée et une colonne. Le courant circulant à ce moment est surveillé, détectant ainsi un courant circulant dans la cellule mémoire. Étant donné que le second circuit de commutation est utilisé pour maintenir les lignes de bit non sélectionnées à la première tension, un commutateur CMOS, qui sépare la ligne de données commune des lignes de bit non sélectionnées, peut être polarisé comme suit. C'est-à-dire, la tension entre la source et le drain du commutateur CMOS peut être atténuée par une première tension, de telle sorte qu'une polarisation inverse de la première tension peut être appliquée entre la grille et la source, et entre le substrat et la source d'un transistor NMOS constituant le commutateur CMOS.
PCT/JP2006/319470 2006-09-29 2006-09-29 Dispositif semi-conducteur WO2008041278A1 (fr)

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JP2008537336A JPWO2008041278A1 (ja) 2006-09-29 2006-09-29 半導体装置
PCT/JP2006/319470 WO2008041278A1 (fr) 2006-09-29 2006-09-29 Dispositif semi-conducteur
TW096124458A TW200818213A (en) 2006-09-29 2007-07-05 Semiconductor device

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JP2010009659A (ja) * 2008-06-25 2010-01-14 Toshiba Corp 半導体記憶装置
WO2010047068A1 (fr) * 2008-10-21 2010-04-29 パナソニック株式会社 Dispositif d’enregistrement non volatil et procédé d’écriture dans une cellule mémoire
WO2012069719A2 (fr) 2010-11-25 2012-05-31 Altis Semiconductor Mémoire électronique

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JPH10241400A (ja) * 1997-02-26 1998-09-11 Toshiba Corp 半導体記憶装置
JPH11232891A (ja) * 1998-02-18 1999-08-27 Sanyo Electric Co Ltd 不揮発性半導体メモリ
JP2002245800A (ja) * 2001-01-03 2002-08-30 Samsung Electronics Co Ltd 半導体メモリ装置およびそのセル電流測定方法
JP2005149548A (ja) * 2003-11-11 2005-06-09 Sanyo Electric Co Ltd 半導体集積回路
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JPH10241400A (ja) * 1997-02-26 1998-09-11 Toshiba Corp 半導体記憶装置
JPH11232891A (ja) * 1998-02-18 1999-08-27 Sanyo Electric Co Ltd 不揮発性半導体メモリ
JP2002245800A (ja) * 2001-01-03 2002-08-30 Samsung Electronics Co Ltd 半導体メモリ装置およびそのセル電流測定方法
JP2005149548A (ja) * 2003-11-11 2005-06-09 Sanyo Electric Co Ltd 半導体集積回路
JP2006202383A (ja) * 2005-01-19 2006-08-03 Elpida Memory Inc メモリ装置及びそのリフレッシュ方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010009659A (ja) * 2008-06-25 2010-01-14 Toshiba Corp 半導体記憶装置
WO2010047068A1 (fr) * 2008-10-21 2010-04-29 パナソニック株式会社 Dispositif d’enregistrement non volatil et procédé d’écriture dans une cellule mémoire
JP4563511B2 (ja) * 2008-10-21 2010-10-13 パナソニック株式会社 不揮発性記憶装置
JPWO2010047068A1 (ja) * 2008-10-21 2012-03-22 パナソニック株式会社 不揮発性記憶装置
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WO2012069719A2 (fr) 2010-11-25 2012-05-31 Altis Semiconductor Mémoire électronique
FR2968117A1 (fr) * 2010-11-25 2012-06-01 Altis Semiconductor Snc Memoire electronique
WO2012069719A3 (fr) * 2010-11-25 2012-07-12 Altis Semiconductor Mémoire électronique

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