US8107314B2 - Semiconductor storage device and method for producing semiconductor storage device - Google Patents
Semiconductor storage device and method for producing semiconductor storage device Download PDFInfo
- Publication number
- US8107314B2 US8107314B2 US12/360,621 US36062109A US8107314B2 US 8107314 B2 US8107314 B2 US 8107314B2 US 36062109 A US36062109 A US 36062109A US 8107314 B2 US8107314 B2 US 8107314B2
- Authority
- US
- United States
- Prior art keywords
- signal
- test
- control
- storage device
- semiconductor storage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related, expires
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40615—Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4076—Timing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4072—Circuits for initialization, powering up or down, clearing memory or presetting
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/10—Aspects relating to interfaces of memory device to external buses
- G11C2207/105—Aspects related to pads, pins or terminals
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
Definitions
- test control signals TEST 1 , TEST 2 , TEST 3 , and TEST 4 are set to a high level, a low level, a low level, and a high level, respectively.
- the signal WEint is set to a high level and the signal CLKint is set to a signal that corresponds to the address signal A 09 .
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Dram (AREA)
- Tests Of Electronic Circuits (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/330,456 US8274854B2 (en) | 2008-01-30 | 2011-12-19 | Semiconductor storage device and method for producing semiconductor storage device |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008019316A JP5629962B2 (ja) | 2008-01-30 | 2008-01-30 | 半導体記憶装置 |
JP2008-019316 | 2008-01-30 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/330,456 Division US8274854B2 (en) | 2008-01-30 | 2011-12-19 | Semiconductor storage device and method for producing semiconductor storage device |
Publications (2)
Publication Number | Publication Date |
---|---|
US20090190416A1 US20090190416A1 (en) | 2009-07-30 |
US8107314B2 true US8107314B2 (en) | 2012-01-31 |
Family
ID=40899070
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/360,621 Expired - Fee Related US8107314B2 (en) | 2008-01-30 | 2009-01-27 | Semiconductor storage device and method for producing semiconductor storage device |
US13/330,456 Expired - Fee Related US8274854B2 (en) | 2008-01-30 | 2011-12-19 | Semiconductor storage device and method for producing semiconductor storage device |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/330,456 Expired - Fee Related US8274854B2 (en) | 2008-01-30 | 2011-12-19 | Semiconductor storage device and method for producing semiconductor storage device |
Country Status (3)
Country | Link |
---|---|
US (2) | US8107314B2 (ko) |
JP (1) | JP5629962B2 (ko) |
KR (1) | KR20090083858A (ko) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20150036438A1 (en) * | 2013-08-01 | 2015-02-05 | SK Hynix Inc. | Semiconductor apparatus |
US9245651B2 (en) | 2013-07-15 | 2016-01-26 | Samsung Electronics Co., Ltd. | Memory device for masking read data and a method of testing the same |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012142562A (ja) * | 2010-12-17 | 2012-07-26 | Semiconductor Energy Lab Co Ltd | 半導体記憶装置 |
US20140164323A1 (en) * | 2012-12-10 | 2014-06-12 | Transparent Io, Inc. | Synchronous/Asynchronous Storage System |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11306796A (ja) | 1998-04-20 | 1999-11-05 | Hitachi Ltd | 半導体記憶装置 |
JP2000163997A (ja) | 1998-11-30 | 2000-06-16 | Matsushita Electric Ind Co Ltd | 半導体装置 |
JP2003151299A (ja) | 2001-11-14 | 2003-05-23 | Seiko Epson Corp | 半導体装置およびその検査方法ならびに電子機器 |
US6778451B2 (en) * | 2000-02-24 | 2004-08-17 | Fujitsu Limited | Semiconductor memory device for masking all bits in a test write operation |
US7023748B2 (en) * | 2003-04-01 | 2006-04-04 | Sony Corporation | Semiconductor storage device |
US7190627B2 (en) * | 2003-11-07 | 2007-03-13 | Fujitsu Limited | Semiconductor device |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3169749B2 (ja) * | 1993-07-21 | 2001-05-28 | 株式会社メガチップス | 半導体記憶装置 |
JP3255132B2 (ja) * | 1998-12-25 | 2002-02-12 | 日本電気株式会社 | 半導体装置 |
JP4315552B2 (ja) * | 1999-12-24 | 2009-08-19 | 株式会社ルネサステクノロジ | 半導体集積回路装置 |
JP2002033363A (ja) * | 2000-07-19 | 2002-01-31 | Hitachi Ltd | 半導体ウエハ、半導体チップ、および半導体装置の製造方法 |
KR100459727B1 (ko) * | 2002-10-21 | 2004-12-03 | 삼성전자주식회사 | 이종의 신호를 하나의 핀을 통하여 내부 회로로 인가할 수있는 집적 회로 장치 및 방법 |
JP2004281001A (ja) * | 2003-03-18 | 2004-10-07 | Fujitsu Ltd | 半導体記憶装置 |
JP4381750B2 (ja) * | 2003-08-28 | 2009-12-09 | 株式会社ルネサステクノロジ | 半導体集積回路 |
JP4261515B2 (ja) * | 2005-06-27 | 2009-04-30 | 富士通マイクロエレクトロニクス株式会社 | 半導体メモリのバーンイン試験方法 |
-
2008
- 2008-01-30 JP JP2008019316A patent/JP5629962B2/ja not_active Expired - Fee Related
-
2009
- 2009-01-20 KR KR1020090004624A patent/KR20090083858A/ko not_active Application Discontinuation
- 2009-01-27 US US12/360,621 patent/US8107314B2/en not_active Expired - Fee Related
-
2011
- 2011-12-19 US US13/330,456 patent/US8274854B2/en not_active Expired - Fee Related
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11306796A (ja) | 1998-04-20 | 1999-11-05 | Hitachi Ltd | 半導体記憶装置 |
JP2000163997A (ja) | 1998-11-30 | 2000-06-16 | Matsushita Electric Ind Co Ltd | 半導体装置 |
US6295243B1 (en) | 1998-11-30 | 2001-09-25 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device |
US6654299B2 (en) | 1998-11-30 | 2003-11-25 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device |
US6778451B2 (en) * | 2000-02-24 | 2004-08-17 | Fujitsu Limited | Semiconductor memory device for masking all bits in a test write operation |
JP2003151299A (ja) | 2001-11-14 | 2003-05-23 | Seiko Epson Corp | 半導体装置およびその検査方法ならびに電子機器 |
US7023748B2 (en) * | 2003-04-01 | 2006-04-04 | Sony Corporation | Semiconductor storage device |
US7190627B2 (en) * | 2003-11-07 | 2007-03-13 | Fujitsu Limited | Semiconductor device |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9245651B2 (en) | 2013-07-15 | 2016-01-26 | Samsung Electronics Co., Ltd. | Memory device for masking read data and a method of testing the same |
US20150036438A1 (en) * | 2013-08-01 | 2015-02-05 | SK Hynix Inc. | Semiconductor apparatus |
US8953391B1 (en) * | 2013-08-01 | 2015-02-10 | SK Hynix Inc. | Semiconductor apparatus |
Also Published As
Publication number | Publication date |
---|---|
JP2009181627A (ja) | 2009-08-13 |
KR20090083858A (ko) | 2009-08-04 |
US8274854B2 (en) | 2012-09-25 |
US20090190416A1 (en) | 2009-07-30 |
JP5629962B2 (ja) | 2014-11-26 |
US20120087195A1 (en) | 2012-04-12 |
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Legal Events
Date | Code | Title | Description |
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AS | Assignment |
Owner name: FUJITSU MICROELECTRONICS LIMITED, JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HARA, KOTA;REEL/FRAME:022594/0233 Effective date: 20090106 |
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AS | Assignment |
Owner name: FUJITSU SEMICONDUCTOR LIMITED, JAPAN Free format text: CHANGE OF NAME;ASSIGNOR:FUJITSU MICROELECTRONICS LIMITED;REEL/FRAME:027414/0015 Effective date: 20100401 |
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STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
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FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
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AS | Assignment |
Owner name: SOCIONEXT INC., JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FUJITSU SEMICONDUCTOR LIMITED;REEL/FRAME:035508/0637 Effective date: 20150302 |
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Year of fee payment: 4 |
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Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
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STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
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FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20200131 |