US7208996B2 - Charge pump circuit - Google Patents

Charge pump circuit Download PDF

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Publication number
US7208996B2
US7208996B2 US11/089,031 US8903105A US7208996B2 US 7208996 B2 US7208996 B2 US 7208996B2 US 8903105 A US8903105 A US 8903105A US 7208996 B2 US7208996 B2 US 7208996B2
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charge transfer
mos transistor
switching element
transfer mos
gate
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US20050213781A1 (en
Inventor
Tatsuya Suzuki
Yasuhiro Kaneda
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Deutsche Bank AG New York Branch
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Sanyo Electric Co Ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H02M3/073—Charge pumps of the Schenkel-type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H02M3/073—Charge pumps of the Schenkel-type
    • H02M3/075—Charge pumps of the Schenkel-type including a plurality of stages and two sets of clock signals, one set for the odd and one set for the even numbered stages
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H02M3/073—Charge pumps of the Schenkel-type
    • H02M3/077—Charge pumps of the Schenkel-type with parallel connected charge pump stages
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
    • H04R19/00—Electrostatic transducers
    • H04R19/04—Microphones

Definitions

  • This invention relates to a charge pump circuit.
  • the charge pump circuit is a simple circuit that is capable of boosting a voltage using a single power supply in the system so that a voltage higher than the power supply voltage is provided.
  • This invention is directed to offer a charge pump circuit suitable for a field of application that requires low current and low power consumption, such as a power supply circuit for a condenser microphone. More specifically, this invention is directed to prevent a voltage loss due to a reverse current in a charge transfer MOS transistor used in the charge pump circuit.
  • the charge pump circuit includes a first switching element for charge transfer and a second switching element for charge transfer that are connected in series, and a first capacitor having a first terminal and a second terminal. The first terminal of the first capacitor is connected to a connecting point between the first switching element for charge transfer and the second switching element for charge transfer.
  • the circuit also includes a third switching element for charge transfer and a fourth switching element for charge transfer that are connected in series, and a second capacitor having a first terminal and a second terminal. The first terminal of the second capacitor is connected to a connecting point between the third switching element for charge transfer and the fourth switching element for charge transfer.
  • the circuit further includes a clock driver for a pair of complementary clocks that alternate between a first voltage level and a second voltage level.
  • the clock driver provides the second terminal of the first capacitor with one of the complementary clocks and the second terminal of the second capacitor with another of the complementary clocks.
  • the circuit includes an input terminal connected to the first switching element for charge transfer and the third switching element for charge transfer, a power supply providing the input terminal with an input voltage, and a control circuit that turns on the second switching element and the third switching element after changing corresponding voltage levels of the complementary clocks while the first switching element, the second switching element, the third switching element and the fourth switching element are turned off, and turns on the first switching element and the fourth switching element after changing corresponding voltage levels of the complementary clocks while the first switching element, the second switching element, the third switching element and the fourth switching element are turned off.
  • FIG. 1 is a circuit diagram showing a condenser microphone system to which a charge pump circuit according to this invention is applied.
  • FIG. 2 is a circuit diagram showing a power supply for biasing the condenser microphone system.
  • FIG. 3 is a circuit diagram showing a conventional charge pump circuit.
  • FIG. 4 is a circuit diagram showing a charge pump circuit according to an embodiment of this invention.
  • FIG. 5 is a timing chart showing an operation of the charge pump circuit according to the embodiment of this invention.
  • FIG. 6 is a circuit diagram showing the operation of the charge pump circuit according to the embodiment of this invention.
  • FIG. 7 is a circuit diagram showing the operation of the charge pump circuit according to the embodiment of this invention.
  • FIG. 8 is a circuit diagram showing the operation of the charge pump circuit according to the embodiment of this invention.
  • FIG. 9 shows a result of a simulation of the charge pump circuit according to the embodiment of this invention.
  • FIG. 1 is a circuit diagram of a condenser microphone system to which the charge pump circuit is applied.
  • a condenser microphone 10 made of a pair of capacitor electrodes and a dielectric disposed between them is formed on a semiconductor die.
  • a biasing power supply 20 is connected to the pair of capacitor electrodes through a resistor 30 .
  • a capacitance of the condenser microphone 10 varies when an external voice (sound pressure) is applied to the pair of capacitor electrodes to cause a fine vibration.
  • the vibration of the capacitor electrodes causes a fine variation in an output signal V of the condenser microphone 10 .
  • An audio output signal is obtained by amplifying the output signal V with a microphone amplifier.
  • the charge pump circuit is used as the biasing power supply 20 .
  • FIG. 2 is a circuit diagram showing the biasing power supply 20 .
  • This circuit is made of n-stages of voltage doublers, i.e. doubler ( 1 )–doubler (N), connected in series.
  • FIG. 3 is a circuit diagram showing an example of a charge pump circuit according to a prior art.
  • a first and a second charge transfer MOS transistors M 1 and M 2 are connected in series.
  • One end of a first pumping capacitor C 1 is connected to a connecting point between the charge transfer MOS transistors M 1 and M 2 .
  • a clock CLK from a clock driver (not shown) is applied to another end of the pumping capacitor C 1 .
  • the input voltage Vin from an input terminal Pin is applied to a source of the first charge transfer MOS transistor M 1 .
  • a source of the second charge transfer MOS transistor M 2 is connected to an output terminal Pout.
  • a third and a fourth charge transfer MOS transistors M 3 and M 4 are connected in series.
  • One end of a second pumping capacitor C 2 is connected to a connecting point between the charge transfer MOS transistors M 3 and M 4 .
  • a reverse clock *CLK from the clock driver (not shown) is applied to another end of the pumping capacitor C 2 .
  • the input voltage Vin from the input terminal Pin is applied to a source of the third charge transfer MOS transistor M 3 .
  • a source of the fourth charge transfer MOS transistor M 4 is connected to the output terminal Pout.
  • a smoothing capacitor Cout is also connected to the output terminal Pout.
  • the first and the third charge transfer MOS transistors M 1 and M 3 are N-channel type, while the second and the fourth charge transfer MOS transistors M 2 and M 4 are P-channel type. It is assumed that a power supply voltage is Vdd and that amplitude of the clock CLK and the reverse clock *CLK is also Vdd.
  • the charge pump circuit operates as described below.
  • M 2 and M 3 are turned on and M 1 and M 4 are turned off.
  • the first pumping capacitor C 1 is discharged while the second pumping capacitor C 2 is charged.
  • M 1 and M 4 are turned on and M 2 and M 3 are turned off.
  • the second pumping capacitor C 2 is discharged while the first pumping capacitor C 1 is charged.
  • Voltage boosting is performed efficiently since the discharging current flows over a whole period of a clock cycle through either M 2 or M 4 .
  • FIG. 4 is a circuit diagram showing a charge pump circuit according to an embodiment of this invention.
  • a first and a second charge transfer MOS transistors M 11 and M 12 are connected in series.
  • One end of a first pumping capacitor CA is connected to a connecting point between the charge transfer MOS transistors M 11 and M 12 .
  • a clock CLK from a clock driver (not shown) is applied to another end of the pumping capacitor CA.
  • An input voltage Vin from an input terminal Pin is applied to a source of the first charge transfer MOS transistor M 11 .
  • a source of the second charge transfer MOS transistor M 12 is connected to an output terminal Pout.
  • a third and a fourth charge transfer MOS transistors M 13 and M 14 are connected in series.
  • One end of a second pumping capacitor CB is connected to a connecting point between the charge transfer MOS transistors M 13 and M 14 .
  • a reverse clock *CLK (an inversion of the clock CLK) from the clock driver (not shown) is applied to another end of the pumping capacitor CB.
  • the input voltage Vin from the input terminal Pin is applied to a source of the third charge transfer MOS transistor M 13 .
  • a source of the fourth charge transfer MOS transistor M 14 is connected to the output terminal Pout.
  • a smoothing capacitor Cout is also connected to the output terminal Pout.
  • the first and the third charge transfer MOS transistors M 11 and M 13 are N-channel type, while the second and the fourth charge transfer MOS transistors M 12 and M 14 are P-channel type.
  • a first clock CLK(B) is provided to a gate of the first charge transfer MOS transistor M 11 through a first coupling capacitor C 11 .
  • a first biasing MOS transistor M 15 is connected between the input terminal Pin and the gate of the first charge transfer MOS transistor M 11 .
  • a third clock CLK(C) is provided to a gate of the third charge transfer MOS transistor M 13 through a third coupling capacitor C 13 .
  • a third biasing MOS transistor M 17 is connected between the input terminal Pin and the gate of the third charge transfer MOS transistor M 13 .
  • a gate of the first biasing MOS transistor M 15 and the gate of the third charge transfer MOS transistor M 13 are connected with each other.
  • a gate of the third biasing MOS transistor M 17 and the gate of the first charge transfer MOS transistor M 11 are connected with each other.
  • a second clock CLK(A) is provided to a gate of the second charge transfer MOS transistor M 12 through a second coupling capacitor C 12 .
  • a second biasing MOS transistor M 16 is connected between the output terminal Pout and the gate of the second charge transfer MOS transistor M 12 .
  • a fourth clock CLK(D) is provided to a gate of the fourth charge transfer MOS transistor M 14 through a fourth coupling capacitor C 14 .
  • a fourth biasing MOS transistor M 18 is connected between the output terminal Pout and the gate of the fourth charge transfer MOS transistor M 14 .
  • a gate of the second biasing MOS transistor M 16 and the gate of the fourth charge transfer MOS transistor M 14 are connected with each other.
  • a gate of the fourth biasing MOS transistor M 18 and the gate of the second charge transfer MOS transistor M 12 are connected with each other.
  • a first initial voltage setting diode D 1 is connected between the gate of the first charge transfer MOS transistor M 11 and the output terminal Pout. That is, an anode of the first initial voltage setting diode D 1 is connected to the gate of the first charge transfer MOS transistor M 11 and a cathode of the first initial voltage setting diode D 1 is connected to the output terminal Pout. Similarly, a third initial voltage setting diode D 3 is connected between the gate of the third charge transfer MOS transistor M 13 and the output terminal Pout.
  • an anode of the third initial voltage setting diode D 3 is connected to the gate of the third charge transfer MOS transistor M 13 and a cathode of the third initial voltage setting diode D 3 is connected to the output terminal Pout.
  • a second initial voltage setting diode D 2 is connected between the gate of the second charge transfer MOS transistor M 12 and the input terminal Pin. That is, a cathode of the second initial voltage setting diode D 2 is connected to the gate of the second charge transfer MOS transistor M 12 and an anode of the second initial voltage setting diode D 2 is connected to the input terminal Pin. Similarly, a fourth initial voltage setting diode D 4 is connected between the gate of the fourth charge transfer MOS transistor M 14 and the input terminal Pin.
  • a cathode of the fourth initial voltage setting diode D 4 is connected to the gate of the fourth charge transfer MOS transistor M 14 and an anode of the fourth initial voltage setting diode D 4 is connected to the input terminal Pin.
  • FIG. 5 is a timing chart of the clocks in the charge pump circuit.
  • FIG. 6 is a circuit diagram to explain the operation in a state A (M 12 and M 13 are turned on) shown in FIG. 5
  • FIG. 7 is a circuit diagram to explain the operation in a state B (M 11 and M 14 are turned on) shown in FIG. 5 .
  • the clock CLK and the reverse clock *CLK from the clock driver are turned from “high” to “low” or from “low” to “high” after all the charge transfer MOS transistors M 11 , M 12 , M 13 and M 14 are turned off again, and then the fourth charge transfer MOS transistor M 14 is turned on to discharge the second pumping capacitor CB and the first charge transfer MOS transistor M 11 is turned on to charge the first pumping capacitor CA, as shown in FIG. 5 (the state B).
  • the first charge transfer MOS transistor M 11 , the second charge transfer MOS transistor M 12 , the third charge transfer MOS transistor M 13 and the fourth charge transfer MOS transistor M 14 are simply referred to as M 11 , M 12 , M 13 and M 14 , respectively, while the first biasing MOS transistor M 15 , the second biasing MOS transistor M 16 , the third biasing MOS transistor M 17 and the fourth biasing MOS transistor M 18 are simply referred to as M 15 , M 16 , M 17 and M 18 , respectively, in the following explanation.
  • the power supply voltage of the clock driver is Vdd
  • the high level is Vdd
  • the low level is Vss (ground voltage) for the clock CLK and the reverse clock *CLK.
  • the high level is Vdd and the low level is Vss for the first clock CLK(B), the second clock CLK(A), the third clock CLK(C) and the fourth clock CLK(D).
  • the input voltage Vin is applied to the input terminal Pin.
  • the clock CLK is turned from “low” to “high” and the reverse clock *CLK is turned from “high” to “low” while all of M 11 , M 12 , M 13 and M 14 are turned off.
  • a voltage at the connecting node between M 11 and M 12 varies from Vin to Vin+Vdd while a voltage at the connecting node between M 13 and M 14 varies from Vin+Vdd to Vin.
  • the second clock CLK(A) is turned from “high” to “low” while the third clock CLK(C) is turned from “low” to “high” at the same time.
  • the charge pump circuit is in the state A shown in FIG. 5 .
  • the operation of the circuit in this state will be explained hereafter, referring to FIG. 6 .
  • the charge pump circuit is in the state B shown in FIG. 5 .
  • the operation of the circuit in this state will be explained hereafter, referring to FIG. 7 .
  • the first and the third initial voltage setting diodes D 1 and D 3 are added to secure the operation of the circuit under an extraordinary initial condition that an initial voltage at a node A or an initial voltage at a node A′ in FIG. 8 is higher than Vout+Vtn, thus one of M 15 and M 17 is always turned on while the other is always turned off.
  • Vtn is a threshold voltage of M 15 and M 17 .
  • the first and the third initial voltage setting diodes D 1 and D 3 are provided so that a forward current of the diode flows to reduce the voltage at the node A or A′ when the voltage at the node A or A′ is higher than Vout.
  • the second and the fourth initial voltage setting diodes D 2 and D 4 are added to secure the operation of the circuit under an extraordinary initial condition that an initial voltage at a node B or an initial voltage at a node B′ in FIG. 8 is lower than Vin+Vtp, thus one of M 16 and M 18 is always turned on while the other is always turned off.
  • Vtp is a threshold voltage of M 16 and M 18 .
  • the initial voltage at the node B is lower than Vin+Vtp.
  • the voltage at the gate of M 18 is also lower than Vin+Vtp, which keeps M 18 turned on.
  • the second and the fourth initial voltage setting diodes D 2 and D 4 are provided so that a forward current of the diode flows to increase the voltage at the node B or B′ when the voltage at the node B or B′ is lower than Vin.
  • FIG. 9 shows a result of simulations of the output voltage Vout of the charge pump circuit according to the embodiment. While voltage loss due to the reverse current are seen for the circuit without the measures against the reverse current (the circuit shown in FIG. 3 ), such voltage loss is not seen for the circuit with the measures against the reverse current (the circuit shown in FIG. 4 ).
  • the charge pump circuit according to the embodiment of this invention can prevent the reverse current in the charge transfer MOS transistor and the resultant voltage loss.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)
US11/089,031 2004-03-26 2005-03-25 Charge pump circuit Active 2025-12-09 US7208996B2 (en)

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JP2004-092639 2004-03-26
JP2004092639A JP4557577B2 (ja) 2004-03-26 2004-03-26 チャージポンプ回路

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JP (1) JP4557577B2 (zh)
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US20090066407A1 (en) * 2007-09-12 2009-03-12 Rochester Institute Of Technology Charge pump systems and methods thereof
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US9083231B2 (en) 2013-09-30 2015-07-14 Sandisk Technologies Inc. Amplitude modulation for pass gate to improve charge pump efficiency
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US20160118879A1 (en) * 2014-10-23 2016-04-28 Infineon Technologies Ag Charge pump
US9385596B1 (en) 2015-01-07 2016-07-05 Ememory Technology Inc. Charge pump circuit capable of reducing reverse currents
US9520776B1 (en) 2015-09-18 2016-12-13 Sandisk Technologies Llc Selective body bias for charge pump transfer switches
US9602921B2 (en) 2015-06-24 2017-03-21 Robert Bosch Gmbh Independently charge pumps for differential microphone
US9647536B2 (en) 2015-07-28 2017-05-09 Sandisk Technologies Llc High voltage generation using low voltage devices
US9917507B2 (en) 2015-05-28 2018-03-13 Sandisk Technologies Llc Dynamic clock period modulation scheme for variable charge pump load currents
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JP4557577B2 (ja) 2010-10-06
KR20060044671A (ko) 2006-05-16

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