US5592001A - Non-volatile semiconductor memory device - Google Patents

Non-volatile semiconductor memory device Download PDF

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US5592001A
US5592001A US08/626,148 US62614896A US5592001A US 5592001 A US5592001 A US 5592001A US 62614896 A US62614896 A US 62614896A US 5592001 A US5592001 A US 5592001A
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memory cells
transistors
data
pair
memory
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Masamichi Asano
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Toshiba Corp
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Toshiba Corp
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
    • G11C16/3495—Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates

Definitions

  • This invention relates to a non-volatile semiconductor memory device.
  • EEPROM Electrically Erasable Programmable ROM
  • FIG. 1 is a cross sectional view showing the device structure of a typical memory cell in the EEPROM
  • FIG. 2 is an equivalent circuit diagram thereof.
  • N-type diffused regions 91, 92 and 93 are provided on a P-type substrate 80.
  • a floating gate electrode 95 formed of a polycrystalline silicon layer of the first layer is provided on an insulating oxide film 94.
  • This floating gate electrode 95 overlaps with the N-type diffused region 92 through a thin film portion 94A of the insulating oxide film 94.
  • a gate electrode 97 formed of a polycrystalline silicon layer of the second layer is provided on an insulating oxide film 96.
  • a gate electrode 99 formed of a polycrystalline silicon layer is provided on an insulating oxide film 98.
  • the memory cell of FIG. 1 includes two transistors 1 and 2. Namely, one is a transistor 2 having a floating gate (called floating gate transistor hereinafter) as a non-volatile memory element having the N-type diffused region 91 as the source, the N-type diffused region 92 as the drain, the floating gate electrode 95 as the floating gate, and the gate electrode 97 as the control gate.
  • the other is a select transistor 1 of enhancement type having the N-type diffused region 92 as the source, the N-type diffused region 93 as the drain, and the gate electrode 99 as the gate.
  • These transistors 1 and 2 are connected in series. As indicated by the equivalent circuit of FIG. 2, the drain and the gate of the transistor 1 are used as the data line DL and the word line WL, respectively.
  • the floating gate and the control gate of the floating gate transistor 2 are used as the floating gate FG and the control gate CG, respectively, and the source of the floating gate transistor 2 is used as the source S. It is to be noted that the memory cell of FIG. 1 constitutes a one bit data memory unit (memory element) for storing data of one bit.
  • FIG. 3 is a characteristic curve showing changes in the threshold voltage (V th ) of the floating gate transistor when the high temperature shelf test is conducted at 300° C.
  • the threshold voltage in an initial state is about 1 volt as indicated by a broken line.
  • the threshold voltage of the floating gate transistor takes a substantially negative value, e.g., -5 volts. For this reason, a current flows even if the potential on the control gate is zero volts.
  • the threshold voltage of the floating gate transistor takes a substantially high value, e.g., +10 volts.
  • the potential on the control gate is set to zero volts.
  • the judgment as to whether the data stored in the memory cell is "0" or "1" is carried out by setting the operating point of the sense amplifier circuit, i.e., sense potential so that a suitable current flows in the memory cell. This sense potential is set to about -1 volt as indicated by the single dotted lines.
  • FIG. 4 shows the change of the cell current (I cell ) at the time of the high temperature shelf test of the memory cell in which "0" level data is stored. With the lapse of time, the cell current decreases. When the cell current is below the sense level current Is in the sense amplifier circuit, the sense amplifier circuit erroneously judges data which has been originally at the "0" level to be “1" level data. It is only the memory cells in which "0" level data is stored, that data may be erroneously detected as stated above. The time when such an erroneous data is detected is now assumed to be t N . In the case of the normal memory cell, the time required for reaching the time t N is sufficiently long, and there is therefore no problem in view of actual use.
  • the time required for reaching the time t N is small. For this reason, there are instances where memory cells may become inferior or defective while they are being used in a product. Particularly, if erasing and/or writing are frequently repeated, the insulating oxide film is considerably deteriorated, so inferiority is apt to occur.
  • FIG. 5 is a circuit diagram of a conventional typical EEPROM in which memory cells similar to the memory cell shown by the equivalent circuit of FIG. 2 are used to constitute a cell array.
  • the control gates of the floating gate transistors 2 of memory cells MC-11 to MC-mn are connected to control gate select lines CGL1 to CGLn selected by column decoders 5-1 to 5-n through control gate select transistors 6. Further, the gate of the control gate select transistor 6 and the gate of the select transistor 1 in each same memory cell are both connected to one of the row lines WL1 to WLm selected by the row decoder 4. Drains of the select transistors 1 in respective memory cells are connected to column lines DL1 to DLn.
  • Respective column lines DL1 to DLn are connected in common to a bus line 8 through column select transistors 7.
  • the gates of the transistors 7 are connected to the corresponding column decoders 5 through column select lines CL1 to CLn, respectively.
  • a data input circuit 9 and a sense amplifier circuit 10 are connected to the bus line 8.
  • the data input circuit 9 outputs data of "0" or “1” level depending on a write data signal Din inputted from the outside.
  • the sense amplifier circuit 10 detects, as “0” or "1", the level of data stored in a selected memory cell MC.
  • the sense amplifier circuit 10 applies a bias voltage necessary for the readout of data to a corresponding data line DL.
  • the sense amplifier circuit 10 includes a bias circuit.
  • the data sensed at the sense amplifier circuit 10 is inputted to a data output circuit 12. Readout data is outputted from the data output circuit 12 to the outside.
  • An object of this invention is to provide a high reliability non-volatile semiconductor memory device as a device having a configuration permitting the memory capacity to be large.
  • a non-volatile semiconductor memory device comprising: a plurality of floating gate transistors constituting non-volatile memory cells and forming a cell array or arrays substantially in a matrix form comprised of said memory cells, a plurality of data lines for transmitting data to the memory cells of respective columns of said cell array or arrays and receiving data therefrom, word lines for selecting the memory cells of respective rows of said cell array or arrays to connect selected memory cells to corresponding data lines, respectively, a column decoder for selecting said data lines, and a row decoder for selecting said word lines, a pair of memory cells of said plurality of memory cells selected by said respective word lines being connected to said respective data lines by the common junction where drains of said a pair of memory cells are commonly connected, one bit data memory unit for storing one bit data being comprised of said a pair of memory cells.
  • a non-volatile semiconductor memory device comprising: a plurality of floating gate transistors constituting non-volatile memory cells and forming a cell array or arrays substantially in a matrix form comprised of said memory cells, a plurality of data lines for transmitting data to the memory cells of respective columns of said cell array or arrays and receiving data therefrom, word lines for selecting the memory cells of respective rows of said cell array or arrays to connect selected memory cells to corresponding data lines, respectively, a column decoder for selecting said data lines, and a row decoder for selecting said word lines, a pair of memory cells of said plurality of memory cells selected by said respective word lines being connected to said respective data lines by the common junction where drains of said pair of memory cells are commonly connected, select transistors turned ON and OFF by said word lines being provided between said common junction and the drains of said respective pair of memory cells, each one bit data memory unit being comprised of said two non-volatile memory cells and one of said select transistors.
  • the 1 bit data memory unit for storing data of 1 bit is constituted with a pair of memory cells, the reliability becomes high as a matter of course.
  • the drains of a pair of memory cells in the bit data memory unit are connected to a single data line at the common junction, the dimension of the memory device becomes smaller as a whole than that of the device in which the drains of a pair of memory cells are connected to different data lines, respectively.
  • the drains of a pair of memory cells are connected to a single data line through a single contact.
  • select transistor may be provided for every memory cell, but only one select transistor may be provided in common to two transistors.
  • An employment of the arrangement including one select transistor is advantageous for miniaturization.
  • a pair of memory cells in the 1 bit data memory unit a pair of memory cells arranged in a row direction of memory cells arranged in a matrix form, or a pair of memory cells arranged in a column direction thereof may be employed.
  • a certain diffused layer can be used as the drain of one memory cell of the adjacent memory cells, and can be used as the source of the other memory cell.
  • the size in a row direction is further reduced.
  • FIG. 1 is a cross sectional view of a memory cell in the prior art
  • FIG. 2 is an equivalent circuit diagram of the memory cell shown in FIG. 1;
  • FIGS. 3 and 4 are characteristic diagrams of the memory cell shown in FIG. 1;
  • FIG. 5 is a circuit diagram showing the entirety of a conventional device
  • FIG. 6 is a diagram showing the plan pattern view of a memory cell according to this invention.
  • FIG. 7 is a cross sectional view taken along the A--A line of FIG. 6;
  • FIG. 8 is a diagram showing a partial plan pattern view of a first embodiment according to this invention.
  • FIG. 9 is a cross sectional view taken along the A--A line of FIG. 8;
  • FIG. 10 is an equivalent circuit diagram of the first embodiment shown in FIG. 8;
  • FIG. 11 is a circuit diagram showing the entirety of a memory device according to this invention.
  • FIG. 12 is a circuit diagram showing an example of a semiconductor memory device of the four bit type
  • FIG. 13 is a diagram showing a partial plan pattern view of a second embodiment according to this invention.
  • FIG. 14 is a cross sectional view taken along the A--A line of FIG. 13;
  • FIG. 15 is an equivalent circuit diagram of the second embodiment shown in FIG. 13;
  • FIG. 16 is a circuit diagram showing the configuration of EEPROM
  • FIG. 17 is a diagram showing a partial plan pattern view of a third embodiment according to this invention.
  • FIG. 18 is an equivalent circuit diagram of the third embodiment shown in FIG. 17;
  • FIG. 19 is a diagram showing a partial plan pattern view of a fourth embodiment according to this embodiment.
  • FIG. 20 is a cross sectional view taken along the A--A line of the fourth embodiment shown in FIG. 19;
  • FIG. 21 is an equivalent circuit diagram of the fourth embodiment shown in FIG. 19;
  • FIG. 22 is a partial cross sectional view of a fifth embodiment according to this invention.
  • FIG. 23 is a partial cross sectional view of a sixth embodiment according to this invention.
  • FIG. 24 is a cross sectional view taken along the line A--A of FIG. 23;
  • FIG. 25 is an equivalent circuit diagram of the sixth embodiment shown in FIG. 23;
  • FIG. 26 is a circuit diagram showing the entirety of a seventh embodiment according to this invention.
  • FIG. 27 is a partial plan view of the seventh embodiment shown in FIG. 26;
  • FIG. 28 is a circuit diagram showing the entirety of an eighth embodiment according to this invention.
  • FIG. 29 is a circuit diagram showing the entirety of a ninth embodiment according to this invention.
  • FIG. 30 is a diagram showing a partial plan pattern view of an actual device constructed on the basis of the ninth embodiment shown in FIG. 29;
  • FIG. 31 is a cross sectional view taken along the A--A line of FIG. 30.
  • FIG. 32 is a cross sectional view taken along the B--B line of FIG. 30.
  • FIGS. 6 and 7 there is shown a portion of an EEPROM (a unit cell, 1 bit data memory unit) according to this invention, constructed so that memory cells can be miniaturized to a greater degree.
  • FIG. 6 shows a plan view of an actual arrangement, with the section encompassed by single-dotted lines a, b, c and d representing a unit memory cell.
  • FIG. 7 is a cross sectional view taken along the A--A line of FIG. 6.
  • the configuration shown in FIG. 7 differs from the configuration shown in FIG. 1 in that the insulating oxide film 94 of the floating gate transistor 2 is formed as a thin film of 100 angstroms, and that the thin film portion 94A of FIG. 1 for allowing a tunnel current to flow therein is omitted.
  • the same reference numerals are attached to parts similar to those in FIG. 1, respectively.
  • the size in a thickness direction of the floating gate transistor 2 can be reduced to a large degree.
  • the size in a lateral direction is determined, as seen from FIG. 6, by the contact portion 90. Namely, by the size l 1 of the contact 90, the margin l 2 between the contact 90 and the drain n + diffused layer 93, and the size l 3 of the field isolation portion between adjacent drain n + diffused layer 93, the size of the cell is determined.
  • These sizes are fixed in the manufacturing process determined in advance. For this reason, it is difficult in practice to arbitrarily reduce these respective sizes. In view of this, even when an attempt is made to use two (a pair of) memory cells of FIGS. 6 and 7 to construct the abovementioned high reliability non-volatile semiconductor memory (1 bit data memory unit), the chip size becomes large also in this case. Accordingly, it is considered difficult to realize a large capacity memory device.
  • FIG. 8 differs from that of FIG. 6 in that a single contact is formed in common to two (a pair of) cells of the NAND structure of the cell including transistors 1A and 2A and the cell including transistors 1B and 2B. Its equivalent circuit is shown in FIG. 10.
  • the size in a lateral direction of the memory cell is not determined by the contact portion 90, but is determined by the width W 1 of the floating gate 95 and the distance W 2 between the floating gates 95 and 95.
  • the size in a lateral direction of the cell is determined by the minimum dimension required for stable process of the floating gate 95, the size of the entirety of the device is reduced to a large degree.
  • the area of the memory cell (1 bit data memory unit) encompassed by the dotted lines a, b, c and d of FIG. 8 is reduced to about 70% of the area in the case of the structure comprised of two memory cells shown in FIG. 6.
  • the cross section taken along the A--A line of FIG. 8 is shown in FIG. 9.
  • Table 1 shows the operational mode of the memory cell indicated by the equivalent circuit of FIG. 10.
  • this memory cell there are four operational modes of: 1 the erase mode, 2 "0" write mode, 3 "1" write mode, and 4 readout mode. These operational modes will now be described below.
  • high potentials H e.g., 20 volts
  • V WL and V CG potentials
  • a potential of zero volts is applied to the data line DL.
  • the potential V FG on the floating gate FG becomes a high potential H (e.g., about 12 volts) by the capacitive coupling between the floating gate FG and the control gate CG.
  • the potential V WL on the word line WL is caused to be a high potential H
  • the potential V CG on the control gate CG is caused to be zero volts
  • the potential V S on the source S is caused to be a high potential H (e.g., 5 volts).
  • the operational mode is the "0" write mode
  • the potential V DL on the data line DL is caused to be a high potential H (data input "0").
  • the floating gate FG is caused to have a low potential L by the capacitive coupling between the floating gate FG and the control gate CG. In this case, by the tunnel effect of Fowler-Noldheim, electrons are discharged from the floating gate FG of the floating gate transistor 2 into the drain through the thin film portion 94. This operation is called a "0" write operation.
  • the operational mode is the "1" write mode
  • the potential V DL on the data line DL is caused to have zero volts (data input "1").
  • the floating gate FG has substantially no potential difference between the floating gate FG and the control gate CG, resulting in substantially zero volts. In this case, there is no movement of electrons.
  • This operation is called a data "1" write operation.
  • the potential VWL on the word line WL is caused to be 5 volts
  • the potential V DL on the data line DL is caused to be equal to about 1 volt
  • the potential V CG on the control gate CG is caused to be equal to zero volts.
  • the memory cell can perform a normal operation as a whole.
  • FIG. 11 is a circuit diagram showing the configuration of a memory cell of one bit type wherein the one bit memory unit of the prior art shown in FIG. 5 is replaced by that in FIG. 10.
  • This circuit may be readily of a structure of the multi-bit type.
  • FIG. 12 shows a memory cell of the four bit type of the section corresponding to the section encompassed by broken lines of FIG. 11. When such a configuration is employed, input/output of 4 bit data may be carried out.
  • FIG. 13 shows the section (1 bit data memory unit) corresponding to the section encompassed by broken lines a, b, c and d of FIG. 8.
  • the configuration of FIG. 13 differs from the configuration of FIG. 8 in that only one select gate transistor is provided.
  • the area of the N-type diffused layer region 93 adjoining the data line DL can be reduced as shown in FIG. 13.
  • the parasitic capacitance of the diffused layer 93 is reduced, so the charge/discharge rate of the data line DL becomes fast.
  • FIG. 14 is a cross sectional view taken along the A--A line of FIG. 13.
  • FIG. 15 is an equivalent circuit of FIG. 13, and
  • FIG. 16 is a circuit diagram showing the configuration of EEPROM.
  • FIGS. 17 and 18 there is shown a third embodiment of this invention.
  • a memory cell suitable for miniaturization is shown.
  • the embodiment of FIG. 17 differs from the embodiment of FIG. 13 in that the common source of two floating gate transistors 2A and 2B is separated into two sources S A and S B .
  • Two source interconnections (Al) for two sources S A and S B are required from a viewpoint of layout of the drawing.
  • sources S A and S B may be connected to the same source line.
  • the memory cell size becomes equal to 63% of that in FIG. 6. Namely, the memory cell size can be reduced to a great extent.
  • a polycrystalline silicon layer of the third layer is used to thereby permit the memory cell size to be further miniaturized.
  • a floating gate 95 is formed by the polycrystalline silicon of the first layer
  • a control gate 97 is formed by the polycrystalline silicon of the second layer.
  • An insulating film 102 is then formed.
  • a select gate 103 serving as the word line is formed by the polycrystalline silicon of the third layer.
  • the memory cell size can be reduced to 56% of that in FIG. 6.
  • an N-layer 96A is provided between the floating gate 95 and the control gate 97, thus allowing the insulating film to be of a triple layer structure of O-N-O (Oxide-Nitride-Oxide). Since such a triple layer structure is employed, even if the insulating film between two gates 95 and 97 is allowed to be thin, it is possible to set the insulating withstand voltage to a higher value.
  • the equivalent circuit of FIG. 19 is shown in FIG. 21.
  • FIG. 22 shows a fifth embodiment as a modified example of FIG. 20 along the same cross section.
  • the floating gate 95 is etched subsequently to form gate 97 by using the gate 97 as a mask.
  • the floating gate 95 is formed so that it has substantially the same size as that of the gate 97.
  • the select gate 103 of the third layer is formed, the select gate 103 and the floating gate 95 directly face each other. For this reason, there is the possibility that the withstand voltage between the floating gate 95 and the select gate 103 may be deteriorated depending upon the circumstances.
  • the modified example shown in FIG. 22 contemplates improving the above problem.
  • a floating gate 95 is first formed, and a control gate 97 is then formed so as to sufficiently cover the floating gate 95.
  • reference numerals 91A and 92A denote N-type diffused layers, respectively. These layers may have a concentration somewhat lower than that of the diffused layer 91 and 93.
  • the floating gate 95 is perfectly covered with the insulating film of O-N-O.
  • the withstand voltage between the floating gate 95 and the select gate 103 is improved, and the reliability is also improved.
  • the initial threshold value of a broken cell is 1 volt.
  • the drain voltage at the time of readout operation is set to a value of less than 1 volt, the broken cell is in an OFF state at all times at the time of readout operation. For this reason, the effects with the memory cell according to this invention can be exhibited.
  • FIGS. 23 to 25 there is shown a portion of a sixth embodiment (EEPROM) adapted so that the 1 bit data memory unit can be constituted with a single transistor, and be suitable for miniaturization.
  • the memory device shown in FIGS. 23 to 25 is equivalent to the memory device in which the select transistor 1 in FIGS. 6 and 7 is omitted, and includes only the floating gate transistor 2 as the transistor.
  • FIG. 24 is a cross sectional view taken along the A--A line of FIG. 23 and FIG. 25 is an equivalent circuit of FIG. 23.
  • a high voltage (e.g., 7 volts) is applied to the drain D, a voltage of zero volts is applied to the source S, and a high voltage (e.g., 12 volts) is applied to the control gate CG.
  • a high voltage e.g., 7 volts
  • a voltage of zero volts is applied to the source S
  • a high voltage e.g., 12 volts
  • the drain D is placed in a floating state, and a low potential (e.g., zero volts) is applied to the control gate CG and a high voltage (e.g., 12 volts) is applied to the source S.
  • a low potential e.g., zero volts
  • a high voltage e.g., 12 volts
  • the threshold value of this transistor shifts to a negative direction. In this case, if erasing is carried out too much, the threshold value takes a negative value. For this reason, it is required to stop erasing at a reasonable time point.
  • the threshold value after erasing is set to a value between 0 to 5 volts.
  • the threshold value is set to about 1 to 2 volts.
  • a voltage of about 1 volt is applied to the drain D, a voltage of zero volts is applied to the source S, and a voltage of 5 volts is applied to the control gate CG.
  • this transistor is turned OFF. As a result, no current flows.
  • the transistor is turned ON. As a result, the current flows. This current is sensed by the sense amplifier. The data stored therein is thus read out.
  • While such a memory cell is suitable for miniaturization, it is required to simultaneously erase a plurality of memory cells (all memory cells in the chip according to the circumstances) at the time of erase operation and provide control such that its threshold value is equal to a fixed value.
  • a tunnel current flows in the oxide film at the time of erase operation, there might be an unsatisfactory operation in which electrons are trapped by defect, etc. in the oxide film, so the erasing characteristic is deteriorated by repetition of writing and/or erasing (W/E). In most cases, such an unsatisfactory operation may take place with a certain probability in an eventual manner.
  • W/E writing and/or erasing
  • FIG. 26 shows the entirety of the EEPROM of a seventh embodiment in which the cell shown in FIGS. 23 to 25 is used to improve such an unsatisfactory erasing.
  • respective 1 bits are comprised of two memory cells 30A and 30B as indicated by the broken lines 40.
  • the common source VS* is provided commonly to all the cells.
  • this memory cell array is divided into a plurality of blocks to provide common sources to respective blocks to carry out erasing of all of the blocks.
  • FIG. 27 is a diagram showing the plane pattern as an actual example of FIG. 26, and corresponds to the section 7b of FIG. 26.
  • the same reference numerals are attached to the same members, respectively.
  • the reference symbols a, b, c and d correspond to the reference symbols a, b, c and d of FIG. 23, respectively.
  • FIG. 28 An eighth embodiment as a modified example of the embodiment of FIG. 26 is shown in FIG. 28.
  • the memory cell array is divided into the first section connected to word lines WL1 to WLk and the second section connected to word lines WL (K+1) to WLm.
  • a first row decoder 32-1 for selecting word lines WL 1 to WLk, and a second row decoder 32-2 for selecting word lines WL (K+1) to WLm are separately provided.
  • the 1 bit data memory unit is comprised of two cells to constitute a high reliability memory area.
  • the second section is formed as the ordinary memory area where the 1 bit data memory unit is comprised of a single cell. It can be said that this configuration is such that the 2 cell/bit structure is applied only to the area for which high reliability of W/E is required. For this reason, an increase in the chip area can be held down to a minimum value while improving the reliability.
  • the common source is separated into two sources VS*1 and VS*2 in this emboidment, such sources may be a single common source.
  • the data lines DL are common in this embodiment.
  • the pitches in a lateral direction of the memory cells of the first and second sections are different from each other. For this reason, it is preferable to completely separate the array at the first and second sections to separately provide row decoders and column decoders at the separated portions, respectively.
  • FIG. 29 A ninth embodiment is shown in FIG. 29.
  • memory cells arranged in a row direction are all connected in left and right directions wherein a pair of memory cells adjacent in left and right directions are assumed as a 1 bit data memory unit.
  • memory cells arranged in a row direction are successively connected in series. Namely, the drain D of a memory cell 30-1 and the drain D of a memory cell 30-2 on the left side thereof are connected, and the source S of the memory cell 30-1 and the source S of a memory cell on the right side thereof are connected. Namely, when attention is drawn to two arbitrary adjacent memory cells, the drain of one cell and the drain of the other cell are connected to each other. On the other hand, when attention is drawn to the other adjacent two memory cells, the source of one cell and the source of the other cell are connected to each other.
  • data lines DL1 to DLn are connected to the drains D of respective memory cells, and common sources S*1 to S* (n+1) are connected to the sources 5 thereof. These common sources S*1 to S* (n+1) are further connected to the common source VS*.
  • a pair of left and right memory cells 30-1 and 30-2 constitute a 1 bit memory cell illustrated as a section encompassed by broken lines 40 in the figure.
  • FIGS. 30 to 32 An example of an actual layout of the embodiment of FIG. 29 is shown in FIGS. 30 to 32.
  • diffused layers for the source S and the drain D are provided one after another in a word line direction. These diffused layers are commonly used with respect to adjacent two transistors. Namely, when attention is drawn to, e.g., memory cells 30-1 and 30-2, the drain D1 existing therebetween is commonly used as drains D and D of the memory cells 30-1 and 30-2. Further, the source S1 existing between memory cells 30-1 and 30-3 is commonly used as sources S and S for these two memory cells. Namely, it is unnecessary to provide an isolation field oxide film between respective memory cells. Actually, no field oxide film exists. For this reason, miniaturization in a word line direction can be attained.
  • data lines DL1, DL2, . . . and common sources (source wirings) S*1, S*2, . . . are formed by an Aluminum interconnection layer in upper and lower directions in the figure.
  • These data lines and source wirings are connected to diffused layers (sources, drains) by contacts 90, 90, . . . at a predetermined interval. The interval between contacts is set to a value such that the resistance of the diffused layer for the drain or source does not affect the characteristic.
  • each gate of the select transistors 1, 1A and 1B of the cell is comprised of a conductive layer (e.g., polysilicon) of the second layer
  • a conductive layer e.g., polysilicon
  • a double layer structure comprised of a conductive layer (e.g., polysilicon) of the first layer and a conductive layer of the second layer forming the floating gate is formed to etch the insulating film between the conductive layers of the first and second layers so that these conductive layers are short-circuited.
  • select transistors 1, 1A and 1B can be formed by the same process as that forming the floating gate transistor 2. The processing margin is therefore improved.

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US5966601A (en) * 1997-01-21 1999-10-12 Holtek Microelectronics Inc. Method of making non-volatile semiconductor memory arrays
US6014328A (en) * 1997-09-05 2000-01-11 Mitsubishi Denki Kabushiki Kaisha Memory cell allowing write and erase with low voltage power supply and nonvolatile semiconductor memory device provided with the same
US6055185A (en) * 1998-04-01 2000-04-25 National Semiconductor Corporation Single-poly EPROM cell with CMOS compatible programming voltages
US6081451A (en) * 1998-04-01 2000-06-27 National Semiconductor Corporation Memory device that utilizes single-poly EPROM cells with CMOS compatible programming voltages
US6118691A (en) * 1998-04-01 2000-09-12 National Semiconductor Corporation Memory cell with a Frohmann-Bentchkowsky EPROM memory transistor that reduces the voltage across an unprogrammed memory transistor during a read
US6141246A (en) * 1998-04-01 2000-10-31 National Semiconductor Corporation Memory device with sense amplifier that sets the voltage drop across the cells of the device
US6157574A (en) * 1998-04-01 2000-12-05 National Semiconductor Corporation Erasable frohmann-bentchkowsky memory transistor that stores multiple bits of data
US6188102B1 (en) * 1995-10-16 2001-02-13 Nec Corporation Non-volatile semiconductor memory device having multiple different sized floating gates
US6388922B1 (en) * 1999-06-09 2002-05-14 Sanyo Electric Co., Ltd. Semiconductor memory and method of operating semiconductor memory
WO2002058071A2 (en) * 2001-01-17 2002-07-25 Cavendish Kinetics Limited Non-volatile memory
EP1089332A3 (de) * 1999-09-30 2003-01-08 Micronas GmbH Verfahren zur Herstellung eines integrierten CMOS-Halbleiterspeichers
US20050041476A1 (en) * 1998-09-10 2005-02-24 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory
US20050047213A1 (en) * 2003-08-28 2005-03-03 Akira Umezawa Nonvolatile semiconductor memory device with MOS transistors each having a floating gate and a control gate
US20060023509A1 (en) * 2004-07-30 2006-02-02 Seiko Epson Corporation Nonvolatile memory device and data write method for nonvolatile memory device
US20090103361A1 (en) * 2007-05-04 2009-04-23 Lee Wang Level verification and adjustment for multi-level cell (mlc) non-volatile memory (nvm)
US10262746B2 (en) 2016-01-19 2019-04-16 Ememory Technology Inc. Nonvolatile memory structure
CN111816235A (zh) * 2019-04-11 2020-10-23 力旺电子股份有限公司 随机比特单元
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JP5629968B2 (ja) * 2008-09-19 2014-11-26 凸版印刷株式会社 不揮発性半導体メモリセル及び不揮発性半導体メモリ装置
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US5949101A (en) * 1994-08-31 1999-09-07 Kabushiki Kaisha Toshiba Semiconductor memory device comprising multi-level logic value of the threshold voltage
US6188102B1 (en) * 1995-10-16 2001-02-13 Nec Corporation Non-volatile semiconductor memory device having multiple different sized floating gates
US5966601A (en) * 1997-01-21 1999-10-12 Holtek Microelectronics Inc. Method of making non-volatile semiconductor memory arrays
US6014328A (en) * 1997-09-05 2000-01-11 Mitsubishi Denki Kabushiki Kaisha Memory cell allowing write and erase with low voltage power supply and nonvolatile semiconductor memory device provided with the same
US6055185A (en) * 1998-04-01 2000-04-25 National Semiconductor Corporation Single-poly EPROM cell with CMOS compatible programming voltages
US6081451A (en) * 1998-04-01 2000-06-27 National Semiconductor Corporation Memory device that utilizes single-poly EPROM cells with CMOS compatible programming voltages
US6118691A (en) * 1998-04-01 2000-09-12 National Semiconductor Corporation Memory cell with a Frohmann-Bentchkowsky EPROM memory transistor that reduces the voltage across an unprogrammed memory transistor during a read
US6137724A (en) * 1998-04-01 2000-10-24 National Semiconductor Corporation Memory device that utilizes single-poly EPROM cells with CMOS compatible programming voltages
US6141246A (en) * 1998-04-01 2000-10-31 National Semiconductor Corporation Memory device with sense amplifier that sets the voltage drop across the cells of the device
US6157574A (en) * 1998-04-01 2000-12-05 National Semiconductor Corporation Erasable frohmann-bentchkowsky memory transistor that stores multiple bits of data
US6271560B1 (en) 1998-04-01 2001-08-07 National Semiconductor Corporation Single-poly EPROM cell with CMOS compatible programming voltages
US7333369B2 (en) 1998-09-10 2008-02-19 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory
US7173850B2 (en) * 1998-09-10 2007-02-06 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory
US20070133283A1 (en) * 1998-09-10 2007-06-14 Kabushiki Kaisha Toshiba Nonvolatile Semiconductor Memory
US7301809B2 (en) 1998-09-10 2007-11-27 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory
US20070133282A1 (en) * 1998-09-10 2007-06-14 Kabushiki Kaisha Toshiba Nonvolatile Semiconductor Memory
US20050041476A1 (en) * 1998-09-10 2005-02-24 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory
US20070127292A1 (en) * 1998-09-10 2007-06-07 Kabushiki Kaisha Toshiba Nonvolatile Semiconductor Memory
US7463540B2 (en) 1998-09-10 2008-12-09 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory
US6388922B1 (en) * 1999-06-09 2002-05-14 Sanyo Electric Co., Ltd. Semiconductor memory and method of operating semiconductor memory
EP1089332A3 (de) * 1999-09-30 2003-01-08 Micronas GmbH Verfahren zur Herstellung eines integrierten CMOS-Halbleiterspeichers
WO2002058071A3 (en) * 2001-01-17 2003-01-16 Cavendish Kinetics Ltd Non-volatile memory
WO2002058071A2 (en) * 2001-01-17 2002-07-25 Cavendish Kinetics Limited Non-volatile memory
US20040056318A1 (en) * 2001-01-17 2004-03-25 Smith Charles Gordon Non-volatile memory
EP1227496A1 (en) * 2001-01-17 2002-07-31 Cavendish Kinetics Limited Non-volatile memory
US20050047213A1 (en) * 2003-08-28 2005-03-03 Akira Umezawa Nonvolatile semiconductor memory device with MOS transistors each having a floating gate and a control gate
US6961268B2 (en) * 2003-08-28 2005-11-01 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device with MOS transistors each having a floating gate and a control gate
US20060023509A1 (en) * 2004-07-30 2006-02-02 Seiko Epson Corporation Nonvolatile memory device and data write method for nonvolatile memory device
US7292475B2 (en) * 2004-07-30 2007-11-06 Seiko Epson Corporation Nonvolatile memory device and data write method for nonvolatile memory device
US20090103361A1 (en) * 2007-05-04 2009-04-23 Lee Wang Level verification and adjustment for multi-level cell (mlc) non-volatile memory (nvm)
US7660154B2 (en) * 2007-05-04 2010-02-09 Flashsilicon, Incorporation Level verification and adjustment for multi-level cell (MLC) non-volatile memory (NVM)
US10892266B2 (en) 2016-01-19 2021-01-12 Ememory Technology Inc. Nonvolatile memory structure and array
US10262746B2 (en) 2016-01-19 2019-04-16 Ememory Technology Inc. Nonvolatile memory structure
CN111816235A (zh) * 2019-04-11 2020-10-23 力旺电子股份有限公司 随机比特单元
TWI726674B (zh) * 2019-04-11 2021-05-01 力旺電子股份有限公司 隨機位元單元
US11101798B2 (en) * 2019-04-11 2021-08-24 Ememory Technology Inc. Random bit cell using P-type transistors
CN111816235B (zh) * 2019-04-11 2022-07-29 力旺电子股份有限公司 随机比特单元
CN112086115A (zh) * 2019-06-14 2020-12-15 力旺电子股份有限公司 存储器系统
CN112086115B (zh) * 2019-06-14 2023-03-28 力旺电子股份有限公司 存储器系统

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JP2685966B2 (ja) 1997-12-08
DE69130993T2 (de) 1999-07-29
EP0463580A3 (en) 1993-06-09
JPH0457293A (ja) 1992-02-25
KR950010725B1 (ko) 1995-09-22
DE69130993D1 (de) 1999-04-22
KR920001720A (ko) 1992-01-30

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