US20180061769A1 - Semiconductor device and method of manufacturing the same - Google Patents

Semiconductor device and method of manufacturing the same Download PDF

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Publication number
US20180061769A1
US20180061769A1 US15/640,042 US201715640042A US2018061769A1 US 20180061769 A1 US20180061769 A1 US 20180061769A1 US 201715640042 A US201715640042 A US 201715640042A US 2018061769 A1 US2018061769 A1 US 2018061769A1
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Prior art keywords
hole
conductive film
semiconductor device
wiring layer
insulating film
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Abandoned
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US15/640,042
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English (en)
Inventor
Toshikazu HANAWA
Kazuhide FUKAYA
Makoto Koshimizu
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Renesas Electronics Corp
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Renesas Electronics Corp
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Assigned to RENESAS ELECTRONICS CORPORATION reassignment RENESAS ELECTRONICS CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: FUKAYA, KAZUHIDE, HANAWA, TOSHIKAZU, KOSHIMIZU, MAKOTO
Publication of US20180061769A1 publication Critical patent/US20180061769A1/en
Priority to US16/668,802 priority Critical patent/US11594489B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76844—Bottomless liners
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
    • H01L23/53266—Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/43—Manufacturing methods
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]

Definitions

  • the present invention relates to a semiconductor device and a method of manufacturing the semiconductor device.
  • the contact plug contains polycrystalline silicone. Since polycrystalline silicon is high in resistance, the configuration of this contact plug is not suited for the power system circuit part to which the adaptability to large current and the resistance reduction are requested. When aluminum is used in place of polycrystalline silicon, coatability of the via hole is worsened.
  • a semiconductor device in which an insulating film has a first through-hole and a second through-hole, a first conductive film has a first sidewall part arranged along a sidewall surface of the first through-hole and contains one or more kinds selected from a group including tungsten, titanium, titanium nitride, tantalum and molybdenum, a second conductive film is embedded in the first through-hole and contains aluminum and a third conductive film is embedded in the second through-hole and contains one or more kinds selected from the group including tungsten, titanium, titanium nitride, tantalum and molybdenum.
  • the semiconductor device which has an internal configuration of the through-hole which is suited for the power system circuit unit and a method of manufacturing the semiconductor device.
  • FIG. 1 is a block diagram illustrating one functional example of a semiconductor device according to a first embodiment.
  • FIG. 2A is a plan view illustrating one configurational example of the semiconductor device according to the first embodiment.
  • FIG. 2B is a plan view illustrating one configurational example of the semiconductor device according to the first embodiment.
  • FIG. 2C is a plan view illustrating one configurational example of the semiconductor device according to the first embodiment.
  • FIG. 3A is a plan view illustrating one example of the lower layer side of the plan view in FIG. 2 .
  • FIG. 3B is a plan view illustrating one example of the lower layer side of the plan view in FIG. 2 .
  • FIG. 4A is a plan view illustrating one example of the upper layer side of the plan view in FIG. 2 .
  • FIG. 4B is a plan view illustrating one example of the upper layer side of the plan view in FIG. 2 .
  • FIG. 5A is a sectional diagram along the VA-VA line in FIG. 2A , illustrating one configurational example of the semiconductor device according to the first embodiment.
  • FIG. 5B is a sectional diagram along the VB-VB line in FIG. 2A , illustrating one configurational example of the semiconductor device according to the first embodiment.
  • FIG. 5C is a sectional diagram along the VC-VC line in FIG. 2A , illustrating one configurational example of the semiconductor device according to the first embodiment.
  • FIG. 6A is a schematic sectional diagram illustrating one example of a first process of a method of manufacturing the semiconductor device according to the first embodiment.
  • FIG. 6B is a schematic sectional diagram illustrating one example of the first process of the method of manufacturing the semiconductor device according to the first embodiment.
  • FIG. 7A is a schematic sectional diagram illustrating one example of a second process of the method of manufacturing the semiconductor device according to the first embodiment.
  • FIG. 7B is a schematic sectional diagram illustrating one example of the second process of the method of manufacturing the semiconductor device according to the first embodiment.
  • FIG. 8A is a schematic sectional diagram illustrating one example of a third process of the method of manufacturing the semiconductor device according to the first embodiment.
  • FIG. 8B is a schematic sectional diagram illustrating one example of the third process of the method of manufacturing the semiconductor device according to the first embodiment.
  • FIG. 9A is a schematic sectional diagram illustrating one example of a fourth process of the method of manufacturing the semiconductor device according to the first embodiment.
  • FIG. 9B is a schematic sectional diagram illustrating one example of the fourth process of the method of manufacturing the semiconductor device according to the first embodiment.
  • FIG. 10A is a schematic sectional diagram illustrating one example of a fifth process of the method of manufacturing the semiconductor device according to the first embodiment.
  • FIG. 10B is a schematic sectional diagram illustrating one example of the fifth process of the method of manufacturing the semiconductor device according to the first embodiment.
  • FIG. 11 is a schematic sectional diagram illustrating one example of a first process of a method of manufacturing a semiconductor device according to a comparative example.
  • FIG. 12 is a schematic sectional diagram illustrating one example of a second process of the method of manufacturing the semiconductor device according to the comparative example.
  • FIG. 13 is a schematic sectional diagram illustrating one example of a third process of the method of manufacturing the semiconductor device according to the comparative example.
  • FIG. 14 is a schematic sectional diagram illustrating one configurational example of a semiconductor device according to a second embodiment.
  • FIG. 15 is a schematic sectional diagram illustrating one example of a method of manufacturing the semiconductor device according to the second embodiment.
  • FIG. 16 is a schematic sectional diagram illustrating one configurational example of a semiconductor device according to a third embodiment.
  • FIG. 17 is a schematic sectional diagram illustrating one example of a first process of a method of manufacturing the semiconductor device according to the third embodiment.
  • FIG. 18 is a schematic sectional diagram illustrating one example of a second process of the method of manufacturing the semiconductor device according to the third embodiment.
  • FIG. 20 is a schematic sectional diagram illustrating one example of a configuration that an air gap has been formed in a second metal wiring layer in the first embodiment.
  • FIG. 21 is a schematic sectional diagram illustrating one example of a configuration that the air gap has been formed in the second metal wiring layer in the second embodiment.
  • FIG. 22 is a schematic sectional diagram illustrating one example of a configuration that the air gap has been formed in the second metal wiring layer in the third embodiment.
  • FIG. 23 is a diagram illustrating one example of an equivalent circuit of a power switch as one example of a power element.
  • FIG. 24 is a diagram illustrating one example of an I-V characteristic of the power element.
  • FIG. 25 is a diagram illustrating one example of an operational image of the power element.
  • a semiconductor device mainly includes an output power element unit OP, an interface/logic circuit IL, a monitor circuit MC, a protection circuit PRC, a driving logic circuit DLC, a power source PS and a plurality of pads PD.
  • the interface/logic circuit IL is electrically coupled with an external MCU (Micro Controller Unit) via the pads PD concerned. Thereby, it becomes possible for the interface/logic circuit IL to input and output a signal from and to the MCU.
  • MCU Micro Controller Unit
  • the MCU is an SOC (System on Chip).
  • the interface/logic circuit IL is capable of inputting signals which have been respectively output from the monitor circuit MC and the protection circuit PRC and is capable of outputting a signal to the driving logic circuit DLC.
  • a load LO is electrically coupled between the output power element unit OP and the monitor circuit MC via the pads PD concerned.
  • the output power element unit OP is capable of controlling the load LO by outputting a signal to the load LO via the pad PD concerned.
  • a signal from the load LO is fed back to the monitor circuit MC via the pad PD concerned.
  • the output power element unit OP is capable of inputting signals which have been respectively output from the protection circuit PRC and the driving logic circuit DLC and is capable of outputting a signal to the monitor circuit MC.
  • the monitor circuit MC is capable of outputting a signal to the protection circuit PRC and is capable of outputting a signal to the driving logic circuit DLC.
  • FIG. 2A illustrates one example of a planar structure of part of the interface/logic circuit IL illustrated in FIG. 1 .
  • FIG. 2B illustrates one example of a planar structure of part of the output power element unit OP illustrated in FIG. 1 .
  • FIG. 2C illustrates one example of a planar structure of the pad PD illustrated in FIG. 1 .
  • FIG. 3A is a plan view of the lower layer side of the interface/logic circuit IL in FIG. 2A and FIG. 3B is a plan view of the lower layer side of the output power element unit PO in FIG. 2B .
  • FIG. 4A is a plan view of the upper layer side of the interface/logic circuit IL in FIG. 2A and FIG. 4B is a plan view of the upper layer side of the output power element unit OP in FIG. 2B .
  • FIG. 5A is a sectional diagram along the VA-VA line in FIG. 2A
  • FIG. 5B is a sectional diagram along the VB-VB line in FIG. 2B
  • FIG. 5C is a sectional diagram along the VC-VC line in FIG. 2C .
  • a MOS (Metal Oxide Semiconductor) transistor TR is formed on/over a surface of a semiconductor substrate SB.
  • the MOS transistor TR includes one pair of source/drain regions SD, a gate insulating film GI, a gate electrode GE and so forth.
  • One pair of the source/drain regions SD are formed on/over the surface of the semiconductor substrate SB apart from each other by leaving a distance between them.
  • the gate electrode GE is formed on/over the surface of the semiconductor substrate SB with the gate insulating film GI being interposed so as to face a region which is sandwiched between one pair of the source/drain regions SD.
  • the MOS transistor TR is formed on a crossing part between the gate electrode GE and an active region of the semiconductor substrate SB in a planar view.
  • the planar view means a viewpoint viewed from a direction vertical to the surface of the semiconductor substrate SB.
  • an interlayer insulating film II 1 is formed on/over the surface of the semiconductor substrate SB so as to cover the MOS transistor TR.
  • a plurality of contact holes CH 2 are formed in the interlayer insulating film II 1 .
  • the contact holes CH 2 reach the respective source/drain regions SD so paired.
  • a plug layer PL 2 is embedded in each contact hole CH 2 .
  • a first metal wiring layer M 1 is formed on/over an upper surface of the interlayer insulating film II 1 so as to be electrically coupled to the source/drain regions SD via the plug layer PL 2 .
  • the first metal wiring layer M 1 is made of a material which contains, for example, aluminum (Al).
  • Al aluminum
  • the first metal wiring layer M 1 is made of the material such as, for example, aluminum, an aluminum-copper alloy and so forth.
  • An interlayer insulating film II 2 (an insulating film) is formed on/over the interlayer insulating film II 1 so as to cover over the first metal wiring layer M 1 .
  • the interlayer insulating film II 2 is configured by, for example, a silicon oxide film.
  • the silicon oxide film is formed by, for example, a plasma CVD method using TEOS (Tetra Ethyl Ortho Silicate) which is one kind of organic silicon compounds.
  • a plurality of via holes VH 2 (second through-holes) are formed in the interlayer insulating film II 2 .
  • the via holes VH 2 reach the first metal wiring layer M 1 .
  • a plug layer PL 3 (a third conductive film) is embedded in each via hole VH 2 .
  • the plug layer PL 3 is configured by a metal film (for example, a high-melting point metal film) formation of which is possible by using, for example, a CVD (Chemical Vapor Deposition) method.
  • the plug layer PL 3 is made of a material which contains, for example, one or more kinds selected from a group including tungsten (W), titanium (Ti), titanium nitride (TiN), a tantalum (Ta) and molybdenum (Mb).
  • a second metal wiring layer M 2 is formed on/over an upper surface of the interlayer insulating film II 2 so as to be electrically coupled with the first metal wiring layer M 1 via the plug layer PL 3 .
  • the second metal wiring layer M 2 is made of the material which contains, for example, aluminum.
  • the second metal wiring layer M 2 is made of the material such as aluminum, the aluminum-copper alloy and so forth.
  • the contact hole CH 2 is formed in a crossing part between the first metal wiring layer M 1 and the active region of the semiconductor substrate SB in the planar view.
  • the via hole VH 2 is formed in a crossing point between the first metal wiring layer M 1 and the second metal wiring layer M 2 in the planer view.
  • a power MOS transistor PTR is formed on/over the surface of the semiconductor substrate SB.
  • the power MOS transistor PTR includes a source region SR, a drain region DR, the gate insulating film, the gate electrode GE and so forth.
  • the source region SR and the drain region DR are formed on/over the surface of the semiconductor substrate SB apart from each other by leaving a distance between them.
  • An element isolation insulating film SI is formed on/over the surface of the semiconductor substrate SB between the source region SR and the drain region DR.
  • the element isolation insulating film SI is configured by, for example, a silicon oxide film which has been formed by a LOCOS (LOCal Oxidation of Silicon) method.
  • the gate electrode GE is formed on/over the surface of the semiconductor substrate SB with the gate insulating film GI being interposed so as to face a region which is sandwiched between the source region SR and the drain region DR.
  • An end on the drain region DR side of the gate electrode GE rides on the element isolation insulating film SI.
  • a contact region CR is formed on/over the surface of the semiconductor substrate SB so as to be adjacent to the source region SR.
  • the gate electrode GE extends so as to be arranged side by side with the active region of the semiconductor substrate SB in the planer view.
  • the interlayer insulating film II 1 is formed on/over the surface of the semiconductor substrate SB so as to cover the power MOS transistor PTR.
  • the interlayer insulating film II 1 is made of the same material as the interlayer insulating film II 1 in the logic section.
  • a plurality of contact holes CH 1 are formed in the interlayer insulating film II 1 .
  • the contact holes CH 1 reach the contact region CR and the source region SR.
  • the first metal wiring layer M 1 is formed on/over the upper surface of the interlayer insulating film II 1 so as to be electrically coupled to the contact region CR and the source region SR via the plug layer PL 1 .
  • the first metal wiring layer M 1 is made of the material which contains, for example, aluminum.
  • the first metal wiring layer M 1 is made of the material such as, for example, aluminum, the aluminum-copper alloy and so forth.
  • the interlayer insulating film II 2 is formed on/over the interlayer insulating film II 1 so as to cover over the first metal wiring layer M 1 .
  • the interlayer insulating film II 2 is configured by, for example, the silicon oxide film.
  • the silicon oxide film is formed by, for example, the plasma CVD method using TEOS which is one kind of the organic silicon compounds.
  • a plurality of via holes VH 1 (first through-holes) are formed in the interlayer insulating film II 2 .
  • the via holes VH 1 reach the first metal wiring layer M 1 .
  • a width L 1 of each via hole VH 1 is wider than a width L 2 of each via hole VH 2 in the logic section.
  • a sidewall spacer shaped sidewall conductive layer SWC (a first conductive film) is formed so as to be arranged along a sidewall surface of each via hole VH 1 .
  • the sidewall conductive layer SWC is made of the material which contains, for example, one or more kinds selected from the group including tungsten, titanium, titanium nitride, tantalum and molybdenum.
  • an upper surface of the first metal wiring layer M 1 is exposed from the sidewall conductive layer SWC.
  • the second metal wiring layer M 2 (a second conductive film) is formed so as to be embedded in the via hole VH 1 and to be located on/over the upper surface of the interlayer insulating film II 2 .
  • the second metal wiring layer M 2 is made of the material which contains, for example, aluminum.
  • the second metal wiring layer M 2 is made of the material such as, for example, aluminum, the aluminum-copper alloy and so forth.
  • the second metal wiring layer M 2 is in contact with an upper surface of the first metal wiring layer M 1 on the bottom part of each via hole VH 1 .
  • the second metal wiring layer M 2 is in contact with a side surface of the sidewall conductive layer SWC in each via hole VH 1 .
  • the first metal wiring layer M 1 extends so as to be arranged side by side with the gate electrode GE in the planar view.
  • the second metal wiring layer M 2 extends in a direction intersecting with (for example, a direction orthogonal to) the first metal wiring layer M 1 in the planar view.
  • the contact hole CH 1 is formed in a crossing part between the first metal wiring layer M 1 and the active region of the semiconductor substrate SB in the planar view.
  • the via hole VH 1 is formed in a crossing part between the first metal wiring layer M 1 and the second metal wiring layer M 2 in the planar view.
  • the sidewall conductive layer SWC is annularly formed along the sidewall surface of each via hole VH 1 in the planar view.
  • the element isolation insulating film SI is formed on/over the surface of the semiconductor substrate SB.
  • the interlayer insulating film II 1 is formed on/over the interlayer insulating film II 1 .
  • the interlayer insulating film ill is made of the same material as the interlayer insulating film II 1 in the logic section.
  • the first metal wiring layer M 1 is formed on/over the interlayer insulating film II 1 .
  • the first metal wiring layer M 1 is made of the material which contains, for example, aluminum.
  • the first metal wiring layer M 1 is made of the material such as, for example, aluminum, the aluminum-copper alloy and so forth.
  • the interlayer insulating film II 2 is formed on/over the interlayer insulating film II 1 so as to cover the first metal wiring layer M 1 .
  • the interlayer insulating film II 2 is configured by, for example, the silicon oxide film.
  • the silicon oxide film is formed by, for example, the plasma CVD method using TEOS which is one kind of the organic silicon compounds.
  • a via hole VH 3 is formed in the interlayer insulating film II 2 .
  • the via hole VH 3 reaches the first metal wiring layer M 1 .
  • a width L 3 of the via hole VH 3 is wider than the width L 1 of each via hole in the power element section.
  • the sidewall spacer shaped sidewall conductive layer SWC is formed so as to be arranged along a sidewall surface of the via hole VH 3 .
  • the sidewall conductive layer SWC is made of the material which contains, for example, one or more kinds selected from the group including tungsten, titanium, titanium nitride, tantalum and molybdenum.
  • the upper surface of the first metal wiring layer M 1 is exposed from the sidewall conducive layer SWC.
  • the sidewall conductive layer SWC is formed annularly along the sidewall surface of the via hole VH 3 in the planar view.
  • the second metal wiring layer M 2 is formed so as to be embedded in the via hole VH 3 and to be located on/over the upper surface of the interlayer insulating film II 2 .
  • the second metal wiring layer M 2 is made of, for example, the material which contains aluminum (Al).
  • the second metal wiring layer M 2 is made of the material such as, for example, aluminum, the aluminum-copper alloy and so forth.
  • the second metal wiring layer M 2 is in contact with the upper surface of the first metal wiring layer M 1 on the bottom part of the via hole VH 3 .
  • the second metal wiring layer M 2 is in contact with a side surface of the sidewall conductive layer SWC in the via hole VH 3 .
  • a barrier metal layer (not illustrated) is formed on/over the upper surface of the first metal wiring layer M 1
  • the second metal wiring layer M 2 may be formed so as to be in contact with an upper surface of the barrier metal layer in the via hole VH 1 .
  • a first barrier metal layer (not illustrated) may be formed so as to cover the upper surface and the side surfaces of the first metal wiring layer M 1 .
  • a second barrier metal layer (not illustrated) may be formed so as to cover the upper surface of the interlayer insulating film II 2 and side surfaces and bottom surfaces of the respective via holes VH 1 to VH 3 .
  • the first metal wiring layer M 1 is formed on/over the interlayer insulating film II 1 (not illustrated).
  • the first metal wiring layer M 1 is formed by, for example, depositing an aluminum layer by sputtering and thereafter patterning the aluminum layer by general photolithography technology and etching technology.
  • a first barrier metal layer BM 1 is formed so as to cover the upper surface and the side surfaces of the first metal wiring layer M 1 .
  • the first barrier metal layer BM 1 is made of, for example, titanium nitride (TiN).
  • the interlayer insulating film II 2 which is configured by, for example, a silicon oxide film is formed on/over the interlayer insulating film II 1 so as to cover the first metal wiring layer M 1 .
  • the interlayer insulating film II 1 is formed by, for example, the plasma CVD method using TEOS which is one kind of the organic silicon compounds.
  • the via holes VH 1 and VH 2 are formed in the interlayer insulating film II 2 by the general photolithography technology and etching technology.
  • the respective via holes VH 1 and VH 2 are formed so as to reach the first metal wiring layer M 1 .
  • the first barrier metal layer BM 1 is formed on/over the upper surface of the first metal wiring layer M 1 as in the first embodiment, the respective via holes VH 1 and VH 2 are formed so as to reach the first barrier metal layer BM 1 .
  • the via hole VH 1 which is to be formed in the power element section is formed so as the have the width L 1 which is wider than the width L 2 of the via hole VH 2 which is to be formed in the logic section.
  • a second barrier metal layer BM 2 is formed so as to cover the upper surface of the interlayer insulating film II 2 and inner wall surfaces (sidewall surfaces and bottom wall surfaces) of the via holes VH 1 and VH 2 .
  • the second barrier metal layer BM 2 is formed by, for example, laminating in order titanium and titanium nitride from below.
  • Each of titanium and titanium nitride which configure the second barrier metal BM 2 is formed by, for example, sputtering.
  • a conductive layer CL is formed on/over the second barrier metal layer BM 2 .
  • the conductive layer CL is formed by, for example, depositing tungsten by the CVD method.
  • the conducive layer CL in the power element section, is not tightly embedded in the via hole VH 1 and is formed along inner wall surfaces (the sidewall surface and the bottom wall surface) of the via hole VH 1 .
  • the conductive layer CL in the logic section, is formed so as to be tightly embedded in the via hole VH 2 .
  • etching-back is performed on the entire surface of the conductive layer CL.
  • the etching-back is performed until the bottom wall surface of the via hole VH 1 is exposed. Specifically, the etching-back is performed until, for example, the second barrier metal layer BM 2 is exposed from the conductive layer CL.
  • the conductive layer CL is left in the form of a sidewall spacer shape so as to cover the sidewall of the via hole VH 1 by the etching-back.
  • the sidewall spacer shaped sidewall conductive film SWC is formed from the conductive layer CL. Therefore, the second barrier metal layer BM 2 is exposed from the sidewall conductive layer SWC on the bottom wall surface of the via hole VH 1 .
  • the conductive layer CL is left in a state of being embedded in the via hole VH 2 by the etching-back.
  • the plug layer PL 3 which is embedded in the via hole VH 2 is formed from the conductive layer CL. Therefore, the second barrier metal layer BM 2 is not exposed from the plug layer PL 3 on the bottom wall surface of the via hole VH 2 .
  • the second metal wiring layer M 2 is formed on/over the interlayer insulating film II 2 .
  • the second metal wiring layer M 2 is formed by, for example, depositing an aluminum layer by sputtering and thereafter patterning the aluminum layer by the general photolithography technology and etching technology.
  • the semiconductor device according to the first embodiment illustrated in FIG. 2 to FIG. 5 is manufactured.
  • the first metal wiring layer M 1 , the first barrier metal layer BM 1 and the interlayer insulating film II 2 are formed on/over the interlayer insulating film II 1 (not illustrated) in the same manner as that illustrated in FIG. 6A and FIG. 6B .
  • the via hole VH 1 is formed in the interlayer insulating film II 2 .
  • the via hole VH 1 is formed by selectively wet-etching the upper surface of the interlayer insulating film II 2 down to a predetermined depth and thereafter dry-etching the upper surface of the interlayer insulating film II 2 .
  • the second barrier metal layer BM 2 is formed in the same manner as that in the first embodiment.
  • an aluminum film is formed by sputtering as the second metal wiring layer M 2 .
  • an upper end of the via hole VH 1 is widened by wet-etching.
  • the coatability of the aluminum film M 2 which is low in coatability is improved.
  • the coatability of the aluminum film M 2 is basically low and a part which is thin in film thickness is formed on the aluminum film M 2 in the vicinity of the bottom part of the via hole VH 1 as illustrated in FIG. 13 . Therefore, when a large current flows, it is feared that resistance to electro-migration may be deteriorated.
  • the sidewall conductive layer SWC is formed on the sidewall of the via hole VH 1 . Accordingly, even when the part which is thin in film thickness is formed on the second metal wiring layer M 2 on the bottom part of the via hole VH 1 , it is possible to ensure the whole film thickness (the sum total of film thicknesses of the sidewall conductive layer SWC and the second metal wiring layer M 2 ) of the conductive layer by the sidewall conductive layer SWC. Accordingly, even when the large current flows, it is possible to more improve the resistance to electro-migration than the comparative example.
  • the sidewall conductive layer SWC is made of the material which contains, for example, one or more kinds selected from the group including tungsten, titanium, titanium nitride, tantalum and molybdenum.
  • the above-mentioned material is the metal film (for example, the high-melting point metal film) formation of which is possible by the CVD method and is the material which is high in coatability in film-deposition. Therefore, it is possible to securely coat the sidewall conductive layer SWC down to the bottom part of the via hole VH 1 by forming the sidewall conductive layer SWC by using this material.
  • the diameter of the via hole VH 1 is more smoothly increased as it goes upward by forming the sidewall conducive layer SWC on the sidewall of the via hole VH 1 . Therefore, the coatability of the second metal wiring layer M 2 which is configured by the aluminum film in the via hole VH 1 becomes preferable and it becomes possible to promote resistance reduction of the second metal wiring layer M 2 .
  • the aluminum film is a low-resistance material and that low-resistance material is embedded in the via hole VH 1 . Accordingly, it becomes possible for the above-mentioned configuration to more promote the resistance reduction than a configuration that only tungsten is embedded in the via hole VH 1 and a configuration that polycrystalline silicon is embedded in the via hole VH 1 .
  • the plug layer PL 3 is embedded in the via hole VH 2 of the logic section.
  • the plug layer PL 3 is formed from the conductive layer CL which is the same as the sidewall conductive layer SWC in material. Accordingly, it is possible to perform embedding of the plug layer PL 3 in the via hole VH 2 in the logic section simultaneously with formation of the sidewall conductive layer SWC on the sidewall of the via hole VH 1 in the power element section. Thereby it becomes possible to promote simplification of a manufacturing process.
  • part (part of the second barrier metal layer BM 2 ) of the bottom wall surface of the via hole VH 1 is exposed from the sidewall conductive layer SWC. Therefore, it becomes possible to largely secure an occupation region of the second metal wiring layer M 2 in the via hole VH 1 . Since the second metal wiring layer M 2 contains low-resistance aluminum, it becomes possible to promote further resistance reduction by largely securing the occupation region of the second metal wiring layer M 2 in the via hole VH 1 .
  • the via hole VH 1 is arranged directly above a region where a power element (for example, the power MOS transistor PTR) is formed.
  • a power element for example, the power MOS transistor PTR
  • the via hole VH 2 is arranged directly above a region where a logic element (for example, the MOS transistor TR) is formed.
  • a logic element for example, the MOS transistor TR
  • the configuration of the second embodiment is different from the configuration of the first embodiment in the configuration of the sidewall conductive layer SWC in the power element section.
  • the sidewall conductive layer SWC in the second embodiment covers the entire of the bottom wall surface of the via hole VH 1 .
  • the sidewall conductive layer SWC covers the entire of the first barrier metal layer BM 2 which is located on the bottom wall surface of the via hole VH 1 .
  • the sidewall conductive layer SWC includes a sidewall spacer shaped part and a thin film part.
  • a thickness T of the thinnest part (the thin film part) of the sidewall conductive layer SWC is not more than 1 ⁇ 2 of a depth D of the via hole VH 1 .
  • the sidewall spacer shaped part of the sidewall conductive layer SWC has a thickness which is almost the same as the depth D of the via hole VH 1 .
  • a manufacturing method in the second embodiment follows processes which are the same as the processes in the first embodiment illustrated in FIG. 6 to FIG. 8 .
  • the entire surface of the conductive layer CL is etched back.
  • etching-back is terminated before the bottom wall surface of the via hole VH 1 is exposed.
  • etching-back is controlled such that the second barrier metal layer BM 2 is not exposed in the via hole VH 1 in the power element section.
  • the second metal wiring layer M 2 is formed in the same manner as that in the first embodiment. From the foregoing, the semiconductor device according to the second embodiment is manufactured.
  • the sidewall conductive layer SWC covers the entire of the bottom wall surface of the via hole VH 1 .
  • the thickness T of the thinnest part of the sidewall conductive layer SWC is not more than 1 ⁇ 2 of the depth D of the via hole VH 1 . Accordingly, it is possible to suppress an increase in resistance while suppressing the migration of aluminum.
  • the configuration of the third embodiment is different from the configuration of the first embodiment in that another sidewall conductive layer SWC 2 (a fourth conductive film) is formed in the via hole VH 1 in the power element section.
  • the sidewall conductive layer SWC 2 in the third embodiment has the sidewall space shape and is in contact with a side part of the sidewall conductive layer SWC.
  • the sidewall conductive layer SWC 2 is made of the material which contains, for example, one or more kinds selected from the group including tungsten, titanium, titanium nitride, tantalum and molybdenum.
  • a manufacturing method in the third embodiment follows processes which are the same as the processes in the first embodiment illustrated in FIG. 6 to FIG. 8 .
  • another conductive layer CL 2 is formed on/over the second barrier metal layer BM 2 and along the inner wall surface of the via hole VH 1 .
  • the conductive layer CL 2 is formed by, for example, depositing tungsten by the CVD method. In this case, in the power element section, the conductive layer CL 2 is formed so as not to be tightly embedded in the via hole VH 1 .
  • the entire surface of the conductive layer CL 2 is etched back. In this case, etching-back is controlled such that the second barrier metal layer BM 2 is not exposed in the via hole VH 1 in the power element section. Then, as illustrated in FIG. 14 , the second metal wiring layer M 2 is formed in the same manner as that in the first embodiment. From the foregoing, a semiconductor device according to the third embodiment is manufactured.
  • the sidewall conductive layer SWC 2 (the fourth conductive film) is formed in the via hole VH 1 in the power element section. Therefore, the sidewall of the sidewall conductive layer SWC 2 is formed more gently than the sidewall of the sidewall conductive layer SWC. Thereby, the coatability of the second barrier metal layer BM 2 which is formed in contact with the sidewall of the sidewall conductive layer SWC 2 becomes more preferable.
  • the sidewall conductive layer SWC 2 may cover the entire of the bottom wall surface of the via hole VH 1 . That is, the sidewall conductive layer SWC 2 covers the entire of the second barrier metal layer BM 2 which is located on the bottom wall surface of the via hole VH 1 .
  • the configuration illustrated in FIG. 19 has both of the advantageous effect of the third embodiment and the advantageous effect of the second embodiment.
  • FIG. 20 is a diagram illustrating one example of a state where an air gap AG has been formed in the second metal wiring layer M 2 in the first embodiment.
  • FIG. 21 is a diagram illustrating one example of a state where the air gap AG has been formed in the second metal wiring layer M 2 in the second embodiment.
  • FIG. 22 is a diagram illustrating one example of a state where the air gap AG has been formed in the second metal wiring layer M 2 in the third embodiment. As illustrated in FIG. 20 to FIG. 22 , the air gap AG is formed directly above the via hole VH 1 .
  • the power MOS transistor PTR has been described as the power element, an IGBT (Insulated Gate Bipolar Transistor) may be also used as the power element.
  • IGBT Insulated Gate Bipolar Transistor
  • the power element in the first to third embodiments means an element for power conversion such as, for example, a power switch and so forth.
  • Performances which are requested to the power element in each of the first to third embodiments in order to drive externally attached loads are high-voltage resistance and large current handleability.
  • the power element in each of the first to third embodiment has such an equivalent circuit as illustrated in, for example, FIG. 23 , exhibits such an I-V characteristic as illustrated in, for example, FIG. 24 and performs such operations as illustrated in, for example, FIG. 25 .
  • the MOS transistor TR has been described as the logic element, a MIS (Metal Insulator Semiconductor) transistor may be also used as the logic element and the logic element is not limited thereto.
  • MIS Metal Insulator Semiconductor
  • the logic element in each of the first to third embodiment means a digital signal processing element such as, for example, a switch of logical information and so forth. Performances which are requested as the logic element are, for example, low-voltage operability and high-speed switchability.

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