US20160372360A1 - Semiconductor structure with junction leakage reduction - Google Patents

Semiconductor structure with junction leakage reduction Download PDF

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Publication number
US20160372360A1
US20160372360A1 US14/742,550 US201514742550A US2016372360A1 US 20160372360 A1 US20160372360 A1 US 20160372360A1 US 201514742550 A US201514742550 A US 201514742550A US 2016372360 A1 US2016372360 A1 US 2016372360A1
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Prior art keywords
well region
semiconductor substrate
region
dti
conductive type
Prior art date
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US14/742,550
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English (en)
Inventor
Chun-Chieh Fang
Chien-Chang Huang
Chi-Yuan Wen
Jian Wu
Ming-Chi Wu
Jung-Yu CHENG
Shih-Shiung Chen
Wei-Tung Huang
Yu-Lung Yeh
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority to US14/742,550 priority Critical patent/US20160372360A1/en
Priority to DE102015110584.5A priority patent/DE102015110584B4/de
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. reassignment TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHEN, SHIH-SHIUNG, HUANG, WEI-TUNG, CHENG, JUNG-YU, FANG, CHUN-CHIEH, HUANG, CHIEN-CHANG, WEN, CHI-YUAN, WU, JIAN, WU, MIN-CHI, YEH, YU-LUNG
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. reassignment TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHEN, SHIH-SHIUNG, CHENG, JUNG-YU, FANG, CHUN-CHIEH, HUANG, CHIEN-CHANG, HUANG, WEI-TUNG, WEN, CHI-YUAN, WU, JIAN, WU, MING-CHI, YEH, YU-LUNG
Priority to KR1020150132650A priority patent/KR101786202B1/ko
Priority to CN201610055864.2A priority patent/CN106257633B/zh
Publication of US20160372360A1 publication Critical patent/US20160372360A1/en
Priority to US17/694,380 priority patent/US20220199459A1/en
Abandoned legal-status Critical Current

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Definitions

  • IoT Internet of Things
  • wearable devices have the advantages of wearable characteristics and small size.
  • An embedded flash integrated circuit may be applied to such wearable devices for minimizing device size.
  • such embedded flash integrated circuit may generate a non-negligible leakage current that results in additional power consumption, and consequently shortening standby time of the wearable devices. How to reduce leakage current in small and concentrative integrated circuits has now become one of the major tasks in related industries.
  • FIG. 1A through FIG. 1H are schematic cross-sectional views of intermediate stages illustrating a method of forming a semiconductor device in accordance with some embodiments.
  • FIG. 2A through FIG. 2B are schematic cross-sectional views of intermediate stages illustrating a method of forming a deep trench of a semiconductor device in accordance with another embodiments.
  • FIG. 3 is a flow chart of a method of forming a semiconductor substrate in accordance with various embodiments.
  • FIG. 4A through FIG. 4C are schematic cross-sectional views of intermediate stages illustrating a method of forming a semiconductor device in accordance with some embodiments.
  • FIG. 5 illustrates formation of a well region using an ion implantation process with non-zero tilting angle in accordance with some embodiments.
  • FIG. 6 illustrates formation of a well region using an ion implantation process in accordance with some embodiments.
  • FIG. 7 is a schematic cross-sectional view of a laterally diffused metal oxide semiconductor (LDMOS) in accordance with some embodiments.
  • LDMOS laterally diffused metal oxide semiconductor
  • FIG. 8 is a flow chart of a method of forming a semiconductor device in accordance with various embodiments.
  • first and second are used for describing various elements, though such terms are only used for distinguishing one element from another element. Therefore, the first element may also be referred to as the second element without departing from the spirit of the claimed subject matter, and the others are deduced by analogy.
  • Embodiments of the present disclosure are directed to providing a semiconductor structure with a deep trench isolation (DTI).
  • the DTI is formed below a shallow trench isolation (STI) and is substantially located between two adjacent well regions with different conductive types. Because of the DTI, the path of the leakage current flowing through the well regions is lengthened, such that the leakage current is reduced. Further, tilting variation of the ion implantation process due to cone angle effect can be neglected.
  • the semiconductor structure of the present disclosure may be useful for such as memory integrated circuits, CMOS image sensors, temperature sensors, and/or the like.
  • the semiconductor structure of the present disclosure used in memory integrated circuits may help reduce power consumption or even improve reading/writing performance because read/write error due to excessive leakage current is reduced.
  • FIG. 1A to FIG. 1F illustrate schematic cross-sectional views of intermediate stages showing a method of forming a semiconductor device 100 in accordance with some embodiments of the present disclosure.
  • a semiconductor substrate 102 is provided.
  • the semiconductor substrate 102 includes such as silicon, bulk silicon, germanium or diamond.
  • the semiconductor substrate 102 may include a compound semiconductor such as silicon carbide, silicon germanium, gallium arsenide, gallium carbide, gallium phosphide, indium arsenide and indium phosphide, or an alloy semiconductor, such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide and gallium indium phosphide.
  • the semiconductor substrate 102 may be a bulk substrate or a silicon-on-insulator (SOI) substrate.
  • a pad layer 104 is formed on the semiconductor substrate 102 , and a barrier layer 106 is formed on the pad layer 104 .
  • the pad layer 104 includes such as silicon oxide
  • the barrier layer 106 includes such as silicon nitride.
  • the pad layer 104 is formed by a process such chemical vapor deposition (CVD) process, thermal oxidation process, or another suitable process
  • the barrier layer 106 is formed by a deposition process such as CVD process, low pressure CVD (LPCVD) process, plasma enhanced CVD (PECVD) process, or another suitable process.
  • an etching process is performed to etch the barrier layer 106 , the pad layer 104 and the semiconductor substrate 102 .
  • a patterned photoresist layer (not shown) is used as a mask, so as to form a shallow trench 108 through the pad layer 104 , the barrier layer 106 and a portion of the semiconductor substrate 102 .
  • the etching process for forming the shallow trench 108 includes such as an anisotropic etching process, an isotropic etching process, or another suitable etching process.
  • the patterned photoresist layer (not shown) is stripped.
  • a protective layer 110 is formed on the semiconductor substrate 102 , the pad layer 104 and the barrier layer 106 for covering the shallow trench 108 .
  • the protective layer 110 may include a material such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, combinations thereof, and/or the like.
  • the protective layer 110 may be a hard mask layer, and may be a single-layer or multi-layer structure. In some embodiments, the protective layer 110 is a two-layer structure, which includes an oxide layer and a nitride layer on the oxide layer.
  • the protective layer 110 is formed by using one or more deposition processes, such as CVD process, PECVD process, high density plasma (HDPCVD) process, physical vapor deposition (PVD) process, atomic layer deposition (ALD) process, thermal oxidation process, combinations thereof, and/or the like.
  • CVD process high density plasma
  • PECVD high density plasma
  • HDPCVD high density plasma
  • PVD physical vapor deposition
  • ALD atomic layer deposition
  • thermal oxidation process combinations thereof, and/or the like.
  • a first etching process is performed to the protective layer 110 .
  • the first etching process is performed until at least a portion of a bottom surface of the shallow trench 108 is exposed by the protective layer 110 .
  • the first etching process is performed until at least a portion of a bottom surface of the shallow trench 108 is exposed by the protective layer 110 .
  • the first etching process may include such as a dry etching process, a wet etching process, a plasma etching process, a reactive ion etching (RIE) process, or another suitable etching process.
  • RIE reactive ion etching
  • the exposed area may be at center position of the bottom surface of the shallow trench 108 , or another position, in accordance with various requirements.
  • a second etching process is then performed on the portion of the bottom surface of the shallow trench 108 .
  • the remained protective layer 110 acts as a photoresist for protecting the other portion of the shallow trench 108 from being etched.
  • the second etching process may include such as a dry etching process, a wet etching process, a RIE process, or another suitable process.
  • a deep trench 112 is formed below the bottom surface of the shallow trench 108 .
  • the shape, width and location of the deep trench 112 may be determined by the pattern of the protective layer 110 , and the thickness of the deep trench 112 may be determined by the time duration of the second etching process.
  • the deep trench 112 is formed having the thickness of at least 1000 angstroms.
  • the remaining protective layer 110 is removed.
  • the barrier layer 106 and the pad layer 104 are removed.
  • the removing process applied to the protective layer 110 , the barrier layer 106 and the pad layer 104 may include one or more etching processes, such as wet etching process, dry etching process, combinations thereof, or another suitable process.
  • the shallow trench 108 and the deep trench 112 are filled with an isolation oxide, so as to form a STI 114 and a DTI 116 respectively.
  • the isolation oxide includes a material such as silicon oxide, silicon dioxide, carbon doped silicon dioxide, nitrogen doped silicon dioxide, germanium doped silicon dioxide, phosphorus doped silicon dioxide, combinations thereof, or the like.
  • the isolation oxide is deposited by such as a HDP CVD process, a HARP, a CVD process, a SACVD process, or another suitable process.
  • a chemical mechanical polishing (CMP) process may be performed to planarize the upper surface of the STI 114 .
  • the deep trench of the semiconductor device 100 may be formed by performing a dry etching process first and a wet etching process after the dry etching process.
  • FIG. 2A through FIG. 2B are schematic cross-sectional views of intermediate stages illustrating a method of forming a deep trench of a semiconductor device in accordance with another embodiments.
  • a dry etching process is performed to the protective layer 110 .
  • the dry etching process is performed until at least a portion of a bottom surface of the shallow trench 108 is exposed by the protective layer 110 .
  • the dry etching process may include a plasma etching process, a sputter etching process, a RIE process, or other suitable process.
  • the dry etching process is performed until at least a portion of a bottom surface of the shallow trench 108 is exposed by the protective layer 100 . As shown in FIG. 2A , the periphery area of the bottom surface of the shallow trench 108 is exposed. In various embodiments, the exposed area may be at center position of the bottom surface of the shallow trench 108 , or another position, in accordance with various requirements.
  • a deep trench 112 ′ is formed below the bottom surface of the shallow trench 108 .
  • the dry etching process may cause damage to the semiconductor substrate 102 .
  • the plasma etching process may cause crystal defects or dislocations of the semiconductor substrate 102 the bottom face and the side face of the deep trench 112 ′.
  • a wet etching process is performed to deeper the deep trench 112 ′.
  • the wet etching process may be isotropic or anisotropic.
  • the enchant used for the etching process may be selected in accordance with the material of the semiconductor substrate 102 .
  • the bottom face and the side face of the deep trench 112 ′ with defects (crystal defects and/or dislocations) are removed from the semiconductor substrate 102 , thereby improving yield rate of the semiconductor device 100 .
  • the deep trench 112 ′ shown in FIG. 2B is for illustrative purposes only and is not meant to limit the scope of the present disclosure.
  • the shape, width and location of the deep trench 112 ′ may be determined by the pattern of the protective layer 110 , and the thickness of the deep trench 112 ′ may be determined by the time duration of the wet etching process.
  • the deep trench 112 ′ is formed having the thickness of at least 1000 angstroms.
  • a thickness ratio of the STI 114 to the deep trench 112 ′ is about 0.5 to about 10.
  • FIG. 3 is a flow chart of a method 200 for fabricating a semiconductor device 100 in accordance with some embodiments.
  • the method 200 begins at operation 202 , where a semiconductor substrate 102 is provided.
  • the semiconductor substrate 102 includes such as silicon, bulk silicon, germanium or diamond.
  • the semiconductor substrate 102 may include a compound semiconductor such as silicon carbide, silicon germanium, gallium arsenide, gallium carbide, gallium phosphide, indium arsenide and indium phosphide, or an alloy semiconductor, such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide and gallium indium phosphide.
  • the semiconductor substrate 102 may be a bulk substrate or a SOI substrate.
  • a pad layer 104 is formed on the semiconductor substrate 102
  • a barrier layer 106 is formed on the pad layer 104 .
  • the pad layer 104 includes such silicon oxide, and is formed by such as a CVD process, a thermal oxidation process, or another suitable process.
  • the barrier layer 106 includes such as silicon nitride, and is formed by such as a CVD process, a LPCVD process, a PECVD process, or another suitable process.
  • an etching process is performed to etch the barrier layer 106 , the pad layer 104 and the semiconductor substrate 102 by using a patterned photoresist layer (not shown) as a mask, so as to form a shallow trench 108 through the pad layer 104 , the barrier layer 106 and a portion of the semiconductor substrate 102 .
  • the etching process for forming the shallow trench 108 includes such as an anisotropic etching process, an isotropic etching process, or another suitable etching process.
  • the patterned photoresist layer (not shown) is stripped.
  • a protective layer 110 is formed on the semiconductor substrate 102 , the pad layer 104 and the barrier layer 106 for covering the shallow trench 108 .
  • the protective layer 110 may include a material such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, combinations thereof, and/or the like.
  • the protective layer 110 may be a hard mask layer, and may be a single-layer or multi-layer structure. In some embodiments, the protective layer 110 is a two-layer structure, which includes an oxide layer and a nitride layer on the oxide layer.
  • the protective layer 110 is formed by using one or more deposition processes, such as CVD process, PECVD process, HDPCVD process, PVD process, ALD process, thermal oxidation process, combinations thereof, and/or the like.
  • a first etching process is performed to the protective layer 110 .
  • the first etching process is performed until at least a portion of a bottom surface of the shallow trench 108 is exposed by the protective layer 110 .
  • the first etching process is performed until at least a portion of a bottom surface of the shallow trench 108 is exposed by the protective layer 100 .
  • the first etching process may include such as a dry etching process, a wet etching process, a plasma etching process, a reactive ion etching process, or another suitable etching process.
  • a second etching process is then performed on the portion of the bottom surface of the shallow trench 108 .
  • the protective layer 110 remained after the first etching process is used for protecting the other portion of the shallow trench 108 from being etched during the second etching process.
  • the second etching process may include such as a dry etching process, a wet etching process, a RIE process, or another suitable process.
  • a deep trench 112 is formed below the bottom surface of the shallow trench 108 .
  • the shape, width and location of the deep trench 112 may be determined by the pattern of the protective layer 110 , and the thickness of the deep trench 112 may be determined by the time duration of the second etching process.
  • the deep trench 112 is formed having the thickness of at least 1000 angstroms.
  • the remaining protective layer 110 , the barrier layer 106 and the pad layer 104 are removed.
  • the applied removing process may include one or more etching processes, such as wet etching process, dry etching process, combinations thereof, or another suitable process.
  • the shallow trench 108 and the deep trench 112 are filled with an isolation oxide, so as to form a STI 114 and a DTI 116 respectively.
  • the isolation oxide includes a material such as silicon oxide, silicon dioxide, carbon doped silicon dioxide, nitrogen doped silicon dioxide, germanium doped silicon dioxide, phosphorus doped silicon dioxide, combinations thereof, or the like.
  • a deposition process such as HDP CVD process, HARP, CVD process, SACVD process, or another suitable process, is perform to fill the isolation oxide into the shallow trench 108 and the deep trench 112 .
  • a CMP process may be performed to planarize the upper surface of the STI 114 .
  • FIG. 4A to FIG. 4C illustrate schematic cross-sectional views of intermediate stages showing a method of forming a semiconductor device 300 in accordance with some embodiments of the present disclosure.
  • a semiconductor substrate 302 , a STI 304 and a DTI 306 are provided, and a well region 308 is formed on the semiconductor substrate 302 .
  • the semiconductor substrate 302 , the STI 304 and the DTI 306 may be the semiconductor substrate 102 , the STI 114 and the DTI 116 shown in FIG. 1 , respectively.
  • the semiconductor substrate 302 may be a P-type or N-type semiconductor substrate.
  • the conductive type of the well region 308 may be P-type or N-type.
  • the dopant for implanting into the well region 308 may include boron for P-type well region, or phosphorous and/or arsenic for an N-type well region.
  • the well region 308 may be a high voltage well with dopant concentration of between 10 13 atoms/cm 2 and 10 16 atoms/cm 2 , for example.
  • the well region 308 may be formed by a process such as ion implantation process, diffusion process, or the like. As shown in FIG. 4A , the DTI 306 is located in the well region 308 after the well region 308 is formed.
  • an active region 310 is formed on the well region 308 .
  • the active region 310 may be formed by a process such as ion implantation process, diffusion process, or another suitable process.
  • the conductive type of the active region 310 is different from that of the well region 308 .
  • the active region 310 is P-type while the well region 308 is N-type.
  • a photoresist 312 is formed on the active region 310 , and an ion implantation process is performed through the STI 304 to form a well region 314 on the semiconductor substrate 302 and laterally adjacent to the well region 308 .
  • the photoresist 312 may be a positive photoresist or a negative photoresist, which is used for protecting the active region 310 from being damaged by the subsequent ion implantation processes.
  • the conductive type of the well region 314 is the same as the active region 310 , and is different from that of the well region 308 .
  • the well region 314 and the active region 310 are P-type
  • the well region 308 is N-type.
  • the well region 314 and the active region 310 are N-type, and the well region 308 is P-type.
  • the DTI 306 is located in the well region 308 and near to the boundary between the well regions 308 and 314 .
  • the DTI 306 is located between the well region 314 and a majority of the well region 308 .
  • the path of the leakage current I LEAK from the well region 314 toward the active region 310 is lengthened, such that the leakage current I LEAK can be reduced.
  • FIG. 4C illustrates the ion implantation process is performed with a tilting angle of zero.
  • the tilting angle of the ion implantation process may be up to 7 degrees for fabricating semiconductor substrate 300 at the periphery area of the wafer.
  • FIG. 5 illustrates formation of the well region 314 using the ion implantation process with non-zero tilting angle in accordance with some embodiments. As shown in FIG. 5 , after the ion implantation process, the well region 314 is formed, such that the DTI 306 is located at the boundary between the well regions 308 and 314 . As can be seen from FIG.
  • the path of the leakage current I LEAK from the well region 314 toward the active region 310 is lengthened because of the DTI 306 and, therefore, the leakage current I LEAK can be reduced in a similar manner as described above with reference to FIG. 4C .
  • the DTI 306 may be located in the well region 314 and near to the boundary between the well regions 308 and 314 . Such structure also helps lengthen the path of the leakage current I LEAK from the well region 314 toward the active region 310 , thus reducing the leakage current I LEAK .
  • FIG. 6 illustrates formation of a well region using an ion implantation process in accordance with some embodiments.
  • the DTI 306 ′ shown in FIG. 6 is formed corresponding to the deep trench 112 ′ shown in FIG. 2B .
  • the well region 314 is formed, such that the DTI 306 ′ is located at the boundary between the well regions 308 and 314 .
  • the path of the leakage current I LEAK from the well region 314 toward the active region 310 is lengthened because of the DTI 306 ′ and, therefore, the leakage current I LEAK can be reduced.
  • the semiconductor structure of the present disclosure can reduce leakage current through well regions.
  • memory integrated circuits e.g., flash memory chips
  • the semiconductor structure of the present disclosure may be applied to other types of integrated circuits as well, such as CMOS image sensors, temperature sensors, and/or the like.
  • FIG. 7 is a schematic cross-sectional view of a semiconductor structure 400 in accordance with some embodiments.
  • the semiconductor structure 400 may a laterally diffused metal oxide semiconductor (LDMOS), a vertical diffused metal oxide semiconductor (VDMOS), or the like.
  • LDMOS laterally diffused metal oxide semiconductor
  • VDMOS vertical diffused metal oxide semiconductor
  • a P-type implant region 412 is formed on a P-type semiconductor substrate 410
  • a N-type well region 414 is formed on the semiconductor substrate 410 and adjacent to the P-type implant region 412 .
  • a N-type implant region 416 is formed in the N-type well region 414 .
  • a gate dielectric 418 and a gate electrode 420 are sequentially formed on the substrate 410 , the P-type implant region 412 and the N-type well region 414 .
  • the gate electrode 420 may be a conductive gate structure, such as polysilicon gate structure, metal gate structure or other suitable gate electrode.
  • a gate spacer 422 is formed on sidewalls of the gate dielectric 418 and the gate electrode 420 .
  • a STI 424 A is formed on the P-type implant region 412
  • STIs 426 A and 428 A are formed on the N-type well region 414 and the N-type implant region 416
  • DTIs 424 B, 426 B and 428 B are formed below the STIs 424 A, 426 A and 428 A, respectively.
  • the STIs 424 A, 426 A and 428 A and the DTIs 424 B, 426 B and 428 B may be similar to the STI 114 and the DTI 116 in FIG. 1H respectively.
  • the lightly doped drain (LDD) region 430 is formed in the P-type implant region 412 and below the gate spacer 422 .
  • the source/drain electrode 432 is formed between the STI 424 A and the LDD region 430
  • the source/drain electrode 434 is formed between the STIs 426 A and 428 A.
  • a N-type implant region 412 is formed on a N-type semiconductor substrate 410 , and a P-type well region 414 is formed on the substrate and adjacent to the N-type implant region 412 .
  • a P-type implant region 416 is formed in the P-type well region 414 .
  • a gate dielectric 418 and a gate electrode 420 are sequentially formed on the N-type semiconductor substrate 410 , the N-type implant region 412 and the P-type well region 414 .
  • a gate spacer 422 is formed on sidewalls of the gate dielectric 418 and the gate electrode 420 .
  • a STI 424 A is formed on the N-type implant region 412
  • STIs 426 A and 428 A are formed on the P-type well region 414 and the P-type implant region 416
  • DTIs 424 B, 426 B and 428 B are formed below the STIs 424 A, 426 A and 428 A, respectively.
  • the lightly doped drain (LDD) region 430 is formed in the N-type implant region 412 and below the gate spacer 422 .
  • the source/drain electrode 432 is formed between the STI 424 A and the LDD region 430
  • the source/drain electrode 434 is formed between the STIs 426 A and 428 A.
  • the LDMOS structure with DTI is the semiconductor structure 400 in the FIG. 7 .
  • the structure without DTI is similar to the semiconductor structure 400 except that no DTIs are included.
  • the breakdown voltage of the LDMOS with DTI is greater than that of the LDMOS without DTI
  • the drain-source on-state resistance (Rdson) of the LDMOS with DTI is greater than that of the LDMOS without DTI.
  • the current path from the source/drain electrode 434 to the source/drain electrode 432 is lengthened, such that the drain-source on-state resistance increases accordingly.
  • the width of the LDMOS with DTI is narrowed from 2.3 ⁇ m to 1.5 ⁇ m, the breakdown voltage decreases from 59.5 V to 55.8 V, which is still greater than that of the LDMOS without DTI, and the power consumption of the LDMOS with DTI decreases from 28.5 to 24.8, which becomes lower than that of the LDMOS without DTI.
  • the DTI helps increase the breakdown voltage the LDMOS and narrow the STI width of the LDMOS, thereby saving the size of the LDMOS.
  • FIG. 8 is a flow chart of a method 500 for fabricating a semiconductor device in accordance with some embodiments.
  • the method 500 begins at operation 502 , where a semiconductor substrate 302 , a STI 304 and a DTI 306 are provided, and a well region 308 is formed on the semiconductor substrate 302 .
  • the semiconductor substrate 302 may be a P-type or N-type semiconductor substrate.
  • the well region 308 has a first conductive type, which may be P-type or N-type, for example.
  • the well region 308 may be formed by a process such as ion implantation process, diffusion process, or the like.
  • the DTI 306 is located in the well region 308 .
  • an active region 310 is formed on the well region 308 .
  • the active region 310 may be formed by a process such as ion implantation process, diffusion process, or another suitable process.
  • the active region 310 has a conductive type is different from the first conductive type of the well region 308 .
  • the conductive type of the active region 310 is P-type if the first conductive type is N-type.
  • a well region 314 of a second conductive type is formed on the semiconductor substrate 302 and laterally adjacent to the well region 308 .
  • a photoresist 312 may be formed on the active region 310 for protecting the active region 310 from being damaged by the subsequent processes.
  • an ion implantation process is performed to form the well region 314 .
  • the second conductive type of the well region 314 is the same as the conductive type of the active region 310 , and is different from the first conductive type of the well region 308 .
  • the second conductive type of the well region 314 and the conductive type of the active region 310 are P-type
  • the first conductive type of the well region 308 is N-type. As shown in FIG.
  • the DTI 306 is located in the well region 308 and near to the boundary between the well regions 308 and 314 . In other words, the DTI 306 is located between the well region 314 and a majority of the well region 308 .
  • the DTI 306 is located at the boundary between the well regions 308 and 314 .
  • the DTI 306 may be located in the well region 314 and near to the boundary between the well regions 308 and 314 .
  • the present disclosure discloses another method of forming a semiconductor structure.
  • a semiconductor substrate is provided.
  • a shallow trench is formed by etching the semiconductor substrate.
  • a protective layer is formed covering the shallow trench.
  • a first etching process is performed to the protective layer until at least a portion of a bottom surface of the shallow trench is exposed by the protective layer.
  • a second etching process is performed on the portion of the bottom surface of the shallow trench, thereby forming at least one deep trench below the bottom surface of the shallow trench.
  • the protective layer remained on the semiconductor substrate and in the shallow trench is removed.
  • An isolation oxide is filled into the deep trench and the shallow trench to form at least one DTI and a STI respectively.
  • a first well region of a first conductive type is formed on the semiconductor substrate.
  • An active region is formed on the first well region.
  • a second well region of a second conductive type is formed on the semiconductor substrate and adjacent to the first well region.
  • the second conductive type is different from the first conductive type, and second conductive type is the same a conductive type of the active region.
  • the first well region and the second well region are formed such that the DTI is disposed between at least a portion of the first well region and at least a portion of the second well region.
  • the present disclosure discloses a semiconductor structure.
  • the semiconductor structure includes a semiconductor substrate, a first well region of a first conductive type on the semiconductor substrate, a second well region of a second conductive type on the semiconductor substrate, an active region on the second well region, a STI between the first well region and the second well region, and at least one DTI below the STI in the semiconductor substrate.
  • the second well region is adjacent to the first well region.
  • the second conductive type is different from the first conductive type.
  • a conductive type of the active region is the same as the second conductive type of the second well region.
  • the DTI is disposed between at least a portion of the first well region and at least a portion of the second well region.
  • the present disclosure discloses a semiconductor structure.
  • the semiconductor structure includes a semiconductor substrate, a first implant region of a first conductive type on the semiconductor substrate, a second implant region of a second conductive type on the semiconductor substrate, a first source/drain electrode in the first implant region, a second source/drain electrode in the second implant region, a gate electrode on the semiconductor substrate and between the first source/drain electrode and the second source/drain electrode, a STI between the first source/drain electrode and the second source/drain electrode, and at least one DTI below the STI in the semiconductor substrate.
  • the second conductive type is different from the first conductive type.
  • the DTI is disposed between at least a portion of the first implant region and at least a portion of the second implant region.

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CN106257633B (zh) 2019-08-02
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US20220199459A1 (en) 2022-06-23
DE102015110584B4 (de) 2023-11-16

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