US20070275543A1 - Manufacturing method of a semiconductor device - Google Patents

Manufacturing method of a semiconductor device Download PDF

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Publication number
US20070275543A1
US20070275543A1 US11/700,926 US70092607A US2007275543A1 US 20070275543 A1 US20070275543 A1 US 20070275543A1 US 70092607 A US70092607 A US 70092607A US 2007275543 A1 US2007275543 A1 US 2007275543A1
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semiconductor wafer
dicing tape
manufacturing
semiconductor
semiconductor device
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Inventor
Yoshiyuki Abe
Hideo Muto
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NEC Electronics Corp
Renesas Electronics Corp
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Renesas Technology Corp
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Assigned to RENESAS TECHNOLOGY CORP. reassignment RENESAS TECHNOLOGY CORP. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ABE, YOSHIYUKI, MUTO, HIDEO
Publication of US20070275543A1 publication Critical patent/US20070275543A1/en
Assigned to RENESAS ELECTRONICS CORPORATION reassignment RENESAS ELECTRONICS CORPORATION CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: NEC ELECTRONICS CORPORATION
Assigned to NEC ELECTRONICS CORPORATION reassignment NEC ELECTRONICS CORPORATION MERGER (SEE DOCUMENT FOR DETAILS). Assignors: RENESAS TECHNOLOGY CORP.
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

Definitions

  • the present invention relates to a manufacturing technology of a semiconductor device and, more particularly, to a manufacturing method of a semiconductor device that uses a dicing tape.
  • a semiconductor wafer is cut along a lattice-shaped region, called a scribe area, of a principal plane of a semiconductor wafer (hereinafter also referred to simply as a wafer) to form semiconductor chips (hereinafter also referred to simply as chips).
  • a cutting tool in the form of a disk called a dicing blade is used to cut the wafer.
  • the wafer is divided into individual chips (dividing) with a dicing blade. After being separated individually, the chips are picked up by expanding spacings among chips in an expanding process. At this time, the pickup of the chip is performed after irradiating the dicing tape with UV following the expanding.
  • this UV irradiation hardens a paste (adhesive layer or binder) of the dicing tape, thereby decreasing adhesive strength of the paste, the picking-up of the chips can be performed easily. That is, the paste of the dicing tape is in a soft state before performing the picking-up. This is because it is preferred that the paste is in a comparatively soft state at the time of using the dicing blade. The reason to do so is not to allow the chips being prepared as individual chips by dicing to disperse away from the dicing tape due to vibration of the dicing blade.
  • the laser dicing process In the laser dicing process, generally, after completion of backside grinding of the wafer, laser light is irradiated from the backside of the wafer to form a fractured layer (or called a modified layer or the like) in the interior of the wafer. After attaching the dicing tape on the wafer, a breaking work (bending work) is performed. In the breaking work, the wafer is bent, so that crack is generated from the fractured layer, which causes the wafer to divide into chips. Then, expanding for expanding spacings among chips is performed.
  • a breaking work bending work
  • UV irradiation on the dicing tape is performed. Since this UV irradiation causes the paste (an adhesive layer or binder) of the dicing tape to be hardened and decreases the adhesive strength of the paste, the chips become easy to pick up.
  • this method comes with a problem that the chip may shift at the time of breaking of the wafer, and chipping may occur in a corner part on the backside of the chip. That is, when the wafer is bent at the time of the breaking, since the paste of the dicing tape is soft, a chip moves and interferes with adjacent chips, which generates chipping of a chip (chipping). This poses problems: reduction in reliability of the semiconductor device and decrease in the yield of the chips.
  • the spacings among the adjacent chips that are divided is sufficiently secured because the dicing blade width is wider (thicker) than the width of a separated region made by laser dicing even if the paste of the dicing tape is soft; therefore, the adjacent chips do not interfere with one other in the picking-up of the chips.
  • the breaking is a necessary work in order not to generate whisker defect in an inspection pattern on the wafer. That is, as shown in a whisker part 1 V of an inspection pattern 1 Wf of the comparative example in FIG. 25 , if the expanding is performed without doing the breaking in advance, since the inspection pattern 1 Wf formed on the principal plane of the wafer is formed with copper etc., which tends to last not so as to be cut, remaining as the whisker part 1 V. Therefore, in order not to allow a whisker part 1 V to form, it is necessary to perform the breaking in advance before the expanding.
  • the paste is soft, a problem that the paste of the dicing tape adheres to a chip backside at the time of being expanded (the expanding) also arises. That is, when the dicing tape is expanded, the paste is also expanded and torn off. Especially, when the chip is mounted on the dicing tape via a DAF (Die Attach Film, adhesive film), if the paste of the dicing tape is soft, even if the DAF is be cut finely, the paste of the dicing tape adheres to the backside of the DAF.
  • DAF Die Attach Film, adhesive film
  • the paste of the dicing tape has adhered to the backside of the DAF, the paste deteriorates by heat imposed on the DAF at the time of a temperature cycle test, reflow, etc., which causes a problem of degrading temperature-cycle-tolerance and reflow-tolerance.
  • the object of this invention is to provide a technology whereby improvement in reliability of a semiconductor device can be aimed at.
  • Another object of this invention is to provide a technology whereby improvement in the yield of obtaining semiconductor chips can be aimed at.
  • Another object of this invention is to provide a technology whereby fall of the temperature-cycle-tolerance and reflow-tolerance can be inhibited.
  • this invention comprises the steps of: forming a fractured layer in the interior of a semiconductor wafer by irradiating laser light onto the semiconductor wafer; mounting the semiconductor wafer on a dicing tape via an adhesive layer; hardening the adhesive layer of the dicing tape; dividing the semiconductor wafer starting from the fractured layer by bending it; and expanding chip spacings by stretching the dicing tape from its peripheral part.
  • the paste Since the paste has hardened at the time of being expanded (the expanding) by hardening the adhesive layer (paste) of the dicing tape and subsequently performing the expanding of the semiconductor wafer, the paste is not torn off and can be prevented from adhering to the backside of the DAF. As a result, the fall of the temperature-cycle-tolerance and the reflow-tolerance can be prevented.
  • FIG. 1 is a flow diagram showing one example of a manufacturing method of a semiconductor device of a first embodiment of this invention
  • FIG. 2 is a sectional view showing one example of a BG-tape attached state in a flow shown in FIG. 1 ;
  • FIG. 3 is a conceptual diagram showing one example of a thickness measurement state of a wafer in the flow shown in FIG. 1 ;
  • FIG. 4 is a conceptual diagram showing one example of a thickness measuring instrument of the wafer in the flow shown in FIG. 1 ;
  • FIG. 5 is a conceptual diagram showing one example of an output waveform of the thickness measuring instrument shown in FIG. 4 ;
  • FIG. 6 is a plan view showing one example of a construction of a backside grinding (BG) machine in the flow shown in FIG. 1 ;
  • BG backside grinding
  • FIG. 7 is a conceptual diagram showing one example of a backside grinding state in the flow shown in FIG. 1 ;
  • FIG. 8 is a conceptual diagram showing one example of a laser dicing state in the flow shown in FIG. 1 ;
  • FIG. 9 is a sectional view showing one example of a structure after attaching a DAF in the flow shown in FIG. 1 ;
  • FIG. 10 is a sectional view showing one example of a wafer mount state in the flow shown in FIG. 1 ;
  • FIG. 11 is a sectional view showing one example of a breaking state in the flow shown in FIG. 1 ;
  • FIG. 12 is a sectional view showing one example of an expanding state in the flow shown in FIG. 1 ;
  • FIG. 13 is a perspective diagram showing one example of a construction of pickup equipment used at the time of the expanding shown in FIG. 12 ;
  • FIG. 14 is a plan view showing one example of a structure of an inspection pattern divided into portions by the expanding shown in FIG. 12 ;
  • FIG. 15 is a sectional view showing one example of a picking-up state in the manufacturing method of a semiconductor device of the first embodiment of this invention.
  • FIG. 16 is a perspective diagram showing one example of a die bonding method in the manufacturing method of a semiconductor device of the first embodiment of this invention.
  • FIG. 17 is a sectional view showing one example of a die bonding method of a second (upper) chip in the manufacturing method of a semiconductor device of the first embodiment of this invention
  • FIG. 18 is a sectional view showing one example of a structure after wire bonding in the manufacturing method of a semiconductor device of the first embodiment of this invention.
  • FIG. 19 is a sectional view showing one example of a structure after resin sealing and bump formation in the manufacturing method of a semiconductor device of the first embodiment of this invention.
  • FIG. 20 is a flow diagram showing one example of the manufacturing method of a semiconductor device of a second embodiment of this invention.
  • FIG. 21 is a sectional view showing one example of a wafer mount state in the flow shown in FIG. 20 ;
  • FIG. 22 is a sectional view showing one example of a UV irradiation state in the flow shown in FIG. 20 ;
  • FIG. 23 is a sectional view showing one example of the expanding state in the flow shown in FIG. 20 ;
  • FIG. 24 is a sectional view showing one example of the picking-up state in the manufacturing method of a semiconductor device of the second embodiment of this invention.
  • FIG. 25 is a plan view showing a structure of an inspection pattern of the comparative example.
  • the embodiments are divided into a plurality of sections or embodiments, which will be explained. Except for cases specially specified, they are not irrelevant to one another but have relations: one of them is a modification, details, supplementary information, or the like of a part or the whole of the others.
  • FIG. 1 is a flow diagram showing one example of a manufacturing method of a semiconductor device of a first embodiment of this invention
  • FIG. 2 is a sectional view showing one example of a BG-tape attached state in the flow shown in FIG. 1
  • FIG. 3 is a conceptual diagram showing one example of a state of thickness measurement of the wafer in the flow shown in FIG. 1
  • FIG. 4 is a conceptual diagram showing one example of a wafer thickness measuring instrument in the flow shown in FIG. 1
  • FIG. 5 is a conceptual diagram showing one example of an output waveform of the thickness measuring instrument shown in FIG. 4
  • FIG. 6 is a plan view showing one example of a construction of backside BG equipment in the flow shown in FIG. 1 ;
  • FIG. 7 is a conceptual diagram showing one example of a backside grinding state in the flow shown in FIG. 1 ;
  • FIG. 8 is a conceptual diagram showing one example of a laser dicing state in the flow shown in FIG. 1 ;
  • FIG. 9 is a sectional diagram showing one example of a structure after DAF attachment in the flow shown in FIG. 1 ;
  • FIG. 10 is a sectional view showing one example of a wafer mount state in the flow shown in FIG. 1 .
  • FIG. 11 is a sectional view showing one example of a breaking state in the flow shown in FIG. 1 ;
  • FIG. 12 is a sectional view showing one example of an expanding state in the flow shown in FIG. 1 ;
  • FIG. 13 is a perspective diagram showing one example of a construction of pickup equipment used at the time of the expanding shown in FIG. 12 ;
  • FIG. 14 is a plan view showing one example of a structure of the inspection pattern divided by the expanding shown in FIG. 12 .
  • FIG. 15 is a sectional view showing one example of a picking-up state of the first embodiment of this invention
  • FIG. 16 is a perspective diagram showing one example of a die bonding method of the first embodiment of this invention
  • FIG. 17 is a sectional view showing one example of the die bonding method of a second (upper) chip of the first embodiment of this invention
  • FIG. 18 is a sectional view showing one example of a structure after wire bonding of the first embodiment of this invention
  • FIG. 19 is a sectional view showing one example of a structure after resin sealing and bump formation of the first embodiment of this invention.
  • a manufacturing method of a semiconductor device of the first embodiment relates to assembly of a semiconductor device with a mounted thin semiconductor chip (for example, chip thickness is 50 ⁇ m or less).
  • a semiconductor wafer 1 W shown in FIG. 2 is prepared.
  • the semiconductor wafer has a principal plane 1 Wa on which a plurality of chip regions 2 shown in FIG. 13 are formed and a backside 1 Wb facing this principal plane 1 Wa.
  • the inspection pattern 1 Wf is formed in a scribe area 1 We of the principal plane 1 Wa of the semiconductor wafer 1 W.
  • the inspection pattern 1 Wf is formed with a copper alloy, for example.
  • BG (Backside Grinding) tape attaching shown in Step S 1 of FIG. 1 is performed.
  • a BG tape (tape for grinding) 3 is attached to the principal plane 1 Wa of the semiconductor wafer 1 W.
  • Step S 2 of FIG. 1 thickness measurement shown in Step S 2 of FIG. 1 is performed as it is.
  • this measurement as shown in FIG. 4 , near infrared light 9 b that is infrared radiation is irradiated on the semiconductor wafer 1 W and reflected light 9 c from interfaces (the backside 1 Wb and the principal plane 1 Wa) of the semiconductor wafer 1 W is detected, whereby thickness of the semiconductor wafer 1 W is measured.
  • the semiconductor wafer 1 W fixed to a chuck table 9 d via the BG tape 3 is irradiated with the near infrared light 9 b from its backside 1 Wb side (from the above) by the thickness measuring instrument 9 a , such as an infrared camera connected with a controller 9 e , reflected light 9 c (a) from the backside 1 Wb and reflected light 9 c (b) for the principal plane 1 Wa are detected, and a distance T between peaks of the reflected light 9 c ′(a) and the reflected light 9 c (b) is derived, as shown in FIG. 5 .
  • the distance T between the peaks of the reflected light 9 c (a) and the reflected light 9 c (b) indicates the thickness of the semiconductor wafer 1 W.
  • the semiconductor 1 W is placed on a rotary table 13 g , as shown in FIG. 3 , and the thickness is measured while rotating the rotary table 13 g , whereby it becomes possible to perform thickness measurement at a plurality of locations on the plane of the semiconductor wafer 1 W.
  • the thickness of the semiconductor wafer 1 W can be determined with a high accuracy by calculating a mean value of these measured values.
  • the wavelength of the near-infrared light 9 b is 800 to 3000 nm.
  • the thickness of the semiconductor wafer 1 W is measured by calculating a distance T between the peaks of the reflected light 9 c from the backside 1 Wb and that from the principal plane 1 Wa, a thickness of the wafer itself not involving the thickness of the BG tape 3 can be measured.
  • the thickness of the semiconductor wafer 1 W can be measured with a high accuracy. Moreover, since the thickness of the semiconductor wafer 1 W can be measured with a high accuracy in grinding (BG) of the backside 1 Wb of the semiconductor wafer 1 W, the amount of grinding can be calculated with a high accuracy, and accordingly finally the thickness of the semiconductor wafer 1 W can be finished with a high accuracy.
  • BG grinding
  • the backside can be ground while the amount of grinding is being corrected, the wafer can be ground without causing thickness defect. That is, by providing the rotary table 13 g shown in FIG. 3 and the thickness measuring instrument 9 a in the BG equipment shown in FIG. 6 , the grinding of the backside 1 Wb can also be done while the thickness of the semiconductor wafer 1 W is being measured in the backside grinding process.
  • FIG. 6 shows one example of a construction of BG equipment 13 , which has a loader 13 a , an unloader 13 b , a grinding section 13 c (Z 1 to Z 3 ), and a BG tape cleaning section 13 d .
  • the backside grinding can be performed with a high accuracy while correcting the amount of grinding, for example, by disposing the thickness measuring instrument 9 a and the rotary table 13 g in the A part.
  • the thickness measurement of the semiconductor wafer 1 W needs not to be done in the backside grinding process, and may be performed as a thickness measurement process prior to the backside grinding process.
  • BG-DP dry polishing shown in Step S 3 of FIG. 1 is performed.
  • the backside 1 Wb of the semiconductor wafer 1 W is ground, based on a measurement result of the thickness of the semiconductor wafer 1 W.
  • the backside 1 Wb of the semiconductor wafer 1 W is ground until the thickness of the semiconductor wafer 1 W reaches a desired thickness. Grinding is performed by the grinding section 13 c of the BG equipment 13 shown in FIG. 6 . In the grinding section 13 c , as shown in FIG.
  • the semiconductor wafer 1 W is fixed onto the rotary table 13 g via the BG tape 3 , and the backside 1 Wb of the semiconductor wafer 1 W is ground with a grinding stone 13 f of a grinder 13 e in this state so that the thickness of the semiconductor wafer 1 W may be adjusted to the desired thickness.
  • the scribe area 1 We of the semiconductor wafer 1 W (see FIG. 14 ) is irradiated with the near infrared light (infrared radiation) 9 b to allow calculation of positions onto which laser light 7 for laser dicing is to be irradiated.
  • a thickness measurement method shown in FIG. 4 is adopted and the laser irradiation positions are derived by irradiating the near infrared light 9 b on the semiconductor wafer 1 W.
  • the laser light 7 is irradiated onto the scribe area 1 We of the semiconductor wafer 1 W to form a fractured layer (also called modified layer or the like) 1 Wd in the interior of the semiconductor wafer 1 W.
  • the laser light 7 is irradiated onto the irradiation positions in the scribe area 1 We of the semiconductor wafer 1 W, derived by irradiation of the near infrared light 9 b via a converging lens 7 a , thereby forming the fractured layer 1 Wd in its interior.
  • the laser light 7 is moved at a speed of 600 mm/sec, for example.
  • the wavelength of the laser light 7 for laser dicing is 1064 nm.
  • Step S 5 DAF attaching shown in Step S 5 is performed.
  • a DAF 4 that is an adhesive film is attached on the backside 1 Wb of the semiconductor wafer 1 W.
  • the DAF 4 is formed in the shape of a film and made of a die bond material.
  • the semiconductor wafer 1 W is mounted on a dicing tape 5 via the DAF 4 , and the BG tape 3 is peeled after the mounting.
  • the semiconductor wafer 1 W is mounted on the dicing tape 5 so that the DAF 4 of the backside 1 Wb of the semiconductor wafer 1 W and a paste (adhesive layer) 5 b of the dicing tape 5 may contact each other, and subsequently the BG tape 3 is peeled.
  • the dicing tape 5 consists of a base material 5 a formed from a resin, such as polyolefin (PO), and the paste (adhesive layer) 5 b formed on the base material 5 a .
  • the paste 5 b is of an ultraviolet curing type.
  • a ring jig 6 is attached to a peripheral part of the dicing tape 5 .
  • the semiconductor wafer 1 W is mounted on its opening 6 a.
  • the dicing tape 5 is irradiated with ultraviolet radiation.
  • the paste 5 b of the dicing tape 5 is hardened.
  • Step S 7 the breaking shown in Step S 7 is performed.
  • the semiconductor wafer 1 W is bent and divided at the fractured layer 1 Wd.
  • the ultraviolet radiation (UV) shown in Step S 8 is irradiated on the paste (adhesive layer) 5 b of the dicing tape 5 .
  • the bending shown in Step S 9 is performed.
  • FIG. 1 the ultraviolet radiation (UV) shown in Step S 8 is irradiated on the paste (adhesive layer) 5 b of the dicing tape 5 .
  • FIG. 11 shows a principal part of breaking equipment 14 for bending a wafer; a semiconductor wafer 1 W is placed so as to cover bar regions 14 c of a first table 14 a and a second table 14 b , the tables suck the semiconductor wafer 1 W tightly by vacuum from their suction holes 14 d , and in this state the wafer is cut at the fractured layer 1 Wd by application of stress to the fractured layer 1 Wd of the semiconductor wafer 1 W, for example, by tilting only the second table 14 b by a predetermined angle ⁇ . For example, ⁇ is 2°.
  • Step S 10 After completion of the bending, the expanding shown in Step S 10 is performed. First, the DAF 4 that is an adhesive film is hardened. Then, the expanding is performed in the state where DAF 4 is hardened. To be concrete, in a state where the DAF 4 is hardened, the dicing tape 5 is stretched from its peripheral part, so that chip spacings are expanded.
  • the dicing tape 5 that is attached to the semiconductor wafer 1 W is positioned horizontally on a support ring 11 of pickup equipment 10 , and the ring jig 6 joined to the peripheral part of the dicing tape 5 is held by the expanding ring 12 .
  • a push-up horse 16 for pushing the semiconductor chip 1 C upward is disposed in the inside of the support ring 11 .
  • the ring jig 6 joined to the peripheral part of the dicing tape 5 is pushed downward, as shown in FIG. 12 .
  • the dicing tape 5 is received strong tension that directs toward the periphery (peripheral part) from its center and stretched in horizontal directions, thereby removing loosing. Since this tension causes the chip regions shown in FIG. 13 to separate from one another along the fractured layer 1 Wd formed in the scribe area 1 We of the semiconductor wafer 1 W, as a result, the plurality of semiconductor chips 1 C that are divided individually are obtained, as shown in FIG. 12 .
  • the DAF 4 on the backside 1 Wb of the semiconductor wafer 1 W is also stretched along with the dicing tape 5 and the chips are separated as individual chips, the DAF 4 of the same size as the semiconductor chip 1 C remains on the backside of each of the semiconductor chips 1 C that are divided individual chips.
  • the DAF 4 can be divided surely at the time of the expanding.
  • the semiconductor chip 1 C can be picked up surely, and generation of chipping etc. can be inhibited.
  • improvement in the reliability of a semiconductor device CSP 24 shown in FIG. 19
  • the yield of obtaining the semiconductor chips 1 C can be raised.
  • the paste 5 in the case where the paste 5 b of the dicing tape 5 is hardened by UV irradiation prior to the bending, the paste 5 can be prevented from adhering to the backside of the DAF 4 while the paste 5 b is not torn off because the paste has been hardened at the time of the expanding. Accordingly, the paste 5 b has not adhered to the backside of the DAF 4 ; therefore, the fall of the temperature-cycle-tolerance and the reflow-tolerance in the subsequent process can be inhibited.
  • the chip is inhibited from degrading in flatness and subsequently leading to mounting defect in laminating the semiconductor chips 1 C (or mounting them in the circuit board) in the chip mounting process that will be described or the like.
  • the inspection pattern 1 Wf can be cut without forming the whisker part 1 V (see FIG. 25 ), as shown in FIG. 14 .
  • the problem that the paste 5 b of the dicing tape 5 adheres to the backside to the DAF 4 can be prevented. If the UV irradiation process is placed after the breaking process, it becomes hard for the dicing tape 5 to be stretched so as to eliminate the loosing in the expanding process. Doing the process in this way comes from a fact that if the breaking process is performed in a state where the adhesive layer 5 b of the dicing 5 is not hardened, only the semiconductor wafer 1 W is divided.
  • the dicing tape 5 is hardened in a state where crack is not formed in the dicing tape 5 . Because of this, the hardened dicing tape 5 becomes hard to stretch in the expanding process. Contrary to this, like this first embodiment, if the UV irradiation is performed prior to the breaking process, both the semiconductor wafer 1 We and at least a part of the hardened dicing tape 5 are divided in the breaking process.
  • the dicing tape 5 can easily be stretched because such a region of the dicing tape 5 that is overlapped two-dimensionally with the fractured layer 1 Wd formed in the semiconductor wafer 1 W has been divided.
  • Step S 11 of FIG. 1 This process removes the loosing of the dicing tape 5 generated by the expanding of the periphery that is the outer portion of a plurality of semiconductor chips 1 C.
  • die bonding shown in Step S 12 is performed.
  • the chip picking-up shown in FIG. 15 is performed. To be concrete, the semiconductor chips 1 C that are divided individual chips are picked up from the dicing tape 5 .
  • the push-up horse 16 is disposed under one semiconductor chip 1 C, and a collet 19 capable of sucking and holding a chip for the picking up is disposed above the semiconductor chip 1 C and is made contact with it closely.
  • the collet 19 is moved upward to effect peeling of the semiconductor chip 1 C and the DAF 4 from the dicing tape 5 .
  • the semiconductor chip 1 C that is peeled from the dicing tape 5 and picked up is conveyed to the next process (pellet attaching process) by being sucked and held by the collet 19 , and mounted on a circuit board 17 , as shown in FIG. 16 .
  • the picked-up semiconductor chip 1 C is transported onto the principal plane of a semiconductor chip 18 C mounted on the principal plane of the circuit board 17 , as shown in FIGS. 16 and 17 .
  • the semiconductor chip 18 C is mounted on the principal plane of the circuit board 17 , as the first (lower) chip, via the adhesive layer 20 a.
  • the semiconductor chip 1 C is lowered while the adhesive layer 8 a of the backside of the semiconductor chip 1 C and the principal plane of the semiconductor chip 18 C are made to face each other.
  • the adhesive layer 8 a is the DAF 4 in this first embodiment.
  • the semiconductor chip 1 C is stacked (laminated) on the semiconductor chip 18 C via the adhesive layer 8 a (DAF 4 ).
  • the number of laminated chips is not restricted to two, and any number of lamination may be adopted.
  • the circuit board 17 is made up of a printed circuit board having a multilayer wiring configuration, for example, and has a principal plane and a backside that are placed in mutually opposite sides across the thickness direction.
  • the semiconductor chip 18 C is mounted on the principal plane of the circuit board 17 .
  • a plurality of electrodes 17 a are arranged on the principal plane of the circuit board 17 so as to surround outer boundary of the semiconductor chip 18 C.
  • a plurality of electrodes 17 b are arranged on the backside of the circuit board 17 .
  • the electrode 17 a on the principal plane of the circuit board 17 and the electrode 17 b of the backside are electrically connected together through wiring in an inner layer of the circuit board 17 .
  • the wiring of the electrodes 17 a , 17 b of the circuit board 17 is made of copper, for example. Exposed surfaces of the electrodes 17 a , 17 b are given gold (Au) plating with a nickel (Ni) base.
  • a semiconductor substrate 18 S for the semiconductor chip 18 C is made of silicon (Si) single crystal, for example, just like the semiconductor substrate 1 S for a semiconductor chip 1 C.
  • an element and a wiring layer 18 L are formed on its principal plane.
  • a structure of the wiring layer 18 L is the same as the wiring layer 1 L of the semiconductor chip 1 C, and a pad 18 LB is disposed on its top layer.
  • the semiconductor chip 18 C is mounted on the principal plane of the circuit board 17 with a principal plane of the semiconductor chip 18 C facing the above and its backside being fixed to the principal plane of the circuit board 17 by the adhesive layer 20 a .
  • the adhesive layer 20 a is formed with a thermoplastic resin like a polyimide resin, for example.
  • the DAF 4 may be used as a material of the adhesive layer 20 a . That is, both the first semiconductor chip 18 C and a second semiconductor chip 1 C may be mounted via the DAF 4 .
  • the pad 1 LB of the second semiconductor chip 1 C and the pad 18 LB of the first semiconductor chip 18 C are connected together using conductive wire 21 ; the pad 18 LB of the first semiconductor chip 18 C and the electrode 17 a of the circuit board 17 are connected together using the wire 21 .
  • the pad 1 LB of the second semiconductor chip 1 c and the electrode 17 a of the circuit board 17 may be connected together using the wire 21 .
  • the wire 21 is formed with gold (Au), for example.
  • a sealing member 22 is formed from an epoxy type resin or the like using the transfer mold method, and sealing is done with this sealing member 22 .
  • a solder ball 23 is formed on the electrode 17 b as an external terminal.
  • the solder ball 23 is made up of a lead solder material of, for example, a lead (Pb)-tin (Sn) system or a lead-free solder material of, for example, a tin (Sn)-silver (Ag)-copper (Cu) system.
  • the CSP 24 semiconductor device
  • FIG. 20 is a flow diagram showing one example of a manufacturing method of a semiconductor device of a second embodiment of this invention.
  • FIG. 21 is a sectional view showing one example of a wafer mount state in the flow shown in FIG. 20 .
  • FIG. 22 is a sectional view showing one example of a UV irradiation state in the flow shown in FIG. 20 ;
  • FIG. 23 is a sectional view showing one example of an expanding state in the flow shown in FIG. 20 , and
  • FIG. 24 is a sectional view showing one example of a picking-up state in the manufacturing method of a semiconductor device of the second embodiment of this invention.
  • the manufacturing method of a semiconductor device of this second embodiment relates to assembly of a semiconductor device with a mounted thin semiconductor chip of a chip thickness of 50 ⁇ m or less.
  • a point different from the first embodiment is that, in mounting the wafer on the dicing tape 5 , the semiconductor wafer 1 W is directly mounted on the dicing tape 5 without using the DAF 4 .
  • the semiconductor wafer 1 W is prepared, like the first embodiment.
  • the semiconductor wafer 1 W has the principal plane 1 Wa on which a plurality of chip regions 2 shown in FIG. 13 are formed and the backside 1 Wb facing this principal plane 1 Wa.
  • the inspection pattern 1 Wf is formed in the scribe area 1 We of the principal plane 1 Wa of the semiconductor wafer 1 W.
  • the inspection pattern 1 Wf is formed with a copper alloy, for example.
  • Step S 21 of FIG. 20 BG-tape attaching shown in Step S 21 of FIG. 20 is performed.
  • the BG tape 3 is attached on the principal plane 1 Wa of the semiconductor wafer 1 W.
  • Step S 22 thickness measurement is performed as it is.
  • thickness measurement is performed by the same method as the first embodiment.
  • the semiconductor wafer 1 W is irradiated with the near infrared light 9 b that is infrared radiation, and the reflected light 9 c from the backside 1 Wb and that from the principal plane 1 Wa of semiconductor wafer 1 W are detected, thereby allowing a thickness of the semiconductor wafer 1 W to be measured.
  • Step S 23 BG-DP (dry polishing) shown in Step S 23 is performed.
  • the backside 1 Wb of the semiconductor wafer 1 W is ground based on the measurement result of the thickness of the semiconductor wafer 1 W.
  • the backside 1 Wb of the semiconductor wafer 1 W is ground until the thickness of the semiconductor wafer 1 W reaches a desired thickness, while measuring the thickness of the semiconductor wafer 1 W.
  • the near infrared light 9 b is irradiated on the scribe area 1 We of the semiconductor wafer 1 W (see FIG. 14 ) to allow calculation of positions onto which the laser light 7 for laser dicing is to be irradiated.
  • a thickness measuring method shown in FIG. 4 is adopted, and the laser irradiation positions are derived by irradiating the near infrared light 9 b.
  • the laser dicing shown in Step S 24 is performed.
  • the fractured layer (also called modified layer or the like) 1 Wd is formed in the interior of the semiconductor wafer 1 W by irradiating the scribe area 1 We of the semiconductor wafer 1 W with the laser light 7 .
  • the laser light 7 is irradiated onto the laser irradiation positions in the scribe area 1 We of the semiconductor wafer 1 W that are derived by irradiating the near infrared light 9 b from the backside 1 Wb side of the semiconductor wafer 1 W, and the fractured layer 1 Wd is formed in its interior.
  • the wavelength of the laser light 7 for laser dicing is 1064 nm.
  • Step S 25 the wafer mounting shown in Step S 25 is performed.
  • the semiconductor wafer 1 W is mounted on the dicing tape 5 , and the BG tape 3 is peeled after the mounting.
  • the semiconductor wafer 1 W is mounted on the dicing tape 5 so that the backside 1 Wb of the semiconductor wafer 1 W and the paste (adhesive layer) 5 b of the dicing tape 5 may contact each other, and subsequently the BG tape 3 is peeled.
  • the dicing tape 5 consists of the base material 5 a formed from a resin, such as polyolefin (PO) and the paste (adhesive layer) 5 b formed on the base material 5 a .
  • the paste 5 b is of an ultraviolet curing type.
  • the ring jig 6 with an opening 6 a is fixed to the peripheral part of the dicing tape 5 .
  • the semiconductor wafer 1 W is mounted in the opening 6 a.
  • Step S 26 the breaking shown in Step S 26 is performed.
  • the UV irradiation shown in Step S 27 is performed.
  • the dicing tape 5 is irradiated with ultraviolet radiation to effect hardening of the paste 5 b of the dicing tape 5 .
  • ultraviolet radiation is irradiated from the backside 1 Wb side of the semiconductor wafer 1 W.
  • a fiber scope 15 a connected with a UV lamp 15 b is disposed on the backside 1 Wb side of the semiconductor wafer 1 W, the ultraviolet radiation is irradiated from the backside 1 Wb side of the semiconductor wafer 1 W.
  • the dicing tape 5 is attached on the backside 1 Wb of the semiconductor wafer 1 W, irradiation of the ultraviolet radiation on the semiconductor wafer 1 W from the backside 1 Wb side thereof hardens the paste 5 b of the dicing tape 5 surely.
  • UV irradiation shown in FIG. 22 a case where the UV lamp 15 b including the fiberscope 15 a is moved beneath the semiconductor wafer 1 W is shown.
  • a method in which the UV lamp 15 b is fixed and the semiconductor wafer 1 W is moved may be adopted, or alternatively a method in which both the UV lamp 15 b and the semiconductor wafer 1 W are fixed and the ultraviolet radiation is irradiated may be used.
  • the UV lamp 15 b is covered with a large reflector on the backside 1 Wb side of the semiconductor wafer 1 W, and the ultraviolet radiation is subjected to irregular reflection by the reflector, whereby the whole backside 1 Wb of the semiconductor wafer 1 W is irradiated with the ultraviolet radiation.
  • Step S 28 of FIG. 20 the bending (the breaking) shown in Step S 28 of FIG. 20 is performed.
  • the semiconductor wafer 1 W is bent by the same method as the first embodiment shown in FIG. 11 , and allowed to be divided at the fractured layer 1 Wd.
  • the paste 5 b of the dicing tape 5 is hardened by the UV irradiation in this second embodiment, shifting and movement of the semiconductor 1 C can be prevented at the time of the bending.
  • This technique can prevent the semiconductor chip 1 C from interfering with adjacent chips, thereby inhibiting generation of chipping.
  • the paste 5 b of the dicing tape 5 needs to be hardened in advance prior to the breaking process.
  • Step S 29 chip spacings are expanded by stretching the dicing tape 5 from its peripheral part.
  • the expanding as shown in FIGS. 13 and 23 , first, the dicing tape 5 to which the semiconductor wafer 1 W is joined is positioned horizontally on the support ring 11 of the pickup equipment 10 , and the ring jig 6 joined to the peripheral part of the dicing tape 5 is held by the expand ring 12 .
  • the push-up horse 16 for pushing the semiconductor chip 1 C upward is disposed in the inside of the support ring 11 .
  • the ring jig 6 joined to the peripheral part of the dicing tape 5 is pushed downward, as shown in FIG. 23 .
  • the dicing tape 5 is stretched in horizontal directions so as to remove the loosing by being received strong tension toward to the periphery (peripheral part) from its center. Since this tension makes the chip regions shown in FIG. 13 separate from one another along the fractured layer 1 Wd formed in the scribe area 1 We of the semiconductor wafer 1 W, a plurality of semiconductor chips 1 C that are divided individual chips can be obtained, as shown in FIG. 23 .
  • the paste 5 b of the dicing tape 5 is hardened by UV irradiation prior to the expanding and the expanding is performed with the paste being hardened, the paste is not torn off at the time of the expanding and accordingly the paste 5 b can be prevented from adhering to the backside of the chip. Therefore, since the paste 5 b is not adhered on the backside of the chip, the chip can be inhibited from causing mounting defect because of degraded flatness of the chip when laminating the semiconductor chips 1 C (or mounting on a circuit board) in a chip mounting process that will be described latter and the like.
  • the inspection pattern 1 Wf can be cut off without forming the whisker part 1 V (see FIG. 25 ), as shown in FIG. 14 .
  • the loosing removal shown in Step S 30 of FIG. 20 is performed. In this process, the loosing of the dicing tape 5 generated by the expanding at the peripheral part of a plurality of semiconductor chips 1 C is removed.
  • Step S 31 the die bonding shown in Step S 31 is performed.
  • the picking-up of a chip shown in FIG. 24 is performed.
  • the semiconductor chips 1 C that are divided individual chips are picked up from the dicing tape 5 .
  • the push-up horse 16 is disposed under one semiconductor chip 1 C
  • the collet 19 for the picking-up capable of sucking and holding a semiconductor chip is disposed on the semiconductor chip 1 C, and the both are made to contact together closely.
  • the semiconductor wafer 1 C is pushed upward by the push-up horse 16 , and the collet 19 is moved upward, so that the semiconductor chip 1 C is peeled from the dicing tape 5 .
  • the semiconductor chip 1 C that was peeled and picked up from the dicing tape 5 in this way is conveyed to the next process (pellet attaching process) by being sucked and held by the collet 19 , and mounted on the circuit board 17 as shown in FIG. 16 .
  • the hardening may be done by cooling.
  • the dicing tape 5 is cooled to effect hardening of the paste 5 b , the semiconductor wafer is bent in this state, the dicing tape is cooled again to effect hardening the paste before the expanding, and the expanding is performed in this state because the dicing tape 5 returns to a normal temperature after the bending.
  • This invention is suitable to a semiconductor manufacturing technology using a dicing tape.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Dicing (AREA)
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US20080233712A1 (en) * 2007-03-22 2008-09-25 Disco Corporation Method of manufacturing device
US20090209088A1 (en) * 2008-02-20 2009-08-20 Disco Corporation Semiconductor chip fabrication method
US8101504B2 (en) * 2008-02-20 2012-01-24 Disco Corporation Semiconductor chip fabrication method
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US9257309B2 (en) 2011-12-09 2016-02-09 Samsung Electronics Co., Ltd. Multi-chip package and method of manufacturing the same
US8710677B2 (en) 2011-12-09 2014-04-29 Samsung Electronics Co., Ltd. Multi-chip package with a supporting member and method of manufacturing the same
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TWI623995B (zh) * 2015-04-20 2018-05-11 Toshiba Memory Corp 半導體裝置之製造方法
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US10672630B2 (en) * 2017-12-22 2020-06-02 Lumileds Llc Method and system for dual stretching of wafers for isolated segmented chip scale packages
US10886152B2 (en) 2017-12-22 2021-01-05 Lumileds Llc Method and system for dual stretching of wafers for isolated segmented chip scale packages
US10283424B1 (en) * 2018-03-08 2019-05-07 Taiwan Semiconductor Manufacturing Co., Ltd. Wafer structure and packaging method
KR20190113573A (ko) * 2018-03-27 2019-10-08 가부시기가이샤 디스코 웨이퍼의 생성 방법 및 웨이퍼의 생성 장치
US11114307B2 (en) * 2018-03-27 2021-09-07 Disco Corporation Method of producing a wafer from an ingot including a peel-off detecting step
KR102594221B1 (ko) * 2018-03-27 2023-10-25 가부시기가이샤 디스코 웨이퍼의 생성 방법 및 웨이퍼의 생성 장치

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CN101047146A (zh) 2007-10-03

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