JP4489492B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP4489492B2 JP4489492B2 JP2004134434A JP2004134434A JP4489492B2 JP 4489492 B2 JP4489492 B2 JP 4489492B2 JP 2004134434 A JP2004134434 A JP 2004134434A JP 2004134434 A JP2004134434 A JP 2004134434A JP 4489492 B2 JP4489492 B2 JP 4489492B2
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- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/45099—Material
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- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
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- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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Description
本発明の半導体装置の製造方法では、複数のデバイス領域にそれぞれ半導体チップを設けた配線基板が一括樹脂封止された一括樹脂封止体を、治具で吸着支持した状態で回転刃により、個々のデバイス領域に個片化する工程を有する。本実施の形態では、かかる半導体装置の製造方法で使用する治具について説明する。
本実施の形態では、複数のデバイス領域にそれぞれ半導体チップを設けた配線基板が一括樹脂封止された一括樹脂封止体を治具で吸着支持した状態で個片化する工程を有する本発明の半導体装置の製造方法で使用する回転刃について説明する。
本実施の形態では、前記実施の形態1で述べた治具10と、前記実施の形態2で述べた回転刃42を用いて、複数のデバイス領域にそれぞれ半導体チップを設けた配線基板が一括樹脂封止された一括樹脂封止体を、個々のデバイス領域に個片化する工程を有する本発明に係る半導体装置の製造方法について述べる。
11 台座
12 支持部
12a 吸着面
12b 外周
13a 孔
13b 孔
14 吸引孔
15 ダイシングライン
15a ダイシングライン
16 位置決めマーク用高さ維持部
17 位置決め用マーク
17a 位置決め用マーク
18 走行ライン
20 一括樹脂封止体
21 配線基板
21a 外周
22 樹脂部
22a 外縁
30 ハンドリングユニット
31 吸着部
32 吸引孔
33 位置決めピン
41 スピンドル
42 回転刃
42a 刃先
43 テーパ部
44 平坦部
45 回転刃
46 切削屑
100 治具
110 台座
120 支持部
120a 吸着面
120b 外周
201 半導体チップ
201a パッド
201b 主面
201c 裏面
203 個片基板(配線基板)
203a 主面
203b 裏面
203c 接続端子
203d バンプランド
203e 絶縁膜
203f 内部配線
204 ワイヤ
205 ダイボンド材
206 封止部
207 多数個取り基板(配線基板)
207a デバイス領域
207b ダイシングライン
207c 基板面(裏面)
208 一括樹脂封止体
208a 表面
209 BGA(半導体装置)
210 ブレード
211 ボール電極
300 治具ダイシング装置
301 ローダ
302 品種判別部
303 ブラシ洗浄部
304 マークモニタ部
305 治具移載部
306 ダイシング部
307 スピンナ洗浄部
308 ピックアップ部
309 水切りローラ部
310 反転部
311 コンタミ除去部
312 検査部
313 中間ポケット部
314 アンローダ部
a 厚さ
b 厚さ
θ 角度
Claims (3)
- (a)複数のデバイス領域が形成された主面、前記主面と反対側の裏面、及び前記複数のデバイス領域のうちの互いに隣り合うデバイス領域間に位置するダイシングラインを有し、かつガラス入りエポキシ基板から成る配線基板を準備する工程と、
(b)前記(a)工程の後、前記配線基板の前記複数のデバイス領域に複数の半導体チップをそれぞれ搭載する工程と、
(c)前記(b)工程の後、エポキシ樹脂から成り、かつ前記配線基板の前記主面上に前記複数の半導体チップを一括して覆う封止部を形成する工程と、
(d)前記(c)工程の後、前記複数のデバイス領域のそれぞれに対応するように、前記配線基板の前記裏面に複数の外部端子を取り付ける工程と、
(e)前記(d)工程の後、前記複数のデバイス領域にそれぞれ対応する複数の吸引孔、および前記ダイシングラインに対応する溝を有する支持部に、前記封止部が形成された前記配線基板を配置する工程と、
(f)前記(e)工程の後、前記複数の吸引孔を介して前記封止部の表面を吸着支持した状態で、前記配線基板の前記裏面側から前記ダイシングラインに沿って、V字型の刃先を有する回転刃の前記刃先が前記封止部の前記表面から露出するように、前記回転刃を押し付けながら走行させることで前記封止部及び前記配線基板を分割する工程と、
を含み、
前記(e)工程では、前記封止部の前記表面が前記支持部と対向し、かつ前記支持部に設けられた前記複数の吸引孔及び前記溝が前記配線基板の前記複数のデバイス領域及び前記ダイシングラインとそれぞれ対応するように、前記配線基板は前記支持部に配置され、
前記(f)工程で使用する前記回転刃の側面には、前記配線基板の前記裏面に対して20度以上、かつ40度以下の範囲からなるテーパが設けられていること特徴とする半導体装置の製造方法。 - 請求項1において、
(g)前記(b)工程の後で、かつ前記(c)工程の前に、前記複数の半導体チップと前記複数のデバイス領域における接続端子とを複数のワイヤを介して電気的に接続する工程、
をさらに含んでいること特徴とする半導体装置の製造方法。 - 請求項1において、
前記(d)工程において取り付けられる前記複数の外部端子のそれぞれは、ボール電極であることを特徴とする半導体装置の製造方法。
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JP2004134434A JP4489492B2 (ja) | 2004-04-28 | 2004-04-28 | 半導体装置の製造方法 |
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JP2004134434A JP4489492B2 (ja) | 2004-04-28 | 2004-04-28 | 半導体装置の製造方法 |
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JP2005317799A JP2005317799A (ja) | 2005-11-10 |
JP4489492B2 true JP4489492B2 (ja) | 2010-06-23 |
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Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2006351908A (ja) * | 2005-06-17 | 2006-12-28 | Renesas Technology Corp | 半導体装置の製造方法 |
JP4846411B2 (ja) * | 2006-03-30 | 2011-12-28 | 株式会社ディスコ | 半導体パッケージ用治具 |
JP2011119535A (ja) * | 2009-12-04 | 2011-06-16 | Renesas Electronics Corp | 半導体製造装置及び半導体装置の製造方法 |
CN107527554B (zh) * | 2017-08-23 | 2020-12-11 | 京东方科技集团股份有限公司 | 柔性显示面板及其制备方法、柔性显示装置 |
CN108511329B (zh) * | 2018-06-15 | 2024-03-15 | 德阳帛汉电子有限公司 | 一种芯片清洗装置 |
CN113488406B (zh) * | 2021-06-09 | 2024-02-20 | 江苏京创先进电子科技有限公司 | 一种规则封装片的自动识别方法、切割方法及划片机 |
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