US20050282375A1 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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Publication number
US20050282375A1
US20050282375A1 US11/152,790 US15279005A US2005282375A1 US 20050282375 A1 US20050282375 A1 US 20050282375A1 US 15279005 A US15279005 A US 15279005A US 2005282375 A1 US2005282375 A1 US 2005282375A1
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region
semiconductor device
prescribed
layer
impurity
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Tetsuya Nitta
Takayuki Igarashi
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Renesas Technology Corp
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Renesas Technology Corp
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Assigned to RENESAS TECHNOLOGY CORP. reassignment RENESAS TECHNOLOGY CORP. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: IGARASHI, TAKAYUKI, NITTA, TETSUYA
Publication of US20050282375A1 publication Critical patent/US20050282375A1/en
Priority to US12/401,889 priority Critical patent/US8030730B2/en
Priority to US13/095,352 priority patent/US20110198726A1/en
Abandoned legal-status Critical Current

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Definitions

  • the present invention relates to a semiconductor device and manufacturing method thereof and, more specifically, to a semiconductor device having a trench isolation structure and a method of manufacturing the same.
  • an isolation structure for electrically separating elements from each other is necessary, in order to avoid electrical influence between elements.
  • trench isolation has been known as a superior method of element isolation to attain higher degree of integration, as it requires relatively small area for separating elements.
  • An isolation structure having a combination of an SOI (Silicon On Insulator) substrate and the trench isolation has been highly appreciated as one element can fully be isolated from another element electrically so that parasitic operation between elements can be suppressed.
  • An example of a semiconductor device using such an SOI substrate will be described.
  • An N ⁇ layer is formed on a silicon semiconductor substrate with a BOX (Buried OXide Layer) layer interposed.
  • BOX Buried OXide Layer
  • an element forming region is formed, and a trench isolation region is formed for separating elements.
  • an n channel type MOS (Metal Oxide Semiconductor) transistor including a source, drain, gate and a body is formed as a semiconductor element.
  • MOS Metal Oxide Semiconductor
  • semiconductor devices described in Japanese Patent Laying-Open Nos. 2001-044437 and 2003-197639 semiconductor devices having a P type region formed to be in contact with the trench isolation region are proposed.
  • the conventional semiconductor devices using an SOI substrate are structured as described above.
  • the N ⁇ layer in the element forming region is in contact with the trench isolation region, and therefore, when the MOS transistor is off, an electric field reaches the trench isolation region. Therefore, in order to prevent decrease in main breakdown voltage of the MOS transistor caused by electric field concentration near the trench isolation region, it has been necessary to ensure a sufficient distance between the P type impurity region as the body of the MOS transistor formed in the element forming region and the trench isolation region. As a result, the element forming region comes to occupy a large area.
  • the MOS transistor When the MOS transistor is off, the electric field reaches even the inside of the trench isolation region, possibly eroding reliability over a long period dependent on the material of the trench isolation region.
  • a P type inverted layer may be formed on an upper surface of the BOX layer.
  • formation of the inverted layer delays in a high speed operation, undesirably decreasing the switching speed.
  • the P type region formed to be in contact with the trench isolation region is connected to two or more different electrode terminals. Therefore, it is impossible to control the electric field in the element forming region, and therefore, there has been a limit in improving the performance of trench isolation.
  • the present invention was made to solve the above-described problems, and its object is to provide a semiconductor device that enables reliable electrical isolation without increasing the area occupied by the element forming region, and another object is to provide a method of manufacturing such a semiconductor device.
  • the present invention provides a semiconductor device that includes an insulating film, a semiconductor layer of a first conductivity type, an isolating region, and a first impurity region of a second conductivity type.
  • the insulating film is formed on a main surface of a prescribed substrate.
  • the semiconductor layer of the first conductivity type is formed on the insulating film.
  • the isolating region continuously surrounds a prescribed region to be the element forming region in the semiconductor layer, is formed over the surface of the semiconductor layer to the surface of the insulating film, and has an inner sidewall and an outer sidewall.
  • the first impurity region of the second conductivity type is formed continuously to be in contact with the entire surface of the inner sidewall of the isolating region, and positioned between the isolating region and that portion of the semiconductor layer which is positioned at the prescribed region.
  • the present invention provides a method of manufacturing a semiconductor device including the following steps. On a semiconductor layer of a first conductivity type formed on a prescribed substrate with an insulating film interposed, a trench is formed to continuously surround a region to be the element forming region and to expose a surface of the insulating film. On an entire surface of that portion of the semiconductor layer exposed in the trench, which is at least on the side where the prescribed region is positioned, an impurity of a second conductivity type is introduced, so as to form a first impurity region of the second conductivity type. Thereafter, the trench is filled with an insulating material.
  • the first impurity region is formed continuously to be in contact with the entire surface of the inner sidewall of the isolating region. Therefore, the isolating region is electrically isolated by the PN junction between that portion of the semiconductor layer which is positioned in the prescribed region and the first impurity region. As a result, reliability of electric isolation can be enhanced without increasing the area of the element forming region.
  • the first impurity region of the second conductivity type is formed on the entire surface of that portion of the semiconductor layer which is on the side of the prescribed region. Therefore, a PN junction is formed at the interface between that portion of the semiconductor layer and the first impurity region, and thus, a structure for electrical isolation can easily be formed.
  • FIG. 1 is a plan view of a semiconductor device in accordance with a first embodiment of the present invention.
  • FIG. 2 is a cross-sectional view taken along the line II-II of FIG. 1 , in accordance with the same embodiment.
  • FIG. 3 is a plan view of a semiconductor device as a comparative example of the embodiment.
  • FIG. 4 is a cross-sectional view taken along the line IV-IV of FIG. 3 .
  • FIG. 5 is a plan view of a semiconductor device in accordance with a second embodiment of the present invention.
  • FIG. 6 is a cross-sectional view taken along the line VI-VI of FIG. 5 .
  • FIG. 7 is a plan view of a semiconductor device in accordance with a third embodiment of the present invention.
  • FIG. 8 is a plan view of a semiconductor device in accordance with a fourth embodiment of the present invention.
  • FIG. 9 is a plan view of a semiconductor device in accordance with a fifth embodiment of the present invention.
  • FIG. 10 is a plan view of a semiconductor device in accordance with a sixth embodiment of the present invention.
  • FIG. 11 is a plan view of a semiconductor device in accordance with a seventh embodiment of the present invention.
  • FIG. 12 is a plan view of a semiconductor device in accordance with an eighth embodiment of the present invention.
  • FIG. 13 shows results of simulation of potential distribution and extension of depletion layer in the element forming region in the semiconductor devices in accordance with various embodiments of the present invention.
  • FIG. 14 is a partial sectional view showing a step of manufacturing the semiconductor device in accordance with an eleventh embodiment of the present invention.
  • FIG. 15 is a cross-sectional view showing the step following the step shown in FIG. 14 .
  • FIG. 16 is a cross-sectional view showing the step following the step shown in FIG. 15 .
  • FIG. 17 is a cross-sectional view showing the step following the step shown in FIG. 16 .
  • FIG. 18 is a cross-sectional view showing the step following the step shown in FIG. 17 .
  • FIG. 19 is a cross-sectional view of a semiconductor device in accordance with a twelfth embodiment of the present invention.
  • FIG. 20 is a cross-sectional view of a semiconductor device in accordance with a first modification of the twelfth embodiment.
  • FIG. 21 is a cross-sectional view of a semiconductor device in accordance with a second modification of the twelfth embodiment.
  • FIG. 22 is a cross-sectional view of a semiconductor device in accordance with a thirteenth embodiment of the present invention.
  • FIG. 23 is a cross-sectional view of a semiconductor device in accordance with a first modification of the thirteenth embodiment.
  • FIG. 24 is a cross-sectional view of a semiconductor device in accordance with a second modification of the thirteenth embodiment.
  • a semiconductor device in accordance with a first embodiment of the present invention will be described.
  • a BOX layer 2 is formed on a semiconductor substrate 1 .
  • an N ⁇ layer 3 of, for example, an epitaxial layer is formed on BOX layer 2 .
  • a trench isolation region 4 is formed to surround that portion (N ⁇ layer 3 a ) of N ⁇ layer 3 which will be the element forming region.
  • Trench isolation region 4 is formed from the surface of N ⁇ layer 3 to reach BOX layer 2 . Outside the trench isolation region 4 , N ⁇ layer 3 b is positioned, which will be another element forming region.
  • an insulating film 15 such as a silicon oxide film, is formed on N ⁇ layer 3 .
  • a P type diffusion region 10 a is formed between trench isolation region 4 and N ⁇ layer 3 .
  • P type diffusion region 10 a is formed continuously without any interruption, to be in contact with the entire surface of an inner sidewall of trench isolation region 4 surrounding the element forming region.
  • a semiconductor element such as a transistor or a diode, is formed, as will be described later.
  • P type diffusion region 10 a is formed continuously without any interruption to be in contact with the entire surface of the inner sidewall of trench isolation region 4 . Therefore, trench isolation region 4 is electrically isolated by the PN junction of N ⁇ layer 3 a and P type diffusion region 10 a.
  • the present semiconductor device can enhance electric isolation. This will be discussed more specifically in the following.
  • an N ⁇ layer 103 is formed on a semiconductor substrate 101 with a BOX layer 102 interposed.
  • a trench isolation region 104 is formed to surround that portion (N ⁇ layer 103 a ) of N ⁇ layer 103 which will be the element forming region. Outside the trench isolation region 104 , an N ⁇ layer 103 b to be another element forming region is positioned.
  • an insulating film 115 is formed on N ⁇ layer 103 .
  • P type diffusion regions 110 a and 110 b are formed respectively, between trench isolation region 104 and N ⁇ layer 103 a.
  • An electrode 120 is electrically connected to P type diffusion region 110 a
  • an electrode 121 is electrically connected to P type diffusion region 110 b.
  • P type diffusion region 110 a will be the drain region and P type diffusion region 110 b will be the source region.
  • Electrode 120 will be the drain electrode, and electrode 121 will be the source electrode.
  • the drain region and the source region make operations different from each other, and therefore, the potentials in the drain region and the source region are different. For this reason, the P type diffusion regions 110 a and 110 b are not continuous but separated by a distance, and they are not electrically connected.
  • P type diffusion regions 110 a and 110 b have mutually different potentials. Therefore, it is difficult to control an electric field inside the element isolating region 104 , and hence, electrical isolation attained by element isolation region 104 has been limited.
  • P type diffusion region 10 a is formed continuously, to be in contact with the entire surface of the inner sidewall of trench isolation region 4 . Therefore, the potential of P type diffusion region 10 a is always the same. Accordingly, the potential of the inner sidewall that is in contact with P type diffusion region 10 a is also kept at the same potential, improving the electrical isolation characteristic.
  • the P type diffusion region is formed along the inner sidewall of the trench isolation region.
  • P type diffusion regions are formed to be in contact with the entire surfaces of inner and outer sidewalls of the trench isolation region.
  • P type diffusion region 10 a is formed between trench isolation region 4 and N ⁇ layer 3 a .
  • P type diffusion region 10 a is formed continuously without any interruption to be in contact with the entire surface of the inner sidewall of trench isolation region 4 surrounding the element forming region.
  • P type diffusion region 10 b is formed continuously to be in contact with the entire surface of the outer sidewall of trench isolation region 4 surrounding the element forming region. Except for this point, the semiconductor device is the same as the one described above, and therefore, the same or corresponding portions are denoted by the same reference characters and description thereof will not be repeated.
  • P type diffusion region 10 b is formed between trench isolation region 4 and N ⁇ layer 3 b as another element forming region. Therefore, trench isolation region 4 comes to be electrically isolated not only by the PN junction between N ⁇ layer 3 a and P type diffusion region 10 a but also by the PN junction between N ⁇ layer 3 b and P type diffusion region 10 b. As a result, electrical isolation between N ⁇ layer 3 a and N ⁇ layer 3 b can be made more reliable by the two PN junctions, than in the semiconductor device described above.
  • the potential of P type diffusion region 10 a can be kept at a constant value.
  • the potential of P type diffusion region 10 a can be kept at 0V.
  • FIG. 8 On insulating film 15 , in addition to electrode 20 a to be electrically connected to P type diffusion region 10 a, an electrode 20 b to be connected to P type diffusion region 10 b is formed. Except for this point, the semiconductor device is the same as the one shown in FIG. 6 . Therefore, the same or corresponding portions will be denoted by the same reference characters, and description thereof will not be repeated.
  • the potential of P type diffusion region 10 a can be kept at a constant value
  • the potential of P type diffusion region 10 b can also be kept at a constant value.
  • the potential of P type diffusion region 10 a as well as P type diffusion region 10 b can be kept at 0V.
  • N ⁇ layer 3 a as the element forming region is positioned inside the trench isolation region 4 .
  • N ⁇ layer 3 b as another element forming region is positioned outside the trench isolation region 4 .
  • a P type diffusion region 5 which will be a body, is formed to be connected to P type diffusion region 10 a formed continuously to be in contact with the entire surface of the inner sidewall of trench isolation region 4 .
  • an N+ diffusion region 6 which will be the source, is formed on the surface of P type diffusion region 5 .
  • a conductive film 8 to be the gate is formed, with an insulating film 9 interposed.
  • an N+ diffusion region 7 Spaced apart from P type diffusion region 5 , an N+ diffusion region 7 , which will be the drain, is formed.
  • An insulating film 15 is formed to cover the element forming region.
  • an electrode 20 is formed to be electrically connected to N+ diffusion region 6 .
  • an electrode 21 is formed to be electrically connected to N+ diffusion region 7 .
  • an n channel MOS transistor including N+ diffusion region (source) 6 , N+ diffusion region (drain) 7 , conductive film (gate) 8 and P type diffusion region (body) 5 is formed.
  • the body is also referred to as a well or a back gate, where a channel is formed and the breakdown voltage is held, in an MOS transistor.
  • P type diffusion region 5 to be the body is connected to P type diffusion region 10 formed continuously to be in contact with the entire surface of the inner sidewall of trench isolation region 4 , so that P type diffusion region 10 a comes to have a structure that includes P type diffusion region 5 . Therefore, it becomes unnecessary to keep a distance between element isolation region 4 and P type diffusion region 5 , and the increase of the area occupied by the element forming region can be suppressed.
  • trench isolation region 4 is electrically isolated from N ⁇ layer 3 , as P type diffusion region 10 is positioned between trench isolation region 4 and N ⁇ layer 3 . Therefore, when the impurity concentration of P type diffusion region 10 is sufficiently high, for example, 1 ⁇ 10 17 cm ⁇ 3 or higher, it is possible to prevent the depletion layer from reaching trench isolation region 4 even when the transistor is off and a high voltage acts between the source and drain. Thus, a high electric field does not affect trench isolation region 4 , and hence, long time reliability of the semiconductor device can be improved.
  • an upper surface of BOX layer 2 is connected to P type diffusion region 5 to be the body, with P type diffusion region 10 interposed. Therefore, even when a high voltage is applied to N+ diffusion region 7 to be the drain and a P type channel layer is formed near the upper surface of BOX layer 2 , holes to form the P type channel layer can be supplied quickly. As a result, speed of operation of the n channel type MOS transistor is improved and the performance of the semiconductor device can be improved.
  • a p channel MOS transistor will be described as an example of the semiconductor element formed in the element forming region.
  • a P type diffusion region 5 to be the drain is formed to be connected to P type diffusion region 10 a , formed continuously to be in contact with the entire surface of the inner sidewall of trench isolation region 4 .
  • N type diffusion region 7 to be the body Adjacent to P type diffusion region 5 , an N type diffusion region 7 to be the body is formed. On the surface of N type diffusion region 7 , a P+ diffusion region 1 to be the source is formed. On a portion of N type diffusion region 7 sandwiched between P+ diffusion region 11 and P type diffusion region 5 , a conductive film 8 to be the gate is formed, with an insulating film 9 interposed.
  • An insulating film 15 is formed to cover the element forming region. On insulating film 15 , an electrode 20 is formed to be electrically connected to P+ diffusion region 5 . Further, an electrode 21 to be electrically connected to P+ diffusion region 11 is formed.
  • a p channel type MOS transistor including P+ diffusion region (source) 11 , P+ diffusion region (drain) 5 , a conductive film (gate) 8 and N type diffusion region (body) 7 is formed.
  • P type diffusion region 10 a formed continuously to be in contact with the entire surface of the inner sidewall of trench isolation region 4 is a part of P type diffusion region 5 . Therefore, it is unnecessary to keep a distance between element forming region 4 and P type diffusion region 5 , and therefore, increase of the area occupied by the element forming region can be suppressed.
  • trench isolation region 4 is electrically isolated from N ⁇ layer 3 as the P type diffusion region 10 is positioned between trench isolation region 4 and N ⁇ layer 3 . Therefore, a high electric field does not act on trench isolation region 4 , and hence, reliability of the semiconductor device over a long time can be improved.
  • a diode will be described as a semiconductor element formed in the element forming region.
  • a P type diffusion region 5 to be an anode is formed to be connected to P type diffusion region 10 a formed continuously to be in contact with the entire surface of the inner sidewall of trench isolation region 4 .
  • an N type diffusion region 7 to be a cathode is formed.
  • An insulating film 15 is formed to cover the element forming region.
  • an electrode 20 to be electrically connected to P+ diffusion region 5 is formed.
  • an electrode 21 to be electrically connected to N type diffusion region 7 is formed.
  • a diode of high breakdown voltage is formed, which includes a P+ diffusion region (anode) 5 and N type diffusion region (cathode) 7 .
  • the P type diffusion region 10 a formed continuously to be in contact with the entire surface of the inner sidewall of trench isolation region 4 is a part of P type diffusion region 5 to be the anode, and therefore, it is unnecessary to keep a distance between element isolating region 4 and P type diffusion region 5 . Therefore, increase of the area occupied by the element forming region can be suppressed.
  • trench isolation region 4 is electrically isolated from N ⁇ layer 3 as the P type diffusion region 10 is positioned between trench isolation region 4 and N ⁇ layer 3 . Therefore, a high electric field does not act on trench isolation region 4 , and hence, reliability of the semiconductor device over a long time can be improved.
  • a bipolar transistor will be described as an example of a semiconductor element formed in the element forming region.
  • a P type diffusion region 5 to be the base is formed to be connected to P type diffusion region 10 a formed continuously to be in contact with the entire surface of the inner sidewall of trench isolation region 4 .
  • an N+ diffusion region 6 to be the emitter is formed on a surface of P type diffusion region 5 .
  • an N type diffusion region 7 to be the collector is formed.
  • An insulating film 15 is formed to cover the element forming region. On insulating film 15 , an electrode 21 is formed to be electrically connected to P+ diffusion region 5 . Further, an electrode to be electrically connected to N+ diffusion region 6 is formed. Further, an electrode 22 to be electrically connected to N type diffusion region 7 is formed.
  • a bipolar transistor of high breakdown voltage is formed, which includes N+ diffusion region (emitter) 6 , P+ diffusion region (base) 5 , and N type diffusion region (collector) 7 .
  • the P type diffusion region 10 a formed continuously to be in contact with the entire surface of the inner sidewall of trench isolation region 4 is a part of P type diffusion region 5 to be the base, and therefore, it is unnecessary to keep a distance between element isolating region 4 and P type diffusion region 5 . Therefore, increase of the area occupied by the element forming region can be suppressed.
  • trench isolation region 4 is electrically isolated from N ⁇ layer 3 as the P type diffusion region 10 is positioned between trench isolation region 4 and N ⁇ layer 3 . Therefore, a high electric field does not act on trench isolation region 4 , and hence, reliability of the semiconductor device over a long time can be improved.
  • P type diffusion region 10 formed along the inner sidewall of trench isolation region 4 has relatively low impurity concentration, the P type diffusion region may be depleted and the electric field may possibly reach the inside of trench isolation region 4 . In that case, it is difficult to maintain reliability of the semiconductor device for a long time.
  • P type diffusion regions 10 a and 10 b have sufficiently high impurity concentrations, and therefore, even when a high voltage is applied to the semiconductor device formed in the element forming region, the depletion layer formed in the N ⁇ layer 3 a cannot reach the trench isolation region. As a result, no electric field is generated inside the trench isolation region 4 , and long time reliability of the semiconductor device can be improved.
  • FIG. 13 equipotential distribution and reach of depletion layer are plotted, where the initial conditions of simulation are as follows. Source potential: 0V, gate potential: 0V, substrate potential: 0V, and about 180 V is applied to the drain.
  • the impurity concentration of P type diffusion region 10 a is set to be at least 1 ⁇ 10 17 cm 3 .
  • crystal defects tend to generate because of damages experienced at the time of forming the trench, or stress experienced when the trench isolation region is filled with an insulating material.
  • An electric field generated at such a portion having crystal defect possibly causes a leakage current.
  • P type diffusion region 10 a formed continuously to be in contact with the inner sidewall of the trench isolation region has sufficiently high impurity concentration, and therefore, electric field does not reach trench isolation region 4 . Therefore, even when a crystal defect generates near trench isolation region 4 , generation of leakage current can be prevented.
  • P type diffusion region 10 a is formed continuously to be in contact with the entire surface of the inner sidewall of trench isolation region.
  • the impurity concentration of P type diffusion region 10 a must be made higher than the impurity concentration of each of the diffusion regions forming the element.
  • diffusion regions forming the element mean substantial diffusion regions forming the element and do not include regions having relatively high impurity concentration intended to attain electrical connection with the electrode.
  • an N ⁇ layer 3 is formed to the thickness of 5 ⁇ m with a BOX layer 2 having the thickness of about 1 ⁇ m interposed, whereby a substrate (SOI substrate) is prepared.
  • a mask material 30 such as a silicon oxide film, having the thickness of about 500 nm is formed.
  • N ⁇ layer 3 is subjected to anisotropic etching, so that a trench 31 having the width of about 1 ⁇ m is formed, exposing the surface of BOX layer 2 .
  • Trench 31 is formed continuously to surround a portion to be the element forming region.
  • boron is introduced by oblique ion implantation, with the dosage of 1 ⁇ 10 13 cm ⁇ 2 to 1 ⁇ 10 15 cm ⁇ 2 at an angle of at most 10 degrees, whereby a P type diffusion region 10 a is formed.
  • ion implantation is performed under the same condition, so that a P type diffusion region 10 b is formed.
  • FIGS. 16 and 17 an example has been described in which P type diffusion regions 10 a and 10 b are formed on the inner and outer sidewalls of trench 31 , on one cross section of a semiconductor device. It is noted, however, that trench 31 is formed to surround the element forming region, as shown, for example, in FIG. 1 . Therefore, oblique ion implantation must be repeated until ions are introduced to all the portions on the outer sidewall and inner sidewall exposed in trench 31 formed to surround the element forming region.
  • mask material 30 used for forming trench 31 may be used as a mask for ion implantation. After the end of ion implantation, mask material 30 is removed.
  • a silicon oxide film or the like is filled in trench 31 , so that trench isolation region 4 is formed.
  • a desired semiconductor element such as an MOS transistor is formed (not shown), and the semiconductor device is completed.
  • P type diffusion regions 10 a and 10 b are formed continuously along the inner sidewall and outer sidewall of trench isolation region 4 , respectively. Therefore, trench isolation region 4 is electrically isolated not only by the PN junction between N ⁇ layer 3 a and P type diffusion region 10 a but also by the PN junction between N ⁇ layer 3 b and P type diffusion region 10 b. As a result, electrical isolation between N ⁇ layer 3 a as one element forming region and N ⁇ layer 3 b as another element forming region can be made more reliable.
  • the impurity concentration of P type diffusion regions 10 a and 10 b must be made higher than the impurity concentrations of diffusion regions forming the element.
  • the condition for implantation is set such that the impurity concentration of P type diffusion regions 10 a and 10 b becomes higher than the impurity concentration of the diffusion regions forming the element.
  • P type diffusion region 10 a and the like are not fully depleted.
  • the diffusion regions forming the element do not include any region having a relatively high impurity concentration for attaining electrical contact with the electrode.
  • the N type diffusion region formed to be in contact with the inner sidewall of the trench isolation region includes a diffusion region to be a cathode in the case of a diode, and a diffusion region to be a collector in the case of a bipolar transistor.
  • CMOS transistor will be described as an example, in which an n channel MOS transistor and a P channel MOS transistor are formed as semiconductor elements formed in the element forming region of the semiconductor device having the P type diffusion regions formed in contact with both the inner and outer sidewalls of the trench isolation region.
  • a P type well region 60 and an N type well region 61 are formed, respectively.
  • an insulating film 11 is formed to expose P type well region 60 and N type well region 61 .
  • N type source/drain regions 62 and 63 are formed spaced apart by a prescribed distance from each other.
  • a gate electrode 68 is formed, with a gate insulating film 66 interposed.
  • N type well 61 In exposed N type well 61 , P type source/drain regions 64 and 65 are formed spaced apart by a prescribed distance from each other. On that region of N type well region 61 which is sandwiched between the source/drain regions 64 and 65 , a gate electrode 69 is formed, with a gate insulating film 67 interposed. By P type source/drain regions 64 , 65 and the gate electrode 69 , a p channel MOS transistor is formed.
  • P type well region 60 is continuous from P type diffusion region 10 a , and is electrically connected to P type diffusion region 10 a.
  • a P+ diffusion region 80 is formed, and to P+ diffusion region 80 , an electrode 75 for fixing the P type well region 60 and P type diffusion region 10 a to a prescribed potential is connected.
  • the N type well region 61 a prescribed region and an electrode connected to the prescribed region (both not shown) are formed to fix the N type well region 61 to a prescribed potential. Except for these points, the structure is the same as that shown in FIG. 9 or 10 , and therefore, same portions are denoted by the same reference characters and description thereof will not be repeated.
  • P type well region 60 is electrically isolated from P type diffusion region 10 a, that is, P type well region 60 a , by N type well region 61 . More specifically, side portions of P type well 60 are surrounded by N type well region 61 , and N ⁇ layer 3 a is positioned at the bottom of P type well 60 .
  • An electrode (not shown) for fixing the P type well region 60 to a prescribed potential is formed in P type well region 60
  • an electrode (not shown) for fixing N type well region 61 to a prescribed potential is also formed in N type well region 61 .
  • P type well region 60 is not electrically connected to P type diffusion region 10 a, and therefore, it can be fixed to a prescribed potential independent from the potential of P type diffusion region 10 a.
  • a semiconductor device in which potentials of the P type well region, N type well region and P type diffusion region can be set independently, will specifically be described. Referring to FIG. 21 , in P type well region 60 , P+ diffusion region 81 is formed, and in N type well region 61 , N+ diffusion region 82 is formed. In P type well region 60 a that is connected to P type diffusion region 10 a, a P+ diffusion region 80 is formed.
  • an electrode 76 for fixing P type well region 60 to a prescribed potential is connected; to N+ diffusion region 82 , an electrode 77 for fixing N type well region 61 to a prescribed potential is connected; and to P+ diffusion region 80 , an electrode 75 for fixing P type diffusion region 10 a to a prescribed potential is connected.
  • CMOS transistor is formed as the semiconductor element in the element forming region.
  • trench isolation region 4 is electrically isolated from N ⁇ layer 3 as there is P type diffusion region 10 a between trench isolation region 4 and N ⁇ layer 3 , and therefore, high electric field does not affect trench isolation region 4 . Therefore, reliability of the semiconductor device over a long time can be improved.
  • a flash memory element will be described as an example of a semiconductor element formed in the element forming region of the semiconductor device in which the P type diffusion regions are formed to be in contact with the inner and outer sidewalls of the trench isolation region.
  • a P type well region 60 is formed at the surface of N ⁇ layer 3 a surrounded by P type diffusion region 10 a and in the vicinity thereof.
  • an insulating film 11 is formed to expose a surface of P type well region 60 .
  • N type source/drain regions 62 and 63 are formed spaced by a prescribed distance from each other.
  • a gate electrode portion 70 is formed, with a gate insulating film 66 interposed.
  • Gate electrode 70 is formed to have a lower electrode 70 a formed on gate insulating film 66 , a dielectric film 70 b formed on lower electrode 70 a , and an upper electrode 70 c formed on dielectric film 70 b.
  • P type well region 60 is continuous from P type diffusion region 10 a, and is electrically connected to P type diffusion region 10 a.
  • P+ diffusion region 80 is formed, and to P+ diffusion region 80 , an electrode 75 for fixing P type well region 60 and P type diffusion region 10 a to a prescribed potential is connected.
  • P type well region 60 is continuous from P type diffusion region 10 a.
  • P type well 60 is not continuous from P type diffusion region 10 a and electrically isolated therefrom will be described.
  • P type well 60 is electrically isolated from P type diffusion region 10 a and P type well region 60 a , by N type well 61 . Specifically, side portions of P type well region 60 are surrounded by N type well region 61 , and at the bottom of P type well region 60 , N ⁇ layer 3 a is positioned. In P type well region 60 , P+ diffusion region 81 is formed, and to P+ diffusion region 81 , an electrode 76 is connected for fixing P type well region 60 to a prescribed potential.
  • P type well region 60 is not electrically connected to P type diffusion region 10 a, and by electrode 76 , it can be fixed to a prescribed potential independently from the potential of P type diffusion region 10 a.
  • P+ diffusion region 81 is formed, and in P type well region 60 continuous from P type diffusion region 10 a, P+ diffusion region 80 is formed.
  • an electrode 76 for fixing P type well region 60 to a prescribed potential is connected, and to P+ diffusion region 80 , an electrode 75 for fixing P type diffusion region 10 a to a prescribed potential is connected.
  • N type well 61 can also be fixed at a prescribed potential.
  • a flash memory element is formed as a semiconductor element in the element forming region.
  • trench isolation region 4 is electrically isolated from N ⁇ layer 3 as the P type diffusion region 10 is positioned between trench isolation region 4 and N ⁇ layer 3 . Therefore, high electric field does not affect trench isolation region 4 , and reliability of the semiconductor device over a long time can be improved.

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