US20050282375A1 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
- Publication number
- US20050282375A1 US20050282375A1 US11/152,790 US15279005A US2005282375A1 US 20050282375 A1 US20050282375 A1 US 20050282375A1 US 15279005 A US15279005 A US 15279005A US 2005282375 A1 US2005282375 A1 US 2005282375A1
- Authority
- US
- United States
- Prior art keywords
- region
- semiconductor device
- prescribed
- layer
- impurity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 145
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 238000002955 isolation Methods 0.000 claims abstract description 120
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 239000012535 impurity Substances 0.000 claims description 47
- 238000005468 ion implantation Methods 0.000 claims description 7
- 239000011810 insulating material Substances 0.000 claims description 3
- 210000000746 body region Anatomy 0.000 claims 3
- 238000009792 diffusion process Methods 0.000 abstract description 189
- 230000005684 electric field Effects 0.000 description 22
- 108091006146 Channels Proteins 0.000 description 14
- 230000004048 modification Effects 0.000 description 14
- 238000012986 modification Methods 0.000 description 14
- 230000015556 catabolic process Effects 0.000 description 10
- 239000000463 material Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000036961 partial effect Effects 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/761—PN junctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76281—Lateral isolation by selective oxidation of silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/7317—Bipolar thin film transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/8611—Planar PN junction diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
Definitions
- the present invention relates to a semiconductor device and manufacturing method thereof and, more specifically, to a semiconductor device having a trench isolation structure and a method of manufacturing the same.
- an isolation structure for electrically separating elements from each other is necessary, in order to avoid electrical influence between elements.
- trench isolation has been known as a superior method of element isolation to attain higher degree of integration, as it requires relatively small area for separating elements.
- An isolation structure having a combination of an SOI (Silicon On Insulator) substrate and the trench isolation has been highly appreciated as one element can fully be isolated from another element electrically so that parasitic operation between elements can be suppressed.
- An example of a semiconductor device using such an SOI substrate will be described.
- An N ⁇ layer is formed on a silicon semiconductor substrate with a BOX (Buried OXide Layer) layer interposed.
- BOX Buried OXide Layer
- an element forming region is formed, and a trench isolation region is formed for separating elements.
- an n channel type MOS (Metal Oxide Semiconductor) transistor including a source, drain, gate and a body is formed as a semiconductor element.
- MOS Metal Oxide Semiconductor
- semiconductor devices described in Japanese Patent Laying-Open Nos. 2001-044437 and 2003-197639 semiconductor devices having a P type region formed to be in contact with the trench isolation region are proposed.
- the conventional semiconductor devices using an SOI substrate are structured as described above.
- the N ⁇ layer in the element forming region is in contact with the trench isolation region, and therefore, when the MOS transistor is off, an electric field reaches the trench isolation region. Therefore, in order to prevent decrease in main breakdown voltage of the MOS transistor caused by electric field concentration near the trench isolation region, it has been necessary to ensure a sufficient distance between the P type impurity region as the body of the MOS transistor formed in the element forming region and the trench isolation region. As a result, the element forming region comes to occupy a large area.
- the MOS transistor When the MOS transistor is off, the electric field reaches even the inside of the trench isolation region, possibly eroding reliability over a long period dependent on the material of the trench isolation region.
- a P type inverted layer may be formed on an upper surface of the BOX layer.
- formation of the inverted layer delays in a high speed operation, undesirably decreasing the switching speed.
- the P type region formed to be in contact with the trench isolation region is connected to two or more different electrode terminals. Therefore, it is impossible to control the electric field in the element forming region, and therefore, there has been a limit in improving the performance of trench isolation.
- the present invention was made to solve the above-described problems, and its object is to provide a semiconductor device that enables reliable electrical isolation without increasing the area occupied by the element forming region, and another object is to provide a method of manufacturing such a semiconductor device.
- the present invention provides a semiconductor device that includes an insulating film, a semiconductor layer of a first conductivity type, an isolating region, and a first impurity region of a second conductivity type.
- the insulating film is formed on a main surface of a prescribed substrate.
- the semiconductor layer of the first conductivity type is formed on the insulating film.
- the isolating region continuously surrounds a prescribed region to be the element forming region in the semiconductor layer, is formed over the surface of the semiconductor layer to the surface of the insulating film, and has an inner sidewall and an outer sidewall.
- the first impurity region of the second conductivity type is formed continuously to be in contact with the entire surface of the inner sidewall of the isolating region, and positioned between the isolating region and that portion of the semiconductor layer which is positioned at the prescribed region.
- the present invention provides a method of manufacturing a semiconductor device including the following steps. On a semiconductor layer of a first conductivity type formed on a prescribed substrate with an insulating film interposed, a trench is formed to continuously surround a region to be the element forming region and to expose a surface of the insulating film. On an entire surface of that portion of the semiconductor layer exposed in the trench, which is at least on the side where the prescribed region is positioned, an impurity of a second conductivity type is introduced, so as to form a first impurity region of the second conductivity type. Thereafter, the trench is filled with an insulating material.
- the first impurity region is formed continuously to be in contact with the entire surface of the inner sidewall of the isolating region. Therefore, the isolating region is electrically isolated by the PN junction between that portion of the semiconductor layer which is positioned in the prescribed region and the first impurity region. As a result, reliability of electric isolation can be enhanced without increasing the area of the element forming region.
- the first impurity region of the second conductivity type is formed on the entire surface of that portion of the semiconductor layer which is on the side of the prescribed region. Therefore, a PN junction is formed at the interface between that portion of the semiconductor layer and the first impurity region, and thus, a structure for electrical isolation can easily be formed.
- FIG. 1 is a plan view of a semiconductor device in accordance with a first embodiment of the present invention.
- FIG. 2 is a cross-sectional view taken along the line II-II of FIG. 1 , in accordance with the same embodiment.
- FIG. 3 is a plan view of a semiconductor device as a comparative example of the embodiment.
- FIG. 4 is a cross-sectional view taken along the line IV-IV of FIG. 3 .
- FIG. 5 is a plan view of a semiconductor device in accordance with a second embodiment of the present invention.
- FIG. 6 is a cross-sectional view taken along the line VI-VI of FIG. 5 .
- FIG. 7 is a plan view of a semiconductor device in accordance with a third embodiment of the present invention.
- FIG. 8 is a plan view of a semiconductor device in accordance with a fourth embodiment of the present invention.
- FIG. 9 is a plan view of a semiconductor device in accordance with a fifth embodiment of the present invention.
- FIG. 10 is a plan view of a semiconductor device in accordance with a sixth embodiment of the present invention.
- FIG. 11 is a plan view of a semiconductor device in accordance with a seventh embodiment of the present invention.
- FIG. 12 is a plan view of a semiconductor device in accordance with an eighth embodiment of the present invention.
- FIG. 13 shows results of simulation of potential distribution and extension of depletion layer in the element forming region in the semiconductor devices in accordance with various embodiments of the present invention.
- FIG. 14 is a partial sectional view showing a step of manufacturing the semiconductor device in accordance with an eleventh embodiment of the present invention.
- FIG. 15 is a cross-sectional view showing the step following the step shown in FIG. 14 .
- FIG. 16 is a cross-sectional view showing the step following the step shown in FIG. 15 .
- FIG. 17 is a cross-sectional view showing the step following the step shown in FIG. 16 .
- FIG. 18 is a cross-sectional view showing the step following the step shown in FIG. 17 .
- FIG. 19 is a cross-sectional view of a semiconductor device in accordance with a twelfth embodiment of the present invention.
- FIG. 20 is a cross-sectional view of a semiconductor device in accordance with a first modification of the twelfth embodiment.
- FIG. 21 is a cross-sectional view of a semiconductor device in accordance with a second modification of the twelfth embodiment.
- FIG. 22 is a cross-sectional view of a semiconductor device in accordance with a thirteenth embodiment of the present invention.
- FIG. 23 is a cross-sectional view of a semiconductor device in accordance with a first modification of the thirteenth embodiment.
- FIG. 24 is a cross-sectional view of a semiconductor device in accordance with a second modification of the thirteenth embodiment.
- a semiconductor device in accordance with a first embodiment of the present invention will be described.
- a BOX layer 2 is formed on a semiconductor substrate 1 .
- an N ⁇ layer 3 of, for example, an epitaxial layer is formed on BOX layer 2 .
- a trench isolation region 4 is formed to surround that portion (N ⁇ layer 3 a ) of N ⁇ layer 3 which will be the element forming region.
- Trench isolation region 4 is formed from the surface of N ⁇ layer 3 to reach BOX layer 2 . Outside the trench isolation region 4 , N ⁇ layer 3 b is positioned, which will be another element forming region.
- an insulating film 15 such as a silicon oxide film, is formed on N ⁇ layer 3 .
- a P type diffusion region 10 a is formed between trench isolation region 4 and N ⁇ layer 3 .
- P type diffusion region 10 a is formed continuously without any interruption, to be in contact with the entire surface of an inner sidewall of trench isolation region 4 surrounding the element forming region.
- a semiconductor element such as a transistor or a diode, is formed, as will be described later.
- P type diffusion region 10 a is formed continuously without any interruption to be in contact with the entire surface of the inner sidewall of trench isolation region 4 . Therefore, trench isolation region 4 is electrically isolated by the PN junction of N ⁇ layer 3 a and P type diffusion region 10 a.
- the present semiconductor device can enhance electric isolation. This will be discussed more specifically in the following.
- an N ⁇ layer 103 is formed on a semiconductor substrate 101 with a BOX layer 102 interposed.
- a trench isolation region 104 is formed to surround that portion (N ⁇ layer 103 a ) of N ⁇ layer 103 which will be the element forming region. Outside the trench isolation region 104 , an N ⁇ layer 103 b to be another element forming region is positioned.
- an insulating film 115 is formed on N ⁇ layer 103 .
- P type diffusion regions 110 a and 110 b are formed respectively, between trench isolation region 104 and N ⁇ layer 103 a.
- An electrode 120 is electrically connected to P type diffusion region 110 a
- an electrode 121 is electrically connected to P type diffusion region 110 b.
- P type diffusion region 110 a will be the drain region and P type diffusion region 110 b will be the source region.
- Electrode 120 will be the drain electrode, and electrode 121 will be the source electrode.
- the drain region and the source region make operations different from each other, and therefore, the potentials in the drain region and the source region are different. For this reason, the P type diffusion regions 110 a and 110 b are not continuous but separated by a distance, and they are not electrically connected.
- P type diffusion regions 110 a and 110 b have mutually different potentials. Therefore, it is difficult to control an electric field inside the element isolating region 104 , and hence, electrical isolation attained by element isolation region 104 has been limited.
- P type diffusion region 10 a is formed continuously, to be in contact with the entire surface of the inner sidewall of trench isolation region 4 . Therefore, the potential of P type diffusion region 10 a is always the same. Accordingly, the potential of the inner sidewall that is in contact with P type diffusion region 10 a is also kept at the same potential, improving the electrical isolation characteristic.
- the P type diffusion region is formed along the inner sidewall of the trench isolation region.
- P type diffusion regions are formed to be in contact with the entire surfaces of inner and outer sidewalls of the trench isolation region.
- P type diffusion region 10 a is formed between trench isolation region 4 and N ⁇ layer 3 a .
- P type diffusion region 10 a is formed continuously without any interruption to be in contact with the entire surface of the inner sidewall of trench isolation region 4 surrounding the element forming region.
- P type diffusion region 10 b is formed continuously to be in contact with the entire surface of the outer sidewall of trench isolation region 4 surrounding the element forming region. Except for this point, the semiconductor device is the same as the one described above, and therefore, the same or corresponding portions are denoted by the same reference characters and description thereof will not be repeated.
- P type diffusion region 10 b is formed between trench isolation region 4 and N ⁇ layer 3 b as another element forming region. Therefore, trench isolation region 4 comes to be electrically isolated not only by the PN junction between N ⁇ layer 3 a and P type diffusion region 10 a but also by the PN junction between N ⁇ layer 3 b and P type diffusion region 10 b. As a result, electrical isolation between N ⁇ layer 3 a and N ⁇ layer 3 b can be made more reliable by the two PN junctions, than in the semiconductor device described above.
- the potential of P type diffusion region 10 a can be kept at a constant value.
- the potential of P type diffusion region 10 a can be kept at 0V.
- FIG. 8 On insulating film 15 , in addition to electrode 20 a to be electrically connected to P type diffusion region 10 a, an electrode 20 b to be connected to P type diffusion region 10 b is formed. Except for this point, the semiconductor device is the same as the one shown in FIG. 6 . Therefore, the same or corresponding portions will be denoted by the same reference characters, and description thereof will not be repeated.
- the potential of P type diffusion region 10 a can be kept at a constant value
- the potential of P type diffusion region 10 b can also be kept at a constant value.
- the potential of P type diffusion region 10 a as well as P type diffusion region 10 b can be kept at 0V.
- N ⁇ layer 3 a as the element forming region is positioned inside the trench isolation region 4 .
- N ⁇ layer 3 b as another element forming region is positioned outside the trench isolation region 4 .
- a P type diffusion region 5 which will be a body, is formed to be connected to P type diffusion region 10 a formed continuously to be in contact with the entire surface of the inner sidewall of trench isolation region 4 .
- an N+ diffusion region 6 which will be the source, is formed on the surface of P type diffusion region 5 .
- a conductive film 8 to be the gate is formed, with an insulating film 9 interposed.
- an N+ diffusion region 7 Spaced apart from P type diffusion region 5 , an N+ diffusion region 7 , which will be the drain, is formed.
- An insulating film 15 is formed to cover the element forming region.
- an electrode 20 is formed to be electrically connected to N+ diffusion region 6 .
- an electrode 21 is formed to be electrically connected to N+ diffusion region 7 .
- an n channel MOS transistor including N+ diffusion region (source) 6 , N+ diffusion region (drain) 7 , conductive film (gate) 8 and P type diffusion region (body) 5 is formed.
- the body is also referred to as a well or a back gate, where a channel is formed and the breakdown voltage is held, in an MOS transistor.
- P type diffusion region 5 to be the body is connected to P type diffusion region 10 formed continuously to be in contact with the entire surface of the inner sidewall of trench isolation region 4 , so that P type diffusion region 10 a comes to have a structure that includes P type diffusion region 5 . Therefore, it becomes unnecessary to keep a distance between element isolation region 4 and P type diffusion region 5 , and the increase of the area occupied by the element forming region can be suppressed.
- trench isolation region 4 is electrically isolated from N ⁇ layer 3 , as P type diffusion region 10 is positioned between trench isolation region 4 and N ⁇ layer 3 . Therefore, when the impurity concentration of P type diffusion region 10 is sufficiently high, for example, 1 ⁇ 10 17 cm ⁇ 3 or higher, it is possible to prevent the depletion layer from reaching trench isolation region 4 even when the transistor is off and a high voltage acts between the source and drain. Thus, a high electric field does not affect trench isolation region 4 , and hence, long time reliability of the semiconductor device can be improved.
- an upper surface of BOX layer 2 is connected to P type diffusion region 5 to be the body, with P type diffusion region 10 interposed. Therefore, even when a high voltage is applied to N+ diffusion region 7 to be the drain and a P type channel layer is formed near the upper surface of BOX layer 2 , holes to form the P type channel layer can be supplied quickly. As a result, speed of operation of the n channel type MOS transistor is improved and the performance of the semiconductor device can be improved.
- a p channel MOS transistor will be described as an example of the semiconductor element formed in the element forming region.
- a P type diffusion region 5 to be the drain is formed to be connected to P type diffusion region 10 a , formed continuously to be in contact with the entire surface of the inner sidewall of trench isolation region 4 .
- N type diffusion region 7 to be the body Adjacent to P type diffusion region 5 , an N type diffusion region 7 to be the body is formed. On the surface of N type diffusion region 7 , a P+ diffusion region 1 to be the source is formed. On a portion of N type diffusion region 7 sandwiched between P+ diffusion region 11 and P type diffusion region 5 , a conductive film 8 to be the gate is formed, with an insulating film 9 interposed.
- An insulating film 15 is formed to cover the element forming region. On insulating film 15 , an electrode 20 is formed to be electrically connected to P+ diffusion region 5 . Further, an electrode 21 to be electrically connected to P+ diffusion region 11 is formed.
- a p channel type MOS transistor including P+ diffusion region (source) 11 , P+ diffusion region (drain) 5 , a conductive film (gate) 8 and N type diffusion region (body) 7 is formed.
- P type diffusion region 10 a formed continuously to be in contact with the entire surface of the inner sidewall of trench isolation region 4 is a part of P type diffusion region 5 . Therefore, it is unnecessary to keep a distance between element forming region 4 and P type diffusion region 5 , and therefore, increase of the area occupied by the element forming region can be suppressed.
- trench isolation region 4 is electrically isolated from N ⁇ layer 3 as the P type diffusion region 10 is positioned between trench isolation region 4 and N ⁇ layer 3 . Therefore, a high electric field does not act on trench isolation region 4 , and hence, reliability of the semiconductor device over a long time can be improved.
- a diode will be described as a semiconductor element formed in the element forming region.
- a P type diffusion region 5 to be an anode is formed to be connected to P type diffusion region 10 a formed continuously to be in contact with the entire surface of the inner sidewall of trench isolation region 4 .
- an N type diffusion region 7 to be a cathode is formed.
- An insulating film 15 is formed to cover the element forming region.
- an electrode 20 to be electrically connected to P+ diffusion region 5 is formed.
- an electrode 21 to be electrically connected to N type diffusion region 7 is formed.
- a diode of high breakdown voltage is formed, which includes a P+ diffusion region (anode) 5 and N type diffusion region (cathode) 7 .
- the P type diffusion region 10 a formed continuously to be in contact with the entire surface of the inner sidewall of trench isolation region 4 is a part of P type diffusion region 5 to be the anode, and therefore, it is unnecessary to keep a distance between element isolating region 4 and P type diffusion region 5 . Therefore, increase of the area occupied by the element forming region can be suppressed.
- trench isolation region 4 is electrically isolated from N ⁇ layer 3 as the P type diffusion region 10 is positioned between trench isolation region 4 and N ⁇ layer 3 . Therefore, a high electric field does not act on trench isolation region 4 , and hence, reliability of the semiconductor device over a long time can be improved.
- a bipolar transistor will be described as an example of a semiconductor element formed in the element forming region.
- a P type diffusion region 5 to be the base is formed to be connected to P type diffusion region 10 a formed continuously to be in contact with the entire surface of the inner sidewall of trench isolation region 4 .
- an N+ diffusion region 6 to be the emitter is formed on a surface of P type diffusion region 5 .
- an N type diffusion region 7 to be the collector is formed.
- An insulating film 15 is formed to cover the element forming region. On insulating film 15 , an electrode 21 is formed to be electrically connected to P+ diffusion region 5 . Further, an electrode to be electrically connected to N+ diffusion region 6 is formed. Further, an electrode 22 to be electrically connected to N type diffusion region 7 is formed.
- a bipolar transistor of high breakdown voltage is formed, which includes N+ diffusion region (emitter) 6 , P+ diffusion region (base) 5 , and N type diffusion region (collector) 7 .
- the P type diffusion region 10 a formed continuously to be in contact with the entire surface of the inner sidewall of trench isolation region 4 is a part of P type diffusion region 5 to be the base, and therefore, it is unnecessary to keep a distance between element isolating region 4 and P type diffusion region 5 . Therefore, increase of the area occupied by the element forming region can be suppressed.
- trench isolation region 4 is electrically isolated from N ⁇ layer 3 as the P type diffusion region 10 is positioned between trench isolation region 4 and N ⁇ layer 3 . Therefore, a high electric field does not act on trench isolation region 4 , and hence, reliability of the semiconductor device over a long time can be improved.
- P type diffusion region 10 formed along the inner sidewall of trench isolation region 4 has relatively low impurity concentration, the P type diffusion region may be depleted and the electric field may possibly reach the inside of trench isolation region 4 . In that case, it is difficult to maintain reliability of the semiconductor device for a long time.
- P type diffusion regions 10 a and 10 b have sufficiently high impurity concentrations, and therefore, even when a high voltage is applied to the semiconductor device formed in the element forming region, the depletion layer formed in the N ⁇ layer 3 a cannot reach the trench isolation region. As a result, no electric field is generated inside the trench isolation region 4 , and long time reliability of the semiconductor device can be improved.
- FIG. 13 equipotential distribution and reach of depletion layer are plotted, where the initial conditions of simulation are as follows. Source potential: 0V, gate potential: 0V, substrate potential: 0V, and about 180 V is applied to the drain.
- the impurity concentration of P type diffusion region 10 a is set to be at least 1 ⁇ 10 17 cm 3 .
- crystal defects tend to generate because of damages experienced at the time of forming the trench, or stress experienced when the trench isolation region is filled with an insulating material.
- An electric field generated at such a portion having crystal defect possibly causes a leakage current.
- P type diffusion region 10 a formed continuously to be in contact with the inner sidewall of the trench isolation region has sufficiently high impurity concentration, and therefore, electric field does not reach trench isolation region 4 . Therefore, even when a crystal defect generates near trench isolation region 4 , generation of leakage current can be prevented.
- P type diffusion region 10 a is formed continuously to be in contact with the entire surface of the inner sidewall of trench isolation region.
- the impurity concentration of P type diffusion region 10 a must be made higher than the impurity concentration of each of the diffusion regions forming the element.
- diffusion regions forming the element mean substantial diffusion regions forming the element and do not include regions having relatively high impurity concentration intended to attain electrical connection with the electrode.
- an N ⁇ layer 3 is formed to the thickness of 5 ⁇ m with a BOX layer 2 having the thickness of about 1 ⁇ m interposed, whereby a substrate (SOI substrate) is prepared.
- a mask material 30 such as a silicon oxide film, having the thickness of about 500 nm is formed.
- N ⁇ layer 3 is subjected to anisotropic etching, so that a trench 31 having the width of about 1 ⁇ m is formed, exposing the surface of BOX layer 2 .
- Trench 31 is formed continuously to surround a portion to be the element forming region.
- boron is introduced by oblique ion implantation, with the dosage of 1 ⁇ 10 13 cm ⁇ 2 to 1 ⁇ 10 15 cm ⁇ 2 at an angle of at most 10 degrees, whereby a P type diffusion region 10 a is formed.
- ion implantation is performed under the same condition, so that a P type diffusion region 10 b is formed.
- FIGS. 16 and 17 an example has been described in which P type diffusion regions 10 a and 10 b are formed on the inner and outer sidewalls of trench 31 , on one cross section of a semiconductor device. It is noted, however, that trench 31 is formed to surround the element forming region, as shown, for example, in FIG. 1 . Therefore, oblique ion implantation must be repeated until ions are introduced to all the portions on the outer sidewall and inner sidewall exposed in trench 31 formed to surround the element forming region.
- mask material 30 used for forming trench 31 may be used as a mask for ion implantation. After the end of ion implantation, mask material 30 is removed.
- a silicon oxide film or the like is filled in trench 31 , so that trench isolation region 4 is formed.
- a desired semiconductor element such as an MOS transistor is formed (not shown), and the semiconductor device is completed.
- P type diffusion regions 10 a and 10 b are formed continuously along the inner sidewall and outer sidewall of trench isolation region 4 , respectively. Therefore, trench isolation region 4 is electrically isolated not only by the PN junction between N ⁇ layer 3 a and P type diffusion region 10 a but also by the PN junction between N ⁇ layer 3 b and P type diffusion region 10 b. As a result, electrical isolation between N ⁇ layer 3 a as one element forming region and N ⁇ layer 3 b as another element forming region can be made more reliable.
- the impurity concentration of P type diffusion regions 10 a and 10 b must be made higher than the impurity concentrations of diffusion regions forming the element.
- the condition for implantation is set such that the impurity concentration of P type diffusion regions 10 a and 10 b becomes higher than the impurity concentration of the diffusion regions forming the element.
- P type diffusion region 10 a and the like are not fully depleted.
- the diffusion regions forming the element do not include any region having a relatively high impurity concentration for attaining electrical contact with the electrode.
- the N type diffusion region formed to be in contact with the inner sidewall of the trench isolation region includes a diffusion region to be a cathode in the case of a diode, and a diffusion region to be a collector in the case of a bipolar transistor.
- CMOS transistor will be described as an example, in which an n channel MOS transistor and a P channel MOS transistor are formed as semiconductor elements formed in the element forming region of the semiconductor device having the P type diffusion regions formed in contact with both the inner and outer sidewalls of the trench isolation region.
- a P type well region 60 and an N type well region 61 are formed, respectively.
- an insulating film 11 is formed to expose P type well region 60 and N type well region 61 .
- N type source/drain regions 62 and 63 are formed spaced apart by a prescribed distance from each other.
- a gate electrode 68 is formed, with a gate insulating film 66 interposed.
- N type well 61 In exposed N type well 61 , P type source/drain regions 64 and 65 are formed spaced apart by a prescribed distance from each other. On that region of N type well region 61 which is sandwiched between the source/drain regions 64 and 65 , a gate electrode 69 is formed, with a gate insulating film 67 interposed. By P type source/drain regions 64 , 65 and the gate electrode 69 , a p channel MOS transistor is formed.
- P type well region 60 is continuous from P type diffusion region 10 a , and is electrically connected to P type diffusion region 10 a.
- a P+ diffusion region 80 is formed, and to P+ diffusion region 80 , an electrode 75 for fixing the P type well region 60 and P type diffusion region 10 a to a prescribed potential is connected.
- the N type well region 61 a prescribed region and an electrode connected to the prescribed region (both not shown) are formed to fix the N type well region 61 to a prescribed potential. Except for these points, the structure is the same as that shown in FIG. 9 or 10 , and therefore, same portions are denoted by the same reference characters and description thereof will not be repeated.
- P type well region 60 is electrically isolated from P type diffusion region 10 a, that is, P type well region 60 a , by N type well region 61 . More specifically, side portions of P type well 60 are surrounded by N type well region 61 , and N ⁇ layer 3 a is positioned at the bottom of P type well 60 .
- An electrode (not shown) for fixing the P type well region 60 to a prescribed potential is formed in P type well region 60
- an electrode (not shown) for fixing N type well region 61 to a prescribed potential is also formed in N type well region 61 .
- P type well region 60 is not electrically connected to P type diffusion region 10 a, and therefore, it can be fixed to a prescribed potential independent from the potential of P type diffusion region 10 a.
- a semiconductor device in which potentials of the P type well region, N type well region and P type diffusion region can be set independently, will specifically be described. Referring to FIG. 21 , in P type well region 60 , P+ diffusion region 81 is formed, and in N type well region 61 , N+ diffusion region 82 is formed. In P type well region 60 a that is connected to P type diffusion region 10 a, a P+ diffusion region 80 is formed.
- an electrode 76 for fixing P type well region 60 to a prescribed potential is connected; to N+ diffusion region 82 , an electrode 77 for fixing N type well region 61 to a prescribed potential is connected; and to P+ diffusion region 80 , an electrode 75 for fixing P type diffusion region 10 a to a prescribed potential is connected.
- CMOS transistor is formed as the semiconductor element in the element forming region.
- trench isolation region 4 is electrically isolated from N ⁇ layer 3 as there is P type diffusion region 10 a between trench isolation region 4 and N ⁇ layer 3 , and therefore, high electric field does not affect trench isolation region 4 . Therefore, reliability of the semiconductor device over a long time can be improved.
- a flash memory element will be described as an example of a semiconductor element formed in the element forming region of the semiconductor device in which the P type diffusion regions are formed to be in contact with the inner and outer sidewalls of the trench isolation region.
- a P type well region 60 is formed at the surface of N ⁇ layer 3 a surrounded by P type diffusion region 10 a and in the vicinity thereof.
- an insulating film 11 is formed to expose a surface of P type well region 60 .
- N type source/drain regions 62 and 63 are formed spaced by a prescribed distance from each other.
- a gate electrode portion 70 is formed, with a gate insulating film 66 interposed.
- Gate electrode 70 is formed to have a lower electrode 70 a formed on gate insulating film 66 , a dielectric film 70 b formed on lower electrode 70 a , and an upper electrode 70 c formed on dielectric film 70 b.
- P type well region 60 is continuous from P type diffusion region 10 a, and is electrically connected to P type diffusion region 10 a.
- P+ diffusion region 80 is formed, and to P+ diffusion region 80 , an electrode 75 for fixing P type well region 60 and P type diffusion region 10 a to a prescribed potential is connected.
- P type well region 60 is continuous from P type diffusion region 10 a.
- P type well 60 is not continuous from P type diffusion region 10 a and electrically isolated therefrom will be described.
- P type well 60 is electrically isolated from P type diffusion region 10 a and P type well region 60 a , by N type well 61 . Specifically, side portions of P type well region 60 are surrounded by N type well region 61 , and at the bottom of P type well region 60 , N ⁇ layer 3 a is positioned. In P type well region 60 , P+ diffusion region 81 is formed, and to P+ diffusion region 81 , an electrode 76 is connected for fixing P type well region 60 to a prescribed potential.
- P type well region 60 is not electrically connected to P type diffusion region 10 a, and by electrode 76 , it can be fixed to a prescribed potential independently from the potential of P type diffusion region 10 a.
- P+ diffusion region 81 is formed, and in P type well region 60 continuous from P type diffusion region 10 a, P+ diffusion region 80 is formed.
- an electrode 76 for fixing P type well region 60 to a prescribed potential is connected, and to P+ diffusion region 80 , an electrode 75 for fixing P type diffusion region 10 a to a prescribed potential is connected.
- N type well 61 can also be fixed at a prescribed potential.
- a flash memory element is formed as a semiconductor element in the element forming region.
- trench isolation region 4 is electrically isolated from N ⁇ layer 3 as the P type diffusion region 10 is positioned between trench isolation region 4 and N ⁇ layer 3 . Therefore, high electric field does not affect trench isolation region 4 , and reliability of the semiconductor device over a long time can be improved.
Abstract
An N− layer is formed on a semiconductor substrate, with a BOX layer interposed. In the N− layer, a trench isolation region is formed to surround the N− layer to be an element forming region. The trench isolation region is formed to reach the BOX layer, from the surface of the N− layer. Between trench isolation region and the N− layer, a P type diffusion region 10 a is formed. The P type diffusion region is formed continuously without any interruption, to be in contact with the entire surface of an inner sidewall of the trench isolation region surrounding the element forming region. In the element forming region of the N− layer, a prescribed semiconductor element is formed. Thus, a semiconductor device is formed, in which electrical isolation is established reliably, without increasing the area occupied by the element forming region.
Description
- 1. Field of the Invention
- The present invention relates to a semiconductor device and manufacturing method thereof and, more specifically, to a semiconductor device having a trench isolation structure and a method of manufacturing the same.
- 2. Description of the Background Art
- In a semiconductor device having an integrated circuit that must withstand a high voltage, an isolation structure for electrically separating elements from each other is necessary, in order to avoid electrical influence between elements. Particularly, trench isolation has been known as a superior method of element isolation to attain higher degree of integration, as it requires relatively small area for separating elements. An isolation structure having a combination of an SOI (Silicon On Insulator) substrate and the trench isolation has been highly appreciated as one element can fully be isolated from another element electrically so that parasitic operation between elements can be suppressed.
- An example of a semiconductor device using such an SOI substrate will be described. An N− layer is formed on a silicon semiconductor substrate with a BOX (Buried OXide Layer) layer interposed. In the N− layer, an element forming region is formed, and a trench isolation region is formed for separating elements. In the element forming region, an n channel type MOS (Metal Oxide Semiconductor) transistor including a source, drain, gate and a body is formed as a semiconductor element.
- In semiconductor devices described in Japanese Patent Laying-Open Nos. 2001-044437 and 2003-197639, semiconductor devices having a P type region formed to be in contact with the trench isolation region are proposed. The conventional semiconductor devices using an SOI substrate are structured as described above.
- In the conventional semiconductor device, the N− layer in the element forming region is in contact with the trench isolation region, and therefore, when the MOS transistor is off, an electric field reaches the trench isolation region. Therefore, in order to prevent decrease in main breakdown voltage of the MOS transistor caused by electric field concentration near the trench isolation region, it has been necessary to ensure a sufficient distance between the P type impurity region as the body of the MOS transistor formed in the element forming region and the trench isolation region. As a result, the element forming region comes to occupy a large area.
- When the MOS transistor is off, the electric field reaches even the inside of the trench isolation region, possibly eroding reliability over a long period dependent on the material of the trench isolation region.
- Further, in some state of operation of the MOS transistor, a P type inverted layer may be formed on an upper surface of the BOX layer. At this time, as the P type impurity region formed on the surface of the N− layer is not in contact with the BOX layer, formation of the inverted layer delays in a high speed operation, undesirably decreasing the switching speed.
- In the semiconductor devices described in Japanese Patent Laying-Open Nos. 2001-044437 and 2003-197639, the P type region formed to be in contact with the trench isolation region is connected to two or more different electrode terminals. Therefore, it is impossible to control the electric field in the element forming region, and therefore, there has been a limit in improving the performance of trench isolation.
- The present invention was made to solve the above-described problems, and its object is to provide a semiconductor device that enables reliable electrical isolation without increasing the area occupied by the element forming region, and another object is to provide a method of manufacturing such a semiconductor device.
- The present invention provides a semiconductor device that includes an insulating film, a semiconductor layer of a first conductivity type, an isolating region, and a first impurity region of a second conductivity type. The insulating film is formed on a main surface of a prescribed substrate. The semiconductor layer of the first conductivity type is formed on the insulating film. The isolating region continuously surrounds a prescribed region to be the element forming region in the semiconductor layer, is formed over the surface of the semiconductor layer to the surface of the insulating film, and has an inner sidewall and an outer sidewall. The first impurity region of the second conductivity type is formed continuously to be in contact with the entire surface of the inner sidewall of the isolating region, and positioned between the isolating region and that portion of the semiconductor layer which is positioned at the prescribed region.
- Further, the present invention provides a method of manufacturing a semiconductor device including the following steps. On a semiconductor layer of a first conductivity type formed on a prescribed substrate with an insulating film interposed, a trench is formed to continuously surround a region to be the element forming region and to expose a surface of the insulating film. On an entire surface of that portion of the semiconductor layer exposed in the trench, which is at least on the side where the prescribed region is positioned, an impurity of a second conductivity type is introduced, so as to form a first impurity region of the second conductivity type. Thereafter, the trench is filled with an insulating material.
- In the semiconductor device in accordance with the present invention, the first impurity region is formed continuously to be in contact with the entire surface of the inner sidewall of the isolating region. Therefore, the isolating region is electrically isolated by the PN junction between that portion of the semiconductor layer which is positioned in the prescribed region and the first impurity region. As a result, reliability of electric isolation can be enhanced without increasing the area of the element forming region.
- By the method of manufacturing a semiconductor device in accordance with the present invention, on the entire surface of that portion of the semiconductor layer which is on the side of the prescribed region, the first impurity region of the second conductivity type is formed. Therefore, a PN junction is formed at the interface between that portion of the semiconductor layer and the first impurity region, and thus, a structure for electrical isolation can easily be formed.
- The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
-
FIG. 1 is a plan view of a semiconductor device in accordance with a first embodiment of the present invention. -
FIG. 2 is a cross-sectional view taken along the line II-II ofFIG. 1 , in accordance with the same embodiment. -
FIG. 3 is a plan view of a semiconductor device as a comparative example of the embodiment. -
FIG. 4 is a cross-sectional view taken along the line IV-IV ofFIG. 3 . -
FIG. 5 is a plan view of a semiconductor device in accordance with a second embodiment of the present invention. -
FIG. 6 is a cross-sectional view taken along the line VI-VI ofFIG. 5 . -
FIG. 7 is a plan view of a semiconductor device in accordance with a third embodiment of the present invention. -
FIG. 8 is a plan view of a semiconductor device in accordance with a fourth embodiment of the present invention. -
FIG. 9 is a plan view of a semiconductor device in accordance with a fifth embodiment of the present invention. -
FIG. 10 is a plan view of a semiconductor device in accordance with a sixth embodiment of the present invention. -
FIG. 11 is a plan view of a semiconductor device in accordance with a seventh embodiment of the present invention. -
FIG. 12 is a plan view of a semiconductor device in accordance with an eighth embodiment of the present invention. -
FIG. 13 shows results of simulation of potential distribution and extension of depletion layer in the element forming region in the semiconductor devices in accordance with various embodiments of the present invention. -
FIG. 14 is a partial sectional view showing a step of manufacturing the semiconductor device in accordance with an eleventh embodiment of the present invention. -
FIG. 15 is a cross-sectional view showing the step following the step shown inFIG. 14 . -
FIG. 16 is a cross-sectional view showing the step following the step shown inFIG. 15 . -
FIG. 17 is a cross-sectional view showing the step following the step shown inFIG. 16 . -
FIG. 18 is a cross-sectional view showing the step following the step shown inFIG. 17 . -
FIG. 19 is a cross-sectional view of a semiconductor device in accordance with a twelfth embodiment of the present invention. -
FIG. 20 is a cross-sectional view of a semiconductor device in accordance with a first modification of the twelfth embodiment. -
FIG. 21 is a cross-sectional view of a semiconductor device in accordance with a second modification of the twelfth embodiment. -
FIG. 22 is a cross-sectional view of a semiconductor device in accordance with a thirteenth embodiment of the present invention. -
FIG. 23 is a cross-sectional view of a semiconductor device in accordance with a first modification of the thirteenth embodiment. -
FIG. 24 is a cross-sectional view of a semiconductor device in accordance with a second modification of the thirteenth embodiment. - A semiconductor device in accordance with a first embodiment of the present invention will be described. As shown in
FIGS. 1 and 2 , on asemiconductor substrate 1, aBOX layer 2 is formed. OnBOX layer 2, an N−layer 3 of, for example, an epitaxial layer is formed. In N−layer 3, atrench isolation region 4 is formed to surround that portion (N−layer 3 a) of N−layer 3 which will be the element forming region.Trench isolation region 4 is formed from the surface of N−layer 3 to reachBOX layer 2. Outside thetrench isolation region 4, N−layer 3 b is positioned, which will be another element forming region. On N−layer 3, an insulatingfilm 15, such as a silicon oxide film, is formed. - Between
trench isolation region 4 and N−layer 3, a Ptype diffusion region 10 a is formed. Ptype diffusion region 10 a is formed continuously without any interruption, to be in contact with the entire surface of an inner sidewall oftrench isolation region 4 surrounding the element forming region. In the element forming region such as N−layer 3 a, a semiconductor element such as a transistor or a diode, is formed, as will be described later. - In the semiconductor device described above, between the N−
layer 3 a to be the element forming region and thetrench isolation region 4, Ptype diffusion region 10 a is formed continuously without any interruption to be in contact with the entire surface of the inner sidewall oftrench isolation region 4. Therefore,trench isolation region 4 is electrically isolated by the PN junction of N−layer 3 a and Ptype diffusion region 10 a. - Therefore, as compared with a conventional semiconductor device in which only the element isolating region is formed between the N−
layer 3 a as an element forming region and the N−layer 3 b as another element forming region without Ptype diffusion region 10 a, electrical isolation can be made more reliable by the PN junction. - Further, as compared with another conventional semiconductor device in which a P type region is formed to be in contact with the trench isolation region and the P type region is connected to two or more different electrode terminals as described above, the present semiconductor device can enhance electric isolation. This will be discussed more specifically in the following.
- As shown in
FIGS. 3 and 4 , in the said another conventional semiconductor device, an N−layer 103 is formed on asemiconductor substrate 101 with aBOX layer 102 interposed. In N−layer 103, atrench isolation region 104 is formed to surround that portion (N−layer 103 a) of N−layer 103 which will be the element forming region. Outside thetrench isolation region 104, an N−layer 103 b to be another element forming region is positioned. On N−layer 103, an insulatingfilm 115 is formed. - At portions of
trench isolation region 104 opposite to each other, Ptype diffusion regions trench isolation region 104 and N− layer 103 a. Anelectrode 120 is electrically connected to Ptype diffusion region 110 a, and anelectrode 121 is electrically connected to Ptype diffusion region 110 b. - Assume that an MOS transistor is formed as the semiconductor element in the element forming region. In that case, P
type diffusion region 110 a will be the drain region and Ptype diffusion region 110 b will be the source region.Electrode 120 will be the drain electrode, andelectrode 121 will be the source electrode. The drain region and the source region make operations different from each other, and therefore, the potentials in the drain region and the source region are different. For this reason, the Ptype diffusion regions - In this manner, in said another conventional semiconductor device, P
type diffusion regions element isolating region 104, and hence, electrical isolation attained byelement isolation region 104 has been limited. - In contrast, in the semiconductor device in accordance with the present embodiment, P
type diffusion region 10 a is formed continuously, to be in contact with the entire surface of the inner sidewall oftrench isolation region 4. Therefore, the potential of Ptype diffusion region 10 a is always the same. Accordingly, the potential of the inner sidewall that is in contact with Ptype diffusion region 10 a is also kept at the same potential, improving the electrical isolation characteristic. - In the semiconductor device described above, the P type diffusion region is formed along the inner sidewall of the trench isolation region. Here, an example will be described in which P type diffusion regions are formed to be in contact with the entire surfaces of inner and outer sidewalls of the trench isolation region.
- As shown in
FIGS. 5 and 6 , first, betweentrench isolation region 4 and N−layer 3 a, a Ptype diffusion region 10 a is formed. Ptype diffusion region 10 a is formed continuously without any interruption to be in contact with the entire surface of the inner sidewall oftrench isolation region 4 surrounding the element forming region. - Between
trench isolation region 4 and N−layer 3 b also, a P type diffusion region lob is formed. Ptype diffusion region 10 b is formed continuously to be in contact with the entire surface of the outer sidewall oftrench isolation region 4 surrounding the element forming region. Except for this point, the semiconductor device is the same as the one described above, and therefore, the same or corresponding portions are denoted by the same reference characters and description thereof will not be repeated. - In the semiconductor device described above, in addition to P
type diffusion region 10 a, Ptype diffusion region 10 b is formed betweentrench isolation region 4 and N−layer 3 b as another element forming region. Therefore,trench isolation region 4 comes to be electrically isolated not only by the PN junction between N−layer 3 a and Ptype diffusion region 10 a but also by the PN junction between N−layer 3 b and Ptype diffusion region 10 b. As a result, electrical isolation between N−layer 3 a and N−layer 3 b can be made more reliable by the two PN junctions, than in the semiconductor device described above. - As a semiconductor device in accordance with a third embodiment of the present invention, an example will be described in which the P type diffusion region is kept at a prescribed potential. As shown in
FIG. 7 , on an insulatingfilm 15, anelectrode 20 a to be electrically connected to Ptype diffusion region 10 a is formed. Except for this point, the semiconductor device is the same as the one shown inFIG. 2 . Therefore, the same or corresponding portions will be denoted by the same reference characters, and description thereof will not be repeated. - In the semiconductor device described above, by applying a prescribed voltage to electrode 20 a, the potential of P
type diffusion region 10 a can be kept at a constant value. By way of example, by applying a voltage of 0V to electrode 20 a, the potential of Ptype diffusion region 10 a can be kept at 0V. Thus, effect of the electric field generated by the potential of N−layer 3 a to trenchisolation region 4 or N−layer 3 b can efficiently be prevented. - Here, another example of a semiconductor device, in which the P type diffusion region is kept at a prescribed potential, will be described. Referring to
FIG. 8 , on insulatingfilm 15, in addition toelectrode 20 a to be electrically connected to Ptype diffusion region 10 a, anelectrode 20 b to be connected to Ptype diffusion region 10 b is formed. Except for this point, the semiconductor device is the same as the one shown inFIG. 6 . Therefore, the same or corresponding portions will be denoted by the same reference characters, and description thereof will not be repeated. - In the semiconductor device described above, by applying a prescribed voltage to electrode 20 a, the potential of P
type diffusion region 10 a can be kept at a constant value, and by applying a prescribed voltage to electrode 20 b, the potential of Ptype diffusion region 10 b can also be kept at a constant value. By way of example, by applying a voltage of 0V toelectrodes type diffusion region 10 a as well as Ptype diffusion region 10 b can be kept at 0V. - Therefore, compared with the example in which only the P
type diffusion region 10 a is provided and kept at 0V, the influence of electric field generated by N−layer 3 a to trenchisolation region 4 or N−layer 3 b can be prevented and the influence of electric field generated by N−layer 3 b to trenchisolation region 4 or N−layer 3 a can also be prevented. - As a result, electrical interaction between N− layers 3 a and 3 b that will be the element forming regions can surely be prevented. Further, even when a potential is applied to N−
layer 3 a and N−layer 3 b, the electric field does not reachtrench isolation region 4, and therefore, reliability of electric isolation can be enhanced. - In the embodiments above, basic structures of the trench isolation region have been described. In the following embodiments, semiconductor elements formed in the element forming region defined by the trench isolation region will be described specifically.
- Here, an n channel MOS transistor will be described as an example of the semiconductor element formed in the element forming region. As shown in
FIG. 9 , inside thetrench isolation region 4, N−layer 3 a as the element forming region is positioned. Outside thetrench isolation region 4, N−layer 3 b as another element forming region is positioned. - On the surface of N−
layer 3 a, a Ptype diffusion region 5, which will be a body, is formed to be connected to Ptype diffusion region 10 a formed continuously to be in contact with the entire surface of the inner sidewall oftrench isolation region 4. On the surface of Ptype diffusion region 5, anN+ diffusion region 6, which will be the source, is formed. On that portion of Ptype diffusion region 5 which is between the N+ diffusion region and N−layer 3, aconductive film 8 to be the gate is formed, with an insulatingfilm 9 interposed. - Spaced apart from P
type diffusion region 5, anN+ diffusion region 7, which will be the drain, is formed. An insulatingfilm 15 is formed to cover the element forming region. On insulatingfilm 15, anelectrode 20 is formed to be electrically connected toN+ diffusion region 6. Further, anelectrode 21 is formed to be electrically connected toN+ diffusion region 7. - In this manner, in the element forming region of N−
layer 3, an n channel MOS transistor including N+ diffusion region (source) 6, N+ diffusion region (drain) 7, conductive film (gate) 8 and P type diffusion region (body) 5 is formed. The body is also referred to as a well or a back gate, where a channel is formed and the breakdown voltage is held, in an MOS transistor. - In the semiconductor device described above, P
type diffusion region 5 to be the body is connected to P type diffusion region 10 formed continuously to be in contact with the entire surface of the inner sidewall oftrench isolation region 4, so that Ptype diffusion region 10 a comes to have a structure that includes Ptype diffusion region 5. Therefore, it becomes unnecessary to keep a distance betweenelement isolation region 4 and Ptype diffusion region 5, and the increase of the area occupied by the element forming region can be suppressed. - Further,
trench isolation region 4 is electrically isolated from N−layer 3, as P type diffusion region 10 is positioned betweentrench isolation region 4 and N−layer 3. Therefore, when the impurity concentration of P type diffusion region 10 is sufficiently high, for example, 1×1017 cm−3 or higher, it is possible to prevent the depletion layer from reachingtrench isolation region 4 even when the transistor is off and a high voltage acts between the source and drain. Thus, a high electric field does not affecttrench isolation region 4, and hence, long time reliability of the semiconductor device can be improved. - In the semiconductor device described above, an upper surface of
BOX layer 2 is connected to Ptype diffusion region 5 to be the body, with P type diffusion region 10 interposed. Therefore, even when a high voltage is applied toN+ diffusion region 7 to be the drain and a P type channel layer is formed near the upper surface ofBOX layer 2, holes to form the P type channel layer can be supplied quickly. As a result, speed of operation of the n channel type MOS transistor is improved and the performance of the semiconductor device can be improved. - Here, a p channel MOS transistor will be described as an example of the semiconductor element formed in the element forming region. As shown in
FIG. 10 , on the surface of N−layer 3 a positioned in the element forming region, a Ptype diffusion region 5 to be the drain is formed to be connected to Ptype diffusion region 10 a, formed continuously to be in contact with the entire surface of the inner sidewall oftrench isolation region 4. - Adjacent to P
type diffusion region 5, an Ntype diffusion region 7 to be the body is formed. On the surface of Ntype diffusion region 7, aP+ diffusion region 1 to be the source is formed. On a portion of Ntype diffusion region 7 sandwiched betweenP+ diffusion region 11 and Ptype diffusion region 5, aconductive film 8 to be the gate is formed, with an insulatingfilm 9 interposed. - An insulating
film 15 is formed to cover the element forming region. On insulatingfilm 15, anelectrode 20 is formed to be electrically connected toP+ diffusion region 5. Further, anelectrode 21 to be electrically connected toP+ diffusion region 11 is formed. - In this manner, in the element forming region formed of N−
layer 3, a p channel type MOS transistor including P+ diffusion region (source) 11, P+ diffusion region (drain) 5, a conductive film (gate) 8 and N type diffusion region (body) 7 is formed. - In the semiconductor device described above, as in the n channel type MOS transistor discussed earlier, P
type diffusion region 10 a formed continuously to be in contact with the entire surface of the inner sidewall oftrench isolation region 4 is a part of Ptype diffusion region 5. Therefore, it is unnecessary to keep a distance betweenelement forming region 4 and Ptype diffusion region 5, and therefore, increase of the area occupied by the element forming region can be suppressed. - Further,
trench isolation region 4 is electrically isolated from N−layer 3 as the P type diffusion region 10 is positioned betweentrench isolation region 4 and N−layer 3. Therefore, a high electric field does not act ontrench isolation region 4, and hence, reliability of the semiconductor device over a long time can be improved. - Here, a diode will be described as a semiconductor element formed in the element forming region. As shown in
FIG. 11 , on a surface of N−layer 3 a positioned in the element forming region, a Ptype diffusion region 5 to be an anode is formed to be connected to Ptype diffusion region 10 a formed continuously to be in contact with the entire surface of the inner sidewall oftrench isolation region 4. Apart from Ptype diffusion region 5, an Ntype diffusion region 7 to be a cathode is formed. - An insulating
film 15 is formed to cover the element forming region. On insulatingfilm 15, anelectrode 20 to be electrically connected toP+ diffusion region 5 is formed. Further, anelectrode 21 to be electrically connected to Ntype diffusion region 7 is formed. In this manner, in the element forming region of N−layer 3, a diode of high breakdown voltage is formed, which includes a P+ diffusion region (anode) 5 and N type diffusion region (cathode) 7. - In the semiconductor device described above, again, the P
type diffusion region 10 a formed continuously to be in contact with the entire surface of the inner sidewall oftrench isolation region 4 is a part of Ptype diffusion region 5 to be the anode, and therefore, it is unnecessary to keep a distance betweenelement isolating region 4 and Ptype diffusion region 5. Therefore, increase of the area occupied by the element forming region can be suppressed. - Further,
trench isolation region 4 is electrically isolated from N−layer 3 as the P type diffusion region 10 is positioned betweentrench isolation region 4 and N−layer 3. Therefore, a high electric field does not act ontrench isolation region 4, and hence, reliability of the semiconductor device over a long time can be improved. - Here, a bipolar transistor will be described as an example of a semiconductor element formed in the element forming region. As shown in
FIG. 12 , on a surface of N−layer 3 a positioned in the element forming region, a Ptype diffusion region 5 to be the base is formed to be connected to Ptype diffusion region 10 a formed continuously to be in contact with the entire surface of the inner sidewall oftrench isolation region 4. On a surface of Ptype diffusion region 5, anN+ diffusion region 6 to be the emitter is formed. Apart from Ptype diffusion region 5, an Ntype diffusion region 7 to be the collector is formed. - An insulating
film 15 is formed to cover the element forming region. On insulatingfilm 15, anelectrode 21 is formed to be electrically connected toP+ diffusion region 5. Further, an electrode to be electrically connected toN+ diffusion region 6 is formed. Further, anelectrode 22 to be electrically connected to Ntype diffusion region 7 is formed. - In this manner, in the element forming region of N−
layer 3, a bipolar transistor of high breakdown voltage is formed, which includes N+ diffusion region (emitter) 6, P+ diffusion region (base) 5, and N type diffusion region (collector) 7. - In the semiconductor device described above, again, the P
type diffusion region 10 a formed continuously to be in contact with the entire surface of the inner sidewall oftrench isolation region 4 is a part of Ptype diffusion region 5 to be the base, and therefore, it is unnecessary to keep a distance betweenelement isolating region 4 and Ptype diffusion region 5. Therefore, increase of the area occupied by the element forming region can be suppressed. - Further,
trench isolation region 4 is electrically isolated from N−layer 3 as the P type diffusion region 10 is positioned betweentrench isolation region 4 and N−layer 3. Therefore, a high electric field does not act ontrench isolation region 4, and hence, reliability of the semiconductor device over a long time can be improved. - When P type diffusion region 10 formed along the inner sidewall of
trench isolation region 4 has relatively low impurity concentration, the P type diffusion region may be depleted and the electric field may possibly reach the inside oftrench isolation region 4. In that case, it is difficult to maintain reliability of the semiconductor device for a long time. - In the semiconductor devices in accordance with various embodiments described above, P
type diffusion regions layer 3 a cannot reach the trench isolation region. As a result, no electric field is generated inside thetrench isolation region 4, and long time reliability of the semiconductor device can be improved. - This was confirmed through simulation, using an n channel MOS transistor as an example. The result is as shown in
FIG. 13 . InFIG. 13 , equipotential distribution and reach of depletion layer are plotted, where the initial conditions of simulation are as follows. Source potential: 0V, gate potential: 0V, substrate potential: 0V, and about 180 V is applied to the drain. Here, the impurity concentration of Ptype diffusion region 10 a is set to be at least 1×1017 cm3. - As shown in
FIG. 13 , when the impurity concentration of Ptype diffusion region 10 a is sufficiently high,equipotential line 53 does not reachtrench isolation region 4, and anedge 51 ofdepletion layer 51 is positioned in Ptype diffusion region 4. Thus, it is confirmed through experiment that high electric field does not affecttrench isolation region 4 and reliability over a long time can be improved. - Generally, at a portion of element forming region near the sidewall of trench isolation region, crystal defects tend to generate because of damages experienced at the time of forming the trench, or stress experienced when the trench isolation region is filled with an insulating material. An electric field generated at such a portion having crystal defect possibly causes a leakage current.
- In each of the semiconductor devices of the embodiments above, P
type diffusion region 10 a formed continuously to be in contact with the inner sidewall of the trench isolation region has sufficiently high impurity concentration, and therefore, electric field does not reachtrench isolation region 4. Therefore, even when a crystal defect generates neartrench isolation region 4, generation of leakage current can be prevented. - In each of the semiconductor devices of the embodiments above, P
type diffusion region 10 a is formed continuously to be in contact with the entire surface of the inner sidewall of trench isolation region. In order to prevent Ptype diffusion region 10 a from being fully depleted at the time of operation of the element formed in the element forming region, the impurity concentration of Ptype diffusion region 10a must be made higher than the impurity concentration of each of the diffusion regions forming the element. - By way of example, when an n channel MOS transistor is formed as the semiconductor device, the impurity concentration of P
type diffusion region 10 a must be made higher than that of Ptype diffusion layer 5 to be the body. Thus, even when a high electric field is generated as in the transistor-off state, P type diffusion region is not fully depleted. Here, diffusion regions forming the element mean substantial diffusion regions forming the element and do not include regions having relatively high impurity concentration intended to attain electrical connection with the electrode. - An example of a method of manufacturing a semiconductor device having the trench isolation region described with reference to each of the embodiments above will be described. First, as shown in
FIG. 14 , on asilicon substrate 1 as a supporting substrate, an N−layer 3 is formed to the thickness of 5 μm with aBOX layer 2 having the thickness of about 1 μm interposed, whereby a substrate (SOI substrate) is prepared. - Thereafter, as shown in
FIG. 15 , on N−layer 3, amask material 30 such as a silicon oxide film, having the thickness of about 500 nm is formed. Using the mask material as a mask, N−layer 3 is subjected to anisotropic etching, so that atrench 31 having the width of about 1 μm is formed, exposing the surface ofBOX layer 2.Trench 31 is formed continuously to surround a portion to be the element forming region. - Thereafter, as shown in
FIG. 16 , to the entire surface of N−layer 3 exposed on the inner sidewall oftrench 31, boron is introduced by oblique ion implantation, with the dosage of 1×1013 cm−2 to 1×1015 cm−2 at an angle of at most 10 degrees, whereby a Ptype diffusion region 10 a is formed. Then, as shown inFIG. 17 , also to the entire surface of N−layer 3 exposed on the outer sidewall oftrench 31, ion implantation is performed under the same condition, so that a Ptype diffusion region 10 b is formed. - In
FIGS. 16 and 17 , an example has been described in which Ptype diffusion regions trench 31, on one cross section of a semiconductor device. It is noted, however, thattrench 31 is formed to surround the element forming region, as shown, for example, inFIG. 1 . Therefore, oblique ion implantation must be repeated until ions are introduced to all the portions on the outer sidewall and inner sidewall exposed intrench 31 formed to surround the element forming region. - Further, in the step of ion implantation,
mask material 30 used for formingtrench 31 may be used as a mask for ion implantation. After the end of ion implantation,mask material 30 is removed. - Referring to
FIG. 18 , next, a silicon oxide film or the like is filled intrench 31, so thattrench isolation region 4 is formed. Thereafter, in N−layer 3 a positioned in the element forming region surrounded bytrench isolation region 4, a desired semiconductor element such as an MOS transistor is formed (not shown), and the semiconductor device is completed. - In the semiconductor device described above, P
type diffusion regions trench isolation region 4, respectively. Therefore,trench isolation region 4 is electrically isolated not only by the PN junction between N−layer 3 a and Ptype diffusion region 10 a but also by the PN junction between N−layer 3 b and Ptype diffusion region 10 b. As a result, electrical isolation between N−layer 3 a as one element forming region and N−layer 3 b as another element forming region can be made more reliable. - As already described, in order to prevent P
type diffusion regions type diffusion regions - For this purpose, when P
type diffusion regions type diffusion regions - Because of such impurity concentration, even when a high electric field acts on N−
layer 3 a and the like, Ptype diffusion region 10 a and the like are not fully depleted. The diffusion regions forming the element do not include any region having a relatively high impurity concentration for attaining electrical contact with the electrode. - Though a P type diffusion region has been described as an example of the region formed to be in contact with the entire surface of inner sidewall of the trench isolation region, the structure having reverse conductivities may be possible. In that case, the N type diffusion region formed to be in contact with the inner sidewall of the trench isolation region includes a diffusion region to be a cathode in the case of a diode, and a diffusion region to be a collector in the case of a bipolar transistor.
- Here, a CMOS transistor will be described as an example, in which an n channel MOS transistor and a P channel MOS transistor are formed as semiconductor elements formed in the element forming region of the semiconductor device having the P type diffusion regions formed in contact with both the inner and outer sidewalls of the trench isolation region.
- As shown in
FIG. 19 , at the surface of N−layer 3 a surrounded by Ptype diffusion region 10 a and in the vicinity thereof, a Ptype well region 60 and an Ntype well region 61 are formed, respectively. On N−layer 3 a, an insulatingfilm 11 is formed to expose Ptype well region 60 and Ntype well region 61. In the exposed Ptype well region 60, N type source/drain regions drain regions gate electrode 68 is formed, with agate insulating film 66 interposed. By N type source/drain regions gate electrode 68, an n channel MOS transistor is formed. - In exposed N type well 61, P type source/
drain regions type well region 61 which is sandwiched between the source/drain regions gate electrode 69 is formed, with agate insulating film 67 interposed. By P type source/drain regions gate electrode 69, a p channel MOS transistor is formed. - Further, as shown in
FIG. 19 , Ptype well region 60 is continuous from Ptype diffusion region 10 a, and is electrically connected to Ptype diffusion region 10 a. In ptype well region 60, aP+ diffusion region 80 is formed, and toP+ diffusion region 80, anelectrode 75 for fixing the Ptype well region 60 and Ptype diffusion region 10 a to a prescribed potential is connected. As to the Ntype well region 61, a prescribed region and an electrode connected to the prescribed region (both not shown) are formed to fix the Ntype well region 61 to a prescribed potential. Except for these points, the structure is the same as that shown inFIG. 9 or 10, and therefore, same portions are denoted by the same reference characters and description thereof will not be repeated. - A semiconductor device having P
type well region 60 connected to Ptype diffusion region 10 a has been described. Next, as a modification, an example in which Ptype well region 60 is not connected but electrically isolated from Ptype diffusion region 10 a will be described. - First Modification
- Referring to
FIG. 20 , Ptype well region 60 is electrically isolated from Ptype diffusion region 10 a, that is, Ptype well region 60 a, by Ntype well region 61. More specifically, side portions of P type well 60 are surrounded by Ntype well region 61, and N−layer 3 a is positioned at the bottom of P type well 60. An electrode (not shown) for fixing the Ptype well region 60 to a prescribed potential is formed in Ptype well region 60, and an electrode (not shown) for fixing Ntype well region 61 to a prescribed potential is also formed in Ntype well region 61. - In the semiconductor device in accordance with the present modification, P
type well region 60 is not electrically connected to Ptype diffusion region 10a, and therefore, it can be fixed to a prescribed potential independent from the potential of Ptype diffusion region 10 a. - Second Modification
- A semiconductor device in which potentials of the P type well region, N type well region and P type diffusion region can be set independently, will specifically be described. Referring to
FIG. 21 , in Ptype well region 60,P+ diffusion region 81 is formed, and in Ntype well region 61,N+ diffusion region 82 is formed. In Ptype well region 60 a that is connected to Ptype diffusion region 10 a, aP+ diffusion region 80 is formed. - To
P+ diffusion region 81, anelectrode 76 for fixing Ptype well region 60 to a prescribed potential is connected; toN+ diffusion region 82, anelectrode 77 for fixing Ntype well region 61 to a prescribed potential is connected; and toP+ diffusion region 80, anelectrode 75 for fixing Ptype diffusion region 10 a to a prescribed potential is connected. - In the semiconductor device in accordance with the present modification, by applying prescribed potentials to
electrodes type well region 60, Ntype well region 61 and Ptype diffusion region 10 a can be set independently. - In the semiconductor devices in accordance with the twelfth embodiment, an example has been described in which a CMOS transistor is formed as the semiconductor element in the element forming region. In the semiconductor device having the CMOS transistor also,
trench isolation region 4 is electrically isolated from N−layer 3 as there is Ptype diffusion region 10 a betweentrench isolation region 4 and N−layer 3, and therefore, high electric field does not affecttrench isolation region 4. Therefore, reliability of the semiconductor device over a long time can be improved. - Particularly in a semiconductor device having elements of high breakdown voltage and low breakdown voltage, influence of high voltage to trench
isolation region 4 is suppressed even in such a pattern having an element of high breakdown voltage arranged adjacent to the element forming region in which a CMOS transistor of low breakdown voltage is formed, and therefore, sufficient reliability is attained. - A flash memory element will be described as an example of a semiconductor element formed in the element forming region of the semiconductor device in which the P type diffusion regions are formed to be in contact with the inner and outer sidewalls of the trench isolation region.
- As shown in
FIG. 22 , at the surface of N−layer 3 a surrounded by Ptype diffusion region 10 a and in the vicinity thereof, a Ptype well region 60 is formed. On N−layer 3 a, an insulatingfilm 11 is formed to expose a surface of Ptype well region 60. In the exposed Ptype well region 60, N type source/drain regions drain regions gate electrode portion 70 is formed, with agate insulating film 66 interposed.Gate electrode 70 is formed to have alower electrode 70 a formed ongate insulating film 66, adielectric film 70 b formed onlower electrode 70 a, and anupper electrode 70 c formed ondielectric film 70 b. - P
type well region 60 is continuous from Ptype diffusion region 10 a, and is electrically connected to Ptype diffusion region 10 a. On Ptype well region 60,P+ diffusion region 80 is formed, and toP+ diffusion region 80, anelectrode 75 for fixing Ptype well region 60 and Ptype diffusion region 10 a to a prescribed potential is connected. - In the semiconductor device, P
type well region 60 is continuous from Ptype diffusion region 10 a. As a modification, an example in which P type well 60 is not continuous from Ptype diffusion region 10 a and electrically isolated therefrom will be described. - First Modification
- As shown in
FIG. 23 , P type well 60 is electrically isolated from Ptype diffusion region 10 a and Ptype well region 60 a, by N type well 61. Specifically, side portions of Ptype well region 60 are surrounded by Ntype well region 61, and at the bottom of Ptype well region 60, N−layer 3 a is positioned. In Ptype well region 60,P+ diffusion region 81 is formed, and toP+ diffusion region 81, anelectrode 76 is connected for fixing Ptype well region 60 to a prescribed potential. - In the semiconductor device in accordance with the first modification, P
type well region 60 is not electrically connected to Ptype diffusion region 10 a, and byelectrode 76, it can be fixed to a prescribed potential independently from the potential of Ptype diffusion region 10 a. - Second Modification
- Here, a semiconductor device in which potentials of the P type well region and P type diffusion region can be set independently, will specifically be described. Referring to
FIG. 24 , in Ptype well region 60,P+ diffusion region 81 is formed, and in Ptype well region 60 continuous from Ptype diffusion region 10 a,P+ diffusion region 80 is formed. ToP+ diffusion region 81, anelectrode 76 for fixing Ptype well region 60 to a prescribed potential is connected, and toP+ diffusion region 80, anelectrode 75 for fixing Ptype diffusion region 10 a to a prescribed potential is connected. - In the semiconductor device in accordance with the present modification, by applying prescribed potentials to
electrodes type diffusion region 10 a can be set independently. Further, aselectrode 77 is connected throughN+ diffusion region 82 formed in N type well 61, N type well 61 can also be fixed at a prescribed potential. - In the semiconductor devices in accordance with the thirteenth embodiment, an example has been described in which a flash memory element is formed as a semiconductor element in the element forming region. In the semiconductor device having the flash memory element also,
trench isolation region 4 is electrically isolated from N−layer 3 as the P type diffusion region 10 is positioned betweentrench isolation region 4 and N−layer 3. Therefore, high electric field does not affecttrench isolation region 4, and reliability of the semiconductor device over a long time can be improved. - Particularly in a semiconductor device having elements of high breakdown voltage and low breakdown voltage, influence of high voltage to trench
isolation region 4 is suppressed even in such a pattern having an element that receives a voltage higher than that applied to the flash memory element arranged adjacent to the element forming region in which a flash memory element is formed, and therefore, sufficient reliability is attained. - It is noted that numerical values such as film thickness and implantation condition mentioned in various embodiments are examples only and not limiting.
- Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.
Claims (15)
1. A semiconductor device, comprising:
an insulating film formed on a main surface of a prescribed substrate;
a semiconductor layer of a first conductivity type formed on said insulating film;
an isolation region, continuously surrounding a prescribed region to be an element forming region in said semiconductor layer, formed from the surface of said semiconductor layer to a surface of said insulating film and having an inner sidewall and an outer sidewall; and
a first impurity region of a second conductivity type formed continuously to be in contact with an entire surface of said inner sidewall of said isolation region, positioned between a portion of said semiconductor layer positioned in said prescribed region and said isolation region.
2. The semiconductor device according to claim 1 , further comprising
a first electrode formed to be electrically connected to said first impurity region for holding said first impurity region at a prescribed potential.
3. The semiconductor device according to claim 1 , further comprising
another prescribed region to be another element forming region positioned outside said isolating region in said semiconductor layer; and
a second impurity region of the second conductivity type formed to be in contact with an entire surface of said outer sidewall of said isolation region, and positioned between a portion of said semiconductor layer positioned in said another prescribed region and said isolation region.
4. The semiconductor device according to claim 3 , further comprising
a second electrode formed to be electrically connected to said second impurity region for holding said second impurity region at a prescribed potential.
5. The semiconductor device according to claim 1 , further comprising
an element formed in said prescribed region.
6. The semiconductor device according to claim 5 , wherein
said element formed in said region is a transistor including
a source region,
a drain region
a body region to be a channel, and
a gate formed on said body region with a gate insulating film interposed; and
said first impurity region includes either said body region or said drain region.
7. The semiconductor device according to claim 5 , wherein
said element formed in said region is a diode including
a cathode region, and
an anode region; wherein
said first impurity region includes either said anode region or said cathode region.
8. The semiconductor device according to claim 5 , wherein
said element formed in said region is a bipolar transistor, including
an emitter region,
a collector region, and
a base region; wherein
said first impurity region includes either said base region or said collector region.
9. The semiconductor device according to claim 1 , wherein
said first impurity region is formed to have a prescribed impurity concentration so that an end of a depletion layer extending from an interface between said first impurity region and a portion of said semiconductor layer positioned in said prescribed region does not reach said isolation region during an operation.
10. The semiconductor device according to claim 5 , wherein
said first impurity region has an impurity concentration set to be higher than that of said element forming region.
11. The semiconductor device according to claim 5 , further comprising:
a well region formed in said prescribed region and having at least one of said first conductivity type and said second conductivity type-, and
another insulating film formed on said semiconductor layer to expose a surface of said well region; wherein
as said element, a transistor including
source and drain regions of opposite conductivity type to said well region, and
a gate electrode portion is formed in said exposed well region.
12. The semiconductor device according to claim 11 , wherein
said gate electrode portion includes
a lower electrode,
a dielectric film formed on said lower electrode, and
an upper electrode formed on said dielectric film.
13. A method of manufacturing a semiconductor device, comprising the steps of
on a semiconductor layer of a first conductivity type formed on a prescribed
substrate with an insulating film interposed, forming a trench to continuously surround a region to be an element forming region and to expose a surface of said insulating film;
on an entire surface of that portion of said semiconductor layer exposed in said trench, which is at least on the side where the prescribed region is positioned, introducing an impurity of a second conductivity type, so as to form a first impurity region of the second conductivity type; and
filling said trench with an insulating material.
14. The method of manufacturing a semiconductor device according to claim 13 , further comprising the step of
forming a prescribed element by introducing a prescribed amount of impurity to said region to be the element forming region; wherein
in said step of forming the first impurity region, an impurity of a larger amount than said prescribed amount is introduced.
15. The method of manufacturing a semiconductor device according to claim 13 , wherein
said step of forming said first impurity region includes the step of introducing an impurity by oblique ion implantation.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/401,889 US8030730B2 (en) | 2004-06-22 | 2009-03-11 | Semiconductor device and manufacturing method thereof |
US13/095,352 US20110198726A1 (en) | 2004-06-22 | 2011-04-27 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004183365 | 2004-06-22 | ||
JP2004-183365(P) | 2004-06-22 | ||
JP2005-125243(P) | 2005-04-22 | ||
JP2005125243A JP4974474B2 (en) | 2004-06-22 | 2005-04-22 | Semiconductor device and manufacturing method thereof |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/401,889 Division US8030730B2 (en) | 2004-06-22 | 2009-03-11 | Semiconductor device and manufacturing method thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
US20050282375A1 true US20050282375A1 (en) | 2005-12-22 |
Family
ID=35481166
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/152,790 Abandoned US20050282375A1 (en) | 2004-06-22 | 2005-06-15 | Semiconductor device and manufacturing method thereof |
US12/401,889 Expired - Fee Related US8030730B2 (en) | 2004-06-22 | 2009-03-11 | Semiconductor device and manufacturing method thereof |
US13/095,352 Abandoned US20110198726A1 (en) | 2004-06-22 | 2011-04-27 | Semiconductor device and manufacturing method thereof |
Family Applications After (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/401,889 Expired - Fee Related US8030730B2 (en) | 2004-06-22 | 2009-03-11 | Semiconductor device and manufacturing method thereof |
US13/095,352 Abandoned US20110198726A1 (en) | 2004-06-22 | 2011-04-27 | Semiconductor device and manufacturing method thereof |
Country Status (2)
Country | Link |
---|---|
US (3) | US20050282375A1 (en) |
JP (1) | JP4974474B2 (en) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060017096A1 (en) * | 2004-07-26 | 2006-01-26 | Kabushiki Kaisha Toshiba | Semiconductor device |
US20070210408A1 (en) * | 2006-03-10 | 2007-09-13 | Atsuo Watanabe | Dielectric material separated-type, high breakdown voltage semiconductor circuit device, and production method thereof |
US20090200610A1 (en) * | 2004-06-22 | 2009-08-13 | Renesas Technology Corporation | Semiconductor device and manufacturing method thereof |
US20100075484A1 (en) * | 2006-06-27 | 2010-03-25 | Stmicroelectronics S.R.L. | Soi device with contact trenches formed during epitaxial growing |
CN102376776A (en) * | 2010-08-26 | 2012-03-14 | 上海华虹Nec电子有限公司 | Parasitic PIN(positive-intrinsic negative) diode in BiCMOS(Bipolar Complementary Metal Oxide Semiconductor) process, and manufacturing method thereof |
US20140035092A1 (en) * | 2007-03-11 | 2014-02-06 | Skyworks Solutions, Inc. | Radio frequency isolation for soi transistors |
ITUA20161531A1 (en) * | 2016-03-10 | 2017-09-10 | St Microelectronics Srl | DIODE WITH REDUCED RECOVERY TIME FOR APPLICATIONS SUBJECT TO THE CURRENT RECIRCULATION PHENOMENON AND / OR TO RAPID VOLTAGE VARIATIONS |
US10236378B2 (en) | 2016-08-30 | 2019-03-19 | Stmicroelectronics S.R.L. | Electronic junction device with a reduced recovery time for applications subject to the current recirculation phenomenon and related manufacturing process |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4610982B2 (en) * | 2003-11-11 | 2011-01-12 | シャープ株式会社 | Manufacturing method of semiconductor device |
JP5410012B2 (en) * | 2007-09-28 | 2014-02-05 | ローム株式会社 | Semiconductor device |
US7999320B2 (en) * | 2008-12-23 | 2011-08-16 | International Business Machines Corporation | SOI radio frequency switch with enhanced signal fidelity and electrical isolation |
US20110198689A1 (en) * | 2010-02-17 | 2011-08-18 | Suku Kim | Semiconductor devices containing trench mosfets with superjunctions |
JP5636827B2 (en) * | 2010-08-31 | 2014-12-10 | 株式会社デンソー | Semiconductor device |
US8399957B2 (en) | 2011-04-08 | 2013-03-19 | International Business Machines Corporation | Dual-depth self-aligned isolation structure for a back gate electrode |
JP5739767B2 (en) * | 2011-08-23 | 2015-06-24 | 株式会社東芝 | Dielectric separation substrate and semiconductor device |
US9040384B2 (en) * | 2012-10-19 | 2015-05-26 | Freescale Semiconductor, Inc. | High voltage diode |
JP6132539B2 (en) * | 2012-12-13 | 2017-05-24 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
JP6355481B2 (en) * | 2014-08-25 | 2018-07-11 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
JP6137208B2 (en) * | 2015-01-26 | 2017-05-31 | トヨタ自動車株式会社 | Semiconductor device |
JP7193053B2 (en) | 2018-07-18 | 2022-12-20 | 株式会社東海理化電機製作所 | Semiconductor device and its manufacturing method |
JP2020191413A (en) * | 2019-05-23 | 2020-11-26 | 株式会社東海理化電機製作所 | Semiconductor device |
JP2020191412A (en) * | 2019-05-23 | 2020-11-26 | 株式会社東海理化電機製作所 | Semiconductor device and method of manufacturing the same |
JP7368121B2 (en) | 2019-06-20 | 2023-10-24 | ローム株式会社 | Semiconductor device and semiconductor device manufacturing method |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6242763B1 (en) * | 1999-09-14 | 2001-06-05 | United Microelectronics Corp. | Low triggering voltage SOI silicon-control-rectifier (SCR) structure |
US6429502B1 (en) * | 2000-08-22 | 2002-08-06 | Silicon Wave, Inc. | Multi-chambered trench isolated guard ring region for providing RF isolation |
US6987303B2 (en) * | 2002-04-10 | 2006-01-17 | Taiwan Semicondcutor Manufacturing Co., Ltd. | Silicon-controlled rectifier structures on silicon-on insulator with shallow trench isolation |
US7041572B2 (en) * | 2002-10-25 | 2006-05-09 | Vanguard International Semiconductor Corporation | Fabrication method for a deep trench isolation structure of a high-voltage device |
Family Cites Families (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS53127282A (en) * | 1977-04-13 | 1978-11-07 | Shindengen Electric Mfg | Semiconductor |
JP2878689B2 (en) * | 1988-07-04 | 1999-04-05 | 株式会社東芝 | High voltage semiconductor device |
US5343067A (en) | 1987-02-26 | 1994-08-30 | Kabushiki Kaisha Toshiba | High breakdown voltage semiconductor device |
US5241210A (en) | 1987-02-26 | 1993-08-31 | Kabushiki Kaisha Toshiba | High breakdown voltage semiconductor device |
JPH04123456A (en) * | 1990-09-14 | 1992-04-23 | Hitachi Ltd | Semiconductor device and manufacture thereof |
JP3293871B2 (en) * | 1991-01-31 | 2002-06-17 | 株式会社東芝 | High voltage semiconductor device |
JPH0629375A (en) * | 1992-07-10 | 1994-02-04 | Fujitsu Ltd | Semiconductor device and its production |
EP0597266A2 (en) * | 1992-11-10 | 1994-05-18 | Siemens Aktiengesellschaft | Process of manufacturing an isolation structure on a substrate |
US5943578A (en) | 1993-02-05 | 1999-08-24 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor device having an element isolating region |
DE4335298C1 (en) | 1993-10-15 | 1995-03-23 | Siemens Ag | Circuit structure with at least one bipolar power component and method for its operation |
US5646063A (en) | 1996-03-28 | 1997-07-08 | Advanced Micro Devices, Inc. | Hybrid of local oxidation of silicon isolation and trench isolation for a semiconductor device |
JPH11251564A (en) * | 1998-02-27 | 1999-09-17 | Unisia Jecs Corp | Semiconductor device |
US6355537B1 (en) | 1999-02-23 | 2002-03-12 | Silicon Wave, Inc. | Method of providing radio frequency isolation of device mesas using guard ring regions within an integrated circuit device |
JP2001044437A (en) | 1999-07-27 | 2001-02-16 | Matsushita Electronics Industry Corp | Mos transistor and manufacture thereof |
JP4765157B2 (en) * | 1999-11-17 | 2011-09-07 | 株式会社デンソー | Manufacturing method of semiconductor substrate |
TW445575B (en) | 2000-05-20 | 2001-07-11 | Nanya Technology Corp | Dynamic random access memory with guard ring and its manufacture method |
JP2001345377A (en) * | 2000-06-01 | 2001-12-14 | Unisia Jecs Corp | Semiconductor device |
US20050090073A1 (en) | 2000-12-20 | 2005-04-28 | Actel Corporation, A California Corporation | MOS transistor having improved total radiation-induced leakage current |
US20050090047A1 (en) | 2000-12-20 | 2005-04-28 | Actel Corporation, A California Corporation. | Method of making a MOS transistor having improved total radiation-induced leakage current |
TW483176B (en) | 2001-05-31 | 2002-04-11 | United Microelectronics Corp | Method for decreasing leakage current of photodiode |
JP2003017704A (en) * | 2001-06-29 | 2003-01-17 | Denso Corp | Semiconductor device |
KR100414735B1 (en) | 2001-12-10 | 2004-01-13 | 주식회사 하이닉스반도체 | A semiconductor device and A method for forming the same |
JP2003179131A (en) * | 2001-12-11 | 2003-06-27 | Matsushita Electric Ind Co Ltd | Semiconductor device |
JP4139105B2 (en) | 2001-12-20 | 2008-08-27 | 株式会社ルネサステクノロジ | Manufacturing method of semiconductor device |
US6518146B1 (en) | 2002-01-09 | 2003-02-11 | Motorola, Inc. | Semiconductor device structure and method for forming |
JP2004031505A (en) * | 2002-06-24 | 2004-01-29 | Denso Corp | Method for manufacturing bipolar transistor |
JP2004228466A (en) | 2003-01-27 | 2004-08-12 | Renesas Technology Corp | Integrated semiconductor device and manufacturing method therefor |
US6949445B2 (en) | 2003-03-12 | 2005-09-27 | Micron Technology, Inc. | Method of forming angled implant for trench isolation |
US7851860B2 (en) | 2004-03-26 | 2010-12-14 | Honeywell International Inc. | Techniques to reduce substrate cross talk on mixed signal and RF circuit design |
JP4974474B2 (en) | 2004-06-22 | 2012-07-11 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
-
2005
- 2005-04-22 JP JP2005125243A patent/JP4974474B2/en not_active Expired - Fee Related
- 2005-06-15 US US11/152,790 patent/US20050282375A1/en not_active Abandoned
-
2009
- 2009-03-11 US US12/401,889 patent/US8030730B2/en not_active Expired - Fee Related
-
2011
- 2011-04-27 US US13/095,352 patent/US20110198726A1/en not_active Abandoned
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6242763B1 (en) * | 1999-09-14 | 2001-06-05 | United Microelectronics Corp. | Low triggering voltage SOI silicon-control-rectifier (SCR) structure |
US6429502B1 (en) * | 2000-08-22 | 2002-08-06 | Silicon Wave, Inc. | Multi-chambered trench isolated guard ring region for providing RF isolation |
US6987303B2 (en) * | 2002-04-10 | 2006-01-17 | Taiwan Semicondcutor Manufacturing Co., Ltd. | Silicon-controlled rectifier structures on silicon-on insulator with shallow trench isolation |
US7041572B2 (en) * | 2002-10-25 | 2006-05-09 | Vanguard International Semiconductor Corporation | Fabrication method for a deep trench isolation structure of a high-voltage device |
Cited By (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110198726A1 (en) * | 2004-06-22 | 2011-08-18 | Renesas Electronic Corporation | Semiconductor device and manufacturing method thereof |
US20090200610A1 (en) * | 2004-06-22 | 2009-08-13 | Renesas Technology Corporation | Semiconductor device and manufacturing method thereof |
US8030730B2 (en) | 2004-06-22 | 2011-10-04 | Renesas Electronics Corporation | Semiconductor device and manufacturing method thereof |
US7564107B2 (en) * | 2004-07-26 | 2009-07-21 | Kabushiki Kaisha Toshiba | Power semiconductor device including a terminal structure |
US20060017096A1 (en) * | 2004-07-26 | 2006-01-26 | Kabushiki Kaisha Toshiba | Semiconductor device |
US20070210408A1 (en) * | 2006-03-10 | 2007-09-13 | Atsuo Watanabe | Dielectric material separated-type, high breakdown voltage semiconductor circuit device, and production method thereof |
US7982266B2 (en) * | 2006-03-10 | 2011-07-19 | Hitachi, Ltd. | Dielectric material separated-type, high breakdown voltage semiconductor circuit device, and production method thereof |
US20100075484A1 (en) * | 2006-06-27 | 2010-03-25 | Stmicroelectronics S.R.L. | Soi device with contact trenches formed during epitaxial growing |
EP2264753A3 (en) * | 2006-06-27 | 2011-04-20 | STMicroelectronics S.r.l. | Integrated device with both SOI insulation and junction insulation and manufacturing method |
US8183098B2 (en) | 2006-06-27 | 2012-05-22 | Stmicroelectronics S.R.L. | SOI device with contact trenches formed during epitaxial growing |
US20140035092A1 (en) * | 2007-03-11 | 2014-02-06 | Skyworks Solutions, Inc. | Radio frequency isolation for soi transistors |
US9548351B2 (en) * | 2007-03-11 | 2017-01-17 | Skyworks Solutions, Inc. | Radio frequency isolation for SOI transistors |
US20170154964A1 (en) * | 2007-03-11 | 2017-06-01 | Skyworks Solutions, Inc. | Radio frequency isolation for soi transistors |
US10453928B2 (en) * | 2007-03-11 | 2019-10-22 | Skyworks Solutions, Inc. | Radio frequency isolation for SOI transistors |
CN102376776A (en) * | 2010-08-26 | 2012-03-14 | 上海华虹Nec电子有限公司 | Parasitic PIN(positive-intrinsic negative) diode in BiCMOS(Bipolar Complementary Metal Oxide Semiconductor) process, and manufacturing method thereof |
ITUA20161531A1 (en) * | 2016-03-10 | 2017-09-10 | St Microelectronics Srl | DIODE WITH REDUCED RECOVERY TIME FOR APPLICATIONS SUBJECT TO THE CURRENT RECIRCULATION PHENOMENON AND / OR TO RAPID VOLTAGE VARIATIONS |
US9911869B2 (en) | 2016-03-10 | 2018-03-06 | Stmicroelectronics S.R.L. | Diode with reduced recovery time for applications subject to the current recirculation phenomenon and/or to fast voltage variations |
US10236378B2 (en) | 2016-08-30 | 2019-03-19 | Stmicroelectronics S.R.L. | Electronic junction device with a reduced recovery time for applications subject to the current recirculation phenomenon and related manufacturing process |
US10535767B2 (en) | 2016-08-30 | 2020-01-14 | Stmicroelectronics S.R.L. | Electronic junction device with a reduced recovery time for applications subject to the current recirculation phenomenon and related manufacturing process |
Also Published As
Publication number | Publication date |
---|---|
JP4974474B2 (en) | 2012-07-11 |
JP2006041476A (en) | 2006-02-09 |
US8030730B2 (en) | 2011-10-04 |
US20090200610A1 (en) | 2009-08-13 |
US20110198726A1 (en) | 2011-08-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8030730B2 (en) | Semiconductor device and manufacturing method thereof | |
KR0178824B1 (en) | Semiconductor device and manufacturing method of the same | |
US6437405B2 (en) | Silicon-on-insulator (SOI) substrate, method for fabricating SOI substrate and SOI MOSFET using the SOI substrate | |
US6794716B2 (en) | SOI MOSFET having body contact for preventing floating body effect and method of fabricating the same | |
USRE41368E1 (en) | High voltage SOI semiconductor device | |
US6297534B1 (en) | Power semiconductor device | |
KR100780967B1 (en) | Structure of schottky diode for high voltage | |
US5294825A (en) | High breakdown voltage semiconductor device | |
JPH04146674A (en) | Semiconductor device and manufacture thereof | |
US7323747B2 (en) | Lateral semiconductor device | |
JP2001102586A (en) | High breakdown voltage semiconductor device | |
US6815794B2 (en) | Semiconductor devices with multiple isolation structure and methods for fabricating the same | |
US20040097019A1 (en) | Semiconductor component and method of manufacturing | |
US20100270613A1 (en) | Method for manufacturing semiconductor device, and semiconductor device | |
JP3354127B2 (en) | High voltage element and method of manufacturing the same | |
US6914270B2 (en) | IGBT with PN insulation and production method | |
KR20130007474A (en) | Semiconductor device | |
US6486512B2 (en) | Power semiconductor device having high breakdown voltage and method for fabricating the same | |
JP3189456B2 (en) | SOI semiconductor device | |
US6525392B1 (en) | Semiconductor power device with insulated circuit | |
KR100518506B1 (en) | Trench gate power mos device and fabricating method therefor | |
JP5092202B2 (en) | Semiconductor device | |
CN112054061B (en) | Body contact structure of partially depleted silicon on insulator and manufacturing method thereof | |
US8008664B2 (en) | Component comprising a thin-film transistor and CMOS-transistors and methods for production | |
JP2000058869A (en) | Semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: RENESAS TECHNOLOGY CORP., JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:NITTA, TETSUYA;IGARASHI, TAKAYUKI;REEL/FRAME:016896/0279 Effective date: 20050729 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |