CN102376776A - Parasitic PIN(positive-intrinsic negative) diode in BiCMOS(Bipolar Complementary Metal Oxide Semiconductor) process, and manufacturing method thereof - Google Patents
Parasitic PIN(positive-intrinsic negative) diode in BiCMOS(Bipolar Complementary Metal Oxide Semiconductor) process, and manufacturing method thereof Download PDFInfo
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- CN102376776A CN102376776A CN201010265370XA CN201010265370A CN102376776A CN 102376776 A CN102376776 A CN 102376776A CN 201010265370X A CN201010265370X A CN 201010265370XA CN 201010265370 A CN201010265370 A CN 201010265370A CN 102376776 A CN102376776 A CN 102376776A
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Abstract
The invention discloses a parasitic PIN(positive-intrinsic negative) diode in a BiCMOS(Bipolar Complementary Metal Oxide Semiconductor) process, comprising an N type region, an I type region and a P type region, wherein the I type region is composed of multiple N type collector injection regions formed in multiple adjacent active regions; the N type region is composed of an N type buried layer formed at the bottom of a shallow trench isolation oxide layer on the side of the I type region; the P type region is composed of multiple base region epitaxial layers and multiple P type buried layers; the base region epitaxial layers are respectively formed on the top surfaces of the active regions in the I type region; and each P type buried layer is formed on the bottom and side wall of the shallow trench isolation oxide layer in the I type region. The invention also discloses a manufacturing method of the parasitic PIN diode in the BiCMOS process. The invention realizes the aim of providing one more device choice for a circuit without additional process conditions, lower insertion loss and higher isolation are achieved, and the forward on state current of the device is increased and the insertion loss of the device improved while the device area is not increased.
Description
Technical field
The present invention relates to semiconductor integrated circuit and make the field, particularly relate to the parasitic PIN diode in a kind of BiCMOS technology; The invention still further relates to the manufacturing approach of the parasitic PIN diode in a kind of BiCMOS technology.
Background technology
Bipolar transistor (Bipolar Transistor) in the existing BiCMOS technology adopts highly doped collector region buried regions; To reduce collector region resistance; Adopt high concentration high-energy N type to inject, connect the collector region buried regions, form collector terminal (collector pick-up).The low-doped collector region in outer Yanzhong on the collector region buried regions, the extension that P type on the throne mixes forms the base, and N type heavily doped polysilicon constitutes emitter then, finally accomplishes the making of Bipolar Transistor.The parasitic PIN diode of existing BiCMOS technology manufacturing will take bigger device area, and manufacturing cost also increases greatly.For forward conduction electric current that increases existing parasitic PIN diode and the insertion loss that improves device, what prior art adopted improves one's methods: the Impurity Distribution of an adjustment device; Two through increasing the area of device.It is very limited wherein increasing device forward conduction method of current through adjustment device Impurity Distribution.And the increase device area is very disadvantageous beyond doubt for entire circuit, manufactures from semiconductor and says originally, increases the increase that device area also means cost.
Summary of the invention
Technical problem to be solved by this invention provides the parasitic PIN diode in a kind of BiCMOS technology; Need not extra process conditions just can be embodied as circuit and provide many a kind of devices to select; And can obtain lower insertion loss and higher isolation; Can be under the situation that does not increase device area, increase the forward conduction electric current of device and improve the insertion loss of device; For this reason, the present invention also provides the manufacturing approach of the parasitic PIN diode in a kind of BiCMOS technology.
For solving the problems of the technologies described above; Parasitic PIN diode in the BiCMOS technology provided by the invention; Be formed on the P type silicon substrate, active area is isolated through the shallow trench isolating oxide layer, and said parasitic PIN diode comprises: a N type district, an I type district and a p type island region.
Said I type district is by being formed in a plurality of adjacent active areas and interconnected a plurality of N type collector electrodes injection region is formed, and the degree of depth of each said N type collector electrode injection region all extends into bottom the said shallow trench isolating oxide layer of each said N type collector electrode injection region side and realizes the connection of whole said N type collector electrodes injection region greater than the bottom of the degree of depth of said shallow trench isolating oxide layer, each said N type collector electrode injection region.The implanted dopant of the collector electrode injection region in said I type district is that phosphorus or arsenic, implantation dosage are 1e12cm
-2～1e15cm
-2, the injection energy is 100KeV～2000KeV.The quantity that forms said a plurality of adjacent active areas in said I type district is more than 2, and the arrangement architecture of said a plurality of adjacent active areas is transversely arranged or vertically arranges.
Said N type district is made up of the counterfeit buried regions of N type of the said shallow trench isolating oxide layer bottom that is formed at said I type district side; The counterfeit buried regions of said N type is that N type ion implanted region also contacts with the formation of said I type district; In the said shallow trench isolating oxide layer at the counterfeit buried regions of said N type top, be formed with the deep hole contact, said deep hole contact is used to draw said N type district.The implantation dosage that the N type ion of the counterfeit buried regions of said N type injects is 1e14cm
-2～1e16cm
-2, to inject energy be phosphorus or arsenic or antimony less than 30KeV, implanted dopant.
Said p type island region is made up of a plurality of base epitaxial layer and the counterfeit buried regions of a plurality of P types; Each said base epitaxial layer is formed at each said adjacent top part of active area surface that said I type district covered and is mixed with p type impurity; The counterfeit buried regions of each said P type is a P type ion implanted region; The counterfeit buried regions of each said P type is formed in the said N type collector electrode injection region of bottom and sidewall of the said shallow trench isolating oxide layer between each said adjacent active area that said I type district covered, and the counterfeit buried regions of each said P type is connected through each said base epitaxial layer formation adjacent with it of its sidewall sections; In the said shallow trench isolating oxide layer at each said P type buried layer top, be formed with the deep hole contact and be formed with Metal Contact at the top of each said base epitaxial layer, each said deep hole contact is used to draw said p type island region with each said Metal Contact.Silicon epitaxy or germanium and silicon epitaxial or germanium silicon-carbon extension that the said base epitaxial layer of each of said p type island region is mixed for the P type; It is to mix to inject with the outer base area ion through P type on the throne to form that the P type of each said base epitaxial layer mixes, and the implanted dopant of said outer base area ion injection is that boron or boron fluoride, implantation dosage are 1e14cm
-2～1e15cm
-2, the injection energy is 2KeV～30KeV.The implantation dosage that the P type ion of the counterfeit buried regions of the said P type of each of said p type island region injects is 1e14cm
-2～1e16cm
-2, to inject energy be boron or boron fluoride less than 30KeV, implanted dopant, the implant angle that the P type ion of the counterfeit buried regions of each said P type injects will guarantee to form the sidewall sections of the counterfeit buried regions of each said P type and can make the concentration of the sidewall sections of the counterfeit buried regions of each said P type is 1e19cm
-3More than.
For solving the problems of the technologies described above, the manufacturing approach of the parasitic PIN diode in the BiCMOS technology provided by the invention comprises the steps:
Step 1, utilize the shallow trench etching technics on a P type silicon substrate, to form shallow trench, and by said shallow trench isolation from going out active area; On the sidewall of said shallow trench, form side wall.
Step 2, carry out N type ion in the bottom of the said shallow trench of the side in I type district and inject and form the counterfeit buried regions of N type, form N type district by the counterfeit buried regions of said N type.The implantation dosage that the N type ion of the counterfeit buried regions of said N type injects is 1e14cm
-2～1e16cm
-2, to inject energy be phosphorus or arsenic or antimony less than 30KeV, implanted dopant.
Step 3, remove the side wall on the sidewall of said shallow trench, and the bottom of the said shallow trench between each said adjacent active area in said I type district carries out the injection of P type ion with sidewall, form the counterfeit buried regions of a plurality of P types.The implantation dosage that the P type ion of the counterfeit buried regions of the said P type of each of said p type island region injects is 1e14cm
-2～1e16cm
-2, to inject energy be boron or boron fluoride less than 30KeV, implanted dopant, the implant angle that the P type ion of the counterfeit buried regions of each said P type injects will guarantee to form the sidewall sections of the counterfeit buried regions of each said P type and can make the concentration of the sidewall sections of the counterfeit buried regions of each said P type is 1e19cm
-3More than.
Step 4, in said shallow trench, insert silica and form the shallow trench isolating oxide layer.
Step 5, in a plurality of adjacent active area that forms said I type district, carry out N type collector electrode and inject and form a plurality of N type collector electrodes injection region, said I type district is formed in said a plurality of N type collector electrodes injection region; The degree of depth of each said N type collector electrode injection region all extends into the said shallow trench isolating oxide layer bottom of each said N type collector electrode injection region side and realizes the connection of whole said N type collector electrodes injection region greater than the degree of depth of said shallow trench isolating oxide layer, the bottom of each said N type collector electrode injection region; Each said N type collector electrode injection region coat fully the counterfeit buried regions of said N type, the counterfeit buried regions of each said P type and and the counterfeit buried regions of said N type, the counterfeit buried regions of each said P type contact.The implanted dopant of the collector electrode injection region in said I type district is that phosphorus or arsenic, implantation dosage are 1e12cm
-2～1e15cm
-2, the injection energy is 100KeV～2000KeV.The quantity that forms said a plurality of adjacent active areas in said I type district is more than 2, and the arrangement architecture of said a plurality of adjacent active areas is transversely arranged or vertically arranges.
Step 6, said silicon substrate is carried out thermal annealing, realize that the annealing in said N type district, the counterfeit buried regions of each said P type, said I type district advances.
Step 7, on said surface of silicon, form an intrinsic base region epitaxial loayer, and the definition ion injects window, injects window through said ion and the outer base area ion that is formed at said intrinsic base region epitaxial loayer on each the said surfaces of active regions in the said I type district and carries out the P type is injected form a plurality of base epitaxial layer on each the said active area in said I type district; The sidewall sections of the counterfeit buried regions of adjacent each the said P type with it of each said base epitaxial layer contacts; Said a plurality of base epitaxial layer and the counterfeit buried regions of said a plurality of P types form said p type island region.Silicon epitaxy or germanium and silicon epitaxial or germanium silicon-carbon extension that the said base epitaxial layer of each of said p type island region is mixed for the P type; It is to mix to inject with the outer base area ion through P type on the throne to form that the P type of each said base epitaxial layer mixes, and the implanted dopant of said outer base area ion injection is that boron or boron fluoride, implantation dosage are 1e14cm
-2～1e15cm
-2, the injection energy is 2KeV～30KeV.
Step 8, in the said shallow trench isolating oxide layer at the counterfeit buried regions of said N type top, form the deep hole contact and draw said N type district; In the said shallow trench isolating oxide layer at each said P type buried layer top, form the deep hole contact and form Metal Contact and draw said p type island region at the top of each said base epitaxial layer.
The shallow trench isolation that the inventive method relates in the BiCMOS technology injects from the counterfeit buried regions of heavy doping, collector region injection, intrinsic base region epitaxial growth and the outer base area that are said shallow trench isolating oxide layer bottom; Need not extra process conditions and just can be embodied as circuit and provide many a kind of devices to select, and can obtain lower insertion loss and higher isolation.Device of the present invention is through carrying out P type high dose, low-energy injection and form the counterfeit buried regions of P type and linking to each other with the heavily doped base epitaxial layer of P type that surfaces of active regions forms from bottom and side at shallow trench isolation; The heavily doped p type island region of forming device with counterfeit buried regions of P type and base epitaxial layer together; Make the device of p type island region with respect to only utilizing base epitaxial layer; Device of the present invention can increase the surface area of p type island region greatly, thereby increases the forward conduction electric current of device, improves the insertion loss of device.
Description of drawings
Below in conjunction with accompanying drawing and embodiment the present invention is done further detailed explanation:
Fig. 1 is the device sectional view of the parasitic PIN diode in the embodiment of the invention BiCMOS technology;
Fig. 2-Fig. 6 is the device sectional view in each step of manufacturing approach of the parasitic PIN diode in the embodiment of the invention BiCMOS technology;
Fig. 7 is the I type district plan structure figure of the parasitic PIN diode in the embodiment of the invention BiCMOS technology.
Embodiment
As shown in Figure 1, be the device sectional view of the parasitic PIN diode in the embodiment of the invention BiCMOS technology.Parasitic PIN diode in the embodiment of the invention BiCMOS technology is formed on the P type silicon substrate, and active area is isolated through the shallow trench isolating oxide layer, and said parasitic PIN diode comprises: a N type district, an I type district and a p type island region.
Said I type district is by being formed in a plurality of adjacent active areas and interconnected a plurality of N type collector electrodes injection region is formed, and the degree of depth of each said N type collector electrode injection region all extends into bottom the said shallow trench isolating oxide layer of each said N type collector electrode injection region side and realizes the connection of whole said N type collector electrodes injection region greater than the bottom of the degree of depth of said shallow trench isolating oxide layer, each said N type collector electrode injection region.The implanted dopant of the collector electrode injection region in said I type district is that phosphorus or arsenic, implantation dosage are 1e12cm
-2～1e15cm
-2, the injection energy is 100KeV～2000KeV.As shown in Figure 7; The quantity that the embodiment of the invention forms said a plurality of adjacent active areas in said I type district is more than 2; The arrangement architecture of said a plurality of adjacent active areas is the two-dimensional structure of transversely arranged and vertical arrangement, and it is that shallow trench isolation shown in Figure 7 leaves that 4 said shallow trench isolating oxide layers are arranged between said a plurality of adjacent active areas.
Said N type district is made up of the counterfeit buried regions of N type of the said shallow trench isolating oxide layer bottom that is formed at said I type district side; The counterfeit buried regions of said N type is that N type ion implanted region also contacts with the formation of said I type district; In the said shallow trench isolating oxide layer at the counterfeit buried regions of said N type top, be formed with the deep hole contact, said deep hole contact is used to draw said N type district.The implantation dosage that the N type ion of the counterfeit buried regions of said N type injects is 1e14cm
-2～1e16cm
-2, to inject energy be phosphorus or arsenic or antimony less than 30KeV, implanted dopant.
Said p type island region is that part and the counterfeit buried regions of a plurality of P types that outer base area shown in Figure 1 injects institute's mark formed by a plurality of base epitaxial layer.Each said base epitaxial layer is formed at each said adjacent top part of active area surface that said I type district covered and is mixed with p type impurity.The counterfeit buried regions of each said P type is a P type ion implanted region; The counterfeit buried regions of each said P type is formed in the said N type collector electrode injection region of bottom and sidewall of the said shallow trench isolating oxide layer between each said adjacent active area that said I type district covered, and the counterfeit buried regions of each said P type is connected through each said base epitaxial layer formation adjacent with it of its sidewall sections.In the said shallow trench isolating oxide layer at each said P type buried layer top, be formed with the deep hole contact and be formed with Metal Contact at the top of each said base epitaxial layer, each said deep hole contact is used to draw said p type island region with each said Metal Contact.Silicon epitaxy or germanium and silicon epitaxial or germanium silicon-carbon extension that the said base epitaxial layer of each of said p type island region is mixed for the P type; It is to mix to inject with the outer base area ion through P type on the throne to form that the P type of each said base epitaxial layer mixes, and the implanted dopant of said outer base area ion injection is that boron or boron fluoride, implantation dosage are 1e14cm
-2～1e15cm
-2, the injection energy is 2KeV～30KeV.The implantation dosage that the P type ion of the counterfeit buried regions of the said P type of each of said p type island region injects is 1e14cm
-2～1e16cm
-2, to inject energy be boron or boron fluoride less than 30KeV, implanted dopant, the implant angle that the P type ion of the counterfeit buried regions of each said P type injects will guarantee to form the sidewall sections of the counterfeit buried regions of each said P type and can make the concentration of the sidewall sections of the counterfeit buried regions of each said P type is 1e19cm
-3More than.
To shown in Figure 6, is the device sectional view in each step of manufacturing approach of the parasitic PIN diode in the embodiment of the invention BiCMOS technology like Fig. 2.The manufacturing approach of the parasitic PIN diode in the embodiment of the invention BiCMOS technology comprises the steps:
Step 1, as shown in Figure 2 utilizes the shallow trench etching technics on a P type silicon substrate, to form shallow trench, and by said shallow trench isolation from going out active area; On the sidewall of said shallow trench, form side wall.
Step 2, as shown in Figure 2 is carried out N type ion and is injected and form the counterfeit buried regions of N type in the bottom of the said shallow trench of the side in I type district, form N type district by the counterfeit buried regions of said N type.The implantation dosage that the N type ion of the counterfeit buried regions of said N type injects is 1e14cm
-2～1e16cm
-2, to inject energy be phosphorus or arsenic or antimony less than 30KeV, implanted dopant.Said side wall can prevent that implanted dopant from entering into shallow trench isolation from the side.The counterfeit buried regions of said N type can be realized heavily doped said N type district's low resistance connection effectively.
Step 3, as shown in Figure 3 is removed the side wall on the sidewall of said shallow trench, and the bottom of the said shallow trench between each said adjacent active area in said I type district and sidewall carry out P type ion and inject, and forms the counterfeit buried regions of a plurality of P types.The implantation dosage that the P type ion of the counterfeit buried regions of the said P type of each of said p type island region injects is 1e14cm
-2～1e16cm
-2, to inject energy be boron or boron fluoride less than 30KeV, implanted dopant, injection and the implant angle that the P type ion of the counterfeit buried regions of each said P type is injected to the band angle will guarantee to form the sidewall sections of the counterfeit buried regions of each said P type and can make the concentration of the sidewall sections of the counterfeit buried regions of each said P type is 1e19cm
-3More than.The P type ion of the counterfeit buried regions of each said P type stops with silicon nitride on the active area in said I type district when injecting, and is injected into each said active area zone to prevent p type impurity.
Step 4, as shown in Figure 4 is inserted silica and is formed the shallow trench isolating oxide layer in said shallow trench.
Step 5, as shown in Figure 4 is carried out N type collector electrode and is injected a plurality of N type collector electrodes of formation injection region in a plurality of adjacent active area that forms said I type district, said I type district is formed in said a plurality of N type collector electrodes injection region; The degree of depth of each said N type collector electrode injection region all extends into the said shallow trench isolating oxide layer bottom of each said N type collector electrode injection region side and realizes the connection of whole said N type collector electrodes injection region greater than the degree of depth of said shallow trench isolating oxide layer, the bottom of each said N type collector electrode injection region; Each said N type collector electrode injection region coat fully the counterfeit buried regions of said N type, the counterfeit buried regions of each said P type and and the counterfeit buried regions of said N type, the counterfeit buried regions of each said P type contact.The implanted dopant of the collector electrode injection region in said I type district is that phosphorus or arsenic, implantation dosage are 1e12cm
-2～1e15cm
-2, the injection energy is 100KeV～2000KeV.As shown in Figure 7; The quantity that the embodiment of the invention forms said a plurality of adjacent active areas in said I type district is more than 2; The arrangement architecture of said a plurality of adjacent active areas is the two-dimensional structure of transversely arranged and vertical arrangement, and it is that shallow trench isolation shown in Figure 7 leaves that 4 said shallow trench isolating oxide layers are arranged between said a plurality of adjacent active areas.
Step 6, as shown in Figure 4 is carried out thermal annealing to said silicon substrate, realizes that the annealing in said N type district, the counterfeit buried regions of each said P type, said I type district advances.
Step 7, as shown in Figure 5 forms an intrinsic base region epitaxial loayer on said surface of silicon.As shown in Figure 6, the definition ion injects window, injects window through said ion and the outer base area ion that is formed at said intrinsic base region epitaxial loayer on each the said surfaces of active regions in the said I type district and carries out the P type is injected form a plurality of base epitaxial layer on each the said active area in said I type district; The part that the sidewall sections of the counterfeit buried regions of adjacent each the said P type with it of each said base epitaxial layer promptly is formed at each said shallow trench isolating oxide layer sidewall contacts; Said a plurality of base epitaxial layer and the counterfeit buried regions of said a plurality of P types form said p type island region.Silicon epitaxy or germanium and silicon epitaxial or germanium silicon-carbon extension that the said base epitaxial layer of each of said p type island region is mixed for the P type; It is to mix to inject with the outer base area ion through P type on the throne to form that the P type of each said base epitaxial layer mixes, and the implanted dopant of said outer base area ion injection is that boron or boron fluoride, implantation dosage are 1e14cm
-2～1e15cm
-2, the injection energy is 2KeV～30KeV.
Step 8, in the said shallow trench isolating oxide layer at the counterfeit buried regions of said N type top, form the deep hole contact and draw said N type district; In the said shallow trench isolating oxide layer at each said P type buried layer top, form the deep hole contact and form Metal Contact and draw said p type island region at the top of each said base epitaxial layer.Form metal connecting line at last and realize the interconnection of device.
As shown in Figure 7, the I type district plan structure figure of the parasitic PIN diode in the embodiment of the invention BiCMOS technology.The length of side in the parasitic PIN diode I type district of the embodiment of the invention is 5 μ m * 5 μ m, between each active area equably etching four shallow trench isolations leave, the degree of depth that said shallow trench isolation leaves is 4000 dusts.Existing relatively parasitic PIN diode, if when the I type district length of side is all identical, the parasitic PIN diode of the embodiment of the invention can increase the area of heavily doped p type island region.The p type island region of existing parasitic PIN diode is directly to be formed on the active area identical with I type district, and the area that the area of said active area is the p type island region of existing parasitic PIN diode is 5 μ m * 5 μ m=25 μ m
2And on the p type island region of the parasitic PIN diode of the embodiment of the invention is formed on a plurality of active areas in said I type district and a plurality of shallow trench isolation leaves the bottom and sidewall, the area of the p type island region of the parasitic PIN diode of the embodiment of the invention is 5 μ m * 5 μ m+4 * 4 * 1 μ m * 0.4 μ m=31.4 μ m
2The area of the p type island region of the parasitic PIN diode of the embodiment of the invention has increased by 25% with respect to the area of the p type island region of existing parasitic PIN diode like this, makes that like this forward conduction electric current of embodiment of the invention device increases significantly, the insertion loss of device is also improved widely.If increase the shallow channel isolation area density in the same I type district, then the surface area of the p type island region of device increase is bigger, and the forward conduction electric current of device is also just big more.
More than through specific embodiment the present invention has been carried out detailed explanation, but these are not to be construed as limiting the invention.Under the situation that does not break away from the principle of the invention, those skilled in the art also can make many distortion and improvement, and these also should be regarded as protection scope of the present invention.
Claims (12)
1. the parasitic PIN diode in the BiCMOS technology; It is characterized in that: said parasitic PIN diode is formed on the P type silicon substrate; Active area is isolated through the shallow trench isolating oxide layer, and said parasitic PIN diode comprises: a N type district, an I type district and a p type island region;
Said I type district is by being formed in a plurality of adjacent active areas and interconnected a plurality of N type collector electrodes injection region is formed, and the degree of depth of each said N type collector electrode injection region all extends into bottom the said shallow trench isolating oxide layer of each said N type collector electrode injection region side and realizes the connection of whole said N type collector electrodes injection region greater than the bottom of the degree of depth of said shallow trench isolating oxide layer, each said N type collector electrode injection region;
Said N type district is made up of the counterfeit buried regions of N type of the said shallow trench isolating oxide layer bottom that is formed at said I type district side; The counterfeit buried regions of said N type is that N type ion implanted region also contacts with the formation of said I type district; In the said shallow trench isolating oxide layer at the counterfeit buried regions of said N type top, be formed with the deep hole contact, said deep hole contact is used to draw said N type district;
Said p type island region is made up of a plurality of base epitaxial layer and the counterfeit buried regions of a plurality of P types; Each said base epitaxial layer is formed at each said adjacent top part of active area surface that said I type district covered and is mixed with p type impurity; The counterfeit buried regions of each said P type is a P type ion implanted region; The counterfeit buried regions of each said P type is formed in the said N type collector electrode injection region of bottom and sidewall of the said shallow trench isolating oxide layer between each said adjacent active area that said I type district covered, and the counterfeit buried regions of each said P type is connected through each said base epitaxial layer formation adjacent with it of its sidewall sections; In the said shallow trench isolating oxide layer at each said P type buried layer top, be formed with the deep hole contact and be formed with Metal Contact at the top of each said base epitaxial layer, each said deep hole contact is used to draw said p type island region with each said Metal Contact.
2. the parasitic PIN diode in the BiCMOS technology as claimed in claim 1 is characterized in that: the implanted dopant of the collector electrode injection region in said I type district is that phosphorus or arsenic, implantation dosage are 1e12cm
-2～1e15cm
-2, the injection energy is 100KeV～2000KeV.
3. the parasitic PIN diode in the BiCMOS technology as claimed in claim 1 is characterized in that: the implantation dosage that the N type ion of the counterfeit buried regions of said N type injects is 1e14cm
-2～1e16cm
-2, to inject energy be phosphorus or arsenic or antimony less than 30KeV, implanted dopant.
4. the parasitic PIN diode in the BiCMOS technology as claimed in claim 1; It is characterized in that: silicon epitaxy or germanium and silicon epitaxial or germanium silicon-carbon extension that the said base epitaxial layer of each of said p type island region is mixed for the P type; It is to mix to inject with the outer base area ion through P type on the throne to form that the P type of each said base epitaxial layer mixes, and the implanted dopant of said outer base area ion injection is that boron or boron fluoride, implantation dosage are 1e14cm
-2～1e15cm
-2, the injection energy is 2KeV～30KeV.
5. the parasitic PIN diode in the BiCMOS technology as claimed in claim 1 is characterized in that: the implantation dosage that the P type ion of the counterfeit buried regions of the said P type of each of said p type island region injects is 1e14cm
-2～1e16cm
-2, to inject energy be boron or boron fluoride less than 30KeV, implanted dopant, the implant angle that the P type ion of the counterfeit buried regions of each said P type injects will guarantee to form the sidewall sections of the counterfeit buried regions of each said P type and can make the concentration of the sidewall sections of the counterfeit buried regions of each said P type is 1e19cm
-3More than.
6. the parasitic PIN diode in the BiCMOS technology as claimed in claim 1; It is characterized in that: the quantity that forms said a plurality of adjacent active areas in said I type district be 2 or more than, the arrangement architecture of said a plurality of adjacent active areas is transversely arranged or vertically arranges.
7. the manufacturing approach of the parasitic PIN diode in the BiCMOS technology as claimed in claim 1 is characterized in that, comprises the steps:
Step 1, utilize the shallow trench etching technics on a P type silicon substrate, to form shallow trench, and by said shallow trench isolation from going out active area; On the sidewall of said shallow trench, form side wall;
Step 2, carry out N type ion in the bottom of the said shallow trench of the side in I type district and inject and form the counterfeit buried regions of N type, form N type district by the counterfeit buried regions of said N type;
Step 3, remove the side wall on the sidewall of said shallow trench, and the bottom of the said shallow trench between each said adjacent active area in said I type district carries out the injection of P type ion with sidewall, form the counterfeit buried regions of a plurality of P types;
Step 4, in said shallow trench, insert silica and form the shallow trench isolating oxide layer;
Step 5, in a plurality of adjacent active area that forms said I type district, carry out N type collector electrode and inject and form a plurality of N type collector electrodes injection region, said I type district is formed in said a plurality of N type collector electrodes injection region; The degree of depth of each said N type collector electrode injection region all extends into the said shallow trench isolating oxide layer bottom of each said N type collector electrode injection region side and realizes the connection of whole said N type collector electrodes injection region greater than the degree of depth of said shallow trench isolating oxide layer, the bottom of each said N type collector electrode injection region; Each said N type collector electrode injection region coat fully the counterfeit buried regions of said N type, the counterfeit buried regions of each said P type and and the counterfeit buried regions of said N type, the counterfeit buried regions of each said P type contact;
Step 6, said silicon substrate is carried out thermal annealing, realize that the annealing in said N type district, the counterfeit buried regions of each said P type, said I type district advances;
Step 7, on said surface of silicon, form an intrinsic base region epitaxial loayer, and the definition ion injects window, injects window through said ion and the outer base area ion that is formed at said intrinsic base region epitaxial loayer on each the said surfaces of active regions in the said I type district and carries out the P type is injected form a plurality of base epitaxial layer on each the said active area in said I type district; The sidewall sections of the counterfeit buried regions of adjacent each the said P type with it of each said base epitaxial layer contacts; Said a plurality of base epitaxial layer and the counterfeit buried regions of said a plurality of P types form said p type island region;
Step 8, in the said shallow trench isolating oxide layer at the counterfeit buried regions of said N type top, form the deep hole contact and draw said N type district; In the said shallow trench isolating oxide layer at each said P type buried layer top, form the deep hole contact and form Metal Contact and draw said p type island region at the top of each said base epitaxial layer.
8. method as claimed in claim 7 is characterized in that: the implanted dopant of the collector electrode injection region in the type of I described in step 5 district is that phosphorus or arsenic, implantation dosage are 1e12cm
-2～1e15cm
-2, the injection energy is 100KeV～2000KeV.
9. method as claimed in claim 7 is characterized in that: the implantation dosage that the N type ion of the counterfeit buried regions of the type of N described in the step 2 injects is 1e14cm
-2～1e16cm
-2, to inject energy be phosphorus or arsenic or antimony less than 30KeV, implanted dopant.
10. method as claimed in claim 7; It is characterized in that: silicon epitaxy or germanium and silicon epitaxial or germanium silicon-carbon extension that the said base epitaxial layer of each of p type island region described in the step 7 is mixed for the P type; It is to mix to inject with the outer base area ion through P type on the throne to form that the P type of each said base epitaxial layer mixes, and the implanted dopant of said outer base area ion injection is that boron or boron fluoride, implantation dosage are 1e14cm
-2～1e15cm
-2, the injection energy is 2KeV～30KeV.
11. method as claimed in claim 7 is characterized in that: the implantation dosage that the P type ion of the counterfeit buried regions of the said P type of each of p type island region described in the step 3 injects is 1e14cm
-2～1e16cm
-2, to inject energy be boron or boron fluoride less than 30KeV, implanted dopant, the implant angle that the P type ion of the counterfeit buried regions of each said P type injects will guarantee to form the sidewall sections of the counterfeit buried regions of each said P type and can make the concentration of the sidewall sections of the counterfeit buried regions of each said P type is 1e19cm
-3More than.
12. method as claimed in claim 7 is characterized in that: the quantity that forms said a plurality of adjacent active areas in said I type district is more than 2, and the arrangement architecture of said a plurality of adjacent active areas is transversely arranged or vertically arranges.
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| CN103367393A (en) * | 2012-03-28 | 2013-10-23 | 上海华虹Nec电子有限公司 | Transient voltage suppressing device and manufacturing technology method |
| CN106654522A (en) * | 2016-12-20 | 2017-05-10 | 西安科锐盛创新科技有限公司 | Preparation method of SiGe-based plasma pin diode for multi-layer holographic antenna |
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| CN108767072A (en) * | 2018-05-31 | 2018-11-06 | 广州锋尚电器有限公司 | Enhanced cmos sensor light emitting diode structure preparation method |
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| CN108767072B (en) * | 2018-05-31 | 2019-11-08 | 广州锋尚电器有限公司 | Enhanced cmos sensor light emitting diode structure preparation method |
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| CN102376776B (en) | 2014-05-21 |
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