CN106654522A - Preparation method of SiGe-based plasma pin diode for multi-layer holographic antenna - Google Patents
Preparation method of SiGe-based plasma pin diode for multi-layer holographic antenna Download PDFInfo
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- CN106654522A CN106654522A CN201611184746.8A CN201611184746A CN106654522A CN 106654522 A CN106654522 A CN 106654522A CN 201611184746 A CN201611184746 A CN 201611184746A CN 106654522 A CN106654522 A CN 106654522A
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- 229910000577 Silicon-germanium Inorganic materials 0.000 title claims abstract description 105
- 238000002360 preparation method Methods 0.000 title claims abstract description 32
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 58
- 239000000758 substrate Substances 0.000 claims abstract description 46
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 29
- 238000001259 photo etching Methods 0.000 claims abstract description 26
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 20
- 239000012535 impurity Substances 0.000 claims abstract description 18
- 238000002955 isolation Methods 0.000 claims abstract description 15
- 239000004065 semiconductor Substances 0.000 claims abstract description 8
- 210000002381 plasma Anatomy 0.000 claims description 117
- 239000010410 layer Substances 0.000 claims description 74
- 238000000034 method Methods 0.000 claims description 44
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 18
- 229920005591 polysilicon Polymers 0.000 claims description 18
- 239000011241 protective layer Substances 0.000 claims description 17
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 14
- 239000003292 glue Substances 0.000 claims description 10
- 229920002120 photoresistant polymer Polymers 0.000 claims description 10
- 238000001039 wet etching Methods 0.000 claims description 10
- 238000005516 engineering process Methods 0.000 claims description 9
- 238000001459 lithography Methods 0.000 claims description 4
- 238000002161 passivation Methods 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 2
- 238000007254 oxidation reaction Methods 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 238000005530 etching Methods 0.000 abstract description 8
- 238000005468 ion implantation Methods 0.000 abstract 2
- 230000003213 activating effect Effects 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 description 17
- 239000007787 solid Substances 0.000 description 16
- 239000000463 material Substances 0.000 description 7
- 238000002347 injection Methods 0.000 description 6
- 239000007924 injection Substances 0.000 description 6
- 229910052681 coesite Inorganic materials 0.000 description 5
- 229910052906 cristobalite Inorganic materials 0.000 description 5
- 229910052682 stishovite Inorganic materials 0.000 description 5
- 229910052905 tridymite Inorganic materials 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000004891 communication Methods 0.000 description 3
- 230000007812 deficiency Effects 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 241000033695 Sige Species 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000008485 antagonism Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005670 electromagnetic radiation Effects 0.000 description 1
- 210000001061 forehead Anatomy 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 229910052752 metalloid Inorganic materials 0.000 description 1
- 150000002738 metalloids Chemical class 0.000 description 1
- 230000011514 reflex Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/12—Supports; Mounting means
- H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
- H01Q1/2283—Supports; Mounting means by structural association with other equipment or articles mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/868—PIN diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/36—Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Element Separation (AREA)
Abstract
The invention discloses a preparation method of a SiGe-based plasma pin diode for a multi-layer holographic antenna. The preparation method of the SiGe-based plasma pin diode for the reconfigurable multi-layer holographic antenna comprises the steps of arranging an isolation region in a SiGeOI semiconductor substrate; etching the SiGeOI substrate to form a P-type groove and an N-type groove, wherein the depths of the P-type groove and the N-type groove are smaller than the thickness of top-layer SiGe of the SiGeOI substrate; forming a first P-type active region and a first N-type active region in the P-type groove and the N-type groove by adopting ion implantation; filling the P-type groove and the N-type groove and forming a second P-type active region and a second N-type active region in the top-layer SiGe of the SiGeOI substrate by adopting ion implantation; generating silicon dioxide on the SiGeOI substrate; activating impurities in the active regions; photoetching lead holes in a P-type contact region and an N-type contact region to form leads; and carrying out passivating treatment and photoetching a PAD to complete preparation of the SiGe-based plasma pin diode.
Description
Technical field
The invention belongs to semiconductor device processing technology field, it is related to antenna technical field, more particularly to a kind of multilayer is complete
The preparation method of breath antenna SiGe base plasma pin diodes.
Background technology
Plasma antenna is a kind of radio-frequency antenna that plasma is oriented to medium as electromagnetic radiation.Plasma day
Li Yong the change plasma density of line is changing the instant bandwidth of antenna and with big dynamic range；Can also pass through
Change plasma resonance, impedance and density etc., adjust frequency, beam angle, power, gain and the directionality dynamic of antenna
Parameter；In addition, plasma antenna is not in the state of exciting, RCS is negligible, and antenna only exists
Communication sends or excites in the short time of reception, improves the disguise of antenna, and these properties can be widely used in various detecing
Examine, early warning and antagonism radar, spaceborne, airborne and missile antenna, microwave imaging antenna, the neck such as microwave communication antenna of high s/n ratio
Domain, greatly causes the concern of domestic and international researcher, becomes the focus of antenna research field.
At present, domestic and international application is body silicon materials in the material that the pin diodes of plasma reconfigurable antenna are adopted, this
Material has that intrinsic region carrier mobility is relatively low, affects pin diodes intrinsic region carrier concentration, and then affects it to consolidate
State plasma density；And the P areas of the structure and N areas are formed using injection technology mostly, the method require implantation dosage and
Energy is larger, high to equipment requirement and incompatible with existing process；And diffusion technique is adopted, though junction depth is deeper, while P areas
Larger with the area in N areas, integrated level is low, and doping content is uneven, affect pin diodes electric property, cause solid-state etc. from
Daughter concentration and the poor controllability of distribution.
With reference to the pin diodes limitation and deficiency of the plasma reconfigurable antenna of silicon materials, it would be highly desirable to which research finds new material
Expect to make a kind of plasma pin diodes with technique, to improve the electric property of solid plasma antenna.
The content of the invention
To solve the technological deficiency and deficiency of the pin diodes of existing solid plasma antenna, the present invention proposes a kind of many
The preparation method of layer holographic antenna SiGe base plasma pin diodes.
The embodiment provides a kind of preparation method of multilayer holographic antenna SiGe bases plasma pin diodes,
Wherein, the multilayer holographic antenna is by the Anneta module (13) being made on SiGeOI semiconductor chips (11), the first holographic circle
Ring (15) and the second holographic annulus (17) composition；The Anneta module (13), the described first holographic annulus (15) and described second
Holographic annulus (17) includes the SiGe base plasma pin diode strings being sequentially connected in series；The SiGe bases plasma pin diodes
Preparation method include step it is as follows：
A () arranges isolated area in the SiGeOI semiconductor chips (11)；
B () etches the SiGeOI substrates and forms p-type groove and N-type groove, the p-type groove and the N-type groove
Thickness of the depth less than top layer Si Ge of the SiGeOI substrates；
C () aoxidizes the p-type groove and the N-type groove so that the inwall of the p-type groove and the N-type groove is formed
Oxide layer；
D () etches the oxide layer of the p-type groove and the N-type trench wall using wet-etching technology described to complete
The planarizing of p-type groove and the N-type trench wall；
E () carries out ion implanting to form the first p-type active area and institute to the p-type groove and the N-type groove
The first N-type active area is stated, the first N-type active area is away from the N-type trenched side-wall and bottom depth along ion dispersal direction
Region less than 1 micron, the first p-type active area is away from the p-type trenched side-wall and bottom depth along ion dispersal direction
Region less than 1 micron；
F () fills described p-type groove and the N-type groove, and using ion implanting the SiGeOI substrates top layer
The second p-type active area and the second N-type active area are formed in SiGe；
G () generates silica on the SiGeOI substrates；The impurity in active area is activated using annealing process；
H () is in the p-type contact zone and N-type contact zone lithography fair lead forming lead；
I () Passivation Treatment and photoetching PAD are completing the preparation of the SiGe bases plasma pin diodes.
In one embodiment of the invention, the Anneta module (13) includes a SiGe base plasma pin diodes
Antenna arm (1301), the 2nd SiGe bases plasma pin diode antenna arms (1302), coaxial feeder (1303), the first direct current are inclined
Put line (1304), the second direct current biasing line (1305), the 3rd direct current biasing line (1306), the 4th direct current biasing line (1307),
Five direct current biasing lines (1308), the 6th direct current biasing line (1309), the 7th direct current biasing line (1310), the 8th direct current biasing line
(1311)；
Wherein, the internal core wire and outer conductor of the coaxial feeder (1303) is respectively welded in the first direct current biasing line
And the second direct current biasing line (1305) (1304)；
The first direct current biasing line (1304), the 5th direct current biasing line (1308), the 3rd direct current biasing line
And the 4th direct current biasing line (1307) is along SiGe bases plasma pin diode antenna arms (1301) (1306)
Length direction is respectively electrically connected to SiGe bases plasma pin diode antenna arms (1301)；Second direct current is inclined
Put line (1305), the 6th direct current biasing line (1309), the 7th direct current biasing line (1310) and the 8th direct current inclined
The length direction that line (1311) is put along the 2nd SiGe bases plasma pin diode antenna arms (1302) is respectively electrically connected to institute
State the 2nd SiGe bases plasma pin diode antenna arms (1302).
In one embodiment of the invention, SiGe bases plasma pin diode antenna arms (1301) includes
SiGe bases plasma pin diode strings (w1), the 2nd SiGe bases plasma pin diode strings (w2) and the institute being sequentially connected in series
State the 3rd SiGe bases plasma pin diode strings (w3), the 2nd SiGe bases plasma pin diode antenna arms (1302) bag
Include the 4th SiGe bases plasma pin diode strings (w4), the 5th SiGe bases plasma pin diode strings (w5) that are sequentially connected in series and
6th SiGe bases plasma pin diode strings (w6) and SiGe bases plasma pin diode strings (w1) and institute
State the 6th SiGe bases plasma pin diode strings (w6), the 2nd SiGe bases plasma pin diode strings (w2) and described
Five SiGe bases plasma pin diode strings (w5), the 3rd SiGe bases plasma pin diode strings (W3) and the described 4th
SiGe bases plasma pin diode strings (w4) is respectively including the SiGe base plasma pin diodes of equivalent amount.
On the basis of above-described embodiment, step (a) includes：
(a1) the first protective layer is formed on the SiGe surfaces；
(a2) the first isolated area figure is formed on first protective layer using photoetching process；
(a3) the specified location etching described first using dry etch process in the first isolated area figure is protected
Layer and the substrate are to form isolation channel, and the depth of the isolation channel is more than or equal to the thickness of top layer Si Ge of the substrate；
(a4) fill the isolation channel to form the isolated area of the plasma pin diodes.
Wherein, step (a1) includes：
(a11) in the SiGe Surface Creations silica forming the first silicon dioxide layer；
(a12) in the first silicon dioxide layer Surface Creation silicon nitride forming the first silicon nitride layer.
On the basis of above-described embodiment, step (b) includes：
(b1) the second protective layer is formed in the substrate surface；
(b2) the second isolated area figure is formed on second protective layer using photoetching process；
(b3) the specified location etching described second using dry etch process in the second isolated area figure is protected
Layer and the substrate are forming the p-type groove and the N-type groove.
Wherein, step (b1) includes：
(b11) in the SiGe Surface Creations silica forming the second silicon dioxide layer；
(b12) in the second silicon dioxide layer Surface Creation silicon nitride forming the second silicon nitride layer.
On the basis of above-described embodiment, step (e) includes：
(e1) p-type groove described in photoetching and the N-type groove；
(e2) using the method with glue ion implanting the p-type groove and the N-type groove are injected separately into p type impurity and
N-type impurity is forming the first p-type active area and the first N-type active area；
(e3) photoresist is removed.
On the basis of above-described embodiment, step (f) includes：
(f1) the p-type groove and the N-type groove are filled using polysilicon；
(f2) after substrate described in planarizing process, polysilicon layer is formed over the substrate；
(f3) polysilicon layer described in photoetching, and using the method with glue ion implanting to the p-type groove and the N-type ditch
Groove position is injected separately into p type impurity and N-type impurity to form the second p-type active area and the second N-type active area and while shape
Into p-type contact zone and N-type contact zone；
(f4) photoresist is removed；
(f5) polysilicon layer beyond the p-type contact zone and the N-type contact zone is removed using wet etching.
Compared with prior art, beneficial effects of the present invention are：
Sige material has high carrier mobility, therefore can form high carrier concentration so as to improve two poles in I areas
The performance of pipe.
Description of the drawings
For the clear explanation embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing skill
The accompanying drawing to be used needed for art description is briefly described.Drawings in the following description are some embodiments of the present invention, right
In those of ordinary skill in the art, on the premise of not paying creative work, can be obtaining other according to these accompanying drawings
Accompanying drawing.
Fig. 1 is a kind of structural representation of restructural multilayer holographic antenna provided in an embodiment of the present invention；
Fig. 2 is a kind of structural representation of Anneta module provided in an embodiment of the present invention；
Fig. 3 is a kind of preparation method flow chart of SiGe bases solid plasma pin diode of the embodiment of the present invention；
Fig. 4 a- Fig. 4 s are a kind of preparation method schematic diagram of SiGe bases plasma pin diodes of the embodiment of the present invention；
Fig. 5 is a kind of device architecture schematic diagram of SiGe bases plasma pin diodes provided in an embodiment of the present invention；
Specific embodiment
To make those skilled in the art more fully understand technical scheme, below in conjunction with the accompanying drawings and specific embodiment party
Case is described in further detail to a kind of restructural multilayer holographic antenna of the invention.Example only represents possible change.Unless bright
Really require, otherwise single components and functionality is optional, and the order for operating can change.The part of some embodiments
The forehead point and feature of other embodiments can be included in or replaced with feature.The scope of embodiment of the present invention includes
The gamut of claims, and all obtainable equivalent of claims.
The present invention is described in further details below in conjunction with the accompanying drawings.
Embodiment one
Fig. 1 is referred to, Fig. 1 is a kind of structural representation of multilayer restructural holographic antenna provided in an embodiment of the present invention,
Wherein, the multilayer holographic antenna is by the Anneta module (13) being made on SiGeOI semiconductor chips (11), the first holographic circle
Ring (15) and the second holographic annulus (17) composition；The Anneta module (13), the described first holographic annulus (15) and described second
Holographic annulus (17) includes the SiGe base plasma pin diode strings being sequentially connected in series；Refer to Fig. 3, described SiGe bases etc. from
The preparation method of sub- pin diodes includes that step is as follows：
A () arranges isolated area in the SiGeOI semiconductor chips (11)；
B () etches the SiGeOI substrates and forms p-type groove and N-type groove, the p-type groove and the N-type groove
Thickness of the depth less than top layer Si Ge of the SiGeOI substrates；
C () aoxidizes the p-type groove and the N-type groove so that the inwall of the p-type groove and the N-type groove is formed
Oxide layer；
D () etches the oxide layer of the p-type groove and the N-type trench wall using wet-etching technology described to complete
The planarizing of p-type groove and the N-type trench wall；
E () carries out ion implanting to form the first p-type active area and institute to the p-type groove and the N-type groove
The first N-type active area is stated, the first N-type active area is away from the N-type trenched side-wall and bottom depth along ion dispersal direction
Region less than 1 micron, the first p-type active area is away from the p-type trenched side-wall and bottom depth along ion dispersal direction
Region less than 1 micron；
F () fills described p-type groove and the N-type groove, and using ion implanting the SiGeOI substrates top layer
The second p-type active area and the second N-type active area are formed in SiGe；
G () generates silica on the SiGeOI substrates；The impurity in active area is activated using annealing process；
H () is in the p-type contact zone and N-type contact zone lithography fair lead forming lead；
I () Passivation Treatment and photoetching PAD are completing the preparation of the SiGe bases plasma pin diodes.
Fig. 2 is referred to, in one embodiment of the invention, the Anneta module (13) is including a SiGe base plasmas
Pin diode antenna arms (1301), the 2nd SiGe bases plasma pin diode antenna arms (1302), coaxial feeder (1303),
One direct current offset line (1304), the second direct current biasing line (1305), the 3rd direct current biasing line (1306), the 4th direct current biasing line
(1307), the 5th direct current biasing line (1308), the 6th direct current biasing line (1309), the 7th direct current biasing line (1310), the 8th straight
Stream offset line (1311)；
Wherein, the internal core wire and outer conductor of the coaxial feeder (1303) is respectively welded in the first direct current biasing line
And the second direct current biasing line (1305) (1304)；
The first direct current biasing line (1304), the 5th direct current biasing line (1308), the 3rd direct current biasing line
And the 4th direct current biasing line (1307) is along SiGe bases plasma pin diode antenna arms (1301) (1306)
Length direction is respectively electrically connected to SiGe bases plasma pin diode antenna arms (1301)；Second direct current is inclined
Put line (1305), the 6th direct current biasing line (1309), the 7th direct current biasing line (1310) and the 8th direct current inclined
The length direction that line (1311) is put along the 2nd SiGe bases plasma pin diode antenna arms (1302) is respectively electrically connected to institute
State the 2nd SiGe bases plasma pin diode antenna arms (1302).
In one embodiment of the invention, SiGe bases plasma pin diode antenna arms (1301) includes
SiGe bases plasma pin diode strings (w1), the 2nd SiGe bases plasma pin diode strings (w2) and the institute being sequentially connected in series
State the 3rd SiGe bases plasma pin diode strings (w3), the 2nd SiGe bases plasma pin diode antenna arms (1302) bag
Include the 4th SiGe bases plasma pin diode strings (w4), the 5th SiGe bases plasma pin diode strings (w5) that are sequentially connected in series and
6th SiGe bases plasma pin diode strings (w6) and SiGe bases plasma pin diode strings (w1) and institute
State the 6th SiGe bases plasma pin diode strings (w6), the 2nd SiGe bases plasma pin diode strings (w2) and described
Five SiGe bases plasma pin diode strings (w5), the 3rd SiGe bases plasma pin diode strings (w3) and the described 4th
SiGe bases plasma pin diode strings (w4) is respectively including the SiGe base plasma pin diodes of equivalent amount.
On the basis of above-described embodiment, step (a) includes：
(a1) the first protective layer is formed on the SiGe surfaces；
(a2) the first isolated area figure is formed on first protective layer using photoetching process；
(a3) the specified location etching described first using dry etch process in the first isolated area figure is protected
Layer and the substrate are to form isolation channel, and the depth of the isolation channel is more than or equal to the thickness of top layer Si Ge of the substrate；
(a4) fill the isolation channel to form the isolated area of the plasma pin diodes.
Wherein, step (a1) includes：
(a11) in the SiGe Surface Creations silica forming the first silicon dioxide layer；
(a12) in the first silicon dioxide layer Surface Creation silicon nitride forming the first silicon nitride layer.
On the basis of above-described embodiment, step (b) includes：
(b1) the second protective layer is formed in the substrate surface；
(b2) the second isolated area figure is formed on second protective layer using photoetching process；
(b3) the specified location etching described second using dry etch process in the second isolated area figure is protected
Layer and the substrate are forming the p-type groove and the N-type groove.
Wherein, step (b1) includes：
(b11) in the SiGe Surface Creations silica forming the second silicon dioxide layer；
(b12) in the second silicon dioxide layer Surface Creation silicon nitride forming the second silicon nitride layer.
On the basis of above-described embodiment, step (e) includes：
(e1) p-type groove described in photoetching and the N-type groove；
(e2) using the method with glue ion implanting the p-type groove and the N-type groove are injected separately into p type impurity and
N-type impurity is forming the first p-type active area and the first N-type active area；
(e3) photoresist is removed.
On the basis of above-described embodiment, step (f) includes：
(f1) the p-type groove and the N-type groove are filled using polysilicon；
(f2) after substrate described in planarizing process, polysilicon layer is formed over the substrate；
(f3) polysilicon layer described in photoetching, and using the method with glue ion implanting to the p-type groove and the N-type ditch
Groove position is injected separately into p type impurity and N-type impurity to form the second p-type active area and the second N-type active area and while shape
Into p-type contact zone and N-type contact zone；
(f4) photoresist is removed；
(f5) polysilicon layer beyond the p-type contact zone and the N-type contact zone is removed using wet etching.
The embodiment of the present invention is employed based on etching by the P areas to SiGe base plasma pin diodes and N areas
The polysilicon damascene technique of SiGeOI deep etchings, the technique can provide abrupt junction pi and tie with ni, and can effectively carry
High pi knots, the junction depth of ni knots, strengthen the concentration of solid state plasma and the controllability of distribution.Also, prepared by the present invention should
SiGeOI base plasma pin diodes for solid plasma reconfigurable antenna employ a kind of SiGeOI depths based on etching
Groove medium isolation technology, is effectively improved the breakdown voltage of device, it is suppressed that impact of the leakage current to device performance.
Embodiment two
Fig. 4 a- Fig. 4 s are referred to, Fig. 4 a- Fig. 4 s are a kind of SiGe bases plasma pin diodes of the embodiment of the present invention
Preparation method schematic diagram, on the basis of above-described embodiment one, with prepare channel length as 22nm (solid plasma zone length
For 100 microns) SiGe base solid plasma pin diodes as a example by be described in detail, comprise the following steps that：
Step 1, backing material preparation process：
(1a) as shown in fig. 4 a, the SiGeOI substrate slices 101 of (100) crystal orientation are chosen, doping type is p-type, doping content
For 1014cm-3, the thickness of top layer Si Ge is 50 μm；
(1b) as shown in Figure 4 b, using chemical vapor deposition (Chemical vapor deposition, abbreviation CVD)
Method, deposits a SiO2 layers 201 of one layer of 40nm thickness on SiGe；
(1c) using the method for chemical vapor deposition, a Si3N4/SiN layers of one layer of 2 μ m thick are deposited on substrate
202；
Step 2, isolates preparation process：
(2a) as illustrated in fig. 4 c, isolated area, wet etching isolated area are formed on above-mentioned protective layer by photoetching process
One Si3N4/SiN layers 202, form isolated area figure；Using dry etching, form wide 5 μm in isolated area, depth be 50 μm it is deep every
From groove 301；
(2b) as shown in figure 4d, after photoetching isolated area, using the method for CVD, SiO2 401 is deposited by the deep isolation trench
Fill up；
(2c) as shown in fig 4e, using chemically mechanical polishing (Chemical Mechanical Polishing, abbreviation
CMP) method, removes the Si3N4/SiN layers 202 of surface the first and a SiO2 layers 201, makes substrate surface smooth；
Step 3, P, N area deep trouth preparation process：
(3a) as shown in fig. 4f, using CVD method, consecutive deposition prolongs two layer materials on substrate, and ground floor is that 300nm is thick
2nd SiO2 layers 601 of degree, the second layer is the 2nd Si3N4/SiN layers 602 of 500nm thickness；
(3b) as shown in figure 4g, photoetching P, N areas deep trouth, the Si3N4/SiN floor 602 and second of wet etching P, N areas the 2nd
SiO2 layers 601, form P, N area figure；Using dry etching, form wide 4 μm in P, N area, deep 5 μm deep trouth 701, P, N area groove
Length determined according to the applicable cases in prepared antenna；
(3c) as shown in figure 4h, at 850 DEG C, high-temperature process 10 minutes, oxidation trough inwall forms oxide layer 801, so that
P, N area groove inwall is smooth；
(3d) as shown in figure 4i, the oxide layer 801 of P, N area groove inwall is removed using wet-etching technology.
Step 4, P, N contact zone preparation process：
(4a) as shown in figure 4j, photoetching P areas deep trouth, p+ notes are carried out using the method with glue ion implanting to P areas groove sidewall
Enter, make to form thin p+ active areas 1001 on the wall of side, concentration reaches 0.5 × 1020cm-3, removes photoresist；
(4b) photoetching N areas deep trouth, n+ injections are carried out using the method with glue ion implanting to N areas groove sidewall, are made on the wall of side
Thin n+ active areas 1002 are formed, concentration reaches 0.5 × 1020cm-3, removes photoresist；
(4c) as shown in fig. 4k, using the method for CVD, the depositing polysilicon 1101 in P, N area groove, and groove is filled up；
(4d) as shown in Fig. 4 l, using CMP, the Si3N4/SiN layers 602 of surface polysilicon 1101 and the 2nd are removed, makes surface
It is smooth；
(4e) as shown in Fig. 4 m, using the method for CVD, in one layer of polysilicon 1301 of surface deposition, thickness is 200～
500nm；
(4f) as shown in Fig. 4 n, photoetching P areas active area carries out p+ injections using band glue ion injection method, makes P areas active
Area's doping content reaches 0.5 × 1020cm-3, removes photoresist, forms P contacts 1401；
(4g) photoetching N areas active area, using band glue ion injection method n+ injections are carried out, and make N areas active area doping content
For 0.5 × 1020cm-3, photoresist is removed, form N contacts 1402；
(4h) as shown in Fig. 4 o, using wet etching, the polysilicon 1301 beyond P, N contact zone is etched away, forms P, N and connect
Tactile area；
(4i) as shown in Fig. 4 p, using the method for CVD, in surface deposition SiO21601, thickness is 800nm；
(4j) at 1000 DEG C, anneal 1 minute, make the impurity activation of ion implanting and advance impurity in polysilicon；
Step 5, constitutes PIN diode step：
(5a) as shown in Fig. 4 q, the lithography fair lead 1701 in P, N contact zone；
(5b) as shown in Fig. 4 r, substrate surface splash-proofing sputtering metal forms metal silicide 1801 in 750 DEG C of alloys, and etches
Fall the metal on surface；
(5c) substrate surface splash-proofing sputtering metal, photoetching lead；
(5d) as shown in Fig. 4 s, deposit Si3N4/SiN forms passivation layer 1901, and photoetching PAD forms PIN diode, as
Prepare solid plasma antenna material.
In the present embodiment, above-mentioned various technological parameters are illustration, according to the conventional meanses of those skilled in the art
The conversion done is the protection domain of the application.
Embodiment of the present invention multilayer holographic antenna adopts SiGe base plasma pin diodes.SiGe base plasmas pin bis-
Pole pipe is to form horizontal pin diodes based on the SiGe in dielectric substrate, and, when Dc bias is added, DC current can be in its table for it
Face forms the solid state plasma of free carrier (electronics and hole) composition, and the plasma has metalloid characteristic, i.e., right
Electromagnetic wave has reflex, and its reflection characteristic is closely related with the microwave transmission characteristic of surface plasma, concentration and distribution.
Laterally solid plasma pin diode plasma reconfigurable antenna can be by the pole of horizontal solid plasma pin bis-
Pipe is arranged in a combination by array, is turned on using the solid plasma pin diode selecting in external control array, makes the battle array
Row form dynamic solid state plasma striped, possess the function of antenna, have transmitting and receive capabilities to specific electromagnetic wave, and
The antenna can pass through array in solid plasma pin diode selectivity conducting, change solid state plasma shape of stripes and
Distribution, so as to realize the reconstruct of antenna, has important application prospect in terms of national defence communication with Radar Technology.
Embodiment three
Fig. 5 is refer to, Fig. 5 is the device architecture schematic diagram of the SiGe base plasma pin diodes of the embodiment of the present invention.Should
Plasma pin diodes are made using above-mentioned preparation method as shown in Figure 3, and specifically, plasma pin diodes exist
Prepare on SiGeOI substrates 301 and formed, and the P areas 305 of pin diodes, N areas 306 and be laterally positioned in the P areas 305 and the N areas
I areas between 306 are respectively positioned in top layer Si Ge302 of substrate.Wherein, the pin diodes can adopt STI deep trench isolations, i.e.,
The P areas 305 and the outside of N areas 306 are each provided with an isolation channel 303, and the depth of the isolation channel 303 is more than or equal to top layer Si Ge
Thickness.In addition, the P areas 305 and the N areas 306 include a thin layer p-type active area 307 can correspond to respectively along substrate direction
With a thin layer N-type active area 304.
In sum, specific case used herein is to solid plasma pin diode of the present invention and preparation method thereof
Principle and embodiment be set forth, the explanation of above example is only intended to help and understands the method for the present invention and its core
Thought is thought；Simultaneously for one of ordinary skill in the art, according to the thought of the present invention, in specific embodiment and model is applied
Place and will change, in sum, this specification content should not be construed as limiting the invention, the protection of the present invention
Scope should be defined by appended claim.
Claims (9)
1. a kind of preparation method of multilayer holographic antenna SiGe bases plasma pin diodes, it is characterised in that the restructural is more
Layer holographic antenna includes being made in Anneta module (13) on SiGeOI semiconductor chips (11), the first holographic annulus (15) and the
Two holographic annulus (17)；Wherein, the Anneta module (13), the described first holographic annulus (15) and the second holographic annulus
(17) the SiGe base plasma pin diode strings being sequentially connected in series are included；The SiGe bases plasma pin diode preparation methods
It is as follows including step：
A () arranges isolated area in the SiGeOI semiconductor chips (11)；
B () etches the depth that the SiGeOI substrates form p-type groove and N-type groove, the p-type groove and the N-type groove
Less than the thickness of top layer Si Ge of the SiGeOI substrates；
C () aoxidizes the p-type groove and the N-type groove so that the inwall of the p-type groove and the N-type groove forms oxidation
Layer；
D () etches the oxide layer of the p-type groove and the N-type trench wall to complete the p-type using wet-etching technology
The planarizing of groove and the N-type trench wall；
E () carries out ion implanting to form the first p-type active area and described to the p-type groove and the N-type groove
One N-type active area, the first N-type active area is to be less than 1 away from the N-type trenched side-wall and bottom depth along ion dispersal direction
The region of micron, the first p-type active area is to be less than 1 away from the p-type trenched side-wall and bottom depth along ion dispersal direction
The region of micron；
F () fills described p-type groove and the N-type groove, and using ion implanting the SiGeOI substrates top layer Si Ge
The second p-type active area of interior formation and the second N-type active area；
G () generates silica on the SiGeOI substrates；The impurity in active area is activated using annealing process；
H () is in the p-type contact zone and N-type contact zone lithography fair lead forming lead；
I () Passivation Treatment and photoetching PAD are completing the preparation of the SiGe bases plasma pin diodes.
2. preparation method according to claim 1, it is characterised in that the Anneta module (13) is including SiGe bases etc.
Ion pin diode antenna arms (1301), the 2nd SiGe bases plasma pin diode antenna arms (1302), coaxial feeder
(1303), the first direct current biasing line (1304), the second direct current biasing line (1305), the 3rd direct current biasing line (1306), the 4th straight
Stream offset line (1307), the 5th direct current biasing line (1308), the 6th direct current biasing line (1309), the 7th direct current biasing line
(1310), the 8th direct current biasing line (1311)；
Wherein, the internal core wire and outer conductor of the coaxial feeder (1303) is respectively welded in the first direct current biasing line (1304)
With the second direct current biasing line (1305)；
The first direct current biasing line (1304), the 5th direct current biasing line (1308), the 3rd direct current biasing line
And the 4th direct current biasing line (1307) is along SiGe bases plasma pin diode antenna arms (1301) (1306)
Length direction is respectively electrically connected to SiGe bases plasma pin diode antenna arms (1301)；Second direct current is inclined
Put line (1305), the 6th direct current biasing line (1309), the 7th direct current biasing line (1310) and the 8th direct current inclined
The length direction that line (1311) is put along the 2nd SiGe bases plasma pin diode antenna arms (1302) is respectively electrically connected to institute
State the 2nd SiGe bases plasma pin diode antenna arms (1302).
3. preparation method according to claim 2, it is characterised in that the SiGe bases plasma pin diodes day
Line arm (1301) includes SiGe bases plasma pin diode strings (w1), the 2nd SiGe base plasmas pin bis- being sequentially connected in series
Pole pipe string (w2) and the 3rd SiGe bases plasma pin diode strings (w3), the 2nd SiGe bases plasma pin diodes
Antenna arm (1302) includes the 4th SiGe bases plasma pin diode strings (w4), the 5th SiGe base plasma pin being sequentially connected in series
Diode string (w5) and the 6th SiGe bases plasma pin diode strings (w6) and the SiGe base plasmas pin bis-
Pole pipe string (w1) and the 6th SiGe bases plasma pin diode strings (w6), the 2nd SiGe bases plasma pin diodes
String (w2) and the 5th SiGe bases plasma pin diode strings (w5), the 3rd SiGe bases plasma pin diode strings
(w3) with the 4th SiGe bases plasma pin diode strings (w4) respectively including the SiGe base plasmas pin bis- of equivalent amount
Pole pipe.
4. preparation method as claimed in claim 1, it is characterised in that isolated area is set on SiGeOI substrates, including：
(a1) the first protective layer is formed on the SiGe surfaces；
(a2) the first isolated area figure is formed on first protective layer using photoetching process；
(a3) using dry etch process the specified location of the first isolated area figure etch first protective layer and
The substrate is to form isolation channel, and the depth of the isolation channel is more than or equal to the thickness of top layer Si Ge of the substrate；
(a4) fill the isolation channel to form the isolated area of the plasma pin diodes.
5. preparation method as claimed in claim 4, it is characterised in that first protective layer include the first silicon dioxide layer and
First silicon nitride layer；Correspondingly, step (a1) includes：
(a11) in the SiGe Surface Creations silica forming the first silicon dioxide layer；
(a12) in the first silicon dioxide layer Surface Creation silicon nitride forming the first silicon nitride layer.
6. preparation method as claimed in claim 5, it is characterised in that step (b) includes：
(b1) the second protective layer is formed in the substrate surface；
(b2) the second isolated area figure is formed on second protective layer using photoetching process；
(b3) using dry etch process the specified location of the second isolated area figure etch second protective layer and
The substrate is forming the p-type groove and the N-type groove.
7. preparation method as claimed in claim 6, it is characterised in that second protective layer include the second silicon dioxide layer and
Second silicon nitride layer；Correspondingly, step (b1) includes：
(b11) in the SiGe Surface Creations silica forming the second silicon dioxide layer；
(b12) in the second silicon dioxide layer Surface Creation silicon nitride forming the second silicon nitride layer.
8. preparation method as claimed in claim 7, it is characterised in that step (e) includes：
(e1) p-type groove described in photoetching and the N-type groove；
(e2) p type impurity and N-type are injected separately into the p-type groove and the N-type groove using the method with glue ion implanting
Impurity is forming the first p-type active area and the first N-type active area；
(e3) photoresist is removed.
9. preparation method as claimed in claim 8, it is characterised in that step (f) includes：
(f1) the p-type groove and the N-type groove are filled using polysilicon；
(f2) after substrate described in planarizing process, polysilicon layer is formed over the substrate；
(f3) polysilicon layer described in photoetching, and using the method with glue ion implanting to the p-type groove and the N-type groove institute
P type impurity and N-type impurity are injected separately into position to form the second p-type active area and the second N-type active area and while form p-type
Contact zone and N-type contact zone；
(f4) photoresist is removed；
(f5) polysilicon layer beyond the p-type contact zone and the N-type contact zone is removed using wet etching.
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