CN106449734A - SPiN diode with GaAs-Ge-GaAs heterostructure and preparation method of SPiN diode - Google Patents
SPiN diode with GaAs-Ge-GaAs heterostructure and preparation method of SPiN diode Download PDFInfo
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- 229910001218 Gallium arsenide Inorganic materials 0.000 title claims abstract description 63
- 238000002360 preparation method Methods 0.000 title claims abstract description 30
- 239000000463 material Substances 0.000 claims abstract description 65
- 238000000034 method Methods 0.000 claims abstract description 55
- 239000000758 substrate Substances 0.000 claims abstract description 43
- 238000005516 engineering process Methods 0.000 claims abstract description 20
- 238000002955 isolation Methods 0.000 claims abstract description 20
- 238000005468 ion implantation Methods 0.000 claims abstract description 14
- 238000004544 sputter deposition Methods 0.000 claims abstract description 9
- 229910052751 metal Inorganic materials 0.000 claims abstract description 8
- 239000002184 metal Substances 0.000 claims abstract description 8
- 239000010410 layer Substances 0.000 claims description 81
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 31
- 239000011241 protective layer Substances 0.000 claims description 23
- 239000000377 silicon dioxide Substances 0.000 claims description 21
- 239000007787 solid Substances 0.000 claims description 19
- 229910052681 coesite Inorganic materials 0.000 claims description 11
- 229910052906 cristobalite Inorganic materials 0.000 claims description 11
- 229910052682 stishovite Inorganic materials 0.000 claims description 11
- 229910052905 tridymite Inorganic materials 0.000 claims description 11
- 238000001259 photo etching Methods 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 239000012535 impurity Substances 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 5
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 claims description 4
- 238000002161 passivation Methods 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 3
- 239000007769 metal material Substances 0.000 claims description 3
- 238000005530 etching Methods 0.000 abstract description 7
- 238000000151 deposition Methods 0.000 abstract description 4
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 abstract 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 29
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 29
- 238000002347 injection Methods 0.000 description 11
- 239000007924 injection Substances 0.000 description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- 235000012239 silicon dioxide Nutrition 0.000 description 10
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 9
- 229910052732 germanium Inorganic materials 0.000 description 8
- 150000002500 ions Chemical class 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 238000009826 distribution Methods 0.000 description 6
- 230000008901 benefit Effects 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052752 metalloid Inorganic materials 0.000 description 1
- 150000002738 metalloids Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000036470 plasma concentration Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000004408 titanium dioxide Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
- H01L29/8725—Schottky diodes of the trench MOS barrier type [TMBS]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/66196—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices with an active layer made of a group 13/15 material
- H01L29/66204—Diodes
- H01L29/66219—Diodes with a heterojunction, e.g. resonant tunneling diodes [RTD]
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Abstract
The invention relates to a SPiN diode with a GaAs-Ge-GaAs heterostructure and a preparation method of the SPiN diode. The preparation method comprises the following steps: (1) selecting a GeOI substrate; (b) etching a Ge layer as a top layer of the GeOI substrate to form a first groove and a second groove in the Ge layer as the top layer; (c) depositing GaAs materials in the first groove and the second groove respectively; (d) carrying out P-type ion implantation on the GaAs material in the first groove by utilizing an ion implantation process to form a P-type active region, and carrying out N-type ion implantation on the GaAs material in second first groove by utilizing second ion implantation process to form an N-type active region; and (e) forming lead wire holes in the surfaces of the P-type active region and the N-type active region respectively, and sputtering metal to form the SPiN diode with the GaAs-Ge-GaAs heterostructure. According to the SPiN diode disclosed by the embodiment of the invention, by utilizing a deep trench isolation technology and the ion implantation process, the high-performance Ge-based SPiN diode suitable for forming a solid-state plasma antenna can be prepared and supplied.
Description
Technical field
The present invention relates to bis- pole of SPiN of technical field of integrated circuits, more particularly to a kind of GaAs-Ge-GaAs heterojunction structure
Pipe and preparation method thereof.
Background technology
At present, domestic and international application is body silicon materials in the material of the SPiN diode employing of plasma reconfigurable antenna,
Be present the relatively low problem of intrinsic region carrier mobility, impact SPiN diode intrinsic region carrier concentration in this material, and then affect
Its solid plasma bulk concentration；And the P area of the structure and N area are formed using injection technology mostly, the method requires injectant
Amount and energy are larger, to equipment requirements height and incompatible with existing process；And diffusion technique is adopted, though junction depth is deeper, simultaneously
P area is larger with the area in N area, and integrated level is low, and doping content is uneven, affects the electric property of SPiN diode, causes solid-state
Plasma density and the poor controllability of distribution.
Therefore, which kind of material and technique is selected just to become to be applied to solid plasma antenna making a kind of SPiN diode
Obtain particularly important.
Content of the invention
Therefore, it is to solve technological deficiency and the deficiency that prior art is present, it is different that the present invention proposes a kind of GaAs-Ge-GaAs
SPiN diode of matter structure and preparation method thereof.
Specifically, the preparation side of the SPiN diode of a kind of GaAs-Ge-GaAs heterojunction structure that the embodiment of the present invention is proposed
Method, the SPiN diode of the GaAs-Ge-GaAs heterojunction structure is used for making solid plasma antenna, the preparation method bag
Include step：
A () chooses GeOI substrate,
B () etches the top layer Ge layer of the GeOI substrate to form first groove and the second ditch in the top layer Ge layer
Groove；
C () deposits GaAs material in the first groove and the second groove；
D () carries out p-type ion implanting formation p-type using ion implantation technology to the GaAs material in the first groove has
Source region, carries out N-type ion implanting and forms N-type active area to the GaAs material in the second groove；
(e) the p-type active area and the N-type surfaces of active regions form fairlead and splash-proofing sputtering metal formed described
The SPiN diode of GaAs-Ge-GaAs heterojunction structure.
In one embodiment of the invention, before step (b), also include：
(x1) in the GeOI substrate surface, the first protective layer is deposited；
(x2) adopt the first mask plate, using dry etch process etch first protective layer and the GeOI substrate with
Isolated groove is formed in the GeOI substrate；
(x3) in the isolated groove, isolated material is filled using CVD technique；
(x4) isolated material for being removed using CMP outside first protective layer and the isolated groove forms institute
State the isolation area of the SPiN diode of GaAs-Ge-GaAs heterojunction structure.
In one embodiment of the invention, step (x1) includes：
(x11) in the GeOI substrate surface, SiO is generated2Material forms a SiO2Layer；
(x12) in a SiO2Layer surface generates SiN material and forms the first SiN layer to ultimately form the described first guarantor
Sheath.
In one embodiment of the invention, step (b) includes：
(b1) in the GeOI substrate surface, the second protective layer is formed；
(b2) the second mask plate being adopted, second protective layer and the top layer Ge is etched using anisotropic etch process
Layer is to form the first groove and the second groove in the top layer Ge layer.
In one embodiment of the invention, step (b1) includes：
(b11) in the GeOI substrate surface, SiO is generated2Material forms the 2nd SiO2Layer；
(b12) in the 2nd SiO2Layer surface generates SiN material and forms the second SiN layer to ultimately form the described second guarantor
Sheath.
In one embodiment of the invention, before step (c), also include：
(y1) at 800 DEG C～900 DEG C, aoxidize the first groove and the second groove with the first groove and
The inwall of the second groove forms oxide layer；
(y2) wet-etching technology is utilized, and the oxide layer of the first groove and the second groove inwall is etched to complete
The first type groove and the planarizing of the second groove inwall.
In one embodiment of the invention, step (c) includes：
(c1) MOCVD technique is utilized, in the first groove and the second groove, deposits GaAs material；
(c2) utilize CMP, remove the first groove and the outer certain thickness GaAs material of the second groove with
Complete the planarizing of the first groove and the second groove.
In one embodiment of the invention, step (d) includes：
(d1) adopt the 3rd mask plate, using ion implantation technology the GaAs material in the first groove is carried out B from
Son injection forms the p-type active area；
(d2) adopt the 4th mask plate, the GaAs material using ion implantation technology in the second groove carry out P from
Son injection forms the N-type active area；
(d3) in the p-type active area and the N-type surfaces of active regions, SiO is deposited2Material, activates institute using annealing process
State the impurity of p-type active area and the N-type active area；
(d4) SiO is removed2Material.
In one embodiment of the invention, step (e) includes：
(e1) in whole substrate surface, SiO is deposited2Material；
(e2) the 5th mask plate is adopted, using anisotropic etch process, etching the p-type active area and the N-type has
The SiO of area surface portion2Material forms the fairlead；
(e3) splash-proofing sputtering metal material in the fairlead；
(e4) Passivation Treatment photoetching PAD is to form the SPiN diode of the GaAs-Ge-GaAs heterojunction structure.
Additionally, a kind of SPiN diode of GaAs-Ge-GaAs heterojunction structure of another embodiment of the present invention proposition, is used for
Solid plasma antenna is made, the SPiN diode of the GaAs-Ge-GaAs heterojunction structure adopts above-mentioned any means embodiment
It is obtained.
From the foregoing, it will be observed that the embodiment of the present invention is by employing heterojunction structure to SPiN diode, so as to improve current-carrying
The injection efficiency of son and electric current, therefore the performance of heterogeneous germanio SPiN diode is made better than homogeneity SPiN diode.Also, polycrystalline
The lattice mismatch of GaAs material and Ge is especially little, so the interface at heterojunction boundary is too especially little, therefore improves the property of device
Energy.In addition, in the conventional P area for making SPiN diode and the preparation technology in N area, all being formed using injection technology, the method will
Ask implantation dosage and energy larger, to equipment requirements height and incompatible with existing process；And adopt diffusion technique, though junction depth is relatively
Deep, but P area is larger with the area in N area simultaneously, and integrated level is low, and doping content is uneven, affects the electric property of SPiN diode,
Cause the poor controllability of solid plasma bulk concentration and distribution.
By the detailed description below with reference to accompanying drawing, the other side of the present invention and feature become obvious.But should know
Road, the accompanying drawing is only the purpose design that explains, not as the restriction of the scope of the present invention, this is because which should refer to
Appended claims.It should also be noted that unless otherwise noted, it is not necessary to scale accompanying drawing, they only try hard to concept
Ground explanation structure described herein and flow process.
Description of the drawings
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Fig. 1 is a kind of manufacture method flow process of the SPiN diode of GaAs-Ge-GaAs heterojunction structure of the embodiment of the present invention
Figure；
Fig. 2 a- Fig. 2 r illustrates for a kind of preparation method of the SPiN of GaAs-Ge-GaAs heterojunction structure of the embodiment of the present invention
Figure；
Fig. 3 illustrates for a kind of device architecture of the SPiN diode of GaAs-Ge-GaAs heterojunction structure of the embodiment of the present invention
Figure.
Specific embodiment
Understandable for enabling the above objects, features and advantages of the present invention to become apparent from, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
The present invention proposes a kind of GaAs-Ge-GaAs hetero-junctions suitable for forming solid state plasma reconfigurable antenna
The preparation method of the SPiN diode of structure and device.The GaAs-Ge-GaAs heterojunction structure be based on the germanium in dielectric substrate
(Germanium-On-Insulator, abbreviation GeOI) forms horizontal PiN diode, its plus during Dc bias, DC current
Can form, on its surface, the solid state plasma that free carrier (electronics and hole) constitutes, the plasma has metalloid spy
Property, i.e., there is reflection to electromagnetic wave, its reflection characteristic is close with the microwave transmission characteristic of surface plasma, concentration and distribution
Cut is closed.
The horizontal SPiN diode plasma reconfigurable antenna of GeOI can be arranged by array by the horizontal SPiN diode of GeOI
Row are combined, using in external control array SPiN diode selecting conducting, make the array formed dynamic solid-state etc. from
Daughter striped, possess the function of antenna, there is to specific electromagnetic wave transmitting and receive capabilities, and the antenna can pass through in array
The selectivity conducting of SPiN diode, changes solid state plasma shape of stripes and distribution, so as to realize the reconstruct of antenna, in state
With important application prospect in terms of anti-communication and Radar Technology.
Hereinafter, the technological process of GeOI base SPiN diode prepared by the present invention is described in further detail.In figure
In, the thickness in layer and region for convenience of explanation, has been zoomed in or out, shown size does not represent actual size.
Embodiment one
Refer to the system of Fig. 1, Fig. 1 for a kind of SPiN diode of GaAs-Ge-GaAs heterojunction structure of the embodiment of the present invention
Make method flow diagram, the method is applied to preparation based on the horizontal SPiN diode of GeOI, and the horizontal SPiN diode master of the GeOI
It is used for making solid plasma antenna.The method comprises the steps：
A () chooses GeOI substrate,
B () etches the top layer Ge layer of the GeOI substrate to form first groove and the second ditch in the top layer Ge layer
Groove；
C () deposits GaAs material in the first groove and the second groove；
D () carries out p-type ion implanting formation p-type using ion implantation technology to the GaAs material in the first groove has
Source region, carries out N-type ion implanting and forms N-type active area to the GaAs material in the second groove；
(e) the p-type active area and the N-type surfaces of active regions form fairlead and splash-proofing sputtering metal formed described
The SPiN diode of GaAs-Ge-GaAs heterojunction structure.
Wherein, for step (a), it is the reason for using GeOI substrate, for solid plasma antenna as which needs
Good microwave property, and SPiN diode is in order to meet this demand, needs to have good isolation characteristic and carrier i.e.
The restriction ability of solid state plasma, and GeOI substrate due to its have can with isolation channel be conveniently formed pin area of isolation,
Silicon dioxide (SiO2) carrier can be also that solid state plasma is limited in top layer Ge, it is advantageous to adopting GeOI conduct
The substrate of SPiN diode.Also, as the carrier mobility of germanium material is than larger, therefore can be formed in I area higher etc.
Plasma levels, improve the performance of device.
In addition, before step (b), also including：
(x1) in the GeOI substrate surface, the first protective layer is deposited；
(x2) adopt the first mask plate, using dry etch process etch first protective layer and the GeOI substrate with
Isolated groove is formed in the GeOI substrate；
(x3) in the isolated groove, isolated material is filled using CVD technique；
(x4) remove the isolated material outside first protective layer and the isolated groove using CMP to be formed
The isolation area of the SPiN diode of the GaAs-Ge-GaAs heterojunction structure.
Specifically, the first protective layer includes the first silicon dioxide (SiO2) layer and the first silicon nitride (SiN) layer；Then first protect
The formation of sheath includes：Silicon dioxide (SiO is generated in GeOI substrate surface2) to form the first silicon dioxide (SiO2) layer；?
One silicon dioxide (SiO2) layer surface generate silicon nitride (SiN) to form the first silicon nitride (SiN) layer.The benefit of do so exists
In using silicon dioxide (SiO2) loose nature, by the stress isolation of silicon nitride (SiN) so as to can not conduct into top layer Ge,
Ensure that stablizing for top layer Ge performance；Based on silicon nitride (SiN) and high selectivity of the Ge in dry etching, using silicon nitride
(SiN) as dry etching, film is sheltered, it is easy to which technique is realized.It is, of course, understood that the number of plies of protective layer and protection
The material of layer is not limited herein, as long as protective layer can be formed.
Wherein, thickness of the depth of isolation channel more than or equal to the top layer Ge of GeOI substrate, it is ensured that titanium dioxide in follow-up groove
Silicon (SiO2) connection with the oxide layer of GeOI substrate, form complete being dielectrically separated from.
Furthermore, for step (b), specifically may include steps of：
(b1) in the GeOI substrate surface, the second protective layer is formed；
(b2) the second mask plate being adopted, second protective layer and the top layer Ge is etched using anisotropic etch process
Layer is to form the first groove and the second groove in the top layer Ge layer.
Specifically, the second protective layer includes the second silicon dioxide (SiO2) layer and the second silicon nitride (SiN) layer；Then second protect
The formation of sheath includes：Silicon dioxide (SiO is generated in GeOI substrate surface2) to form the second silicon dioxide (SiO2) layer；?
Two silicon dioxide (SiO2) layer surface generate silicon nitride (SiN) to form the second silicon nitride (SiN) layer.The benefit of do so is similar to
In the effect of the first protective layer, here is omitted.
Preferably, distance of the bottom of the first groove and second groove away from top layer Ge bottom is 0.5 micron～30 microns,
The deep trouth being generally acknowledged that is formed, so can form Impurity Distribution when p-type and N-type active area is formed uniform and highly doped dense
P, N area of degree and tie with precipitous Pi and Ni, be beneficial to raising i area plasma density.
Furthermore, before step (c), can also include：
(y1) at 800 DEG C～900 DEG C, aoxidize the first groove and the second groove with the first groove and
The inwall of the second groove forms oxide layer；
(y2) wet-etching technology is utilized, and the oxide layer of the first groove and the second groove inwall is etched to complete
The first type groove and the planarizing of the second groove inwall.
This have the advantage that：Can prevent the projection of trenched side-wall from electric field concentrated area is formed, cause Pi and Ni knot
Puncture.
Furthermore, step (c) can include：
(c1) MOCVD technique is utilized, in the first groove and the second groove, deposits GaAs material；
(c2) utilize CMP, remove the first groove and the outer certain thickness GaAs material of the second groove with
Complete the planarizing of the first groove and the second groove.
Furthermore, for step (d), specifically may include steps of：
Step (d) includes：
(d1) adopt the 3rd mask plate, using ion implantation technology the GaAs material in the first groove is carried out B from
Son injection forms the p-type active area；
(d2) adopt the 4th mask plate, the GaAs material using ion implantation technology in the second groove carry out P from
Son injection forms the N-type active area；
(d3) in the p-type active area and the N-type surfaces of active regions, SiO is deposited2Material, activates institute using annealing process
State the impurity of p-type active area and the N-type active area；
(d4) SiO is removed2Material.
In addition, step (e) can include：
(e1) in whole substrate surface, SiO is deposited2Material；
(e2) the 5th mask plate is adopted, using anisotropic etch process, etching the p-type active area and the N-type has
The SiO of area surface portion2Material forms the fairlead；
(e3) splash-proofing sputtering metal material in the fairlead；
(e4) Passivation Treatment photoetching PAD is to form the SPiN diode of the GaAs-Ge-GaAs heterojunction structure.
The preparation method of the SPiN diode of the GaAs-Ge-GaAs heterojunction structure that the present invention is provided possesses following advantage：
(1) germanium material used by SPiN diode, due to its high mobility and the characteristic of big carrier lifetime, can be effective
Improve the solid plasma bulk concentration of PiN diode；
(2) SPiN diode adopts heterojunction structure, as i area is the high and energy gap ratio of germanium, its carrier mobility
Narrower, in P, N area, filling polycrystalline GaAs is so as to form heterojunction structure, and the energy gap of GaAs material is more than germanium, therefore can produce
High injection ratio, improves device performance；
(3) SPiN diode adopts heterojunction structure, and the lattice mismatch ratio of the polycrystalline GaAs in the germanium in I area and P, N area
Relatively low, therefore the defect at heterojunction boundary is little, so as to improve the performance of device；
(4) SPiN diode employs a kind of Deep trench isolation technique based on etching, is effectively improved device
Breakdown voltage, it is suppressed that impact of the leakage current to device performance.
Embodiment two
Fig. 2 a- Fig. 2 r, Fig. 2 a- Fig. 2 r is referred to for a kind of GaAs-Ge-GaAs heterojunction structure of the embodiment of the present invention
The preparation method schematic diagram of SPiN diode, on the basis of above-described embodiment one, with prepare channel length as 22nm (solid-state etc.
Ion range length be 100 microns) GaAs-Ge-GaAs heterojunction structure SPiN diode as a example by be described in detail, specifically
Step is as follows：
Step 1, backing material preparation process：
(1a) as shown in Figure 2 a, (100) crystal orientation is chosen, and it is 10 that doping type is p-type, doping content14cm-3GeOI lining
Egative film 101, the thickness of top layer Ge is 50 μm；
(1b) as shown in Figure 2 b, using chemical vapor deposition (Chemical vapor deposition, abbreviation CVD)
Method, deposits a SiO of one layer of 40nm thickness on GeOI substrate2Layer 201；
(1c) using the method for chemical vapor deposition, a Si of one layer of 2 μ m thick is deposited on substrate3N4/ SiN layer
202；
Step 2, isolates preparation process：
(2a) as shown in Figure 2 c, using mask plate, isolation area is formed on above-mentioned protective layer by photoetching process, wet method is carved
Erosion the first Si of isolation area3N4/ SiN layer 202, forms isolation area figure；Using dry etching, formed in isolation area wide 5 μm, be deeply
50 μm of deep isolation trench 301；
(2b) as shown in Figure 2 d, using the method for CVD, SiO is deposited2The deep isolation trench is filled up by 401；
(2c) as shown in Figure 2 e, using chemically mechanical polishing (Chemical Mechanical Polishing, referred to as
CMP) method, removes the first Si of surface3N4/ SiN layer 202 and a SiO2Layer 201, makes GeOI substrate surface smooth；
Step 3, P, N area deep trouth preparation process：
(3a) as shown in figure 2f, using CVD method, on substrate, consecutive deposition prolongs two layer materials, and ground floor is 300nm thickness
2nd SiO of degree2Layer 601, the second layer is the 2nd Si of 500nm thickness3N4/ SiN layer 602；
(3b) as shown in Figure 2 g, using mask plate, photoetching P, N area deep trouth, the 2nd Si of wet etching P, N area3N4/ SiN layer
602 and the 2nd SiO2Layer 601, forms P, N area figure；Using dry etching, wide 4 μm, deep 5 μm deep trouth is formed in P, N area
701, P, the length of N area groove is determined according to the applicable cases in prepared antenna；
(3c) as shown in fig. 2h, at 850 DEG C, high-temperature process 10 minutes, oxidation trough inwall forms oxide layer 801, so that
P, N area groove inwall is smooth；
(3d) as shown in fig. 2i, the oxide layer 801 of P, N area groove inwall is removed using wet-etching technology.
Step 4, P, N contact area preparation process：
(4a) as shown in figure 2j, using Metalorganic chemical vapor deposition (Metal-organic Chemical Vapor
Deposition, abbreviation MOCVD) technique, polycrystalline GaAs1001 is deposited in P, N area groove, and groove is filled up；
(4b) as shown in Fig. 2 k, using CMP, surface polycrystalline GaAs1001 and the 2nd Si is removed3N4/ SiN layer 602, makes surface
Smooth；
(4c) as illustrated in figure 21, using the method for CVD, in one layer of polycrystalline GaAs1201 of surface deposition, thickness is 200～
500nm；
(4d) as shown in Fig. 2 m, using mask plate, photoetching P area active area, P is carried out using band glue ion injection method+Note
Enter, make P area active area doping content reach 0.5 × 1020cm-3, photoresist is removed, forms P contact 1301；
(4e) mask plate adopted, photoetching N area active area, N is carried out using band glue ion injection method+Injection, makes N area active
Area's doping content is 0.5 × 1020cm-3, photoresist is removed, forms N contact 1302；
(4f) as shown in Fig. 2 n, using selective etch, the polycrystalline GaAs1201 beyond P, N contact area is etched away, is formed
P, N contact area；
(4g) as shown in figure 2o, using the method for CVD, in surface deposition SiO21501, thickness is 800nm；
(4h) at 1000 DEG C, anneal 1 minute, make the impurity activation of ion implanting and advance impurity in GaAs；
Step 5, constitutes PIN diode step：
(5a) as illustrated in figure 2p, in P, N contact area lithography fair lead 1601；
(5b) as shown in figure 2q, substrate surface splash-proofing sputtering metal, forms metal silicide 1701 in 750 DEG C of alloys, and etches
Fall the metal on surface；
(5c) substrate surface splash-proofing sputtering metal, photoetching lead；
(5d) as shown in Fig. 2 r, Si is deposited3N4/ SiN formation passivation layer 1801, photoetching PAD, PIN diode is formed, as
Prepare solid plasma antenna material.
In the present embodiment, above-mentioned various technological parameters are illustration, according to the conventional meanses of those skilled in the art
The conversion that is done is the protection domain of the application.
The SPiN diode for being applied to solid plasma reconfigurable antenna prepared by the present invention, first, the germanium material that used
Material, due to its high mobility and the characteristic of big carrier lifetime, improves the solid plasma bulk concentration of SPiN diode；Separately
Outward, the P area of Ge base SPiN diode employs the polycrystalline GaAs mosaic technology of the deep etching based on etching, the technique with N area
Abrupt junction pi can be provided tie with ni, and pi knot, the junction depth of ni knot can be effectively improved, make the concentration of solid state plasma
Strengthen with the controllability of distribution, be conducive to preparing high performance plasma antenna；Secondly, germanium material is due to its oxide GeO
The characteristic of heat stability difference, the process of P area and the deep groove side wall planarizing of N area can be automatically performed in hot environment, simplify material
Preparation method；Again, the GeOI base SPiN diode for being applied to solid plasma reconfigurable antenna that prepared by the present invention is adopted
A kind of Deep trench isolation technique based on etching, is effectively improved the breakdown voltage of device, it is suppressed that leakage current is to device
The impact of part performance.
Embodiment three
Refer to the device architecture schematic diagram of Fig. 3, Fig. 3 for the heterogeneous Ge base SPiN diode of the embodiment of the present invention.Should
The SPiN diode of GaAs-Ge-GaAs heterojunction structure is made using above-mentioned preparation method as shown in Figure 1, specifically, should
The SPiN diode of GaAs-Ge-GaAs heterojunction structure prepares formation on GeOI substrate 301, and the P area 304 of SPiN diode,
N area 305 and the i area (intrinsic region) being laterally positioned between the P area 304 and the N area 305 are respectively positioned on the top layer of the GeOI substrate
In Ge302.Wherein, the SPiN diode can adopt STI deep trench isolation, i.e., the P area 304 and 305 outside of the N area are each provided with
One isolation channel 303, and thickness of the depth of the isolation channel 303 more than or equal to top layer Ge302.
In sum, principle and reality of the specific case to SPiN diode of the present invention and preparation method thereof used herein
The mode of applying is set forth, and the explanation of above example is only intended to help and understands the method for the present invention and its core concept；With
When, for one of ordinary skill in the art, according to the thought of the present invention, all have in specific embodiments and applications
Change part, in sum, this specification content should not be construed as limiting the invention, and protection scope of the present invention should be with institute
Attached claim is defined.
Claims (10)
1. a kind of preparation method of the SPiN diode of GaAs-Ge-GaAs heterojunction structure, it is characterised in that include：
A () chooses GeOI substrate；
B () etches the top layer Ge layer of the GeOI substrate to form first groove and second groove in the top layer Ge layer；
C () deposits GaAs material in the first groove and the second groove；
D () carries out p-type ion implanting formation p-type using ion implantation technology to the GaAs material in the first groove active
Area, carries out N-type ion implanting and forms N-type active area to the GaAs material in the second groove；
E () forms fairlead in the p-type active area and the N-type surfaces of active regions and splash-proofing sputtering metal forms the GaAs-Ge-
The SPiN diode of GaAs heterojunction structure.
2. preparation method as claimed in claim 1, it is characterised in that before step (b), also include：
(x1) in the GeOI substrate surface, the first protective layer is deposited；
(x2) the first mask plate is adopted, and first protective layer and the GeOI substrate is etched with institute using dry etch process
State in GeOI substrate and form isolated groove；
(x3) in the isolated groove, isolated material is filled using CVD technique；
(x4) isolated material for being removed outside first protective layer and the isolated groove using CMP forms described
The isolation area of the SPiN diode of GaAs-Ge-GaAs heterojunction structure.
3. preparation method as claimed in claim 2, it is characterised in that step (x1) includes：
(x11) in the GeOI substrate surface, SiO is generated2Material forms a SiO2Layer；
(x12) in a SiO2Layer surface generates SiN material and forms the first SiN layer to ultimately form first protective layer.
4. preparation method as claimed in claim 1, it is characterised in that step (b) includes：
(b1) in the GeOI substrate surface, the second protective layer is formed；
(b2) adopt the second mask plate, using anisotropic etch process etch second protective layer and the top layer Ge layer with
The first groove and the second groove are formed in the top layer Ge layer.
5. preparation method as claimed in claim 4, it is characterised in that step (b1) includes：
(b11) in the GeOI substrate surface, SiO is generated2Material forms the 2nd SiO2Layer；
(b12) in the 2nd SiO2Layer surface generates SiN material and forms the second SiN layer to ultimately form second protective layer.
6. preparation method as claimed in claim 1, it is characterised in that before step (c), also include：
(y1) at 800 DEG C～900 DEG C, the first groove and the second groove are aoxidized with the first groove and described
The inwall of second groove forms oxide layer；
(y2) wet-etching technology is utilized, etches the oxide layer of the first groove and the second groove inwall described to complete
First type groove and the planarizing of the second groove inwall.
7. preparation method as claimed in claim 1, it is characterised in that step (c) includes：
(c1) MOCVD technique is utilized, in the first groove and the second groove, deposits GaAs material；
(c2) CMP is utilized, and the first groove and the outer certain thickness GaAs material of the second groove is removed to complete
The first groove and the planarizing of the second groove.
8. preparation method as claimed in claim 1, it is characterised in that step (d) includes：
(d1) the 3rd mask plate is adopted, using ion implantation technology, B ion note is carried out to the GaAs material in the first groove
Enter to be formed the p-type active area；
(d2) the 4th mask plate is adopted, and the GaAs material using ion implantation technology in the second groove carries out P ion note
Enter to be formed the N-type active area；
(d3) in the p-type active area and the N-type surfaces of active regions, SiO is deposited2Material, activates the p-type using annealing process
Active area and the impurity of the N-type active area；
(d4) SiO is removed2Material.
9. preparation method as claimed in claim 1, it is characterised in that step (e) includes：
(e1) in whole substrate surface, SiO is deposited2Material；
(e2) the 5th mask plate is adopted, using anisotropic etch process, etches the p-type active area and the N-type active area
The SiO of surface portion position2Material forms the fairlead；
(e3) splash-proofing sputtering metal material in the fairlead；
(e4) Passivation Treatment photoetching PAD is to form the SPiN diode of the GaAs-Ge-GaAs heterojunction structure.
10. a kind of SPiN diode of GaAs-Ge-GaAs heterojunction structure, it is characterised in that for making solid plasma day
Line, the SPiN diode of the GaAs-Ge-GaAs heterojunction structure adopts the method system as any one of claim 1～9
?.
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| CN115084308A (en) * | 2021-03-15 | 2022-09-20 | 中国科学院物理研究所 | Germanium substrate-gallium arsenide/germanium heterojunction film composite structure and preparation method and application thereof |
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| CN101714591A (en) * | 2009-11-10 | 2010-05-26 | 大连理工大学 | Method for manufacturing silicon photoelectric diode |
| CN102842595A (en) * | 2011-06-20 | 2012-12-26 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
| CN105977338A (en) * | 2016-07-18 | 2016-09-28 | 苏州北鹏光电科技有限公司 | Low-dark-current PIN detector and processing method thereof |
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|---|---|---|---|---|
| CN101714591A (en) * | 2009-11-10 | 2010-05-26 | 大连理工大学 | Method for manufacturing silicon photoelectric diode |
| CN102842595A (en) * | 2011-06-20 | 2012-12-26 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
| CN105977338A (en) * | 2016-07-18 | 2016-09-28 | 苏州北鹏光电科技有限公司 | Low-dark-current PIN detector and processing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115084308A (en) * | 2021-03-15 | 2022-09-20 | 中国科学院物理研究所 | Germanium substrate-gallium arsenide/germanium heterojunction film composite structure and preparation method and application thereof |
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