CN105977338A - Low-dark-current PIN detector and processing method thereof - Google Patents
Low-dark-current PIN detector and processing method thereof Download PDFInfo
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- CN105977338A CN105977338A CN201610562077.7A CN201610562077A CN105977338A CN 105977338 A CN105977338 A CN 105977338A CN 201610562077 A CN201610562077 A CN 201610562077A CN 105977338 A CN105977338 A CN 105977338A
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- 238000000034 method Methods 0.000 claims description 30
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 28
- 230000004888 barrier function Effects 0.000 claims description 23
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- 229910052681 coesite Inorganic materials 0.000 claims description 16
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- 229910052682 stishovite Inorganic materials 0.000 claims description 16
- 229910052905 tridymite Inorganic materials 0.000 claims description 16
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- 238000002360 preparation method Methods 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 14
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- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
- H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier
- H01L31/105—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier being of the PIN type
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- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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Abstract
The invention discloses a low-dark-current PIN detector comprising a substrate. A P-type ohmic contact layer is grown on the upper end surface of the substrate. At least one P-type ohmic contact electrode contacted with the P-type ohmic contact layer is arranged on the P-type ohmic contact layer. An antireflection film of the specific thickness for different wavelength is grown on the upper end surface of the substrate. The upper end surface of the substrate is provided with two isolation grooves which are used for realizing blocking of the internal electric field of a device and the edge of the device. The isolation grooves are arranged at the two sides of the P-type ohmic contact layer. Isolation material is filled in the isolation grooves. A blocking layer covers the area apart from the grooves of the upper end surface of the substrate. An N-type ohmic contact layer and N-type ohmic contact electrodes are grown on the lower end surface of the substrate from the top to the bottom in turn in a covering way. Dark current in the device can be effectively reduced and the use effect is excellent so that the low-dark-current PIN detector has extremely high use and popularization value.
Description
Technical field
The present invention relates to a kind of photodetector, be specifically related to a kind of low-dark current PIN detector, belong to semiconductor photoelectric device field.
Background technology
PIN detector is as important " carrier " realizing optical signal detection, have that technique is simple, detection efficient is high, steady performance, in the applications such as remotely monitored sensing, industry, military and national defense, medical treatment, Aero-Space, survey of deep space, play important support effect, be the commanding elevation seized of every country.Such as in the high energy radial imaging such as safety check, medical treatment, PIN photoelectric detector coordinates with scintillator, it is achieved low light signals is converted to the signal of telecommunication and exports the process of imaging.
The dark current of PIN detector, can be divided into according to the relation of device size: the line dark current relevant with girth and the face dark current relevant with area, and the dark current compensation unrelated with size.Line dark current is mainly determined by sidewall leakage stream, and face dark current is then determined by factors such as the dissufion current of device inside, thermally stimulated current, generation recombination currents.Along with the raising of integrated level, the size of photodetector is constantly reducing, and integrated level improves constantly, and reduces power attenuation and the cost of system simultaneously.But experimental data shows, when the device gross area is less than 1 mm2Time, its line dark current is more than 25 times of face dark current.
Specifically, line dark current is mainly derived from the factors such as sidewall leakage, scribing process or side wall passivation be bad and all can improve the line dark current of device.Owing to PIN detector is generally operational under low bias even zero-bias, the online dark current of sidewall leakage therefore caused by its internal electric field accounts for major part.Again because the junction depth of PIN detector is relatively deep, the most traditional ion implantation technology is difficult to be directly applied for the production and processing of PIN detector.
In sum, how to design a kind of novel PIN detector, from structure, reduce the dark current of device, isolate the line dark current relevant to electric field the most as much as possible, just become the staff's problem demanding prompt solution in this area.
Summary of the invention
In view of prior art exists drawbacks described above, the purpose of the present invention is to propose to a kind of low-dark current PIN detector.
The purpose of the present invention, will be achieved by the following technical programs:
nullA kind of low-dark current PIN detector，Can be used for infrared、Visible ray、Light detection in the range of ultraviolet or terahertz wave band，Including substrate，Described Grown has p-type ohmic contact layer，It is coated with anti-reflection film on described p-type ohmic contact layer，At least one p-type Ohm contact electrode touched with described p-type ohmic contact layer it is provided with on described anti-reflection film，The upper surface of described substrate offers a circle for realizing the isolated groove that device inside electric field blocks with device edge，Described isolated groove is positioned at the outer circumferential side of described p-type ohmic contact layer，It is filled with barrier material in described isolated groove，Region in addition to described shape groove, the upper surface of described substrate is all covered with barrier layer，The upper surface of described barrier layer is coated with anti-reflection film，The lower surface of described substrate covers growth the most successively N-type ohmic contact layer and N-type Ohm contact electrode.
Preferably, the material of described substrate is Si, GaAs, GaN, InP, Ge, SiC, SOI or GOI.
Preferably, described anti-reflection film offers at least one for by exposed for described p-type ohmic contact layer electrode through hole out, described p-type Ohm contact electrode touches with described p-type ohmic contact layer by described electrode through hole.
Preferably, described p-type Ohm contact electrode is arranged at the both side ends position of described p-type ohmic contact layer upper surface.
Preferably, described low-dark current PIN detector includes one for photosensitive active area, within described active area is positioned at described p-type Ohm contact electrode.
Preferably, the plane at place, described isolated groove lower surface is less than the plane at place, described p-type ohmic contact layer lower surface.
Preferably, the material of described anti-reflection film is SiNxOr SiO2, the thickness of described anti-reflection film is 60 ~ 160nm.
Preferably, the material of described barrier material is SiO2, the material of described barrier layer is SiO2, the thickness of described barrier layer is 400 ~ 600nm.
Present invention further teaches a kind of processing method for preparing above-mentioned low-dark current PIN detector, it is characterised in that comprise the steps:
Step 1, need the material of resistivity 2000 Ω/more than cm substrate is selected according to processing, and described substrate is carried out Chemical cleaning, ensure the cleanliness factor of described substrate in order to avoid affecting late stage process, at the SiO of one layer of 400 ~ 600nm of the upper surface of described substrate deposit2, carrying out photoetching subsequently in the upper surface of described substrate, etch a circle isolated groove in patterned area afterwards, etching depth is 2 ~ 6 μm；
Step 2, upper surface to described substrate carry out thermal oxidation, make the upper surface of described substrate form the fine and close SiO of one layer of 20nm2Layer, subsequently at the SiO of one layer of 2 ~ 6 μm of the upper surface of described substrate deposit2, to ensure that described isolated groove is completely filled, afterwards the upper surface of described substrate is chemically-mechanicapolish polished, removes unnecessary oxide；
Step 3, the upper surface of described substrate deposit one layer of 400 ~ 600nm SiO2, carry out photoetching subsequently in the upper surface of described substrate, and to described patterned area ion implanting B, make the upper surface of described substrate form p-type ohmic contact layer, and ensure that its doping content is 1 × 1019 ~1×1020 cm-3；
Step 4, described substrate being carried out the high temperature anneal, activate with the foreign ion that will inject, annealing temperature is 900 ~ 1100 DEG C, and annealing time is 30 ~ 60min；
Step 5, the upper surface of described substrate deposit one layer of 60 ~ 160nm SiN or SiO2As anti-reflection film；
Step 6, carry out photoetching in the upper surface of described substrate and on described anti-reflection film, etch electrode through hole, the Al of 500nm ~ 2 μm is deposited subsequently to form p-type Ohm contact electrode above described electrode through hole, and carry out photoetching, corrosion electrode, expose for photosensitive active area；
Step 7, by described substrate back-off, make the lower surface of described substrate upwards, and to its lower surface ion implanting P, form N-shaped ohmic contact layer, and ensure that its doping content is 1 × 1019 ~1×1020 cm-3, subsequently described substrate is carried out process annealing process；
Step 8, on described N-shaped ohmic contact layer, deposit the Al of one layer of 300nm ~ 2 μm again, form N-shaped Ohm contact electrode, and then complete device fabrication.
Preferably, described deposit processing method includes magnetron sputtering or PECVD growth；Described lithography method includes dry etch process or wet corrosion technique.
The prominent effect of the present invention is: compared with tradition PIN detector, the detection wavelength of the present invention is wider, it is widely portable to infrared, visible ray, ultraviolet or terahertz wave band, and the present invention can meet the needs of the various ways detections such as the incidence of device front or back surface incident by structural modification, the suitability and practicality are higher.Meanwhile, the present invention can be prevented effectively from conventional processes intermediate ion and inject the impurity defect and lattice damage introduced, and reduces the dark current of device.Additionally, the groove structure in the present invention can be by the isolation of device edge Yu device active region, it is achieved that device edge and the blocking-up of active area electric field, weaken the diffusion of few son, further reduce the dark current of device, improve the using effect of the present invention.
In sum, the present invention can effectively reduce the dark current of device inside, and using effect is excellent, has the highest use and promotional value.
Hereinafter accompanying drawing the most in conjunction with the embodiments, is described in further detail the detailed description of the invention of the present invention, so that technical solution of the present invention is more readily understood, grasps.
Accompanying drawing explanation
Fig. 1 is Electric Field Distribution schematic diagram under the schematic cross-section of the present invention and zero-bias；
Fig. 2 is the schematic diagram of step 1 in processing method of the present invention；
Fig. 3 is the schematic diagram of step 2 in processing method of the present invention；
Fig. 4 is the schematic diagram of step 3 in processing method of the present invention；
Fig. 5 is the schematic diagram of step 5 in processing method of the present invention；
Fig. 6 is the schematic diagram of step 6 in processing method of the present invention；
Fig. 7 is the schematic diagram of step 7 in processing method of the present invention；
Fig. 8 is the schematic diagram of step 8 in processing method of the present invention；
Wherein: 101, substrate, 102, anti-reflection film, 103, p-type ohmic contact layer, 104, isolated groove, 105, N-shaped ohmic contact layer, 106, p-type Ohm contact electrode, 107, N-shaped Ohm contact electrode, 108, barrier layer.
Detailed description of the invention
Present invention is disclosed a kind of low-dark current PIN detector.
nullAs shown in the figure，A kind of low-dark current PIN detector，Can be used for infrared、Visible ray、Light detection in the range of ultraviolet or terahertz wave band，Including substrate 101，The growth of described substrate 101 upper surface has p-type ohmic contact layer 103，It is coated with anti-reflection film 102 on described p-type ohmic contact layer 103，At least one p-type Ohm contact electrode 106 touched with described p-type ohmic contact layer 103 it is provided with on described anti-reflection film 102，The upper surface of described substrate 101 offers a circle for realizing the isolated groove 104 that device inside electric field blocks with device edge，Described isolated groove 104 is positioned at the outer circumferential side of described p-type ohmic contact layer 103，It is filled with barrier material in described isolated groove 104，Region in addition to described shape groove, the upper surface of described substrate 101 is all covered with barrier layer 108，The upper surface of described barrier layer 108 is coated with anti-reflection film 102，The lower surface of described substrate 101 covers growth the most successively N-type ohmic contact layer 105 and N-type Ohm contact electrode 106.
The material of described substrate 101 is Si, GaAs, GaN, InP, Ge, SiC, SOI(novel silicon base integrated circuit material) or GOI(Novel Ge base integrated circuit material).In the present embodiment, described substrate 101 selects Si to make.
Offer on described anti-reflection film 102 at least one for by exposed for described p-type ohmic contact layer 103 electrode through hole out, described p-type Ohm contact electrode 106 touches with described p-type ohmic contact layer 103 by described electrode through hole.
Described anti-reflection film 102 is different due to the existence effect of electrode, and the described anti-reflection film 102 being positioned on described p-type ohmic contact layer 103 can strengthen the absorbance of light, and the described anti-reflection film 102 being positioned on described barrier layer 108 can play good passivation effect.
Being provided with two p-type Ohm contact electrodes 106 on described anti-reflection film 102, described p-type Ohm contact electrode 106 is arranged at the both side ends position of described p-type ohmic contact layer 103 upper surface.
Described low-dark current PIN detector includes that one for photosensitive active area, described active area is between two described p-type Ohm contact electrodes 106.During the use of the present invention, probing light all can be injected from described active area.
The plane at trench bottom place, described isolated groove 104 lower surface is less than the plane at place, described p-type ohmic contact layer 103 lower surface.
Specifically, in the present embodiment, the degree of depth of the most described isolated groove 104 should be deeper than the thickness of described p-type ohmic contact layer 103.Such structure arranges and is because the present invention in use, and the zero-bias electric field that its active area produces exists a crest in the position, lower surface (the most described p-type ohmic contact layer 103 and the position, boundary of described substrate 101) of described p-type ohmic contact layer 103.The degree of depth making described isolated groove 104 exceedes this position, boundary and i.e. may further ensure that the isolation of device edge and device active region internal electric field, so that it is guaranteed that the using effect of the present invention.
The material of described anti-reflection film 102 is SiNxOr SiO, the thickness of described anti-reflection film 102 is 60 ~ 160nm。
Specifically, different and required photosensitive light source the wavelength of the characteristic of material selected by described anti-reflection film 102 is different, and its thickness changes the most therewith, and in the present embodiment, described anti-reflection film 102 selects thickness during SiN material less than selecting SiO2Time thickness.For more specifically, in the present embodiment, described anti-reflection film 102 can select the SiO of SiN or 93nm thickness of 70nm thickness2, the specification that both is different is identical with material effect in use.In addition it is also necessary to explanation, described anti-reflection film 102 is possible not only to increase the surface printing opacity of device, it is also possible to play passivation interface, the effect of reduction tracking current.
The material of described barrier material is metal or SiO2, the material of described barrier layer 108 is metal or SiO2, the thickness of described barrier layer 108 is 400 ~ 600nm.
In the present embodiment, the material of described barrier material is identical with the material of described barrier layer 108, and both is preferably SiO2, the thickness of described barrier layer 108 is 500nm.
Present invention further teaches a kind of processing method for preparing above-mentioned low-dark current PIN detector, comprise the steps:
Step 1, need the material of resistivity 2000 Ω/more than cm substrate 101 is selected according to processing, and described substrate 101 is carried out Chemical cleaning, ensure that the cleanliness factor of described substrate 101, in order to avoid affecting late stage process, deposits the SiO of one layer of 400 ~ 600nm in the upper surface of described substrate 1012, thickness is 500nm in the present embodiment, and the upper surface at described substrate 101 carries out photoetching subsequently, etches a circle isolated groove 104 in patterned area afterwards, and etching depth is 2 ~ 6 μm, is 4 μm at the present embodiment etching depth；
Step 2, upper surface to described substrate 101 carry out thermal oxidation, make the upper surface of described substrate 101 form the fine and close SiO of one layer of thin about 20nm2Layer, to improve the interfacial characteristics of described substrate (101) and implant, subsequently at the SiO of one layer of 3.5 ~ 4.5 μm of the upper surface of described substrate 101 deposit2, thickness is 4 μm in the present embodiment, and that need guarantee is deposited SiO herein2Thickness identical with the etching depth in step 1, to ensure that described isolated groove 104 is completely filled, afterwards the upper surface of described substrate 101 is chemically-mechanicapolish polished, removes unnecessary oxide；
Step 3, the upper surface of described substrate 101 deposit one layer of 400 ~ 600nm SiO2, thickness is 500nm in the present embodiment, and the upper surface at described substrate 101 carries out photoetching subsequently, and to described patterned area ion implanting B, makes the upper surface of described substrate 101 form p-type ohmic contact layer 103, and ensure that its doping content is 1 × 1019 ~1×1020 cm-3, doping content is preferably 1 × 10 in the present embodiment19 cm-3；
Step 4, described substrate 101 being carried out the high temperature anneal, activate with the foreign ion that will inject, annealing temperature is 900 ~ 1100 DEG C, and annealing time is 30 ~ 60min, and annealing temperature in the present embodiment is 1100 DEG C, and annealing time is 30min；
Step 5, the upper surface of described substrate 101 deposit one layer of 60 ~ 160nm SiN or SiO2As anti-reflection film 102, one layer of 70nm SiN or 93nmSiO can be deposited in the present embodiment in the upper surface of described substrate 1012；
Step 6, carry out photoetching in the upper surface of described substrate 101 and on described anti-reflection film 102, etch two electrode through holes, the Al of 500nm ~ 2 μm is deposited subsequently to form p-type Ohm contact electrode 106 above described electrode through hole, and carry out photoetching, corrosion electrode, expose for photosensitive active area, the method for sputtering can be used in the present embodiment to deposit the Al of 1.5 μm to form p-type Ohm contact electrode 106；
Step 7, by described substrate 101 back-off, make the lower surface of described substrate 101 upwards, and to its lower surface ion implanting P, form N-shaped ohmic contact layer 105, and ensure that its doping content is 1 × 1019 ~1×1020 cm-3, doping content is preferably 1 × 10 in the present embodiment20 cm-3, subsequently described substrate 101 is carried out process annealing process；
Step 8, on described N-shaped ohmic contact layer 105, deposit the AL of one layer of 300nm ~ 2 μm again, form N-shaped Ohm contact electrode 107, and then complete device fabrication, the Al of method deposit 500nm of sputtering can be used in the present embodiment to form N-shaped Ohm contact electrode 107.
Described deposit processing method includes magnetron sputtering or PECVD(plasma enhanced chemical vapor deposition method) growth；Described lithography method includes dry etch process or wet corrosion technique.
Also, it should be noted the described isolated groove 104 in the present invention is filled, the method for low-pressure chemical vapor phase deposition both can be used to be formed, it is also possible to utilize various Oxide chemical vapor deposition apparatus to complete.It addition, the material in the present invention selects and coating layer thickness is inventor and proves the optimal case drawn through test of many times, as used other materials or coating layer thickness, technical scheme may be directly resulted in and can not realize reducing the effect of device dark electric current.
The present invention can reduce the principle of dark current and be, (this is due in conventional processes to avoid the impurity defect that at groove, ion implanting introduces, implantation annealing is insufficient, it is easily caused the impurity after injection and can not be converted to instead type impurity by clearance-type impurity) and lattice damage, and then reduce device dark electric current.Additionally, the defect that causes due to scribing process of device edge or damage all can increase the dark current of device；Electric field region is diffused into additionally, due to few son, it is collected under the effect of electric field, this process also can produce dark current, and device edge and active area isolation can be opened by the groove structure of the present invention, achieve the blocking-up of device edge and active area electric field, weaken the diffusion of few son, thus reduce the dark current of device.
Compared with tradition PIN detector, the detection wavelength of the present invention is wider, being widely portable to infrared, visible ray, ultraviolet or terahertz wave band, and the present invention can meet the needs of the various ways detections such as the incidence of device front or back surface incident by structural modification, the suitability and practicality are higher.Meanwhile, the present invention can be prevented effectively from conventional processes intermediate ion and inject the impurity defect and lattice damage introduced, and reduces the dark current of device.Additionally, the groove structure in the present invention can be by the isolation of device edge Yu device active region, it is achieved that device edge and the blocking-up of active area electric field, further reduce the dark current of device, improve the using effect of the present invention.
In sum, the present invention can effectively reduce the dark current of device inside, and using effect is excellent, has the highest use and promotional value.
The present invention still has numerous embodiments, all employing equivalents or equivalent transformation and all technical schemes of being formed, within all falling within protection scope of the present invention.
Claims (10)
- null1. a low-dark current PIN detector，Can be used for infrared、Visible ray、Light detection in the range of ultraviolet or terahertz wave band，It is characterized in that: include substrate (101)，The upper growth of described substrate (101) has p-type ohmic contact layer (103)，It is coated with anti-reflection film (102) on described p-type ohmic contact layer (103)，At least one p-type Ohm contact electrode (106) touched with described p-type ohmic contact layer (103) it is provided with on described anti-reflection film (102)，The upper surface of described substrate (101) offers a circle for realizing the isolated groove (104) that device inside electric field blocks with device edge，Described isolated groove (104) is positioned at the outer circumferential side of described p-type ohmic contact layer (103)，Described isolated groove is filled with barrier material in (104)，Region in addition to described shape groove, the upper surface of described substrate (101) is all covered with barrier layer (108)，The upper surface of described barrier layer (108) is coated with anti-reflection film (102)，The lower surface of described substrate (101) covers growth the most successively N-type ohmic contact layer (105) and N-type Ohm contact electrode (106).
- Low-dark current PIN detector the most according to claim 1, it is characterised in that: the material of described substrate (101) is Si, GaAs, GaN, InP, Ge, SiC, SOI or GOI.
- Low-dark current PIN detector the most according to claim 1, it is characterized in that: offer on described anti-reflection film (102) at least one for by exposed for described p-type ohmic contact layer (103) electrode through hole out, described p-type Ohm contact electrode (106) touches with described p-type ohmic contact layer (103) by described electrode through hole.
- Low-dark current PIN detector the most according to claim 1, it is characterised in that: described p-type Ohm contact electrode (106) is arranged at the both side ends position of described p-type ohmic contact layer (103) upper surface.
- Low-dark current PIN detector the most according to claim 4, it is characterised in that: described low-dark current PIN detector includes one for photosensitive active area, within described active area is positioned at described p-type Ohm contact electrode (106).
- Low-dark current PIN detector the most according to claim 1, it is characterised in that: the plane at described isolated groove (104) place, lower surface is less than the plane at described p-type ohmic contact layer (103) place, lower surface.
- Low-dark current PIN detector the most according to claim 1, it is characterised in that: the material of described anti-reflection film (102) is SiNxOr SiO2, the thickness of described anti-reflection film (102) is 60 ~ 160nm.
- Low-dark current PIN detector the most according to claim 1, it is characterised in that: the material of described barrier material is SiO2, the material of described barrier layer (108) is SiO2, the thickness of described barrier layer (108) is 400 ~ 600nm.
- 9. the processing method being used for preparation low-dark current PIN detector as described in claim 1 ~ 8, it is characterised in that comprise the steps:Step 1, need the material of resistivity 2000 Ω/more than cm substrate (101) is selected according to processing, and described substrate (101) is carried out Chemical cleaning, ensure that the cleanliness factor of described substrate (101), in order to avoid affecting late stage process, deposits the SiO of one layer of 400 ~ 600nm in the upper surface of described substrate (101)2, the upper surface at described substrate (101) carries out photoetching subsequently, etches a circle isolated groove (104) in patterned area afterwards, and etching depth is 2 ~ 6 μm；Step 2, upper surface to described substrate (101) carry out thermal oxidation, make the upper surface of described substrate (101) form the fine and close SiO of one layer of 20nm2Layer, subsequently at the SiO of one layer of 2 ~ 6 μm of the upper surface of described substrate (101) deposit2, to ensure that described isolated groove (104) is completely filled, afterwards the upper surface of described substrate (101) is chemically-mechanicapolish polished, removes unnecessary oxide；Step 3, the upper surface of described substrate (101) deposit one layer of 400 ~ 600nm SiO2, the upper surface at described substrate (101) carries out photoetching subsequently, and to described patterned area ion implanting B, makes the upper surface of described substrate (101) form p-type ohmic contact layer (103), and ensure that its doping content is 1 × 1019 ~1×1020 cm-3；Step 4, described substrate (101) being carried out the high temperature anneal, activate with the foreign ion that will inject, annealing temperature is 900 ~ 1100 DEG C, and annealing time is 30 ~ 60min；Step 5, the upper surface of described substrate (101) deposit one layer of 60 ~ 160nm SiN or SiO2As anti-reflection film (102)；Step 6, carry out photoetching in the upper surface of described substrate (101) and etch electrode through hole on described anti-reflection film (102), the Al of 500nm ~ 2 μm is deposited subsequently to form p-type Ohm contact electrode (106) above described electrode through hole, and carry out photoetching, corrosion electrode, exposes for photosensitive active area；Step 7, by described substrate (101) back-off, make the lower surface of described substrate (101) upwards, and to its lower surface ion implanting P, form N-shaped ohmic contact layer (105), and ensure that its doping content is 1 × 1019 ~1×1020 cm-3, subsequently described substrate (101) is carried out process annealing process；Step 8, on described N-shaped ohmic contact layer (105), deposit the Al of one layer of 300nm ~ 2 μm again, form N-shaped Ohm contact electrode (107), and then complete device fabrication.
- The processing method of low-dark current PIN detector the most according to claim 9, it is characterised in that: described deposit processing method includes magnetron sputtering or PECVD growth；Described lithography method includes dry etch process or wet corrosion technique.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106449734A (en) * | 2016-12-20 | 2017-02-22 | 西安电子科技大学 | SPiN diode with GaAs-Ge-GaAs heterostructure and preparation method of SPiN diode |
| CN109841701A (en) * | 2017-11-24 | 2019-06-04 | 宁波比亚迪半导体有限公司 | Photodiode and its manufacturing process |
| CN111767795A (en) * | 2019-11-07 | 2020-10-13 | 友达光电股份有限公司 | Display device |
| CN111933739A (en) * | 2020-07-10 | 2020-11-13 | 中国电子科技集团公司第十三研究所 | Back incidence silicon photoelectric detector based on one-dimensional grating and preparation method |
| CN113644165A (en) * | 2021-08-11 | 2021-11-12 | 全磊光电股份有限公司 | Low-dark-current high-sensitivity photoelectric detector structure and manufacturing method thereof |
| CN116913938A (en) * | 2023-09-06 | 2023-10-20 | 北京邮电大学 | Low-noise high-density integrated photoelectric detection array chip and preparation method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1556546A (en) * | 2003-12-31 | 2004-12-22 | 天津大学 | Silicon photoelectric probe compatible with deep submicron radio frequency technology |
| CN103646985A (en) * | 2013-12-26 | 2014-03-19 | 中国电子科技集团公司第四十四研究所 | PIN photoelectric detector with responsivity space variable and manufacturing method thereof |
| CN103887362A (en) * | 2014-03-28 | 2014-06-25 | 重庆邮电大学 | NP-type CMOS avalanche photodiode with deep N-trap |
| CN104900752A (en) * | 2015-04-14 | 2015-09-09 | 中国电子科技集团公司第四十四研究所 | Black silicon layer preparation method and black silicon PIN photoelectric detector preparation method |
| CN205944122U (en) * | 2016-07-18 | 2017-02-08 | 苏州北鹏光电科技有限公司 | Low dark current PIN detector |
-
2016
- 2016-07-18 CN CN201610562077.7A patent/CN105977338B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1556546A (en) * | 2003-12-31 | 2004-12-22 | 天津大学 | Silicon photoelectric probe compatible with deep submicron radio frequency technology |
| CN103646985A (en) * | 2013-12-26 | 2014-03-19 | 中国电子科技集团公司第四十四研究所 | PIN photoelectric detector with responsivity space variable and manufacturing method thereof |
| CN103887362A (en) * | 2014-03-28 | 2014-06-25 | 重庆邮电大学 | NP-type CMOS avalanche photodiode with deep N-trap |
| CN104900752A (en) * | 2015-04-14 | 2015-09-09 | 中国电子科技集团公司第四十四研究所 | Black silicon layer preparation method and black silicon PIN photoelectric detector preparation method |
| CN205944122U (en) * | 2016-07-18 | 2017-02-08 | 苏州北鹏光电科技有限公司 | Low dark current PIN detector |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106449734A (en) * | 2016-12-20 | 2017-02-22 | 西安电子科技大学 | SPiN diode with GaAs-Ge-GaAs heterostructure and preparation method of SPiN diode |
| CN109841701A (en) * | 2017-11-24 | 2019-06-04 | 宁波比亚迪半导体有限公司 | Photodiode and its manufacturing process |
| CN109841701B (en) * | 2017-11-24 | 2021-09-10 | 比亚迪半导体股份有限公司 | Photodiode and manufacturing process thereof |
| CN111767795A (en) * | 2019-11-07 | 2020-10-13 | 友达光电股份有限公司 | Display device |
| CN111767795B (en) * | 2019-11-07 | 2023-11-17 | 友达光电股份有限公司 | display device |
| CN111933739A (en) * | 2020-07-10 | 2020-11-13 | 中国电子科技集团公司第十三研究所 | Back incidence silicon photoelectric detector based on one-dimensional grating and preparation method |
| CN113644165A (en) * | 2021-08-11 | 2021-11-12 | 全磊光电股份有限公司 | Low-dark-current high-sensitivity photoelectric detector structure and manufacturing method thereof |
| CN113644165B (en) * | 2021-08-11 | 2023-12-08 | 全磊光电股份有限公司 | Low dark current high sensitivity photoelectric detector structure and manufacturing method thereof |
| CN116913938A (en) * | 2023-09-06 | 2023-10-20 | 北京邮电大学 | Low-noise high-density integrated photoelectric detection array chip and preparation method thereof |
| CN116913938B (en) * | 2023-09-06 | 2023-11-21 | 北京邮电大学 | Low-noise high-density integrated photoelectric detection array chip and preparation method thereof |
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