CN205863193U - Low-dark current high speed PIN detector - Google Patents
Low-dark current high speed PIN detector Download PDFInfo
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- CN205863193U CN205863193U CN201620751818.1U CN201620751818U CN205863193U CN 205863193 U CN205863193 U CN 205863193U CN 201620751818 U CN201620751818 U CN 201620751818U CN 205863193 U CN205863193 U CN 205863193U
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- isolated groove
- contact layer
- ohmic contact
- dark current
- groove
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Abstract
nullThis utility model discloses a kind of low-dark current high speed PIN detector,Including substrate,Described Grown has p-type ohmic contact layer,It is coated with anti-reflection film on described p-type ohmic contact layer,At least one p-type Ohm contact electrode it is provided with on described anti-reflection film,Region in addition to p-type ohmic contact layer, the described substrate upper surface is all covered with barrier layer,It is coated with anti-reflection film on described barrier layer,Described substrate lower surface covers growth the most successively N-type ohmic contact layer and N-type Ohm contact electrode,Described substrate upper surface offers the first isolated groove,Described substrate lower surface offers the second isolated groove,Barrier material all it is filled with in described first isolated groove and the second isolated groove,Described first isolated groove is positioned at the outer circumferential side of described p-type ohmic contact layer,Described first isolated groove is the most corresponding with the second isolated groove.This utility model can effectively reduce the dark current of device inside, excellent effect, has the highest use and promotional value.
Description
Technical field
This utility model relates to a kind of photodetector, is specifically related to low-dark current high speed PIN detector, belongs to quasiconductor
Field of photoelectric devices.
Background technology
PIN detector, as realizing important " carrier " of optical signal detection, has that technique is simple, detection efficient is high, performance
The advantage such as stable, plays weight in the applications such as remotely monitored sensing, industry, military and national defense, medical treatment, Aero-Space, survey of deep space
Want supporting role, be the commanding elevation seized of every country.Such as in the high energy radial imaging such as safety check, medical treatment, PIN photodetection
Device coordinates with scintillator, it is achieved low light signals is converted to the signal of telecommunication and exports the process of imaging.
The dark current of PIN detector, can be divided into according to the relation of device size: the line dark current relevant with girth and
The face dark current relevant to area, and the dark current compensation unrelated with size.Line dark current is mainly determined by sidewall leakage stream,
Face dark current is then determined by factors such as the dissufion current of device inside, thermally stimulated current, generation recombination currents.Along with integrated level
Raising, the size of photodetector is constantly reducing, and integrated level improves constantly, and reduces the power attenuation of system simultaneously and becomes
This.But experimental data shows, when the device gross area is less than 1 mm2Time, its line dark current is more than 25 times of face dark current.
Specifically, line dark current is mainly derived from the factors such as sidewall leakage, scribing process or side wall passivation be bad and all can
Improve the line dark current of device.Owing to PIN detector is generally operational under low bias even zero-bias, therefore by its internal electric field
The online dark current of sidewall leakage caused accounts for major part.Again because the structure of PIN detector is relatively deep, the most traditional ion
Injection technology is difficult to be directly applied for the production and processing of PIN detector.
In sum, how to design a kind of novel PIN detector, from structure, reduce the dark current of device, simultaneously
Isolate the line dark current relevant to electric field as much as possible, just become the staff's problem demanding prompt solution in this area.
Summary of the invention
In view of prior art exists drawbacks described above, the purpose of this utility model is to propose low-dark current high speed PIN detector.
The purpose of this utility model, will be achieved by the following technical programs:
Low-dark current high speed PIN detector, can be used for the light in the range of infrared, visible ray, ultraviolet or terahertz wave band
Detection, including substrate, described Grown has p-type ohmic contact layer, and described p-type ohmic contact layer is coated with anti-reflection film,
At least one p-type Ohm contact electrode touched with described p-type ohmic contact layer it is provided with, on described substrate on described anti-reflection film
End face region in addition to described p-type ohmic contact layer is all covered with barrier layer, and described barrier layer is coated with anti-reflection film, described lining
The lower surface at the end covers growth the most successively N-type ohmic contact layer and N-type Ohm contact electrode, the upper end of described substrate
Face offers circle first isolated groove, and the lower surface of described substrate offers circle second isolated groove, described first isolation
All being filled with barrier material in groove and the second isolated groove, described first isolated groove is positioned at described p-type ohmic contact layer
Outer circumferential side, described first isolated groove is the most corresponding with the second isolated groove.
Preferably, the lower surface of described substrate offers a groove, the internal diameter of described groove and described first isolated groove
External diameter match, the degree of depth of described groove is 100 ~ 300 μm.
Preferably, described second isolated groove is opened in described groove, and the external diameter of described second isolated groove is with described
The internal diameter of groove matches.
Preferably, the material of described substrate is Si, GaAs, GaN, InP, Ge, SiC, SOI or GOI.
Preferably, described anti-reflection film offers at least one for by exposed for described p-type ohmic contact layer electricity out
Pole through hole, described p-type Ohm contact electrode touches with described p-type ohmic contact layer by described electrode through hole.
Preferably, described anti-reflection film being provided with p-type Ohm contact electrode, described p-type Ohm contact electrode is arranged at institute
State the both side ends position of p-type ohmic contact layer upper surface.
Preferably, described low-dark current high speed PIN detector includes that one is positioned at for photosensitive active area, described active area
Between described p-type Ohm contact electrode;Also include that one for transmitting the uptake zone of light source, described uptake zone is positioned at described p-type Europe
Between nurse contact layer and N-type ohmic contact layer.
Preferably, the degree of depth of described first isolated groove is more than the thickness of described p-type ohmic contact layer, described first isolation
Place, groove lower surface plane is less than place, described p-type ohmic contact layer lower surface plane.
Preferably, the degree of depth of described second isolated groove is more than the thickness of described N-type ohmic contact layer, described second isolation
The plane at place, groove upper surface is higher than the plane at the place, N-type ohmic contact layer upper surface in described groove.
Preferably, described first isolated groove is loop configuration with the second isolated groove and the two is the most corresponding, described
The degree of depth of the first isolated groove is 2 ~ 6 μm, and the degree of depth of described second isolated groove is 0.1-6 μm.
Preferably, the material of described anti-reflection film is SiNxOr SiO2, the thickness of described anti-reflection film is 60 ~ 160nm.
Preferably, the material of described barrier material is SiO2, the material of described barrier layer is SiO2, the thickness of described barrier layer
Degree is 400 ~ 600nm.
Prominent effect of the present utility model is: compared with tradition PIN detector, detection wave-length coverage of the present utility model is more
Extensively, it is widely portable to infrared, visible ray, ultraviolet or terahertz wave band, the suitability and practicality are higher.This utility model can
It is prevented effectively from conventional processes intermediate ion and injects the impurity defect and lattice damage introduced, reduce the dark current of device.With
Time, the groove structure of upper and lower two end faces of this utility model can be real fully by the isolation of device edge Yu device active region
Show the blocking-up of device edge and active area electric field, weakened the diffusion of few son, reduce the dark current of device.Additionally, this reality
By the way of back etched or corrosion, the thickness of device uptake zone is reduced with novel, reduced the series electrical of device
Resistance so that device can respond rapidly for incident optical signal, improves using effect of the present utility model further.
In sum, this utility model can effectively reduce the dark current of device inside, and using effect is excellent, has the highest
Use and promotional value.
Hereinafter accompanying drawing the most in conjunction with the embodiments, is described in further detail detailed description of the invention of the present utility model, so that this
Utility model technical scheme is more readily understood, grasps.
Accompanying drawing explanation
Fig. 1 is Electric Field Distribution schematic diagram under schematic cross-section of the present utility model and zero-bias;
Fig. 2 is the schematic diagram of step 1 in this utility model processing method;
Fig. 3 is the schematic diagram of step 2 in this utility model processing method;
Fig. 4 is the schematic diagram of step 3 in this utility model processing method;
Fig. 5 is the schematic diagram of step 5 in this utility model processing method;
Fig. 6 is the schematic diagram of step 6 in this utility model processing method;
Fig. 7 is the schematic diagram of step 7 in this utility model processing method;
Fig. 8 is the schematic diagram of step 8 in this utility model processing method;
Fig. 9 is the schematic diagram of step 9 in this utility model processing method;
Figure 10 is the schematic diagram of step 10 in this utility model processing method;
Wherein: 101, substrate, 102, anti-reflection film, 103, p-type ohmic contact layer, the 104, first isolated groove, 105, N-shaped Europe
Nurse contact layer, 106, p-type Ohm contact electrode, 107, N-shaped Ohm contact electrode, 108, barrier layer, the 109, second isolated groove.
Detailed description of the invention
This utility model discloses a kind of low-dark current high speed PIN detector.
As it can be seen, low-dark current high speed PIN detector, can be used for infrared, visible ray, ultraviolet or THz wave segment limit
Interior light detection, including substrate 101, on described substrate 101, growth has p-type ohmic contact layer 103, described p-type Ohmic contact
It is coated with anti-reflection film 102 on layer 103, described anti-reflection film 102 is provided with at least one and touches with described p-type ohmic contact layer 103
The p-type Ohm contact electrode 106 connect, region in addition to described p-type ohmic contact layer 103, described substrate 101 upper surface all covers
Having barrier layer 108, described barrier layer 108 is coated with anti-reflection film 102, the lower surface of described substrate 101 is covered the most successively
Lid growth has N-type ohmic contact layer 105 and N-type Ohm contact electrode 106, the upper surface of described substrate 101 to offer a circle
One isolated groove 104, the lower surface of described substrate 101 offers circle second isolated groove 109, described first isolated groove
104 and second are all filled with barrier material in isolated groove 109, and described first isolated groove 104 is positioned at described p-type Ohmic contact
The outer circumferential side of layer 103, described first isolated groove 104 is corresponding with the second isolated groove about 109.
The lower surface of described substrate 101 offers a groove, the internal diameter of described groove (the most described groove the widest
Degree) match with the external diameter of described first isolated groove 104 (the outer radial width of the most described first isolated groove 104), institute
The degree of depth stating groove is 100 ~ 300 μm.In the present embodiment, outside the internal diameter of described groove is with described first isolated groove 104
Footpath is equal, and the degree of depth of described groove is 200 μm.
Described second isolated groove 109 is opened in described groove, and the external diameter of described second isolated groove 109 is (i.e. described
The outer radial width of the second isolated groove 109) with the internal diameter of described groove (the radially inside width of the most described groove) mutually
Join.In the present embodiment, the external diameter of described second isolated groove 109 is equal with the internal diameter of described groove.
The material of described substrate 101 is Si, GaAs, GaN, InP, Ge, SiC, SOI(novel silicon base integrated circuit material) or
GOI(Novel Ge base integrated circuit material).In the present embodiment, described substrate 101 selects Si to make.
At least one is offered for by exposed for described p-type ohmic contact layer 103 electrode out on described anti-reflection film 102
Through hole, described p-type Ohm contact electrode 106 touches with described p-type ohmic contact layer 103 by described electrode through hole.
Described anti-reflection film 102 is different due to the existence effect of electrode, and be positioned on described p-type ohmic contact layer 103 is described
Anti-reflection film 102 can strengthen the absorbance of light, and the described anti-reflection film 102 being positioned on described barrier layer 108 can play well
Passivation effect.
Being provided with p-type Ohm contact electrode 106 on described anti-reflection film 102, described p-type Ohm contact electrode 106 is arranged at
The both side ends position of described p-type ohmic contact layer 103 upper surface.
Described low-dark current high speed PIN detector includes that one is positioned at described p-type for photosensitive active area, described active area
Between Ohm contact electrode 106;Also include that one for transmitting the uptake zone of light source, described uptake zone is positioned at described p-type ohm and connects
Between contact layer 103 and N-type ohmic contact layer 105.During use of the present utility model, probing light all can be from described active
District injects.
The degree of depth of described first isolated groove 104 is more than the thickness of described p-type ohmic contact layer 103, described first isolation
Place, groove 104 lower surface plane is less than place, described p-type ohmic contact layer 103 lower surface plane.
Specifically, such structure arranges and is because during use of the present utility model, and device upper surface produces
Zero-bias electric field at position, lower surface (the most described p-type ohmic contact layer 103 and the described lining of described p-type ohmic contact layer 103
The position, boundary at the end 101) there is a crest, make the degree of depth of described first isolated groove 104 exceed this position, boundary i.e.
May further ensure that the isolation of device upper surface outer ledge and device active region, use effect so that it is guaranteed that of the present utility model
Really.
The degree of depth of described second isolated groove 109 is more than the thickness of described N-type ohmic contact layer 105, described second isolation
The plane at place, groove 109 upper surface is higher than the plane at the place, N-type ohmic contact layer 105 upper surface in described groove.
Specifically, in the present embodiment, in the plane at described second isolated groove 109 notch place and described groove
The co-planar at place, N-type ohmic contact layer 105 lower surface.Such setting is because in use process of the present utility model
In, the zero-bias electric field that device lower surface produces is at position, upper surface (the most described N-type ohm of described N-type ohmic contact layer 105
Contact layer 105 and the position, boundary of described substrate 101) there is a crest, make the degree of depth of described second isolated groove 109 surpass
Cross this position, boundary, make the plane at described second isolated groove 109 notch place connect with the N-type ohm in described groove simultaneously
The co-planar at place, contact layer 105 lower surface can fully ensure that device lower end outside edge and device lower center position every
From, so that it is guaranteed that using effect of the present utility model.
Described first isolated groove 104 is loop configuration with the second isolated groove 109 and the two is the most corresponding, and described
The degree of depth of one isolated groove is 2 ~ 6 μm, and the degree of depth of described second isolated groove 109 is 0.1-6 μm.
It is further preferred that the degree of depth of described second isolated groove 109 is preferably 0.1-1 μm, specifically, described
The degree of depth of the first isolated groove can be 4 μm, and the degree of depth of described second isolated groove 109 can be 1 μm.Such setting be because of
For in the course of processing of the present utility model, the lower surface of described substrate 101 is without going past annealing, and its junction depth can be less than upper
Surface, the degree of depth of the most described second isolated groove 109 can be less than the degree of depth of described first isolated groove 104.Also need to herein
Illustrating, the thickness of described p-type ohmic contact layer 103 and N-shaped ohmic contact layer 105 needs according to described first isolated groove
104 are adjusted with the degree of depth of the second isolated groove 109, but need the degree of depth meeting described first isolated groove 104 more than institute
State the thickness of p-type ohmic contact layer 103, the degree of depth of described second isolated groove 109 is more than described N-shaped ohmic contact layer 105
Thickness.
Additionally, the most corresponding structure is arranged also for ensureing isolation effect of the present utility model, promote this further
The function of utility model.
The material of described anti-reflection film 102 is SiNxOr SiO2, the thickness of described anti-reflection film 102 is 60 ~ 160nm.
Specifically, the characteristic of material selected by described anti-reflection film 102 is different and the wavelength of targeted light source not
With, its thickness changes the most therewith, and in the present embodiment, described anti-reflection film 102 selects thickness during SiN material less than selecting SiO2
Time thickness.For more specifically, in the present embodiment, described anti-reflection film 102 can select SiN or 93nm of 70nm thickness
The SiO of thickness2, the specification that both is different is identical with material effect in use.In addition it is also necessary to explanation, described
Anti-reflection film 102 is possible not only to increase the surface printing opacity of device, it is also possible to play passivation interface, the effect of reduction tracking current.
The material of described barrier material is metal or SiO2, the material of described barrier layer 108 is metal or SiO2, described resistance
The thickness of interlayer 108 is 400 ~ 600nm.
In the present embodiment, the material of described barrier material is identical with the material of described barrier layer 108, and both is preferably
SiO2, the thickness of described barrier layer 108 is 500nm.
This utility model further discloses a kind of processing method for preparing above-mentioned low-dark current high speed PIN detector, bag
Include following steps:
Step 1, need the material of resistivity 2000 Ω/more than cm substrate 101 is selected according to processing, and to institute
State substrate 101 and carry out Chemical cleaning, it is ensured that the cleanliness factor of described substrate 101 is in order to avoid affecting late stage process, at described substrate 101
The SiO of one layer of 400 ~ 600nm of upper surface deposit2, thickness is 500nm in the present embodiment, subsequently in the upper end of described substrate 101
Face carries out photoetching, etches circle first isolated groove 104 in patterned area afterwards, and etching depth is 2 ~ 6 μm, at the present embodiment
Etching depth is 4 μm;
Step 2, upper surface to described substrate 101 carry out thermal oxidation, make the upper surface of described substrate 101 form one
The SiO that layer is fine and close2Layer, subsequently at the SiO of one layer of 2 ~ 6 μm of the upper surface of described substrate 101 deposit2, thickness is in the present embodiment
4 μm, that need guarantee is deposited SiO herein2Thickness identical with the etching depth in step 1, to ensure described first
Isolated groove 104 is completely filled, and chemically-mechanicapolish polishes the upper surface of described substrate 101 afterwards, removes unnecessary oxygen
Compound;
Step 3, the upper surface of described substrate 101 deposit one layer of 400 ~ 600nm SiO2, thickness is in the present embodiment
500nm, the upper surface at described substrate 101 carries out photoetching subsequently, and to described patterned area ion implanting B, makes described substrate
The upper surface of 101 forms p-type ohmic contact layer 103, and ensures that its doping content is 1 × 1019 ~1×1020 cm-3, in this reality
Execute doping content in example and be preferably 1 × 1019 cm-3;
Step 4, described substrate 101 being carried out the high temperature anneal, activate with the foreign ion that will inject, annealing temperature is
900 ~ 1100 DEG C, annealing time is 30 ~ 60min, and annealing temperature in the present embodiment is 1100 DEG C, and annealing time is 30min;
Step 5, the upper surface of described substrate 101 deposit one layer of 60 ~ 100nm SiN or SiO2As anti-reflection film 102,
One layer of 70nm SiN or 93nmSiO can be deposited in the present embodiment in the upper surface of described substrate 1012;
Step 6, carry out photoetching in the upper surface of described substrate 101 and on described anti-reflection film 102, etch two electrodes
Through hole, deposits the Al of 500nm ~ 2 μm subsequently above described electrode through hole to form p-type Ohm contact electrode 106, and carries out
Photoetching, corrosion electrode, expose for photosensitive active area, the method for sputtering can be used in the present embodiment to deposit the Al of 1.5 μm
To form p-type Ohm contact electrode 106;
Step 7, by described substrate 101 back-off, make the lower surface of described substrate 101 upwards, in the lower end of described substrate 101
Face carries out photoetching and etches the groove that degree of depth is 100 ~ 300 μm, and in the present embodiment, the degree of depth of described groove is
200nm;
Step 8, the lower surface of described substrate 101 deposit one layer of 400 ~ 600nm SiO2, thickness is in the present embodiment
500nm, carries out photoetching subsequently, and etches circle second isolated groove 109 in described groove described grooved area, etching
The degree of depth is 0.1-6 μm, is 0.5 μm at the present embodiment etching depth, and ensure described second isolated groove 109 with described first every
Corresponding from groove about 104;
Step 9, lower surface to described substrate 101 carry out thermal oxidation, make the lower surface of described substrate 101 form one
The SiO that layer is fine and close2Layer, subsequently at the SiO of one layer of 0.1-6 μm of the lower surface of described substrate 101 deposit2, thickness in the present embodiment
Being 4 μm, that need guarantee is deposited SiO herein2Thickness identical with the etching depth in step 8, to ensure described
Two isolated grooves 109 are completely filled, and chemically-mechanicapolish polish the lower surface of described substrate 101 afterwards, and it is unnecessary to remove
Oxide;
Step 10, described substrate 101 lower surface is carried out photoetching, after photoetching completes, ion implanting P in patterned area,
Form N-shaped ohmic contact layer 105, and ensure that its doping content is 1 × 1019 ~1×1020 cm-3, adulterate in the present embodiment dense
Degree is preferably 1 × 1020 cm-3, subsequently described substrate 101 is carried out process annealing process;
Step 11, on described N-shaped ohmic contact layer 105, deposit the Al of one layer of 500nm ~ 2 μm again, form N-shaped ohm and connect
Touched electrode 107, and then complete device fabrication, the AL of method deposit 500nm of sputtering can be used in the present embodiment to form N-shaped
Ohm contact electrode 107.
Described deposit processing method includes magnetron sputtering or PECVD growth (plasma enhanced chemical vapor deposition method);
Described lithography method includes dry etch process or wet corrosion technique.
Also, it should be noted the described isolated groove 104 in this utility model is filled, low pressure chemical gas both can be used
The method deposited mutually is formed, it is also possible to utilize various Oxide chemical vapor deposition apparatus to complete.It addition, in this utility model
Material selects and coating layer thickness is utility model people and proves the optimal case drawn through test of many times, as used other materials
Or coating layer thickness, the technical solution of the utility model may be directly resulted in and can not realize reducing the effect of device dark electric current.
This utility model can reduce the principle of dark current and be, it is to avoid the impurity defect that at groove, ion implanting introduces
(this is owing to, in conventional processes, implantation annealing is insufficient, and being easily caused the impurity after injection can not be by clearance-type
Impurity is converted to instead type impurity) and lattice damage, and then reduce device dark electric current.Additionally, device edge is due to scribing process
The defect caused or damage all can increase the dark current of device;Electric field region is diffused into, at the work of electric field additionally, due to few son
Being collected under with, this process also can produce dark current, and groove structure of the present utility model can be by device edge with active
Separate and leave, it is achieved that device edge and the blocking-up of active area electric field, weaken the diffusion of few son, thus reduce the dark of device
Electric current.
With tradition PIN detector compared with, detection wavelength of the present utility model is wider, be widely portable to infrared, can
See that light, ultraviolet or terahertz wave band, the suitability and practicality are higher.This utility model can be prevented effectively from conventional processes
The impurity defect of ion implanting introducing and lattice damage, reduce the dark current of device.Meanwhile, upper and lower two ends of this utility model
The groove structure in face can be fully by the isolation of device edge Yu device active region, it is achieved that device edge and active area electric field
Blocking-up, weaken the diffusion of few son, reduce the dark current of device.Additionally, this utility model is by back etched or corrosion
Mode the thickness of device uptake zone is reduced, reduce the series resistance of device so that device for incident illumination believe
Number can respond rapidly, improve using effect of the present utility model further.
In sum, this utility model can effectively reduce the dark current of device inside, and using effect is excellent, can reduce
Series resistance so that device responds rapidly for incident optical signal, has the highest use and promotional value.
This utility model still has numerous embodiments, all employing equivalents or equivalent transformation and all technology of being formed
Scheme, within all falling within protection domain of the present utility model.
Claims (12)
1. low-dark current high speed PIN detector, can be used for the light in the range of infrared, visible ray, ultraviolet or terahertz wave band and visits
Survey, it is characterised in that: including substrate (101), the upper growth of described substrate (101) has p-type ohmic contact layer (103), described p-type Europe
It is coated with anti-reflection film (102) on nurse contact layer (103), described anti-reflection film (102) is provided with at least one and described p-type ohm
The p-type Ohm contact electrode (106) that contact layer (103) touches, described p-type ohmic contact layer is removed in described substrate (101) upper surface
(103) region outward is all covered with barrier layer (108), and described barrier layer (108) is coated with anti-reflection film (102), described substrate
(101) lower surface covers growth the most successively N-type ohmic contact layer (105) and N-type Ohm contact electrode (106),
The upper surface of described substrate (101) offers a circle the first isolated groove (104), and the lower surface of described substrate (101) offers
One circle the second isolated groove (109), is all filled with obstruct in described first isolated groove (104) and the second isolated groove (109)
Material, described first isolated groove (104) is positioned at the outer circumferential side of described p-type ohmic contact layer (103), described first isolated groove
(104) the most corresponding with the second isolated groove (109).
Low-dark current PIN detector the most according to claim 1, it is characterised in that: the lower surface of described substrate (101) is opened
Being provided with a groove, the internal diameter of described groove matches with the external diameter of described first isolated groove (104), and the degree of depth of described groove is
100~300μm。
Low-dark current PIN detector the most according to claim 2, it is characterised in that: described second isolated groove (109) is opened
Being located in described groove, the described external diameter of the second isolated groove (109) matches with the internal diameter of described groove.
Low-dark current PIN detector the most according to claim 1, it is characterised in that: the material of described substrate (101) is
Si, GaAs, GaN, InP, Ge, SiC, SOI or GOI.
Low-dark current PIN detector the most according to claim 1, it is characterised in that: described anti-reflection film offers on (102)
At least one is for by exposed for described p-type ohmic contact layer (103) electrode through hole out, described p-type Ohm contact electrode
(106) touch with described p-type ohmic contact layer (103) by described electrode through hole.
Low-dark current PIN detector the most according to claim 1, it is characterised in that: described anti-reflection film is provided with on (102)
P-type Ohm contact electrode (106), described p-type Ohm contact electrode (106) is arranged at described p-type ohmic contact layer (103) upper end
The both side ends position in face.
Low-dark current PIN detector the most according to claim 6, it is characterised in that: described low-dark current high speed PIN detects
Device includes that one for photosensitive active area, described active area is positioned between described p-type Ohm contact electrode (106);Also include one
For transmitting the uptake zone of light source, described uptake zone is positioned at described p-type ohmic contact layer (103) and N-type ohmic contact layer (105)
Between.
Low-dark current PIN detector the most according to claim 1, it is characterised in that: described first isolated groove (104)
The degree of depth is more than the thickness of described p-type ohmic contact layer (103), and described first isolated groove (104) place, lower surface plane is less than
Described p-type ohmic contact layer (103) place, lower surface plane.
Low-dark current PIN detector the most according to claim 3, it is characterised in that: described second isolated groove (109)
The degree of depth is more than the thickness of described N-type ohmic contact layer (105), and the plane at described second isolated groove (109) place, upper surface is high
The plane at N-type ohmic contact layer (105) place, upper surface in described groove.
Low-dark current PIN detector the most according to claim 1, it is characterised in that: described first isolated groove (104)
It being loop configuration with the second isolated groove (109) and the two is the most corresponding, the degree of depth of described first isolated groove (104) is 2 ~
6 μm, the degree of depth of described second isolated groove (109) is 0. 1 ~ 6 μm.
11. low-dark current PIN detector according to claim 1, it is characterised in that: the material of described anti-reflection film (102)
For SiNxOr SiO2, the thickness of described anti-reflection film (102) is 60 ~ 160nm.
12. low-dark current PIN detector according to claim 1, it is characterised in that: the material of described barrier material is
SiO2, the material of described barrier layer (108) is SiO2, the thickness of described barrier layer (108) is 400 ~ 600nm.
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CN105977337A (en) * | 2016-07-18 | 2016-09-28 | 苏州北鹏光电科技有限公司 | Low-dark-current high-speed PIN detector and processing method thereof |
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CN105977337A (en) * | 2016-07-18 | 2016-09-28 | 苏州北鹏光电科技有限公司 | Low-dark-current high-speed PIN detector and processing method thereof |
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