CN106711236A - SiGe-based solid-state plasma PiN diode and preparation method thereof - Google Patents
SiGe-based solid-state plasma PiN diode and preparation method thereof Download PDFInfo
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- 229910000577 Silicon-germanium Inorganic materials 0.000 title claims abstract description 45
- 238000002360 preparation method Methods 0.000 title claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 65
- 238000002955 isolation Methods 0.000 claims abstract description 23
- 238000005530 etching Methods 0.000 claims abstract description 14
- 238000005516 engineering process Methods 0.000 claims abstract description 13
- 239000013078 crystal Substances 0.000 claims abstract description 7
- 239000010410 layer Substances 0.000 claims description 92
- 238000000034 method Methods 0.000 claims description 64
- 239000007787 solid Substances 0.000 claims description 64
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 53
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 37
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 37
- 239000011241 protective layer Substances 0.000 claims description 28
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 27
- 229920005591 polysilicon Polymers 0.000 claims description 27
- 238000001259 photo etching Methods 0.000 claims description 24
- 239000000377 silicon dioxide Substances 0.000 claims description 22
- 239000012535 impurity Substances 0.000 claims description 19
- 235000012239 silicon dioxide Nutrition 0.000 claims description 12
- 238000001039 wet etching Methods 0.000 claims description 11
- 239000003292 glue Substances 0.000 claims description 10
- 229920002120 photoresistant polymer Polymers 0.000 claims description 10
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 238000001459 lithography Methods 0.000 claims description 4
- 238000002161 passivation Methods 0.000 claims description 4
- 230000004913 activation Effects 0.000 claims description 3
- 238000000137 annealing Methods 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 1
- 229910052760 oxygen Inorganic materials 0.000 claims 1
- 239000001301 oxygen Substances 0.000 claims 1
- 238000005468 ion implantation Methods 0.000 abstract description 4
- 238000011049 filling Methods 0.000 abstract description 2
- 108090000699 N-Type Calcium Channels Proteins 0.000 abstract 4
- 102000004129 N-Type Calcium Channels Human genes 0.000 abstract 4
- 108010075750 P-Type Calcium Channels Proteins 0.000 abstract 4
- 210000002381 plasma Anatomy 0.000 description 64
- 150000002500 ions Chemical class 0.000 description 20
- 239000000463 material Substances 0.000 description 15
- 238000009826 distribution Methods 0.000 description 7
- 238000002347 injection Methods 0.000 description 7
- 239000007924 injection Substances 0.000 description 7
- 230000008901 benefit Effects 0.000 description 6
- 239000002184 metal Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 210000002421 cell wall Anatomy 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910052752 metalloid Inorganic materials 0.000 description 1
- 150000002738 metalloids Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000011514 reflex Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/868—PIN diodes
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Abstract
The invention relates to a SiGe-based solid-state plasma PiN diode and a preparation method thereof. The preparation method comprises the following steps: selecting a SiGeOI substrate of a certain crystal orientation, and setting an isolation area on the SiGeOI substrate; etching the substrate to form a P-type channel and an N-type channel, wherein the depth of the P-type channel and N-type channel is less than the thickness of the top-layer SiGe of the substrate; forming a first P-type active area and a first N-type active area in the P-type channel and N-type channel by ion implantation; filling the P-type channel and N-type channel, and forming a second P-type active area and a second N-type active area in the top-layer SiGe of the substrate by ion implantation; and forming a lead on the substrate to finish the preparation of a SiGe-based solid-state plasma PiN diode. In the embodiment of the invention, the high-performance SiGe-based solid-state plasma PiN diode suitable for forming a solid-state plasma antenna is prepared and provided by using the deep trench isolation technology and ion implantation technology.
Description
Technical field
The present invention relates to semiconductor device processing technology field, more particularly to a kind of SiGe bases solid state plasma PiN bis-
Pole pipe and preparation method thereof.
Background technology
At present, domestic and international application is body silicon materials in the material that the PiN diodes of plasma reconfigurable antenna are used, this
Material has that intrinsic region carrier mobility is relatively low, influence PiN diodes intrinsic region carrier concentration, and then influences it to consolidate
State plasma density；And the P areas of the structure and N areas are formed using injection technology mostly, the method requirement implantation dosage and
Energy is larger, high to equipment requirement, and incompatible with existing process；And diffusion technique is used, though junction depth is deeper, P areas simultaneously
Area with N areas is larger, and integrated level is low, and doping concentration is uneven, influence PiN diodes electric property, cause solid-state etc. from
Daughter concentration and the poor controllability of distribution.
Which kind of therefore, material and technique is selected to make a kind of solid state plasma PiN diodes to be applied to solid-state etc.
Ion antenna just becomes particularly important.
The content of the invention
Therefore, be to solve technological deficiency and deficiency that prior art is present, the present invention propose a kind of SiGe bases solid-state etc. from
Daughter PiN diodes and preparation method thereof.
Specifically, a kind of preparation method of SiGe bases solid state plasma PiN diodes that the embodiment of the present invention is proposed, institute
State solid state plasma PiN diodes includes step for making solid plasma antenna, the preparation method：
A () chooses the SiGeOI substrates of a certain crystal orientation, isolated area is set on SiGeOI substrates；
B the depth of () etching substrate formation p-type groove and the N-type groove, the p-type groove and the N-type groove is small
In the thickness of the top layer Si Ge of the substrate；
C () forms the first p-type active area and the first N-type in the p-type groove and the N-type groove using ion implanting
Active area；
D () fills the p-type groove and the N-type groove, and using ion implanting in the top layer Si Ge of the substrate
Form the second p-type active area and the second N-type active area；And
E () forms lead over the substrate, to complete the preparation of the SiGe bases solid state plasma PiN diodes.
On the basis of above-described embodiment, isolated area is set in the substrate, including：
(a1) the first protective layer is formed on the SiGe surfaces；
(a2) the first isolated area figure is formed on first protective layer using photoetching process；
(a3) the specified location etching described first using dry etch process in the first isolated area figure is protected
Layer and the substrate to form isolation channel, and the isolation channel thickness of the depth more than or equal to the top layer Si Ge of the substrate；
(a4) isolation channel is filled to form the isolated area of the solid state plasma PiN diodes.
On the basis of above-described embodiment, first protective layer includes the first silicon dioxide layer and the first silicon nitride layer；
Correspondingly, step (a2) includes：
(a21) in the SiGe Surface Creations silica forming the first silicon dioxide layer；
(a22) in the first silicon dioxide layer Surface Creation silicon nitride forming the first silicon nitride layer.
On the basis of above-described embodiment, step (b) includes：
(b1) the second protective layer is formed on the SiGe surfaces；
(b2) the second isolated area figure is formed on second protective layer using photoetching process；
(b3) the specified location etching described second using dry etch process in the second isolated area figure is protected
Layer and the substrate are forming the p-type groove and the N-type groove.
On the basis of above-described embodiment, second protective layer includes the second silicon dioxide layer and the second silicon nitride layer；
Correspondingly, step (b1) includes：
(b11) in the SiGe Surface Creations silica forming the second silicon dioxide layer；
(b12) in the second silicon dioxide layer Surface Creation silicon nitride forming the second silicon nitride layer.
On the basis of above-described embodiment, step (c) includes：
(c1) the p-type groove and the N-type groove are aoxidized so that the inwall shape of the p-type groove and the N-type groove
Into oxide layer；
(c2) oxide layer of the p-type groove and the N-type trench wall is etched to complete using wet-etching technology
State the planarizing of p-type groove and the N-type trench wall；
(c3) the p-type groove and the N-type groove are carried out ion implanting to form the first p-type active area and institute
The first N-type active area is stated, the first N-type active area is away from the N-type trenched side-wall and bottom depth along ion dispersal direction
Region less than 1 micron, the first p-type active area is away from the p-type trenched side-wall and bottom depth along ion dispersal direction
Region less than 1 micron.
On the basis of above-described embodiment, step (c3) includes：
(c31) p-type groove described in photoetching and the N-type groove；
(c32) p type impurity is injected separately into the p-type groove and the N-type groove using the method with glue ion implanting
With N-type impurity forming the first p-type active area and the first N-type active area；
(c33) photoresist is removed.
On the basis of above-described embodiment, step (d) includes：
(d1) the p-type groove and the N-type groove are filled using polysilicon；
(d2) after substrate described in planarizing process, polysilicon layer is formed over the substrate；
(d3) polysilicon layer described in photoetching, and using the method with glue ion implanting to the p-type groove and the N-type ditch
Groove position is injected separately into p type impurity and N-type impurity to form the second p-type active area and the second N-type active area and simultaneously shape
Into p-type contact zone and N-type contact zone；
(d4) photoresist is removed；
(d5) polysilicon layer beyond the p-type contact zone and the N-type contact zone is removed using wet etching.
On the basis of above-described embodiment, step (e) includes：
(e1) silica is generated over the substrate；
(e2) using the impurity in annealing process activation active area；
(e3) in the p-type contact zone and N-type contact zone lithography fair lead forming lead；
(e4) Passivation Treatment and photoetching PAD are forming the solid state plasma PiN diodes.
Additionally, a kind of SiGe bases solid state plasma PiN diodes that another embodiment of the present invention is proposed, solid for making
State plasma antenna, the SiGe bases solid state plasma PiN diodes are obtained using above-mentioned any means embodiment.
From the foregoing, it will be observed that the embodiment of the present invention is used by the P areas to SiGe base solid state plasma PiN diodes and N areas
The polysilicon damascene technique of the deep etching based on etching, the technique can provide abrupt junction pi and ni and tie, and can have
Effect ground improves pi knots, the junction depth of ni knots, strengthens the concentration of solid state plasma and the controllability of distribution.Also, due to SiGe
Material has carrier mobility high, therefore can form carrier concentration high so as to improve the performance of diode in I areas.Separately
Outward, in the preparation technology in the conventional P areas for making solid state plasma PiN diodes and N areas, formed using injection technology, this
Method requirement implantation dosage and energy are larger, high to equipment requirement and incompatible with existing process；And diffusion technique is used, though
Junction depth is deeper, but P areas are larger with the area in N areas simultaneously, and integrated level is low, and doping concentration is uneven, influence solid state plasma PiN
The electric property of diode, causes the poor controllability of solid plasma bulk concentration and distribution.
By the detailed description below with reference to accompanying drawing, other side of the invention and feature become obvious.But should know
Road, the accompanying drawing is only the purpose design explained, not as the restriction of the scope of the present invention, because it should refer to
Appended claims.It should also be noted that unless otherwise noted, it is not necessary to scale accompanying drawing, they only try hard to concept
Ground explanation structure described herein and flow.
Brief description of the drawings
Below in conjunction with accompanying drawing, specific embodiment of the invention is described in detail.
Fig. 1 is a kind of preparation method flow chart of SiGe bases solid state plasma PiN diodes of the embodiment of the present invention.
Fig. 2 a- Fig. 2 s show for a kind of preparation method of SiGe bases solid state plasma PiN diodes of the embodiment of the present invention
It is intended to.
Fig. 3 is the device architecture schematic diagram of the SiGe base solid state plasma PiN diodes of the embodiment of the present invention.
Specific embodiment
To enable the above objects, features and advantages of the present invention more obvious understandable, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
The present invention proposes a kind of SiGe base solid state plasmas suitable for forming solid state plasma reconfigurable antenna
The preparation method and device of PiN diodes.The SiGe base solid state plasma PiN diodes are based on the SiGe in dielectric substrate
Transverse direction pin diodes are formed,, when Dc bias is added, DC current can form free carrier (electronics and sky on its surface for it
Cave) composition solid state plasma, the plasma has metalloid characteristic, i.e., has reflex to electromagnetic wave, its reflection
The microwave transmission characteristic of characteristic and surface plasma, concentration and it is distributed closely related.
Horizontal solid state plasma PiN diode plasmas reconfigurable antenna can be by horizontal solid state plasma PiN
Diode is arranged in a combination by array, is turned on using the solid state plasma PiN diode selectings in external control array,
The array formed dynamic solid state plasma striped, possessed the function of antenna, have to specific electromagnetic wave and launch and receive work(
Can, and the antenna can change solid state plasma bar by the selectivity conducting of solid state plasma PiN diodes in array
Line shape and distribution, so as to realize the reconstruct of antenna, have important application prospect in terms of national defence communication with Radar Technology.
Hereinafter, the technological process of the SiGe base solid state plasma PiN diodes that will be prepared to the present invention is made further in detail
Thin description.In figure, for convenience of explanation, the thickness in layer and region is zoomed in or out, shown size does not represent actual chi
It is very little.
Embodiment one
Fig. 1 is referred to, Fig. 1 is a kind of making side of SiGe bases solid state plasma PiN diodes of the embodiment of the present invention
Method flow chart, the method is applied to the horizontal solid state plasma PiN diodes of preparation, and the horizontal solid state plasma PiN bis-
Pole pipe is mainly used in making solid plasma antenna.The method comprises the following steps：
A () chooses the SiGeOI substrates of a certain crystal orientation, isolated area is set on SiGeOI substrates；
B the depth of () etching substrate formation p-type groove and the N-type groove, the p-type groove and the N-type groove is small
In the thickness of the top layer Si Ge of the substrate；
C () forms the first p-type active area and the first N-type in the p-type groove and the N-type groove using ion implanting
Active area；
D () fills the p-type groove and the N-type groove, and using ion implanting in the top layer Si Ge of the substrate
Form the second p-type active area and the second N-type active area；And
E () forms lead over the substrate, to complete the preparation of the SiGe bases solid state plasma PiN diodes.
Wherein, it is for step (a), the reason for using SiGeOI substrates, for solid plasma antenna because it is needed
Good microwave property, and solid state plasma PiN diodes are wanted in order to meet this demand, it is necessary to possess good isolation spy
Property and carrier are the restriction ability of solid state plasma, and SiGeOI substrates due to it has can be with the convenient shape of isolation channel
Into pin area of isolation, silica (SiO2) also can be that solid state plasma is limited in top layer silicon by carrier, so excellent
Choosing uses SiGeOI as the substrate of solid state plasma PiN diodes.And the carrier mobility of sige material is than larger, therefore
Device performance can be improved.
In addition, for step (a), isolated area, including step are set on SiGeOI substrates：
(a1) the first protective layer is formed in the SiGe layer of SiGeOI substrate surfaces；
Specifically, the first protective layer includes the first silica (SiO2) layer and the first silicon nitride (SiN) layer；Then first protect
The formation of sheath includes：In SiGe Surface Creation silica (SiO2) forming the first silica (SiO2) layer；The one or two
Silica (SiO2) layer surface generates silicon nitride (SiN) forming the first silicon nitride (SiN) layer.This have the advantage that, profit
With silica (SiO2) loose nature, by the stress isolation of silicon nitride (SiN), prevent it from conducting into top layer Si Ge, protect
The stabilization of top layer Si Ge performances is demonstrate,proved；Based on silicon nitride (SiN) and high selectivities of the SiGe in dry etching, using silicon nitride
(SiN) film is sheltered as dry etching, it is easy to which technique is realized.It is, of course, understood that the number of plies of protective layer and protection
The material of layer is not limited herein, as long as protective layer can be formed.
(a2) the first isolated area figure is formed on the first protective layer using photoetching process.
(a3) specified location using dry etch process in the first isolated area figure etches the first protective layer and substrate
To form isolation channel, and isolation channel thickness of the depth more than or equal to the top layer Si Ge of substrate；Wherein, the depth of isolation channel is more than
Equal to the thickness of top layer Si Ge, it is ensured that silica (SiO in follow-up groove2) connection with the oxide layer of substrate, form complete
Be dielectrically separated from.
(a4) isolation channel is filled to form the isolated area of solid state plasma PiN diodes.Wherein, the material of isolation channel is filled
Material can be silica (SiO2)。
Furthermore, for step (b), specifically may include steps of：
(b1) the second protective layer is formed in substrate surface；
Specifically, the second protective layer includes the second silica (SiO2) layer and the second silicon nitride (SiN) layer；Then second protect
The formation of sheath includes：In substrate surface generation silica (SiO2) forming the second silica (SiO2) layer；The two or two
Silica (SiO2) layer surface generates silicon nitride (SiN) forming the second silicon nitride (SiN) layer.The benefit of do so is similar to
The effect of one protective layer, here is omitted.
(b2) the second isolated area figure is formed on the second protective layer using photoetching process；
(b3) specified location using dry etch process in the second isolated area figure etches the second protective layer and substrate
To form p-type groove and N-type groove.
Wherein, the depth of p-type groove and N-type groove is more than the second protective layer thickness and less than the second protective layer and substrate top
Layer SiGe thickness sums.Preferably, distance of the bottom of the p-type groove and N-type groove away from the top layer Si Ge bottoms of substrate is 0.5
Micron~30 microns, forms the deep trouth being generally acknowledged that, it is equal so can to form Impurity Distribution when p-type and N-type active area is formed
Even and high-dopant concentration P, N area and tied with precipitous Pi and Ni, be beneficial to raising i areas plasma density.
Furthermore, for step (c), specifically may include steps of：
(c1) oxidation p-type groove and N-type groove are so that the inwall of p-type groove and N-type groove forms oxide layer.
(c2) etch the oxide layer of p-type groove and N-type trench wall to complete p-type groove and N using wet-etching technology
The planarizing of type trench wall.
Specifically, planarizing process can use following steps：Oxidation p-type groove and N-type groove are so that p-type groove and N
The inwall of type groove forms oxide layer；Etch the oxide layer of p-type groove and N-type trench wall to complete using wet-etching technology
The planarizing of p-type groove and N-type trench wall.This have the advantage that：Can prevent the projection of trenched side-wall from forming electric field
Concentrated area, causes Pi and Ni junction breakdowns.
(c3) ion implanting is carried out to p-type groove and N-type groove to form the first p-type active area and the first N-type active area,
First N-type active area is the region less than 1 micron along ion dispersal direction away from N-type trenched side-wall and bottom depth, and the first p-type has
Source region is the region less than 1 micron along ion dispersal direction away from p-type trenched side-wall and bottom depth.
Specifically, ion implantation process can be：Photoetching p-type groove and N-type groove；Using the method with glue ion implanting
P type impurity and N-type impurity are injected separately into p-type groove and N-type groove to form the first p-type active area and the first N-type active area；
Removal photoresist.
Wherein, the purpose of the first active area of formation is：One layer of uniform heavily doped region is formed in the side wall of groove, should
Region is the heavily doped region in Pi and Ni knots, and the formation of the first active area has following several benefits, many to be inserted in groove
Crystal silicon illustrates as a example by electrode, first, avoid hetero-junctions between polysilicon and SiGe and tied with Pi and Ni and overlap, it is caused
The uncertainty of performance；Secondth, the diffusion velocity of impurity in polysilicon can be utilized than characteristic faster, further to P and N areas
Diffusion, further improves the doping concentration in P and N areas；3rd, this prevents during polysilicon process, polysilicon is given birth to
Cavity is formed between polysilicon that inequality long is caused and cell wall, the cavity can cause polysilicon bad with the contact of side wall,
Influence device performance.
Furthermore, for step (d), specifically may include steps of：
(d1) p-type groove and N-type groove are filled using polysilicon；
Wherein, the material of filling groove can also be metal, heavily doped polysilicon germanium or heavily doped silicon, be preferably herein many
Crystal silicon.
(d2) after planarizing process substrate, polysilicon layer is formed on substrate；
(d3) photoetching polysilicon layer, and using the method with glue ion implanting to p-type groove and N-type groove position point
Other implanting p-type impurity and N-type impurity with form the second p-type active area and the second N-type active area and formed simultaneously p-type contact zone and
N-type contact zone；
(d4) photoresist is removed；
(d5) polysilicon layer beyond p-type contact zone and N-type contact zone is removed using wet etching.
Furthermore, for step (e), specifically may include steps of：
(e1) silica is generated on substrate；
(e2) impurity in p-type active area and N-type active area is activated using annealing process；
(e3) in p-type contact zone and N-type contact zone lithography fair lead forming lead；
(e4) Passivation Treatment and photoetching PAD are forming solid state plasma PiN diodes.
The preparation method of the SiGe base solid state plasma PiN diodes that the present invention is provided possesses following advantage：
(1) sige material that PiN diodes are used, due to its high mobility and the characteristic of big carrier lifetime, can have
Effect improves the solid plasma bulk concentration of PiN diodes；
(2) the P areas of PiN diodes employ the polysilicon damascene technique of the deep etching based on etching, the technique with N areas
Abrupt junction pi and ni can be provided to tie, and pi knots, the junction depth of ni knots can be effectively improved, make the concentration of solid state plasma
With the good controllability of realization of distribution；
(3) PiN diodes employ a kind of Deep trench isolation technique based on etching, are effectively improved hitting for device
Wear voltage, it is suppressed that influence of the leakage current to device performance.
Embodiment two
Refer to a kind of SiGe bases solid state plasma PiN bis- that Fig. 2 a- Fig. 2 s, Fig. 2 a- Fig. 2 s are the embodiment of the present invention
The preparation method schematic diagram of pole pipe, on the basis of above-described embodiment one, to prepare channel length as 22nm (solid-state plasmas
Length of field be 100 microns) SiGe base solid state plasma PiN diodes as a example by be described in detail, comprise the following steps that：
Step 1, backing material preparation process：
(1a) as shown in Figure 2 a, chooses the SiGeOI substrate slices 101 of (100) crystal orientation, and doping type is p-type, doping concentration
It is 1014cm-3, the thickness of top layer Si Ge is 50 μm；
(1b) as shown in Figure 2 b, using chemical vapor deposition (Chemical vapor deposition, abbreviation CVD)
Method, deposits one layer of SiO of 40nm thickness on SiGe2Layer 201；
(1c) deposits one layer of 2 Si of μ m thick using the method for chemical vapor deposition on substrate3N4/ SiN layer
202；
Step 2, isolates preparation process：
(2a) as shown in Figure 2 c, isolated area, wet etching isolated area is formed by photoetching process on above-mentioned protective layer
One Si3N4/ SiN layer 202, forms isolated area figure；Using dry etching, form wide 5 μm in isolated area, depth be 50 μm it is deep every
From groove 301；
(2b) as shown in Figure 2 d, after photoetching isolated area, using the method for CVD, deposits SiO2401 by the deep isolation trench
Fill up；
(2c) as shown in Figure 2 e, using chemically mechanical polishing (Chemical Mechanical Polishing, referred to as
CMP) method, removes the Si of surface the3N4The SiO of/SiN layer 202 and the2Layer 201, makes substrate surface smooth；
Step 3, P, N area deep trouth preparation process：
(3a) as shown in figure 2f, using CVD method, consecutive deposition prolongs two layer materials on substrate, and ground floor is 300nm thick
2nd SiO of degree2Layer 601, the second layer is the 2nd Si of 500nm thickness3N4/ SiN layer 602；
(3b) as shown in Figure 2 g, photoetching P, N areas deep trouth, the Si of wet etching P, N areas the 2nd3N4The SiO of/SiN layer 602 and the 2nd2
Layer 601, forms P, N area figure；Using dry etching, form wide 4 μm in P, N area, deep 5 μm deep trouth 701, the length of P, N area groove
Degree determines according to the applicable cases in prepared antenna；
(3c) as shown in fig. 2h, at 850 DEG C, high-temperature process 10 minutes, oxidation trough inwall forms oxide layer 801, so that
P, N area groove inwall are smooth；
(3d) as shown in fig. 2i, the oxide layer 801 of P, N area groove inwall is removed using wet-etching technology.
Step 4, P, N contact zone preparation process：
(4a) as shown in figure 2j, photoetching P areas deep trouth carries out p using the method with glue ion implanting to P areas groove sidewall+Note
Enter, make to form thin p on the wall of side+Active area 1001, concentration reaches 0.5 × 1020cm-3, remove photoresist；
(4b) photoetching N areas deep trouth, n is carried out using the method with glue ion implanting to N areas groove sidewall+Injection, makes on the wall of side
Form thin n+Active area 1002, concentration reaches 0.5 × 1020cm-3, remove photoresist；
(4c) using the method for CVD, the depositing polysilicon 1101 in P, N area groove, and groove is filled up as shown in Fig. 2 k；
(4d) as illustrated in figure 21, using CMP, removes the Si of surface polysilicon 1101 and the 2nd3N4/ SiN layer 602, puts down surface
It is whole；
(4e) as shown in Fig. 2 m, using the method for CVD, in one layer of polysilicon 1301 of surface deposition, thickness is 200~
500nm；
(4f) as shown in Fig. 2 n, photoetching P areas active area carries out p using band glue ion injection method+Injection, makes P areas active
Area's doping concentration reaches 0.5 × 1020cm-3, photoresist is removed, form P contacts 1401；
(4g) photoetching N areas active area, n is carried out using band glue ion injection method+Injection, makes N areas active area doping concentration
It is 0.5 × 1020cm-3, photoresist is removed, form N contacts 1402；
(4h) as shown in figure 2o, using wet etching, etches away the polysilicon 1301 beyond P, N contact zone, forms P, N and connects
Touch area；
(4i) as illustrated in figure 2p, using the method for CVD, in surface deposition SiO21601, thickness is 800nm；
(4j) anneals 1 minute at 1000 DEG C, makes the impurity activation of ion implanting and advances impurity in polysilicon；
Step 5, constitutes PIN diode step：
(5a) as shown in figure 2q, the lithography fair lead 1701 in P, N contact zone；
(5b) as shown in Fig. 2 r, substrate surface splash-proofing sputtering metal forms metal silicide 1801, and etch in 750 DEG C of alloys
Fall the metal on surface；
(5c) substrate surface splash-proofing sputtering metal, photoetching lead；
(5d) deposits Si as shown in Fig. 2 s3N4/ SiN forms passivation layer 1901, and photoetching PAD forms PIN diode, as
Prepare solid plasma antenna material.
In the present embodiment, above-mentioned various technological parameters are for example, according to the conventional meanses of those skilled in the art
The conversion done is the protection domain of the application.
The PiN diodes for being applied to solid plasma reconfigurable antenna prepared by the present invention, first, the SiGe materials for being used
Material, due to its high mobility and the characteristic of big carrier lifetime, improves the solid plasma bulk concentration of PiN diodes；In addition,
The P areas of PiN diodes employ the polysilicon damascene technique of the deep etching based on etching with N areas, and the technique can provide prominent
Become knot pi and ni to tie, and pi knots, the junction depth of ni knots can be effectively improved, make the concentration of solid state plasma and distribution can
The enhancing of control property, is conducive to preparing high performance plasma antenna；Again, what prepared by the present invention is applied to solid plasma can weigh
The PiN diodes of structure antenna employ a kind of Deep trench isolation technique based on etching, are effectively improved puncturing for device
Voltage, it is suppressed that influence of the leakage current to device performance.
Embodiment three
Fig. 3 is refer to, Fig. 3 shows for the device architecture of the SiGe base solid state plasma PiN diodes of the embodiment of the present invention
It is intended to.Solid state plasma PiN diodes are made of above-mentioned preparation method as shown in Figure 1, specifically, the solid-state etc. from
Daughter PiN diodes prepare formation on SiGeOI substrates 301, and the P areas 305 of PiN diodes, N areas 306 and are laterally positioned in
I areas between the P areas 305 and the N areas 306 are respectively positioned in the top layer Si Ge302 of substrate.Wherein, the PiN diodes can be used
STI deep trench isolations, i.e. the P areas 305 and the outside of N areas 306 are each provided with an isolation channel 303, and the depth of the isolation channel 303 is big
In the thickness equal to top layer Si Ge.In addition, the P areas 305 and the N areas 306 include that one is thin can be corresponded to respectively along substrate direction
Layer p-type active area 307 and a thin layer N-type active area 304.
In sum, specific case used herein is to solid state plasma PiN diodes of the present invention and its preparation side
The principle and implementation method of method are set forth, the explanation of above example be only intended to help understand the method for the present invention and its
Core concept；Simultaneously for those of ordinary skill in the art, according to thought of the invention, in specific embodiment and application
Be will change in scope, in sum, this specification content should not be construed as limiting the invention, guarantor of the invention
Shield scope should be defined by appended claim.
Claims (10)
1. a kind of preparation method of SiGe bases solid state plasma PiN diodes, it is characterised in that described SiGe bases solid-state etc. from
Daughter PiN diodes are used to make solid plasma antenna, and the preparation method includes step：
A () chooses the SiGeOI substrates of a certain crystal orientation, isolated area is set on SiGeOI substrates；
B the depth of () etching substrate formation p-type groove and the N-type groove, the p-type groove and the N-type groove is less than institute
State the thickness of the top layer Si Ge of substrate；
C () forms the first p-type active area using ion implanting in the p-type groove and the N-type groove and the first N-type is active
Area；
D () fills the p-type groove and the N-type groove, and formed in the top layer Si Ge of the substrate using ion implanting
Second p-type active area and the second N-type active area；And
E () forms lead over the substrate, to complete the preparation of the SiGe bases solid state plasma PiN diodes.
2. preparation method as claimed in claim 1, it is characterised in that isolated area is set on SiGeOI substrates, including：
(a1) the first protective layer is formed on the SiGe surfaces；
(a2) the first isolated area figure is formed on first protective layer using photoetching process；
(a3) using dry etch process the specified location of the first isolated area figure etch first protective layer and
The substrate to form isolation channel, and the isolation channel thickness of the depth more than or equal to the top layer Si Ge of the substrate；
(a4) isolation channel is filled to form the isolated area of the solid state plasma PiN diodes.
3. preparation method as claimed in claim 2, it is characterised in that first protective layer include the first silicon dioxide layer and
First silicon nitride layer；Correspondingly, step (a1) includes：
(a11) in the SiGe Surface Creations silica forming the first silicon dioxide layer；
(a12) in the first silicon dioxide layer Surface Creation silicon nitride forming the first silicon nitride layer.
4. preparation method as claimed in claim 1, it is characterised in that step (b) includes：
(b1) the second protective layer is formed in the substrate surface；
(b2) the second isolated area figure is formed on second protective layer using photoetching process；
(b3) using dry etch process the specified location of the second isolated area figure etch second protective layer and
The substrate is forming the p-type groove and the N-type groove.
5. preparation method as claimed in claim 4, it is characterised in that second protective layer include the second silicon dioxide layer and
Second silicon nitride layer；Correspondingly, step (b1) includes：
(b11) in the SiGe Surface Creations silica forming the second silicon dioxide layer；
(b12) in the second silicon dioxide layer Surface Creation silicon nitride forming the second silicon nitride layer.
6. preparation method as claimed in claim 1, it is characterised in that step (c) includes：
(c1) the p-type groove and the N-type groove are aoxidized so that the inwall of the p-type groove and the N-type groove forms oxygen
Change layer；
(c2) etch the oxide layer of the p-type groove and the N-type trench wall to complete the p-type using wet-etching technology
The planarizing of groove and the N-type trench wall；
(c3) carry out ion implanting to the p-type groove and the N-type groove to form the first p-type active area and described
One N-type active area, the first N-type active area is to be less than 1 away from the N-type trenched side-wall and bottom depth along ion dispersal direction
The region of micron, the first p-type active area is to be less than 1 away from the p-type trenched side-wall and bottom depth along ion dispersal direction
The region of micron.
7. preparation method as claimed in claim 6, it is characterised in that step (c3) includes：
(c31) p-type groove described in photoetching and the N-type groove；
(c32) p type impurity and N-type are injected separately into the p-type groove and the N-type groove using the method with glue ion implanting
Impurity is forming the first p-type active area and the first N-type active area；
(c33) photoresist is removed.
8. preparation method as claimed in claim 1, it is characterised in that step (d) includes：
(d1) the p-type groove and the N-type groove are filled using polysilicon；
(d2) after substrate described in planarizing process, polysilicon layer is formed over the substrate；
(d3) polysilicon layer described in photoetching, and using the method with glue ion implanting to the p-type groove and the N-type groove institute
P type impurity and N-type impurity are injected separately into position to form the second p-type active area and the second N-type active area and while form p-type
Contact zone and N-type contact zone；
(d4) photoresist is removed；
(d5) polysilicon layer beyond the p-type contact zone and the N-type contact zone is removed using wet etching.
9. preparation method as claimed in claim 1, it is characterised in that step (e) includes：
(e1) silica is generated over the substrate；
(e2) using the impurity in annealing process activation active area；
(e3) in the p-type contact zone and N-type contact zone lithography fair lead forming lead；
(e4) Passivation Treatment and photoetching PAD are forming the solid state plasma PiN diodes.
10. a kind of SiGe bases solid state plasma PiN diodes, it is characterised in that described for making solid plasma antenna
Solid state plasma PiN diodes are obtained using method as claimed in any one of claims 1-9 wherein.
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| CN102956993A (en) * | 2012-11-14 | 2013-03-06 | 华南理工大学 | S-PIN-diode-based directional diagram reconfigurable disk microstrip antenna |
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| CN102956993A (en) * | 2012-11-14 | 2013-03-06 | 华南理工大学 | S-PIN-diode-based directional diagram reconfigurable disk microstrip antenna |
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