CN106785335A - The preparation technology of the Ge base plasma pin diodes of frequency reconfigurable dipole antenna - Google Patents
The preparation technology of the Ge base plasma pin diodes of frequency reconfigurable dipole antenna Download PDFInfo
- Publication number
- CN106785335A CN106785335A CN201611184783.9A CN201611184783A CN106785335A CN 106785335 A CN106785335 A CN 106785335A CN 201611184783 A CN201611184783 A CN 201611184783A CN 106785335 A CN106785335 A CN 106785335A
- Authority
- CN
- China
- Prior art keywords
- type
- direct current
- current biasing
- biasing line
- pin diodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000002360 preparation method Methods 0.000 title claims abstract description 41
- 238000005516 engineering process Methods 0.000 title claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 56
- 238000005530 etching Methods 0.000 claims abstract description 10
- 238000004519 manufacturing process Methods 0.000 claims abstract description 3
- 210000002381 plasma Anatomy 0.000 claims description 60
- 238000000034 method Methods 0.000 claims description 51
- 239000010410 layer Substances 0.000 claims description 34
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 27
- 229920005591 polysilicon Polymers 0.000 claims description 27
- 230000008569 process Effects 0.000 claims description 24
- 238000001259 photo etching Methods 0.000 claims description 20
- 239000011241 protective layer Substances 0.000 claims description 19
- 229910052751 metal Inorganic materials 0.000 claims description 15
- 239000002184 metal Substances 0.000 claims description 15
- 239000012535 impurity Substances 0.000 claims description 12
- 238000002955 isolation Methods 0.000 claims description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 11
- 239000004065 semiconductor Substances 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 8
- 238000005229 chemical vapour deposition Methods 0.000 claims description 7
- 239000003292 glue Substances 0.000 claims description 7
- 229920002120 photoresistant polymer Polymers 0.000 claims description 7
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- 238000001039 wet etching Methods 0.000 claims description 7
- 238000002347 injection Methods 0.000 claims description 6
- 239000007924 injection Substances 0.000 claims description 6
- 238000001459 lithography Methods 0.000 claims description 4
- 238000002161 passivation Methods 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 239000004411 aluminium Substances 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 238000000137 annealing Methods 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 230000009191 jumping Effects 0.000 abstract description 2
- 150000002500 ions Chemical class 0.000 description 18
- 239000007787 solid Substances 0.000 description 8
- 230000008901 benefit Effects 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 229910052681 coesite Inorganic materials 0.000 description 3
- 238000004891 communication Methods 0.000 description 3
- 229910052906 cristobalite Inorganic materials 0.000 description 3
- 230000007812 deficiency Effects 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 229910052682 stishovite Inorganic materials 0.000 description 3
- 229910052905 tridymite Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000002708 enhancing effect Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 210000002421 cell wall Anatomy 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000036470 plasma concentration Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/12—Supports; Mounting means
- H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
- H01Q1/2283—Supports; Mounting means by structural association with other equipment or articles mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/868—PIN diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/36—Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/50—Structural association of antennas with earthing switches, lead-in devices or lightning protectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q5/00—Arrangements for simultaneous operation of antennas on two or more different wavebands, e.g. dual-band or multi-band arrangements
- H01Q5/30—Arrangements for providing operation on different wavebands
- H01Q5/307—Individual or coupled radiating elements, each element being fed in an unspecified way
- H01Q5/314—Individual or coupled radiating elements, each element being fed in an unspecified way using frequency dependent circuits or components, e.g. trap circuits or capacitors
- H01Q5/321—Individual or coupled radiating elements, each element being fed in an unspecified way using frequency dependent circuits or components, e.g. trap circuits or capacitors within a radiating element or between connected radiating elements
Abstract
The present invention provides a kind of preparation technology of the Ge base plasma pin diodes of frequency reconfigurable dipole antenna, and the Ge bases plasma pin diodes are used to manufacture the frequency reconfigurable antenna, and the preparation method of the Ge base plasma pin diodes includes step：GeOI substrates are chosen, isolated area is formed in GeOI substrates；Etching GeOI substrates form p-type groove and N-type groove；P-type active area and N-type active area are formed using ion implanting in p-type groove and N-type groove；Lead is formed on GeOI substrates, the preparation of Ge base plasma pin diodes is completed.The present invention provide reconfigurable antenna have lightweight, simple structure, low cost, frequency can rapid jumping the characteristics of.
Description
Technical field
The present invention relates to antenna technical field, more particularly to a kind of Ge bases for frequency reconfigurable dipole antenna etc. from
The preparation method of sub- pin diodes.
Background technology
In recent decades, wireless communication technology is developed rapidly, and importance in social life is growing day by day, as people
An indispensable part in daily life.Antenna as wireless communication field building block, for radiating and receiving
Radio wave.High frequency electric or guided wave are changed into the electromagnetic wave of free space in transmitting procedure, are radiated to surrounding space.
During reception, opposite conversion is carried out.
To realize that the required antenna amounts such as the demand of communication, navigation, guidance, warning, weapon, aircraft, naval vessel, satellite are got over
Come more so that the load weight on platform is continuously increased, and expense needed for building antenna constantly rises, meanwhile, each antenna
Between electromagnetic interference it is also very big, have a strong impact on system worked well.In order to mitigate the antenna weights of platform loads, reduce into
Originally, reduce the radar scattering interface of platform, realize the characteristics such as good electromagnetic compatibility, using reconfigurable antenna technology, realize using
One antenna realizes the function of multiple antennas.
Although but the frequency reconfigurable dipole antenna for using at present can realize the restructural of frequency antenna sections
There is mutual coupling, frequency hopping is slow, and feed structure is complicated, and Stealth Fighter is not good, and section is high, and the difficulty of integrated processing is high.
The content of the invention
Therefore, to solve technological deficiency and deficiency that prior art is present, the present invention proposes a kind of frequency reconfigurable dipole
The preparation method of the Ge base plasma pin diodes of sub-antenna.
Specifically, the system of the Ge base plasma pin diodes of a kind of frequency reconfigurable dipole antenna proposed by the present invention
Standby technique, the Ge base plasma pin diodes are used to manufacture frequency reconfigurable antenna, the system of the Ge base plasma pin diodes
Preparation Method includes step：
GeOI substrates are chosen, isolated area is formed in the GeOI substrates；
Etch the GeOI substrates and form p-type groove and N-type groove；
P-type active area and N-type active area are formed using ion implanting in the p-type groove and the N-type groove；
Lead is formed on the GeOI substrates, the preparation of the Ge bases plasma pin diodes is completed；
The frequency reconfigurable antenna includes：Ge base GeOI semiconductor chips (1)；It is fixed on the Ge bases GeOI semiconductors
First antenna arm (2), the second antenna arm (3), coaxial feeder (4) on substrate (1), the first direct current biasing line (5), the second direct current
Offset line (6), the 3rd direct current biasing line (7), the 4th direct current biasing line (8), the 5th direct current biasing line (9), the 6th direct current biasing
Line (10), the 7th direct current biasing line (11), the 8th direct current biasing line (12)；The first antenna arm (2) and second antenna
Arm (3) is respectively arranged at the both sides of the coaxial feeder (4) and including multiple Ge bases plasma pin diode strings；Described first
Direct current biasing line (5), the second direct current biasing line (6), the 3rd direct current biasing line (7), the 4th direct current biasing line
(8), the 5th direct current biasing line (9), the 6th direct current biasing line (10), the 7th direct current biasing line (11) and described
8th direct current biasing line (12) is fixed on the Ge bases GeOI semiconductor chips (1) using the method for chemical vapor deposition, its
Material is for copper, aluminium or through any one in the polysilicon of overdoping.
A kind of preparation technology of the Ge base plasma pin diodes of the frequency reconfigurable dipole antenna provided in the present invention
In, isolated area is formed in GeOI substrates, including：
The first protective layer is formed in the GeOI substrate surfaces；
The first isolated area figure is formed on first protective layer using photoetching process；
Using dry etch process the specified location of the first isolated area figure etch first protective layer and
The GeOI substrates are forming isolation channel；
The isolation channel is filled to form the isolated area.
A kind of preparation technology of the Ge base plasma pin diodes of the frequency reconfigurable dipole antenna provided in the present invention
In, etching GeOI substrates form p-type groove and N-type groove, including：
The second protective layer is formed in the GeOI substrate surfaces；
The second isolated area figure is formed on second protective layer using photoetching process；
Using dry etch process the specified location of the second isolated area figure etch second protective layer and
The GeOI substrates are forming the p-type groove and the N-type groove.
A kind of preparation technology of the Ge base plasma pin diodes of the frequency reconfigurable dipole antenna provided in the present invention
In, p-type active area and N-type active area are formed using ion implanting in p-type groove and the N-type groove, including：
Carry out ion implanting to the p-type groove and the N-type groove has to form the first p-type active area and the first N-type
Source region, the first N-type active area is to be less than 1 micron away from the N-type trenched side-wall and bottom depth along ion dispersal direction
Region；The first p-type active area is to be less than 1 micron away from the p-type trenched side-wall and bottom depth along ion dispersal direction
Region；
The p-type groove and the N-type groove are filled using polysilicon；
After GeOI substrates described in planarizing process, polysilicon layer is formed on the GeOI substrates；
Polysilicon layer described in photoetching, and using the method with glue ion implanting to the p-type groove and the N-type groove institute
P type impurity and N-type impurity are injected separately into position to form the second p-type active area and the second N-type active area and while form p-type
Contact zone and N-type contact zone；
Removal photoresist；
The polysilicon layer beyond the p-type contact zone and the N-type contact zone is removed using wet etching.
A kind of preparation technology of the Ge base plasma pin diodes of the frequency reconfigurable dipole antenna provided in the present invention
In, lead is formed on GeOI substrates, including：
Silica is generated on the GeOI substrates；
The impurity in the p-type active area and the N-type active area is activated using annealing process；
In p-type contact zone and N-type contact zone lithography fair lead forming lead；
Passivation Treatment and photoetching PAD are forming the Ge bases plasma pin diodes.
A kind of preparation technology of the Ge base plasma pin diodes of the frequency reconfigurable dipole antenna provided in the present invention
In, the first antenna arm (2) including be sequentially connected in series Ge bases plasma pin diodes string (w1), etc. the 2nd Ge bases from
Sub- pin diodes string (w2) and the 3rd Ge bases plasma pin diodes string (w3).
A kind of preparation technology of the Ge base plasma pin diodes of the frequency reconfigurable dipole antenna provided in the present invention
In, second antenna arm (3) including be sequentially connected in series the 4th Ge bases plasma pin diodes string (w4), etc. the 5th Ge bases from
Sub- pin diodes string (w5) and the 6th Ge bases plasma pin diodes string (w6).
A kind of preparation technology of the Ge base plasma pin diodes of the frequency reconfigurable dipole antenna provided in the present invention
In, the internal core wire of the coaxial feeder (4) is welded in the sheet metal of the first antenna arm (2), the first antenna arm (2)
Sheet metal is connected with direct current biasing line (5)；The screen layer of the coaxial feeder (4) is welded in the gold of second antenna arm (3)
Category piece, the sheet metal of second antenna arm (3) is connected with the second direct current biasing line (6)；The first direct current biasing line (5),
Second direct current biasing line (6) is connected with the negative pole of DC offset voltage, to form public negative pole.
From the foregoing, it will be observed that a kind of poles of Ge base plasmas pin bis- for frequency reconfigurable dipole antenna that the present invention is provided
The preparation technology of pipe, the preparation technology P areas employ the polysilicon damascene technique of the GeOI deep etchings based on etching with N areas,
The technique can provide abrupt junction pi and ni and tie, and can effectively improve pi knots, the junction depth of ni knots, make solid state plasma
Concentration and distribution controllability enhancing.The Ge base plasmas for being applied to solid plasma reconfigurable antenna prepared by the present invention
Pin diodes employ a kind of GeOI Deep trench isolation techniques based on etching, are effectively improved the breakdown voltage of device,
Inhibit influence of the leakage current to device performance.Additionally, the frequency based on Ge base plasma pin diodes that the present invention is provided can
Reconstruct dipole antenna small volume, section are low, simple structure, easy to process；Using coaxial cable as feed, without complicated feed
Structure；Pin diodes need to be only turned on or off, you can realize frequency as the basic component units of antenna by controlling it
Restructural.
Brief description of the drawings
In order to more clearly illustrate the technical scheme of the present invention or prior art, embodiment or prior art will be retouched below
The accompanying drawing to be used needed for stating is briefly described.It should be evident that drawings in the following description are more of the invention
Embodiment, for those of ordinary skill in the art, on the premise of not paying creative work, can also be attached according to these
Figure obtains other accompanying drawings.Below in conjunction with accompanying drawing, specific embodiment of the invention is described in detail.
Fig. 1 is a kind of Ge base plasma pin diodes of frequency reconfigurable dipole antenna provided in an embodiment of the present invention
Preparation technology schematic flow sheet；
Fig. 2 is a kind of frequency reconfigurable dipole antenna configuration schematic diagram provided in an embodiment of the present invention；
Fig. 3 is a kind of Ge bases plasma pin diode structure schematic diagrames provided in an embodiment of the present invention；
Fig. 4 a- Fig. 4 s are the preparation method schematic diagram of another Ge bases plasma pin diodes of the embodiment of the present invention.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing of the invention, to this hair
Bright technical scheme carries out clear, complete description.Obviously, described embodiment is a part of embodiment of the invention, without
It is whole embodiments.Based on embodiments of the invention, those of ordinary skill in the art are not making creative work premise
Lower obtained every other embodiment, belongs to protection scope of the present invention.
Embodiment one
Fig. 1, Fig. 2 are referred to, Fig. 1 is Ge bases of a kind of frequency reconfigurable dipole antenna provided in an embodiment of the present invention etc.
The preparation technology schematic flow sheet of ion pin diodes, Fig. 2 is a kind of frequency reconfigurable dipole provided in an embodiment of the present invention
Antenna structure view.The preparation technology of the Ge base plasma pin diodes comprises the following steps：
GeOI substrates are chosen, isolated area is formed in the GeOI substrates；
Etch the GeOI substrates and form p-type groove and N-type groove；
P-type active area and N-type active area are formed using ion implanting in the p-type groove and the N-type groove；
Lead is formed on the GeOI substrates, the preparation of the Ge bases plasma pin diodes is completed；
The preparation technology of the Ge base plasma pin diodes mainly applies to frequency reconfigurable dipole antenna, the antenna
Including：Ge base GeOI semiconductor chips (1)；Be fixed on first antenna arm (2) on the Ge bases GeOI semiconductor chips (1),
Second antenna arm (3), coaxial feeder (4), the first direct current biasing line (5), the second direct current biasing line (6), the 3rd direct current biasing line
(7), the 4th direct current biasing line (8), the 5th direct current biasing line (9), the 6th direct current biasing line (10), the 7th direct current biasing line
(11), the 8th direct current biasing line (12)；The first antenna arm (2) and second antenna arm (3) are respectively arranged at described same
Both sides of feeder shaft (4) and including multiple Ge bases plasma pin diode strings；The first direct current biasing line (5), described second
Direct current biasing line (6), the 3rd direct current biasing line (7), the 4th direct current biasing line (8), the 5th direct current biasing line
(9), the 6th direct current biasing line (10), the 7th direct current biasing line (11) and the 8th direct current biasing line (12) use
The method of chemical vapor deposition is fixed on the Ge bases GeOI semiconductor chips (1), and its material is for copper, aluminium or through overdoping
Any one in polysilicon.
The reason for using GeOI substrates, is, for solid plasma antenna due to the good microwave property of its needs, and
Solid plasma pin diodes in order to meet this demand, it is necessary to possess good isolation characteristic and carrier i.e. solid-state etc. from
The restriction ability of daughter, and GeOI substrates can be conveniently formed pin area of isolation, silica because it has with isolation channel
(SiO2) also can be that solid state plasma is limited in top layer Ge by carrier, it is advantageous to using GeOI as solid-state etc. from
The substrate of sub- pin diodes.
Using this implementation provide frequency reconfigurable dipole antenna small volume, simple structure, it is easy to process, without complexity present
Source structure, frequency can rapid jumping, effectively overcome the deficiencies in the prior art.
Further, in the present embodiment, isolated area is formed in GeOI substrates, specially：
The first protective layer is formed in the GeOI substrate surfaces；
The first isolated area figure is formed on first protective layer using photoetching process；
Using dry etch process the specified location of the first isolated area figure etch first protective layer and
The GeOI substrates are forming isolation channel；
The isolation channel is filled to form the isolated area.
Further, in the present embodiment, etching GeOI substrates form p-type groove and N-type groove, specially：
The second protective layer is formed in the GeOI substrate surfaces；
The second isolated area figure is formed on second protective layer using photoetching process；
Using dry etch process the specified location of the second isolated area figure etch second protective layer and
The GeOI substrates are forming the p-type groove and the N-type groove.
Further, in the present embodiment, in p-type groove and N-type groove using ion implanting formed p-type active area and
N-type active area, specially：
Carry out ion implanting to the p-type groove and the N-type groove has to form the first p-type active area and the first N-type
Source region, the first N-type active area is to be less than 1 micron away from the N-type trenched side-wall and bottom depth along ion dispersal direction
Region；The first p-type active area is to be less than 1 micron away from the p-type trenched side-wall and bottom depth along ion dispersal direction
Region；
The p-type groove and the N-type groove are filled using polysilicon；
After GeOI substrates described in planarizing process, polysilicon layer is formed on the GeOI substrates；
Polysilicon layer described in photoetching, and using the method with glue ion implanting to the p-type groove and the N-type groove institute
P type impurity and N-type impurity are injected separately into position to form the second p-type active area and the second N-type active area and while form p-type
Contact zone and N-type contact zone；
Wherein, the purpose of the first active area of formation is：One layer of uniform heavily doped region is formed in the side wall of groove, should
Region is the heavily doped region in pi and ni knots, and the formation of the first active area has following several benefits, many to be inserted in groove
Crystal silicon illustrates as a example by electrode, first, avoid hetero-junctions between polysilicon and germanium and tied with pi and ni and overlap, caused property
The uncertainty of energy；Secondth, the diffusion velocity of impurity in the polysilicon characteristic faster than in germanium can be utilized, further to P and N areas
Diffusion, further improves the doping concentration in P and N areas；3rd, this prevents during polysilicon process, polysilicon is given birth to
Cavity is formed between polysilicon that inequality long is caused and cell wall, the cavity can cause polysilicon bad with the contact of side wall,
Influence device performance；
Removal photoresist；
The polysilicon layer beyond the p-type contact zone and the N-type contact zone is removed using wet etching.
Further, in the present embodiment, lead is formed on GeOI substrates, specially：
Silica is generated on the GeOI substrates；
The impurity in the p-type active area and the N-type active area is activated using annealing process；
In p-type contact zone and N-type contact zone lithography fair lead forming lead；
Passivation Treatment and photoetching PAD are forming the Ge bases plasma pin diodes.
Further, in another embodiment of the present invention, the first antenna arm (2) of the antenna is including what is be sequentially connected in series
First Ge bases plasma pin diodes string (w1), the 2nd Ge bases plasma pin diodes string (w2) and the 3rd Ge base plasmas
Pin diodes string (w3).
Further, in another embodiment of the present invention, second antenna arm (3) of the antenna is including what is be sequentially connected in series
4th Ge bases plasma pin diodes string (w4), the 5th Ge bases plasma pin diodes string (w5) and the 6th Ge base plasmas
Pin diodes string (w6).
Further, in another embodiment of the present invention, the internal core wire of coaxial feeder (4) is welded in described first day
The sheet metal of line arm (2), the sheet metal of the first antenna arm (2) is connected with direct current biasing line (5)；The coaxial feeder (4)
Screen layer be welded in the sheet metal of second antenna arm (3), the sheet metal of second antenna arm (3) is inclined with the second direct current
Line (6) is put to be connected；The first direct current biasing line (5), the second direct current biasing line (6) with the negative pole phase of DC offset voltage
Even, to form public negative pole.
Embodiment two
Refer to another Ge bases plasma pin diodes that Fig. 4 a- Fig. 4 s, Fig. 4 a- Fig. 4 s are the embodiment of the present invention
Preparation method schematic diagram.The present embodiment on the basis of above-described embodiment, for Ge bases plasma pin diodes of the invention
Preparation technology is described in detail.
Step 1, the preparation process of substrate：
(1a) as shown in fig. 4 a, chooses (100) crystal orientation, and doping type is p-type, and doping concentration is 1014cm-3GeOI lining
Egative film 101, the thickness of top layer Ge is 50 μm；
(1b) as shown in Figure 4 b, using chemical vapor deposition (Chemical vapor deposition, abbreviation CVD)
Method, deposits one layer of SiO of 40nm thickness on GeOI substrates2Layer 201；Using the method for chemical vapor deposition, in SiO2
One layer of 2 Si of μ m thick of layer deposit3N4/ SiN layer 202；
Step 2, isolates preparation process：
(2a) as illustrated in fig. 4 c, isolated area, wet etching isolated area is formed by photoetching process on above-mentioned protective layer
One Si3N4/ SiN layer 202, forms isolated area figure；Using dry etching, form wide 5 μm in isolated area, depth be 50 μm it is deep every
From groove 301；
(2b) as shown in figure 4d, using the method for CVD, deposits SiO2401 fill up the deep isolation trench；
(2c) as shown in fig 4e, using chemically mechanical polishing (Chemical Mechanical Polishing, referred to as
CMP) method, removes the Si of surface the3N4The SiO of/SiN layer 202 and the2Layer 201, makes GeOI substrate surfaces smooth.
Step 3, P, N area deep trouth preparation process：
(3a) as shown in fig. 4f, using CVD method, the consecutive deposition materials at two layers on substrate, ground floor is 300nm thickness
The 2nd SiO2Layer 601, the second layer is the 2nd Si of 600nm thickness3N4/ SiN layer 602；
(3b) as shown in figure 4g, photoetching P, N areas deep trouth, the Si of wet etching P, N areas the 2nd3N4The SiO of/SiN layer 602 and the 2nd2
Layer 601, forms P, N area figure；Using dry etching, form wide 4 μm in P, N area, deep 5 μm deep trouth 701, the length of P, N area groove
Degree determines according to the applicable cases in prepared antenna；
(3c) as shown in figure 4h, at 850 DEG C, high-temperature process 10 minutes, oxidation trough inwall forms oxide layer 801；
(3d) as shown in figure 4i, the oxide layer 801 of P, N area groove inwall is removed using wet-etching technology, so that P, N area groove
Inwall is smooth.This have the advantage that：Can prevent the projection of trenched side-wall from forming electric field concentrated area, cause pi and ni to tie
Puncture.
Step 4, P, N contact zone preparation process：
(4a) as shown in figure 4j, photoetching P areas deep trouth carries out P using the method with glue ion implanting to P areas groove sidewall+Note
Enter, make to form thin P on the wall of side+Active area 1001, concentration reaches 0.5 × 1020cm-3, remove photoresist；
(4b) photoetching N areas deep trouth, n is carried out using the method with glue ion implanting to N areas groove sidewall+Injection, makes on the wall of side
Form thin n+Active area 1002, concentration reaches 0.5 × 1020cm-3, remove photoresist；
(4c) as shown in fig. 4k, using the method for CVD, the depositing polysilicon 1101 in P, N area groove, and groove is filled up；
(4d), using CMP, removes the Si of surface polysilicon 1101 and the 2nd as shown in Fig. 4 l3N4/ SiN layer 602, puts down surface
It is whole；
(4e) as shown in Fig. 4 m, using the method for CVD, in one layer of polysilicon 1301 of surface deposition, thickness is 200~
500nm；
(4f) as shown in Fig. 4 n, photoetching P areas active area carries out P using band glue ion injection method+Injection, makes P areas active
Area's doping concentration reaches 0.5 × 1020cm-3, photoresist is removed, form P contacts 1401；
(4g) photoetching N areas active area, N is carried out using band glue ion injection method+Injection, makes N areas active area doping concentration
It is 0.5 × 1020cm-3, photoresist is removed, form N contacts 1402；
(4h), using wet etching, etches away the polysilicon 1301 beyond P, N contact zone as shown in Fig. 4 o, forms P, N and connects
Touch area；
(4i) as shown in Fig. 4 p, using the method for CVD, in surface deposition SiO21601, thickness is 800nm；
(4j) anneals 1 minute at 1000 DEG C, makes the impurity activation of ion implanting and advances impurity in polycrystalline germanium.
Step 5, constitutes pin diode steps：
(5a) as shown in Fig. 4 q, the lithography fair lead 1701 in P, N contact zone；
(5b) as shown in Fig. 4 r, substrate surface splash-proofing sputtering metal forms metal silicide 1801, and etch in 750 DEG C of alloys
Fall the metal on surface；
(5c) substrate surface splash-proofing sputtering metal, photoetching lead；
(5d) deposits Si as shown in Fig. 4 s3N4/ SiN forms passivation layer 1901, and photoetching PAD forms pin diodes, as
Prepare solid plasma antenna material.
In the present embodiment, above-mentioned various technological parameters are for example, according to the conventional meanses of those skilled in the art
The conversion done is the protection domain of the application.
The Ge base plasma pin diodes for being applied to frequency reconfigurable dipole antenna prepared by the present invention, first, are made
Ge materials, due to its high mobility and the characteristic of big carrier lifetime, the solid state plasma that improve pin diodes is dense
Degree；In addition, the P areas of Ge base plasma pin diodes employ the polysilicon damascene work of the deep etching based on etching with N areas
Skill, the technique can provide abrupt junction pi and ni and tie, and can effectively improve pi knots, the junction depth of ni knots, make solid-state etc. from
The concentration of daughter and the controllability enhancing of distribution, are conducive to preparing high performance plasma antenna；Secondly, Ge materials are due to it
The treatment of the characteristic of oxide GeO heat endurances difference, P areas and the deep groove side wall planarizing of N areas can be automatically performed in hot environment, letter
The preparation method of material is changed；Again, the Ge base pin diodes for being applied to solid plasma reconfigurable antenna that prepared by the present invention
A kind of Deep trench isolation technique based on etching is employed, the breakdown voltage of device is effectively improved, it is suppressed that leakage current
Influence to device performance.
A kind of frequency based on Ge base plasma pin diodes produced using technique provided in an embodiment of the present invention can
The advantage for reconstructing dipole antenna is low small volume, section, simple structure, easy to process, using coaxial cable as feed,
Without complicated feed structure, using pin diodes as the basic component units of antenna, need to be only turned on or off by controlling it,
The restructural of frequency is capable of achieving, all constituents are in semiconductor chip side, it is easy to plate-making processing.
In sum, specific case used herein is set forth to the principle of the invention and implementation method, above reality
The explanation for applying example is only intended to help and understands the method for the present invention and its core concept；Simultaneously for the general technology of this area
Personnel, according to thought of the invention, will change in specific embodiments and applications, in sum, this theory
Bright book content be should not be construed as limiting the invention, and protection scope of the present invention should be defined by appended claim.
Claims (8)
1. a kind of preparation technology of the Ge base plasma pin diodes of frequency reconfigurable antenna, it is characterised in that described Ge bases etc.
Ion pin diodes are used to manufacture the frequency reconfigurable antenna, and the preparation method of the Ge bases plasma pin diodes includes
Step：
GeOI substrates are chosen, isolated area is formed in the GeOI substrates；
Etch the GeOI substrates and form p-type groove and N-type groove；
P-type active area and N-type active area are formed using ion implanting in the p-type groove and the N-type groove；
Lead is formed on the GeOI substrates, the preparation of the Ge bases plasma pin diodes is completed；
The frequency reconfigurable antenna includes：Ge base GeOI semiconductor chips (1)；It is fixed on the Ge bases GeOI semiconductor chips
(1) first antenna arm (2), the second antenna arm (3), coaxial feeder (4) on, the first direct current biasing line (5), the second direct current biasing
Line (6), the 3rd direct current biasing line (7), the 4th direct current biasing line (8), the 5th direct current biasing line (9), the 6th direct current biasing line
(10), the 7th direct current biasing line (11), the 8th direct current biasing line (12)；The first antenna arm (2) and second antenna arm
(3) both sides of the coaxial feeder (4) are respectively arranged at and including multiple Ge bases plasma pin diode strings；Described first is straight
Stream offset line (5), the second direct current biasing line (6), the 3rd direct current biasing line (7), the 4th direct current biasing line
(8), the 5th direct current biasing line (9), the 6th direct current biasing line (10), the 7th direct current biasing line (11) and described
8th direct current biasing line (12) is fixed on the Ge bases GeOI semiconductor chips (1) using the method for chemical vapor deposition, its
Material is for copper, aluminium or through any one in the polysilicon of overdoping.
2. preparation technology as claimed in claim 1, it is characterised in that form isolated area in the GeOI substrates, including：
The first protective layer is formed in the GeOI substrate surfaces；
The first isolated area figure is formed on first protective layer using photoetching process；
Using dry etch process first protective layer and described is etched in the specified location of the first isolated area figure
GeOI substrates are forming isolation channel；
The isolation channel is filled to form the isolated area.
3. preparation technology as claimed in claim 1, it is characterised in that the etching GeOI substrates form p-type groove and N-type ditch
Groove, including：
The second protective layer is formed in the GeOI substrate surfaces；
The second isolated area figure is formed on second protective layer using photoetching process；
Using dry etch process second protective layer and described is etched in the specified location of the second isolated area figure
GeOI substrates are forming the p-type groove and the N-type groove.
4. preparation technology as claimed in claim 1, it is characterised in that used in the p-type groove and the N-type groove from
Son injection forms p-type active area and N-type active area, including：
Ion implanting is carried out to the p-type groove and the N-type groove to form the first p-type active area and the first N-type active area,
The first N-type active area is the region less than 1 micron along ion dispersal direction away from the N-type trenched side-wall and bottom depth；
The first p-type active area is the region less than 1 micron along ion dispersal direction away from the p-type trenched side-wall and bottom depth；
The p-type groove and the N-type groove are filled using polysilicon；
After GeOI substrates described in planarizing process, polysilicon layer is formed on the GeOI substrates；
Polysilicon layer described in photoetching, and it is in place to the p-type groove and N-type groove institute using the method with glue ion implanting
Put and be injected separately into p type impurity and N-type impurity to form the second p-type active area and the second N-type active area and form p-type contact simultaneously
Area and N-type contact zone；
Removal photoresist；
The polysilicon layer beyond the p-type contact zone and the N-type contact zone is removed using wet etching.
5. preparation technology as claimed in claim 1, it is characterised in that form lead on the GeOI substrates, including：
Silica is generated on the GeOI substrates；
The impurity in the p-type active area and the N-type active area is activated using annealing process；
In p-type contact zone and N-type contact zone lithography fair lead forming lead；
Passivation Treatment and photoetching PAD are forming the Ge bases plasma pin diodes.
6. preparation technology as claimed in claim 1, it is characterised in that the first antenna arm (2) including be sequentially connected in series
One Ge bases plasma pin diodes string (w1), the 2nd Ge bases plasma pin diodes string (w2) and the 3rd Ge base plasmas pin
Diode string (w3).
7. preparation technology as claimed in claim 1, it is characterised in that second antenna arm (3) including be sequentially connected in series
Four Ge bases plasma pin diodes string (w4), the 5th Ge bases plasma pin diodes string (w5) and the 6th Ge base plasmas pin
Diode string (w6).
8. preparation technology as claimed in claim 1, it is characterised in that the internal core wire of the coaxial feeder (4) is welded in described
The sheet metal of first antenna arm (2), the sheet metal of the first antenna arm (2) is connected with direct current biasing line (5)；The coaxial feed
The screen layer of line (4) is welded in the sheet metal of second antenna arm (3), the sheet metal and second of second antenna arm (3)
Direct current biasing line (6) is connected；The first direct current biasing line (5), the second direct current biasing line (6) are negative with DC offset voltage
Extremely it is connected, to form public negative pole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611184783.9A CN106785335A (en) | 2016-12-20 | 2016-12-20 | The preparation technology of the Ge base plasma pin diodes of frequency reconfigurable dipole antenna |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611184783.9A CN106785335A (en) | 2016-12-20 | 2016-12-20 | The preparation technology of the Ge base plasma pin diodes of frequency reconfigurable dipole antenna |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106785335A true CN106785335A (en) | 2017-05-31 |
Family
ID=58895951
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611184783.9A Pending CN106785335A (en) | 2016-12-20 | 2016-12-20 | The preparation technology of the Ge base plasma pin diodes of frequency reconfigurable dipole antenna |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106785335A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112993048A (en) * | 2021-02-07 | 2021-06-18 | 中国人民武装警察部队工程大学 | Preparation method and device of PiN diode array and silicon-based reconfigurable symmetrical dipole antenna |
| CN112993053A (en) * | 2021-02-07 | 2021-06-18 | 中国人民武装警察部队工程大学 | Preparation method and device of silicon-based transverse PiN diode and high-integration stealth antenna |
| CN112992676A (en) * | 2021-02-07 | 2021-06-18 | 中国人民武装警察部队工程大学 | Preparation method and device of high-injection-ratio heterogeneous PiN diode with AlAs-GeSn-AlAs structure |
| CN113013258A (en) * | 2021-02-07 | 2021-06-22 | 中国人民武装警察部队工程大学 | Preparation method of SiGe-GeSn-SiGe heterostructure high injection ratio PiN diode array and device thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050042806A1 (en) * | 2001-10-29 | 2005-02-24 | Kawasaki Microelectronics, Inc. | Silicon on insulator device and layout method of the same |
| CN101714591A (en) * | 2009-11-10 | 2010-05-26 | 大连理工大学 | Method for manufacturing silicon photoelectric diode |
| CN102842595A (en) * | 2011-06-20 | 2012-12-26 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
-
2016
- 2016-12-20 CN CN201611184783.9A patent/CN106785335A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050042806A1 (en) * | 2001-10-29 | 2005-02-24 | Kawasaki Microelectronics, Inc. | Silicon on insulator device and layout method of the same |
| CN101714591A (en) * | 2009-11-10 | 2010-05-26 | 大连理工大学 | Method for manufacturing silicon photoelectric diode |
| CN102842595A (en) * | 2011-06-20 | 2012-12-26 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
Non-Patent Citations (1)
| Title |
|---|
| ALY E. FATHY等: ""Silicon-Based Reconfigurable Antennas—Concepts, Analysis, Implementation, and Feasibility"", 《IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES》 * |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112993048A (en) * | 2021-02-07 | 2021-06-18 | 中国人民武装警察部队工程大学 | Preparation method and device of PiN diode array and silicon-based reconfigurable symmetrical dipole antenna |
| CN112993053A (en) * | 2021-02-07 | 2021-06-18 | 中国人民武装警察部队工程大学 | Preparation method and device of silicon-based transverse PiN diode and high-integration stealth antenna |
| CN112992676A (en) * | 2021-02-07 | 2021-06-18 | 中国人民武装警察部队工程大学 | Preparation method and device of high-injection-ratio heterogeneous PiN diode with AlAs-GeSn-AlAs structure |
| CN113013258A (en) * | 2021-02-07 | 2021-06-22 | 中国人民武装警察部队工程大学 | Preparation method of SiGe-GeSn-SiGe heterostructure high injection ratio PiN diode array and device thereof |
| CN112993048B (en) * | 2021-02-07 | 2023-12-01 | 中国人民武装警察部队工程大学 | PiN diode array preparation method, device and reconfigurable symmetrical dipole antenna |
| CN112993053B (en) * | 2021-02-07 | 2023-12-05 | 中国人民武装警察部队工程大学 | Preparation method of transverse Pin diode, device and high-integration stealth antenna |
| CN112992676B (en) * | 2021-02-07 | 2023-12-05 | 中国人民武装警察部队工程大学 | Preparation method of AlAs-GeSn-AlAs structure high injection ratio heterogeneous Pin diode and device thereof |
| CN113013258B (en) * | 2021-02-07 | 2023-12-05 | 中国人民武装警察部队工程大学 | Preparation method of SiGe-GeSn-SiGe heterostructure high injection ratio PiN diode array and device thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106785335A (en) | The preparation technology of the Ge base plasma pin diodes of frequency reconfigurable dipole antenna | |
| CN106847903A (en) | For the preparation method of the heterogeneous SPiN diodes of SiGe bases of restructural loop aerial | |
| CN106816684A (en) | For the Ge base plasma pin diode preparation methods of restructural multilayer holographic antenna | |
| CN106847904A (en) | For the preparation method of the GaAs/Ge/GaAs heterojunction structure SPiN diode strings of sleeve antenna | |
| CN106784019A (en) | A kind of Ge bases solid state plasma PiN diodes and preparation method thereof | |
| CN106601616B (en) | Heterogeneous Ge base pin diode string preparation method in restructural multilayer holographic antenna | |
| CN106876872A (en) | The preparation method of the Ge base restructural dipole antennas based on AlAs/Ge/AlAs structures | |
| WO2018113454A1 (en) | Preparation method for heterogeneous sige-based plasma pin diode string used for sleeve antenna | |
| CN106783591A (en) | Frequency reconfigurable holographic antenna preparation method based on Ge base heterojunction materials | |
| CN106847899A (en) | For the preparation method of the GaAs/Ge/GaAsSPiN diode strings of restructural dipole antenna | |
| CN106783559B (en) | Frequency reconfigurable sleeve-dipole antenna preparation method based on SPiN diode | |
| CN106783594A (en) | The preparation technology of the heterogeneous Ge base pins diode of restructural multilayer holographic antenna | |
| CN112993052B (en) | Heterogeneous GeSn-based solid-state plasma Pin diode with mesa structure and preparation method thereof | |
| CN106783597A (en) | For the preparation method of the AlAs/Ge/AlAs solid state plasma PiN diode strings of sleeve antenna | |
| CN112993046B (en) | Deep groove protection Pin diode of SiGe-GeSn-SiGe structure and preparation method thereof | |
| CN112992677B (en) | Preparation method of heterogeneous InP-GeSn-InP deep groove protection PiN diode array and device thereof | |
| CN106783595A (en) | A kind of preparation method of the heterogeneous SPiN diodes of the GaAs/Ge/GaAs for loop aerial | |
| CN112993044B (en) | Preparation method of CdTe-GeSn-CdTe heterogeneous transverse PiN diode and device thereof | |
| CN112993047B (en) | Heterogeneous GeSn-based deep groove protection Pin diode and preparation method thereof | |
| CN106783598A (en) | The preparation method of the SiGe base plasma pin diodes of frequency reconfigurable dipole antenna | |
| CN106785336A (en) | Possesses SiO2The preparation method of the frequency reconfigurable holographic antenna of protective layer | |
| CN106953155A (en) | A kind of preparation method of solid plasma restructural dipole antenna | |
| CN106876873A (en) | The preparation method of the GaAs base plasma pin diodes of frequency reconfigurable dipole antenna | |
| CN106783601A (en) | The preparation method and its device of a kind of heterogeneous Ge bases solid state plasma PiN diodes of Si Ge Si | |
| CN106898857A (en) | The preparation method of Ge fundamental frequency restructural sleeve-dipole antennas |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20170531 |
|
| RJ01 | Rejection of invention patent application after publication |