CN112993048B - PiN diode array preparation method, device and reconfigurable symmetrical dipole antenna - Google Patents
PiN diode array preparation method, device and reconfigurable symmetrical dipole antenna Download PDFInfo
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- 238000002955 isolation Methods 0.000 claims abstract description 47
- 238000005530 etching Methods 0.000 claims abstract description 23
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 20
- 239000000956 alloy Substances 0.000 claims abstract description 20
- 238000005468 ion implantation Methods 0.000 claims abstract description 14
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 54
- 230000008569 process Effects 0.000 claims description 41
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- 238000001259 photo etching Methods 0.000 claims description 30
- 235000012239 silicon dioxide Nutrition 0.000 claims description 27
- 239000000377 silicon dioxide Substances 0.000 claims description 27
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 22
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 22
- 239000012535 impurity Substances 0.000 claims description 20
- 238000005516 engineering process Methods 0.000 claims description 15
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- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/868—PIN diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/36—Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q23/00—Antennas with active circuits or circuit elements integrated within them or attached to them
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6661—High-frequency adaptations for passive devices
- H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
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Abstract
The application relates to a preparation method and a device of a Pin diode array and a reconfigurable symmetrical dipole antenna, wherein the preparation method comprises the following steps: selecting a GeOI substrate with a certain crystal orientation, and doping the GeOI substrate to form a top GeSn region; a deep groove isolation region is arranged in the GeSn region on the top layer of the substrate; etching the GeSn region to form a P-type groove and an N-type groove, wherein the depth of the P-type groove and the N-type groove is smaller than the thickness of the top GeSn region; ion implantation is adopted in the P-type groove and the N-type groove to form a P-type active region and an N-type active region; and forming a GeSn alloy lead on the substrate and connecting the diodes in series to finish the preparation of the GaP-GeSn-GaP heterogeneous Pin diode array. The PiN diode array is prepared by dynamically controlling the content of Sn components in the top layer Ge and GeSn alloy leads.
Description
Technical Field
The application relates to the technical field of semiconductor materials and device manufacturing, in particular to a preparation method of a Pin diode array, a device and a reconfigurable symmetrical dipole antenna.
Background
In order to achieve excellent electromagnetic compatibility and reduce the weight and complexity of the system, a technology of realizing the functions of multiple antennas by using a single antenna in a modern communication system and a reconfigurable antenna is generated and is valued by a large number of researchers. Reconfigurable antenna technology has been developed, which means that the antenna functions implemented in an antenna system can be flexibly changed according to actual needs, and that the functions of a plurality of antennas can be implemented in a single system instead of being fixed. The antenna system can realize the performance reconfiguration through the adjustment of a variable device in the system, so that the antenna system can adapt to different electromagnetic environments and application occasions. The silicon-based PiN diode is used as a basic radiation unit of the solid-state plasma reconfigurable antenna, so that the silicon-based high-integration reconfigurable antenna has the advantages of low power consumption, wide bandwidth, high integration and the like, and has wide application prospects in the aspects of radar communication, helicopters, carrier-based communication and the like.
Therefore, it becomes important to choose what materials and processes are used to fabricate a PiN diode array for reconfigurable symmetric dipole antennas.
Disclosure of Invention
In order to solve the technical defects and shortcomings in the prior art, the application provides a preparation method of a PiN diode array, a device and a reconfigurable symmetrical dipole antenna.
The technical scheme of the application is as follows:
the preparation method of the Pin diode array comprises the following steps:
(a) Selecting a GeOI substrate with a certain crystal orientation, and doping the GeOI substrate to form a top GeSn region;
(b) A deep groove isolation region is arranged in the GeSn region on the top layer of the substrate;
(c) Etching the GeSn region to form a P-type groove and an N-type groove, wherein the depth of the P-type groove and the N-type groove is smaller than the thickness of the top GeSn region;
(d) Ion implantation is adopted in the P-type groove and the N-type groove to form a P-type active region and an N-type active region;
(e) And forming a GeSn alloy lead on the substrate and connecting the diodes in series to finish the preparation of the GaP-GeSn-GaP heterogeneous PiN diode array in the reconfigurable symmetrical dipole antenna.
Preferably, doping in the GeOI substrate in step (a) forms a top GeSn region, comprising the steps of:
(a1) Photoetching the GeOI substrate;
(a2) Carrying out Sn component doping on the GeOI substrate to form a top GeSn region, and dynamically controlling the content of Sn components in the top Ge to realize the maximum injection ratio of carriers;
(a3) The photoresist is removed.
Preferably, in the step (b), a deep trench isolation region is disposed in the GeSn region on the top layer of the substrate, which includes the following steps:
(b1) Forming a first protective layer on the surface of the GeSn region, wherein the preparation of the first protective layer comprises the following steps:
(b11) Generating a silicon dioxide layer on the surface of the substrate;
(b12) Generating a silicon nitride layer on the surface of the silicon dioxide layer;
(b2) Forming an isolation region pattern on the first protective layer by using a photoetching process;
(b3) Etching the first protective layer and the substrate at the appointed position of the isolation region graph by utilizing a dry etching process to form an isolation groove, wherein the depth of the isolation groove is greater than or equal to the thickness of a top GeSn region of the substrate;
(b4) Filling the isolation groove to form the isolation region of the Pin diode;
(b5) The substrate is planarized.
Preferably, the step (c) of etching the GeSn region to form a P-type trench and an N-type trench includes the following steps:
(c1) Forming a second protective layer on the surface of the substrate, wherein the preparation method of the second protective layer is the same as that of the first protective layer;
(c2) Forming P-type grooves and N-type groove patterns on the second protective layer by utilizing a photoetching process;
(c3) And etching the second protective layer and the GeSn region at the appointed position of the groove by utilizing a dry etching process to form the P-type groove and the N-type groove.
Preferably, in the step (d), ion implantation is adopted in the P-type trench and the N-type trench to form a P-type active region and an N-type active region, which comprises the following steps:
(d1) Forming a first P type active region and a first N type active region in the P type groove and the N type groove;
(d2) And forming a second P type active region and a second N type active region in the P type groove and the N type groove.
Preferably, in step (d 1), a first P-type active region and a first N-type active region are formed in the P-type trench and the N-type trench, including the steps of:
(d11) Oxidizing the P-type groove and the N-type groove to form a silicon dioxide oxide layer on the inner walls of the P-type groove and the N-type groove;
(d12) Etching the oxide layers on the inner walls of the P-type groove and the N-type groove by utilizing a wet etching process to finish planarization of the inner walls of the P-type groove and the N-type groove;
(d13) Performing ion implantation on the P-type trench and the N-type trench to form the first P-type active region and the first N-type active region, wherein the first P-type active region is a region with a depth of less than 1 micrometer from the side wall and the bottom of the P-type trench along an ion diffusion direction, and the first N-type active region is a region with a depth of less than 1 micrometer from the side wall and the bottom of the N-type trench along the ion diffusion direction, and the step (d 13) comprises the following steps:
(d131) Photoetching the P-type groove and the N-type groove;
(d132) Injecting P-type impurities and N-type impurities into the P-type groove and the N-type groove respectively by adopting a method of injecting glued ions so as to form a first P-type active region and a first N-type active region;
(d133) The photoresist is removed.
Preferably, step (d 2) comprises the steps of:
(d21) Filling the P-type groove and the N-type groove with polycrystalline GaP;
(d22) After flattening the substrate, forming a polycrystalline GaP layer on the surface of the substrate;
(d23) Photoetching the polycrystalline GaP layer, and respectively injecting P-type impurities and N-type impurities into the positions of the P-type groove and the N-type groove by adopting a method of injecting glued ions so as to form a second P-type active region and a second N-type active region and simultaneously form a P-type contact region and an N-type contact region;
(d24) Removing the photoresist;
(d25) And removing the polycrystalline GaP layer outside the P type contact region and the N type contact region by wet etching.
Preferably, step (e) comprises the steps of:
(e1) Generating silicon dioxide on the substrate;
(e2) Activating impurities in the active region using an annealing process;
(e3) Photoetching a lead hole in the P-type contact area and the N-type contact area;
(e4) Forming a GeSn alloy lead wire in the lead wire hole by adopting the RPCVD technology;
(e5) Passivating and photoetching PAD;
(e6) The diodes are connected in series with each other to form a GaP-GeSn-GaP hetero-Pin diode array in the reconfigurable symmetrical dipole antenna.
A Pin diode array is manufactured by the method described above.
A reconfigurable symmetrical dipole antenna comprising a PiN diode array as described above.
Compared with the prior art, the application discloses a preparation method, a device and a reconfigurable symmetrical dipole antenna of a PiN diode array, wherein Sn components are doped in the top layer Ge of a GaP-GeSn-GaP heterogeneous PiN diode array, and GeSn alloy with a forbidden band width much narrower than that of GaP materials is obtained by dynamically controlling the content of the Sn components in the top layer Ge, so that the injection ratio of carriers from a source region to an intrinsic region is further improved, and the concentration and the distribution uniformity of solid plasmas in the diode are improved. In addition, the mobility of carriers in the intrinsic region can be further improved by introducing the GeSn material, so that the performance of the silicon-based solid-state plasma high-integration antenna is greatly improved. The electrodes in the traditional silicon-based antenna pin diode are prepared from metal, and the existence of the metal electrodes can greatly influence the radar scattering cross section of the antenna system, so that the stealth characteristic of the communication system is reduced. Meanwhile, the interaction between the plasma region and electromagnetic waves is greatly influenced by the existence of the large metal electrode, so that the influence of solid plasma on the radiation performance of the antenna is weakened, and the development of silicon-based solid plasma in the directions of miniaturization, integration and intellectualization is limited. According to the embodiment of the application, the RPCVD technology is adopted to form the GeSn alloy lead, so that the metal electrode in the traditional diode is replaced, and the integration level and stealth performance of the antenna system are greatly improved. In addition, the solid-state plasma Pin diode performance is improved by using the GeOI deep-groove medium isolation process and the ion implantation process based on etching, and the solid-state plasma PiN diode is high in practicability and worthy of popularization.
Drawings
Fig. 1 is a schematic diagram of a reconfigurable symmetrical dipole antenna based on PiN diode array according to an embodiment of the present application.
Fig. 2 is a flowchart of a method for manufacturing a PiN diode array according to an embodiment of the present application.
Fig. 3 a-3 u are schematic diagrams illustrating a method for manufacturing a PiN diode array according to an embodiment of the present application.
Fig. 4 is a schematic diagram of a device structure of a PiN diode according to an embodiment of the present application.
Fig. 5 is a schematic structural diagram of a PiN diode array according to an embodiment of the present application.
Fig. 6 is a schematic diagram of a reconfigurable symmetrical dipole antenna based on PiN diode array according to an embodiment of the present application.
Description of the embodiments
In order that the above objects, features and advantages of the present application will be readily understood, a more particular description of the application will be rendered by reference to specific embodiments thereof which are illustrated in appended fig. 1 to 6, but it is to be understood that the application is not limited to specific embodiments.
The application provides a preparation method of a PiN diode array suitable for forming a reconfigurable symmetrical dipole antenna, wherein the PiN diode array is a GaP-GeSn-GaP heterogeneous PiN diode array, a transverse heterogeneous GeSn-based PiN diode is formed by doping Sn components based On Germanium (Germanium-On-Insulator, geOI for short) On an insulating substrate, the formation of a solid plasma region in an intrinsic region is controlled by externally applying forward bias voltage, the diode is in a large injection state, and the plasma concentration exceeds 1018 cm-3. At this time, the SPiN diode has very high conductivity, has a metalloid characteristic, and can replace metal and external electromagnetic wave to be mutually coupled, so that the radiation performance of the antenna is realized.
The reconfigurable symmetrical dipole antenna can be formed by combining GaP-GeSn-GaP heterogeneous PiN diodes according to an array arrangement, the optimized PiN diode array unit with high-concentration carriers replaces a metal antenna arm to serve as an antenna basic radiation unit, when forward bias voltage is externally applied, the SPIN diode array units in different areas are conducted, a plasma channel is formed by high-concentration solid-state plasmas, and when external electromagnetic waves or high-frequency electric signals are mutually coupled with the carriers, carrier oscillation is caused, so that the radiation and the reception of the electromagnetic waves are realized. The plasma channel is controlled to form different shapes and electric lengths by externally applying bias voltage, so that the reconfigurable performance of the plasma antenna is obtained, and the plasma antenna has important application prospect in aspects of helicopters, communication anti-interference and radar technology.
Hereinafter, the process flow of the PiN diode array prepared by the present application will be described in further detail. In the drawings, thicknesses of layers and regions are enlarged or reduced for convenience of description, and the illustrated sizes do not represent actual dimensions.
Examples
Referring to fig. 1, fig. 1 is a schematic structural diagram of a reconfigurable symmetrical dipole antenna according to an embodiment of the application, where the reconfigurable symmetrical dipole antenna includes: a semiconductor substrate 1, a first antenna arm 2, a second antenna arm 3, a third antenna arm 4, a fourth antenna arm 5, a first dc offset line 6, a second dc offset line 7, a third dc offset line 8, a fourth dc offset line 9, a fifth dc offset line 10, a sixth dc offset line 11, a seventh dc offset line 12, an eighth dc offset line 13, and a coaxial feeder 14; the antenna arm is composed of a plurality of GaP-GeSn-GaP heterogeneous Pin diode array units.
The reconfigurable symmetrical dipole antenna comprises a first antenna arm, a second antenna arm, a third antenna arm and a fourth antenna arm, wherein the antenna arm comprises a plurality of GaP-GeSn-GaP heterogeneous PiN diode array units, and the reconfiguration of the antenna performance is realized by controlling the on and off of the different PiN diode array units; the number of diode array units in other similar systems can be increased or decreased as required by the antenna performance.
The first antenna arm, the second antenna arm, the third antenna arm, the fourth antenna arm, the first direct current offset line, the second direct current offset line, the third direct current offset line, the fourth direct current offset line, the fifth direct current offset line, the sixth direct current offset line, the seventh direct current offset line, the eighth direct current offset line and the coaxial feeder are all manufactured on the semiconductor substrate by adopting a semiconductor process, and the diode antenna arms 2, 3, 4 and 5 are connected through the coaxial feeder 14.
Wherein the first antenna arm 2 includes GaP-GeSn-GaP hetero-PiN diode array units L1, L2, and L3 connected in series, the second antenna arm 3 includes GaP-GeSn-GaP hetero-PiN diode array units L4, L5, and L6 connected in series, the third antenna arm 4 includes GaP-GeSn-GaP hetero-PiN diode array units L7, L8, and L9 connected in series, and the fourth antenna arm 5 includes GaP-GeSn-GaP hetero-PiN diode array units L10, L11, and L12 connected in series. The different GaP-GeSn-GaP heterogeneous PiN diode array units are connected to a direct current bias power supply through direct current bias lines 6, 7, 8, 9, 10, 11, 12 and 13.
Fig. 2 is a flow chart of a method for manufacturing a PiN diode array according to an embodiment of the present application, which is suitable for manufacturing a GeOI-based lateral solid-state plasma PiN diode, and the GaP-GeSn-GaP heterogeneous PiN diode array is mainly used for manufacturing a reconfigurable symmetrical dipole antenna. The method comprises the following steps:
(a) Selecting a GeOI substrate with a certain crystal orientation, and doping the GeOI substrate to form a top GeSn region;
(b) A deep groove isolation region is arranged in the GeSn region on the top layer of the substrate;
(c) Etching the GeSn region to form a P-type groove and an N-type groove, wherein the depth of the P-type groove and the N-type groove is smaller than the thickness of the top GeSn region;
(d) Ion implantation is adopted in the P-type groove and the N-type groove to form a P-type active region and an N-type active region; and
(e) And forming a GeSn alloy lead on the substrate and connecting the diodes in series to finish the preparation of the GaP-GeSn-GaP heterogeneous PiN diode array in the reconfigurable symmetrical dipole antenna.
The reason why the top GeSn region is doped in the GeOI substrate for step (a) is that the radiation unit diode of the silicon-based solid state plasma antenna needs to have a high concentration of solid state plasma because of its good microwave characteristics. The GaP-GeSn-GaP heterogeneous PiN diode array obtains GeSn alloy with a forbidden band width which is much narrower than that of GaP materials by doping Sn components in the top layer Ge and dynamically controlling the content of the Sn components in the top layer Ge, so that the injection ratio of carriers from a source region to an intrinsic region is further improved, and the concentration and distribution uniformity of solid plasma in the diode are greatly improved. In addition, the introduction of the buried oxide layer and the deep trench isolation technology further improves the carrier confinement capability, so Sn is doped in the GeOI substrate to form a top GeSn region.
For step (a), doping the GeOI substrate to form a top GeSn region may include the steps of:
(a1) Photoetching the GeOI substrate;
(a2) Carrying out Sn component doping on the GeOI substrate to form a top GeSn region, and dynamically controlling the content of Sn components in the top Ge to realize the maximum injection ratio of carriers;
(a3) The photoresist is removed.
Furthermore, for the step (b), a deep trench isolation region is disposed in the GeSn region on the top layer of the substrate, which specifically includes the following steps:
(b1) Forming a protective layer on the surface of the GeSn region;
specifically, the protective layer includes a silicon dioxide (SiO 2) layer and a silicon nitride (SiN) layer, and the forming of the protective layer includes: generating a silicon dioxide layer on the surface of the GeSn region of the substrate; and generating a silicon nitride layer on the surface of the silicon dioxide layer. The method has the advantages that the stress of the silicon nitride is isolated by utilizing the loose property of the silicon dioxide, so that the silicon nitride cannot be conducted into the top GeSn area, and the stability of the performance of the top GeSn area is ensured; based on the high selectivity ratio of silicon nitride and germanium in dry etching, the silicon nitride is used as a masking film for dry etching, so that the process is easy to realize. Of course, it is understood that the number of layers of the protective layer and the material of the protective layer are not limited herein as long as the protective layer can be formed.
(b2) Forming an isolation region pattern on the protective layer by using a photoetching process;
(b3) Etching the protective layer and the substrate at the appointed position of the isolation region graph by utilizing a dry etching process to form an isolation groove, wherein the depth of the isolation groove is greater than or equal to the thickness of a top GeSn region of the substrate;
the depth of the isolation groove is larger than or equal to the thickness of the top GeSn region, and the advantage of the isolation groove is that silicon dioxide in the subsequent groove is connected with the buried oxide layer of the GeOI substrate to form complete insulation isolation of the diode device, so that lateral diffusion of carriers among the devices is prevented.
(b4) Filling the isolation groove to form the isolation region of the Pin diode;
(b5) The substrate is planarized.
Further, for step (c), the following steps may be specifically included:
(c1) Forming a protective layer on the surface of the substrate;
specifically, the protective layer comprises a silicon dioxide layer and a silicon nitride layer, and the forming of the protective layer comprises the following steps: generating a silicon dioxide layer on the surface of the GeSn region of the substrate; and generating a silicon nitride layer on the surface of the silicon dioxide layer. The benefits of this are similar to the function of the protective layer above and will not be described in detail here.
(c2) Forming P-type grooves and N-type groove patterns on the protective layer by utilizing a photoetching process;
(c3) And etching the protective layer and the GeSn region at the appointed position of the groove by utilizing a dry etching process to form the P-type groove and the N-type groove.
The depth of the P-type groove and the N-type groove is larger than the thickness of the protective layer and smaller than the sum of the thicknesses of the protective layer and the top GeSn region. Preferably, the distance between the bottoms of the P-type trench and the N-type trench and the bottom of the top GeSn region is 5 micrometers to 25 micrometers, so that a deep groove which is generally considered as a deep groove is formed, and a P, N region with uniform impurity distribution and high doping concentration and a steep Pi and Ni junction can be formed when the P-type active region and the N-type active region are formed, so that the plasma concentration of the intrinsic region can be improved.
Further, for step (d), the following steps may be specifically included:
(d1) Forming a first P type active region and a first N type active region in the P type groove and the N type groove;
specifically, the process of forming the first active region may be: oxidizing the P-type groove and the N-type groove to form an oxidation layer on the inner wall of the groove, flattening the groove by utilizing a wet etching process, and performing ion implantation on the P-type groove and the N-type groove to form the first P-type active region and the first N-type active region.
Among them, the flattening treatment has the following advantages: the protrusion of the trench sidewall can be prevented from forming an electric field concentration region, causing Pi and Ni junction breakdown. The ion implantation process may be: photoetching a P-type groove and an N-type groove; injecting P-type impurities and N-type impurities into the P-type groove and the N-type groove respectively by adopting a method of injecting glued ions so as to form a first P-type active region and a first N-type active region; the photoresist is removed. The first P-type active region and the first N-type active region are regions with a depth of less than 1 micron from the side wall and the bottom of the groove along the ion diffusion direction.
The first active region is formed for the purpose of: forming a layer of uniform heavy doped region on the side wall of the groove, wherein the region is a heavy doped region in a Pi and Ni junction, and the formation of the first active region has the following advantages that firstly, the phenomenon that a heterojunction between polycrystalline GaP and GeSn coincides with the Pi and Ni junction and the performance uncertainty is caused is avoided; secondly, in the polycrystalline GaP process, a cavity is prevented from being formed between the polycrystalline GaP and the groove wall due to the non-uniformity of the polycrystalline GaP growth, and the cavity can cause poor contact between the polycrystalline GaP and the side wall, so that the performance of the device is affected.
(d2) Forming a second P type active region and a second N type active region in the P type groove and the N type groove;
specifically, the process of forming the second active region may be: filling the P-type groove and the N-type groove with polycrystalline GaP; after flattening the substrate, forming a polycrystalline GaP layer on the surface of the substrate; photoetching the polycrystalline GaP layer, and respectively injecting P-type impurities and N-type impurities into the positions of the P-type groove and the N-type groove by adopting a method of injecting glued ions so as to form a second P-type active region and a second N-type active region and simultaneously form a P-type contact region and an N-type contact region; removing the photoresist; and removing the polycrystalline GaP layer outside the P type contact region and the N type contact region by wet etching.
Further, for step (e), the following steps may be specifically included:
(e1) Generating silicon dioxide on the substrate;
(e2) Activating impurities in the active region using an annealing process;
(e3) Photoetching a lead hole in the P-type contact area and the N-type contact area;
(e4) Forming a GeSn alloy lead wire in the lead wire hole by adopting the RPCVD technology;
(e5) Passivating and photoetching PAD;
(e6) The diodes are connected in series with each other to form an array of PiN diodes in the reconfigurable symmetrical dipole antenna.
The preparation method of the Pin diode array provided by the application has the following advantages:
(1) The method is used for forming the reconfigurable symmetrical dipole antenna, and the dynamic reconfiguration of the antenna performance is realized by dynamically controlling the on and off of the PiN diode array unit.
(2) The content of Sn component in the top layer Ge is dynamically controlled, so that the adjustment of the GeSn forbidden bandwidth of the diode intrinsic region is realized, and the concentration and the distribution uniformity of solid plasma of the PiN diode can be effectively improved due to the characteristics of large injection ratio and high mobility.
(3) The GeSn alloy lead is formed by adopting the RPCVD technology to replace a metal electrode in the traditional pin diode, so that the integration level and stealth performance of the silicon-based antenna system are greatly improved.
(4) The P region and the N region of the PiN diode array adopt a polysilicon mosaic process based on etching deep groove etching, and the process can provide abrupt junction Pi and Ni junction, effectively improve junction depth and improve concentration and distribution of solid plasma.
(5) The Pin diode array adopts a deep-groove dielectric isolation process, so that the breakdown voltage of the diode is effectively improved, and the influence of leakage current on the performance of the device is inhibited.
Examples
Referring to fig. 3 a-3 u, fig. 3 a-3 u are schematic diagrams illustrating a method for manufacturing a PiN diode array according to an embodiment of the present application, based on the first embodiment, a GaP-GeSn-GaP hetero PiN diode array with an intrinsic region length of 90 micrometers (the intrinsic region length may be between 50 micrometers and 150 micrometers) is manufactured, which comprises the following specific steps:
s10, selecting the GeOI substrate.
Referring to fig. 3a, the crystal orientation of the GeOI substrate 101 may be (100) or (110) or (111), without limitation. The GeOI substrate 101 may be n-type or p-type in doping concentration of, for example, 0.5X104 to 0.5X11015 cm-3, and the top layer Ge has a thickness of, for example, 30 to 120. Mu.m.
S20, doping the GeOI substrate to form a top GeSn region.
Referring to fig. 3b, the specific implementation may be: and photoetching the GeOI substrate, carrying out Sn component doping on the GeOI substrate to form a top GeSn region 201 on the substrate, wherein the Sn component in the GeSn region is 1-30%, and removing the photoresist.
S30, forming a protective layer on the surface of the GeSn region.
Referring to fig. 3c, two layers of materials may be continuously grown on the top GeSn region 201 by chemical vapor deposition (Chemical vapor deposition, CVD for short), wherein the first layer may be a silicon dioxide layer 301 with a thickness of 500-600 nm, and the second layer may be a silicon nitride layer 302 with a thickness of 0.5-2 μm. The method has the advantages that the stress of the silicon nitride is isolated by utilizing the loose property of the silicon dioxide, so that the silicon nitride cannot be conducted into the top GeSn area, and the stability of the performance of the top GeSn material is ensured; based on the high selectivity ratio of silicon nitride and germanium in dry etching, the silicon nitride is used as a masking film for dry etching, so that the process is easy to realize.
S40, photoetching the isolation region.
Referring to fig. 3d, an isolation region is formed on the passivation layer by a photolithography process. The specific method comprises the following steps: etching the silicon nitride layer by a wet etching process to form an isolation region pattern, and then forming an isolation region 401 with a width of 5-10 μm and a depth of 30-125 μm by dry etching; in the step, the isolation region is formed by adopting a deep groove isolation technology, and the advantage of the deep groove isolation technology is that the depth of the groove is larger than or equal to the thickness of the top GeSn layer, so that the connection between silicon dioxide in the subsequent groove and silicon dioxide on the substrate is ensured, and the complete insulation isolation of the device is formed.
S50, filling the isolation groove.
Referring to fig. 3e, after the isolation region is etched, a CVD method is used to deposit a silicon dioxide material 501 to fill the deep trench, so as to form the isolation region of the PiN diode.
S60, flattening the surface.
Referring to fig. 3f, the surface silicon dioxide layer and the silicon nitride layer are removed by chemical mechanical polishing (Chemical Mechanical Polishing, CMP for short) to planarize the surface.
S70, forming a protective layer on the surface of the substrate.
Referring to fig. 3g, the specific implementation may be: two layers of materials are continuously grown on a substrate by a CVD method, wherein the first layer is a silicon dioxide layer 701 with the thickness of 500-600 nm, and the second layer is a silicon nitride layer 702 with the thickness of 0.5-2 mu m.
S80, photoetching the P-type groove and the N-type groove.
Referring to fig. 3h, the specific implementation may be: etching the P, N area groove pattern by a wet method, and etching the P, N area silicon nitride layer by a wet method to form a P, N area pattern; by dry etching, deep grooves 801 having a width of 2 to 10 μm and a depth of 2 to 15 μm are formed. The purpose of etching the deep trench 801 is to: a P, N region with uniform impurity distribution and high doping concentration and a steep Pi and Ni junction are formed, so that the plasma concentration of the intrinsic region is improved.
S90, carrying out groove flattening treatment.
Referring to fig. 3i and 3j, the specific implementation may be: oxidizing the substrate to form an oxide layer 901 with the thickness of 5-60 nm on the inner wall of the groove, and wet etching the oxide layer 901 of the groove to smooth the inner wall of the groove. The smooth purpose of slot inner wall is: the protrusion of the sidewall is prevented from forming an electric field concentration region, causing breakdown of Pi and Ni junctions.
S100, forming a first active region.
Referring to fig. 3k, the specific implementation may be: p+ implantation is carried out on the side wall of the P region groove by photoetching the P region groove through a method of ion implantation with glue, so that a thin p+ active region 1001 is formed in the side wall, the concentration reaches 0.1-8 multiplied by 1020cm < -3 >, the thickness reaches 0.1-1 mu m, and photoresist is removed; and photoetching an N region deep groove, carrying out n+ implantation on the side wall of the N region groove by adopting a method of ion implantation with glue, forming a thin n+ active region 1002 in the side wall, enabling the concentration to reach 0.1-8 multiplied by 1020cm < -3 >, enabling the thickness to reach 0.1-1 mu m, and removing photoresist.
S110, filling polycrystalline GaP.
Referring to fig. 3l, a poly-GaP 1101 is deposited in the P, N trench by CVD and the trench is filled as a contact electrode.
S120, flattening the surface.
Referring to fig. 3m, a CMP process may be used to remove the polysilicon GaP and silicon nitride layer from the surface to planarize the surface.
S130, growing a polycrystalline GaP layer.
Referring to fig. 3n, a polycrystalline GaP layer 1301 may be deposited on the surface using CVD to a thickness of 300-600 nm.
S140, forming a second active region.
Referring to fig. 3o, the specific implementation may be: photoetching a P region groove, carrying out p+ injection by adopting a rubberized ion injection method, enabling the doping concentration of an active region of the P region to reach 0.1-8 multiplied by 1020cm < -3 >, and removing photoresist to form a P contact 1401; and photoetching the N region groove, carrying out n+ implantation by adopting ion implantation with glue, so that the doping concentration of the N region active region is 0.1-8 multiplied by 1020cm < -3 >, removing the photoresist, and forming an N contact 1402.
S150, forming a P/N contact region.
Referring to fig. 3p, a wet etch may be used to etch away the poly GaP outside the P, N contact region to form a P, N contact region.
S160, silicon dioxide is formed on the surface of the substrate.
Referring to fig. 3q, a silicon dioxide layer 1601 may be deposited on the surface of the substrate by CVD to a thickness of 500-800 nm.
S170, activating impurities.
Annealing is performed at 950-1150 ℃ for 0.5-2 minutes, so that the ion implanted impurities activate and push the impurities in the polycrystalline GaP.
And S180, photoetching a lead hole in a P, N contact area.
Referring to fig. 3r, a lead hole 1801 is etched in the silicon dioxide layer.
And S190, forming a GeSn alloy lead.
Referring to fig. 3s, a GeSn alloy may be formed in the lead hole by using RPCVD technique, and the alloy on the surface may be etched away; and forming GeSn alloy 1901 on the surface of the substrate by adopting the RPCVD technology to form a lead. The Sn component in the GeSn alloy is, for example, 1% to 30%.
S200, passivation treatment and photoetching PAD.
Referring to fig. 3t, passivation layer 2001 may be formed by depositing silicon nitride, and PAD is etched. Finally, the GaP-GeSn-GaP heterogeneous PiN diode is formed and used for preparing the reconfigurable symmetrical dipole antenna.
S210, forming a diode array.
Referring to fig. 3u, the GaP-GeSn-GaP hetero-PiN diode array is formed by sequentially connecting the GaP-GeSn-GaP hetero-PiN diodes end to end, so as to form a reconfigurable symmetrical dipole antenna basic unit.
In the present embodiment, the above-mentioned various process parameters are exemplified, and the modifications made by the conventional means of those skilled in the art are all within the scope of the present application.
The PiN diode array applied to the reconfigurable symmetrical dipole antenna prepared by the application is characterized in that firstly, the content of Sn component in the top Ge is dynamically controlled by using GeSn material, so that the adjustment of the GeSn forbidden band width of the intrinsic region of the diode is realized, the injection ratio of carriers from a source region to the intrinsic region and the carrier mobility are further improved, the concentration and the distribution uniformity of solid plasma in the diode are improved, and the performance of the silicon-based solid plasma high-integration antenna is greatly improved; secondly, the metal electrode in the traditional pin diode is replaced by the GeSn alloy electrode formed by adopting the RPCVD technology, so that the influence of solid plasma on the radiation performance of the antenna and the integration level and stealth performance of the antenna system are greatly improved, and the silicon-based solid plasma has wide application prospect in the miniaturized, integrated and intelligent directions of a communication system; in addition, the P region and the N region of the diode adopt an etching-based polysilicon mosaic process, the process can provide abrupt junction Pi and Ni junction, and can effectively improve the junction depth of the Pi and Ni junction, so that the concentration and distribution controllability of solid plasma are enhanced, and the preparation of a high-performance plasma antenna is facilitated; meanwhile, the preparation of the GaP-GeSn-GaP heterogeneous PiN diode array adopts a deep-slot dielectric isolation process, so that the breakdown voltage of the diode is effectively improved, and the influence of leakage current on the performance of the device is inhibited.
Examples
Referring to fig. 4, fig. 4 is a schematic diagram of a device structure of a PiN diode according to an embodiment of the present application, the high-injection-ratio hetero-PiN diode is manufactured by the manufacturing method shown in fig. 2, specifically, the GaP-GeSn-GaP hetero-PiN diode is manufactured on a GeOI substrate 301, and a P region 303, an N region 304, and an intrinsic region laterally located between the P region 303 and the N region 304 of the diode are all located in a top GeSn layer 302 of the substrate. The PiN diode adopts a deep trench isolation technology, i.e., a deep trench isolation region 307 is disposed outside the P region 303 and the N region 304, and the depth of the isolation trench 307 is greater than or equal to the thickness of the top GeSn layer 302. In addition, the P region 303 and the N region 304 may respectively include a thin P-type active region 305 and a thin N-type active region 306 along the carrier diffusion direction.
Referring to fig. 5, fig. 5 is a schematic structural diagram of a PiN diode array according to an embodiment of the application. The PiN diode array is formed by sequentially connecting PiN diodes of basic radiating units of the reconfigurable symmetrical dipole antenna end to end, and a P area and an N area between adjacent diodes are connected with each other to form mutual series connection between the diodes, so that the GaP-GeSn-GaP heterogeneous PiN diode array in the reconfigurable symmetrical dipole antenna is finally formed.
Referring to fig. 6, fig. 6 is a schematic structural diagram of a reconfigurable symmetrical dipole antenna based on PiN diode array according to an embodiment of the present application, where the reconfigurable symmetrical dipole antenna includes: a semiconductor substrate 1, a first antenna arm 2, a second antenna arm 3, a third antenna arm 4, a fourth antenna arm 5, a first dc offset line 6, a second dc offset line 7, a third dc offset line 8, a fourth dc offset line 9, a fifth dc offset line 10, a sixth dc offset line 11, a seventh dc offset line 12, an eighth dc offset line 13, and a coaxial feeder 14; the antenna arm is composed of a plurality of GaP-GeSn-GaP heterogeneous Pin diode array units. The reconfigurable symmetrical dipole antenna comprises a first antenna arm, a second antenna arm, a third antenna arm and a fourth antenna arm, wherein the antenna arms comprise a plurality of GaP-GeSn-GaP heterogeneous PiN diode array units, and the reconfiguration of the antenna performance is realized by controlling the on and off of the different PiN diode array units.
In summary, the application discloses a preparation method, a device and a reconfigurable symmetrical dipole antenna of a PiN diode array, which are characterized in that Sn components are doped in the top layer Ge of the PiN diode array, and GeSn alloy with a forbidden band width much narrower than that of GaP materials is obtained by dynamically controlling the content of the Sn components in the top layer Ge, so that the injection ratio of carriers from a source region to an intrinsic region is further improved, and the concentration and distribution uniformity of solid plasmas in the diode are improved. In addition, the mobility of carriers in the intrinsic region can be further improved by introducing the GeSn material, so that the performance of the silicon-based solid-state plasma high-integration antenna is greatly improved. The electrodes in the traditional silicon-based antenna pin diode are prepared from metal, and the existence of the metal electrodes can greatly influence the radar scattering cross section of the antenna system, so that the stealth characteristic of the communication system is reduced. Meanwhile, the interaction between the plasma region and electromagnetic waves is greatly influenced by the existence of the large metal electrode, so that the influence of solid plasma on the radiation performance of the antenna is weakened, and the development of silicon-based solid plasma in the directions of miniaturization, integration and intellectualization is limited. According to the embodiment of the application, the RPCVD technology is adopted to form the GeSn alloy lead, so that the metal electrode in the traditional diode is replaced, and the integration level and stealth performance of the antenna system are greatly improved. In addition, the solid-state plasma Pin diode performance is improved by using the GeOI deep-groove medium isolation process and the ion implantation process based on etching, and the solid-state plasma PiN diode is high in practicability and worthy of popularization.
The above description of embodiments is only for aiding in the understanding of the method of the present application and its core ideas; meanwhile, as for those skilled in the art, there are variations in the specific embodiments and the application scope according to the idea of the present application, and in summary, the present disclosure should not be construed as limiting the present application, and the scope of the present application should be defined by the appended claims.
The foregoing disclosure is merely illustrative of some embodiments of the application, but the embodiments are not limited thereto and variations within the scope of the application will be apparent to those skilled in the art.
Claims (7)
1. The preparation method of the Pin diode array is characterized by comprising the following steps of:
(a) Selecting a GeOI substrate with a certain crystal orientation, and doping the GeOI substrate to form a top GeSn region, wherein the method comprises the following steps:
(a1) Photoetching the GeOI substrate;
(a2) Carrying out Sn component doping on the GeOI substrate to form a top GeSn region, and dynamically controlling the content of Sn components in the top Ge to realize the maximum injection ratio of carriers;
(a3) Removing the photoresist;
(b) A deep groove isolation region is arranged in the GeSn region on the top layer of the substrate;
(c) Etching the GeSn region to form a P-type groove and an N-type groove, wherein the depth of the P-type groove and the N-type groove is smaller than the thickness of the top GeSn region;
(d) Ion implantation is adopted in the P-type groove and the N-type groove to form a P-type active region and an N-type active region, and the method comprises the following steps:
(d1) Forming a first P type active region and a first N type active region in the P type groove and the N type groove;
(d2) Forming a second P-type active region and a second N-type active region in the P-type trench and the N-type trench, comprising the following steps:
(d21) Filling the P-type groove and the N-type groove with polycrystalline GaP;
(d22) After flattening the substrate, forming a polycrystalline GaP layer on the surface of the substrate;
(d23) Photoetching the polycrystalline GaP layer, and respectively injecting P-type impurities and N-type impurities into the positions of the P-type groove and the N-type groove by adopting a method of injecting glued ions so as to form a second P-type active region and a second N-type active region and simultaneously form a P-type contact region and an N-type contact region;
(d24) Removing the photoresist;
(d25) Removing the polycrystalline GaP layer outside the P type contact region and the N type contact region by wet etching;
(e) And forming a GeSn alloy lead on the substrate and connecting the diodes in series to finish the preparation of the GaP-GeSn-GaP heterogeneous PiN diode array in the reconfigurable symmetrical dipole antenna.
2. The method for manufacturing a PiN diode array according to claim 1, wherein in the step (b), a deep trench isolation region is disposed in a GeSn region on a top layer of the substrate, comprising the steps of:
(b1) Forming a first protective layer on the surface of the GeSn region, wherein the preparation of the first protective layer comprises the following steps:
(b11) Generating a silicon dioxide layer on the surface of the substrate;
(b12) Generating a silicon nitride layer on the surface of the silicon dioxide layer;
(b2) Forming an isolation region pattern on the first protective layer by using a photoetching process;
(b3) Etching the first protective layer and the substrate at the appointed position of the isolation region graph by utilizing a dry etching process to form an isolation groove, wherein the depth of the isolation groove is greater than or equal to the thickness of a top GeSn region of the substrate;
(b4) Filling the isolation groove to form the isolation region of the Pin diode;
(b5) The substrate is planarized.
3. The method of manufacturing a PiN diode array as defined in claim 2, wherein the step (c) of etching the GeSn region to form a P-type trench and an N-type trench comprises the steps of:
(c1) Forming a second protective layer on the surface of the substrate, wherein the preparation method of the second protective layer is the same as that of the first protective layer;
(c2) Forming P-type grooves and N-type groove patterns on the second protective layer by utilizing a photoetching process;
(c3) And etching the second protective layer and the GeSn region at the appointed position of the groove by utilizing a dry etching process to form the P-type groove and the N-type groove.
4. The method of manufacturing a PiN diode array as defined in claim 1, wherein forming a first P-type active region and a first N-type active region in the P-type trench and the N-type trench in step (d 1) comprises the steps of:
(d11) Oxidizing the P-type groove and the N-type groove to form a silicon dioxide oxide layer on the inner walls of the P-type groove and the N-type groove;
(d12) Etching the oxide layers on the inner walls of the P-type groove and the N-type groove by utilizing a wet etching process to finish planarization of the inner walls of the P-type groove and the N-type groove;
(d13) Performing ion implantation on the P-type trench and the N-type trench to form the first P-type active region and the first N-type active region, wherein the first P-type active region is a region with a depth of less than 1 micrometer from the side wall and the bottom of the P-type trench along an ion diffusion direction, and the first N-type active region is a region with a depth of less than 1 micrometer from the side wall and the bottom of the N-type trench along the ion diffusion direction, and the step (d 13) comprises the following steps:
(d131) Photoetching the P-type groove and the N-type groove;
(d132) Injecting P-type impurities and N-type impurities into the P-type groove and the N-type groove respectively by adopting a method of injecting glued ions so as to form a first P-type active region and a first N-type active region;
(d133) The photoresist is removed.
5. The method of manufacturing a PiN diode array as defined in claim 1, wherein step (e) comprises the steps of:
(e1) Generating silicon dioxide on the substrate;
(e2) Activating impurities in the active region using an annealing process;
(e3) Photoetching a lead hole in the P-type contact area and the N-type contact area;
(e4) Forming a GeSn alloy lead wire in the lead wire hole by adopting the RPCVD technology;
(e5) Passivating and photoetching PAD;
(e6) The diodes are connected in series with each other to form a GaP-GeSn-GaP hetero-Pin diode array in the reconfigurable symmetrical dipole antenna.
6. A PiN diode array produced by the method of any one of claims 1-5.
7. A reconfigurable symmetrical dipole antenna comprising the PiN diode array of claim 6.
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| US7603016B1 (en) * | 2007-04-30 | 2009-10-13 | The United States Of America As Represented By The Secretary Of The Air Force | Semiconductor photonic nano communication link apparatus |
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