CN106783599B - Preparation method of heterogeneous Ge-based plasma pin diode for manufacturing dipole antenna - Google Patents
Preparation method of heterogeneous Ge-based plasma pin diode for manufacturing dipole antenna Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims description 18
- 238000002360 preparation method Methods 0.000 title description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 84
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- 238000002955 isolation Methods 0.000 claims abstract description 47
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- 238000005530 etching Methods 0.000 claims abstract description 19
- 239000012535 impurity Substances 0.000 claims abstract description 13
- 238000011049 filling Methods 0.000 claims abstract description 10
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- 239000010410 layer Substances 0.000 claims description 99
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 43
- 239000011241 protective layer Substances 0.000 claims description 30
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 20
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 17
- 239000002184 metal Substances 0.000 claims description 16
- 238000005229 chemical vapour deposition Methods 0.000 claims description 10
- 238000001312 dry etching Methods 0.000 claims description 10
- 238000001039 wet etching Methods 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 claims description 7
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- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
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Abstract
The invention relates to a method for preparing a heterogeneous Ge-based plasma pin diode of a dipole antenna, wherein a Ge-based plasma pin diode antenna arm of the dipole antenna is formed by sequentially connecting a plurality of Ge-based plasma pin diodes end to form a plasma pin diode string, and the method for preparing the Ge-based plasma pin diode comprises the following steps: selecting a GeOI substrate and arranging an isolation region; etching the GeOI substrate to form a P-type groove and an N-type groove, and oxidizing the P-type groove and the N-type groove to form an oxide layer; filling the P-type groove and the N-type groove, and forming a P-type active area and an N-type active area in the top Ge layer of the GeOI substrate by adopting ion implantation; generating silicon dioxide on the GeOI substrate; activating impurities in the active region by using an annealing process; photoetching lead holes in the P-type contact area and the N-type contact area to form leads; passivating and photoetching PAD to form the Ge-based plasma pin diode.
Description
Technical Field
The invention relates to the technical field of semiconductor device manufacturing, in particular to a method for manufacturing a heterogeneous Ge-based plasma pin diode of a dipole antenna.
Background
In modern communication and remote sensing systems, reconfigurable antennas, especially frequency reconfigurable antennas, can work under a plurality of frequencies, greatly expands the application range of the antennas, and is one of the key points of the research in the field of domestic and foreign antennas.
At present, the materials adopted by pin diodes applied to plasma reconfigurable antennas at home and abroad are all bulk silicon materials, and the materials have the problem of low intrinsic region carrier mobility, influence on the intrinsic region carrier concentration of the pin diodes and further influence on the solid plasma concentration of the pin diodes; the P region and the N region of the structure are mostly formed by adopting an injection process, and the method requires large injection dosage and energy, has high requirements on equipment and is incompatible with the prior process; and by adopting the diffusion process, although the junction depth is deeper, the areas of the P region and the N region are larger, the integration level is low, the doping concentration is uneven, the electrical performance of the pin diode is influenced, and the controllability of the concentration and the distribution of the solid plasma is poor.
Therefore, it becomes important how to select a suitable material and fabrication process to produce a plasma pin diode for application in solid state plasma antennas.
Disclosure of Invention
Therefore, in order to solve the technical defects and shortcomings in the prior art, the invention provides a method for manufacturing a heterogeneous Ge-based plasma pin diode of a dipole antenna.
The invention provides a preparation method of a heterogeneous Ge-based plasma pin diode for manufacturing a dipole antenna, wherein the dipole antenna comprises a semiconductor substrate GeOI, a Ge-based plasma pin diode antenna arm, a coaxial feeder line and a direct current bias line, the Ge-based plasma pin diode antenna arm is formed by sequentially connecting a plurality of Ge-based plasma pin diodes end to form a plasma pin diode string, and the preparation method of the Ge-based plasma pin diode comprises the following steps:
(a) selecting a GeOI substrate with a certain crystal orientation, and arranging an isolation region in the GeOI substrate;
(b) etching the GeOI substrate to form a P-type groove and an N-type groove, wherein the depth of the P-type groove and the depth of the N-type groove are smaller than the thickness of the top Ge layer of the GeOI substrate;
(c) oxidizing the P-type groove and the N-type groove to enable the inner walls of the P-type groove and the N-type groove to form an oxide layer;
(d) etching the oxide layers on the inner walls of the P-type groove and the N-type groove by using a wet etching process to finish the flattening of the inner walls of the P-type groove and the N-type groove;
(e) filling the P-type groove and the N-type groove, and forming a P-type active area and an N-type active area in the top Ge layer of the GeOI substrate by adopting ion implantation;
(f) generating silicon dioxide on the GeOI substrate; activating impurities in the active region by using an annealing process;
(g) photoetching lead holes in the P-type contact area and the N-type contact area to form leads; passivating and photoetching PAD to form the Ge-based plasma pin diode.
In an embodiment of the present invention, the plasma pin diode antenna arm includes a first antenna arm and a second antenna arm, and the number of the diode strings of the first antenna arm is the same as that of the diode strings of the second antenna arm, and the diode strings are symmetrically distributed with the coaxial feed line as a symmetry axis.
In one embodiment of the present invention, the dipole antenna comprises:
a first antenna arm (2), a second antenna arm (3) and a coaxial feed line (4) fixed on the semiconductor substrate GeOI (1);
the first antenna arm (2) and the second antenna arm (3) are respectively arranged on two sides of the coaxial feeder (4) and comprise a plurality of plasma pin diode strings, and when the antenna is in a working state, the first antenna arm (2) and the second antenna arm (3) realize the adjustment of the length of the antenna arms according to the connection and disconnection of the plurality of plasma pin diode strings.
In an embodiment of the invention, a plasma pin diode in a plasma pin diode string comprises a P + region (27), an N + region (26) and an intrinsic region (22), and further comprises a first metal contact region (23) and a second metal contact region (24); wherein the content of the first and second substances,
the first metal contact area (23) is electrically connected with the P + area (27) and the anode of the direct current bias voltage respectively, and the second metal contact area (24) is electrically connected with the N + area (26) and the cathode of the direct current bias voltage respectively, so that all plasma pin diodes of the corresponding plasma pin diode string are in a forward conduction state after the direct current bias voltage is applied to the corresponding plasma pin diode string.
In one embodiment of the present invention, an isolation region is provided within the GeOI substrate, comprising:
(a1) forming a first protective layer on the surface of the GeOI substrate;
(a2) forming a first isolation region pattern on the first protection layer by utilizing a photoetching process;
(a3) etching the first protective layer and the GeOI substrate at the designated position of the first isolation region pattern by using a dry etching process to form an isolation groove, wherein the depth of the isolation groove is more than or equal to the thickness of the top Ge layer of the GeOI substrate;
(a4) filling the isolation trench to form the isolation region of the Ge-based plasma pin diode.
On the basis of the above embodiment, the first protective layer includes a first silicon dioxide layer and a first silicon nitride layer; accordingly, step (a1) includes:
(a11) generating silicon dioxide on the surface of the GeOI substrate to form a first silicon dioxide layer;
(a12) and generating silicon nitride on the surface of the first silicon dioxide layer to form a first silicon nitride layer.
On the basis of the above embodiment, the step (b) includes:
(b1) forming a second protective layer on the surface of the GeOI substrate;
(b2) forming a second isolation region pattern on the second protective layer by utilizing a photoetching process;
(b3) and etching the second protective layer and the GeOI substrate at the designated position of the second isolation region pattern by using a dry etching process to form the P-type groove and the N-type groove.
On the basis of the above embodiment, the second protective layer includes a second silicon oxide layer and a second silicon nitride layer; accordingly, step (b1) includes:
(b11) generating silicon dioxide on the surface of the GeOI substrate to form a second silicon dioxide layer;
(b12) and generating silicon nitride on the surface of the second silicon dioxide layer to form a second silicon nitride layer.
On the basis of the above embodiment, the step (e) includes:
(e1) filling the P-type groove and the N-type groove with polycrystalline SiGe;
(e2) after the GeOI substrate is subjected to planarization processing, a polycrystalline SiGe layer is formed on the GeOI substrate;
(e3) photoetching the polycrystalline SiGe layer, and respectively injecting P-type impurities and N-type impurities into the positions of the P-type groove and the N-type groove by adopting a method of ion implantation with glue to form a P-type active region and an N-type active region and simultaneously form a P-type contact region and an N-type contact region;
(e4) removing the photoresist;
(e5) and removing the polycrystalline SiGe layer outside the P-type contact region and the N-type contact region by wet etching.
Therefore, the embodiment of the invention adopts the heterojunction structure for the plasma pin diode, thereby improving the injection efficiency and current of the current carrier, and ensuring that the performance of the heterogeneous germanium-based plasma pin diode is superior to that of a homogeneous plasma pin diode. In addition, the GeOI-based plasma pin diode applied to the solid-state plasma reconfigurable antenna, which is prepared by the invention, adopts an etching-based GeOI deep groove dielectric isolation process, so that the breakdown voltage of the device is effectively improved, and the influence of leakage current on the performance of the device is inhibited. In addition, in the conventional preparation process for manufacturing the P region and the N region of the solid plasma pin diode, the P region and the N region are both formed by adopting an injection process, and the method requires larger injection dosage and energy, has high requirements on equipment and is incompatible with the prior process; and by adopting the diffusion process, although the junction depth is deeper, the areas of the P region and the N region are larger, the integration level is low, the doping concentration is uneven, the electrical performance of the solid plasma pin diode is influenced, and the controllability of the concentration and the distribution of the solid plasma is poor.
Other aspects and features of the present invention will become apparent from the following detailed description, which proceeds with reference to the accompanying drawings. It is to be understood, however, that the drawings are designed solely for purposes of illustration and not as a definition of the limits of the invention, for which reference should be made to the appended claims. It should be further understood that the drawings are not necessarily drawn to scale and that, unless otherwise indicated, they are merely intended to conceptually illustrate the structures and procedures described herein.
Drawings
The following detailed description of embodiments of the invention will be made with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a reconfigurable dipole antenna according to an embodiment of the present invention;
fig. 2 is a flowchart of a method for manufacturing a heterogeneous Ge-based plasma pin diode according to an embodiment of the present invention;
fig. 3 a-fig. 3r are schematic diagrams of a method for manufacturing a heterogeneous Ge-based plasma pin diode according to an embodiment of the invention;
fig. 4 is a schematic structural diagram of another hetero-Ge-based plasma pin diode according to an embodiment of the present invention.
Fig. 5 is a schematic structural diagram of a heterogeneous Ge-based plasma pin diode string according to an embodiment of the present invention;
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
The invention provides a preparation method of a heterogeneous Ge-based plasma pin diode applied to a dipole antenna. The heterogeneous Ge-based plasma pin diode is a transverse pin diode formed On the basis of Germanium (GeOI for short) On an insulating substrate, when a direct current bias is applied, a solid plasma consisting of free carriers (electrons and holes) is formed On the surface of direct current, the plasma has a metalloid characteristic, namely has a reflection effect On electromagnetic waves, and the reflection characteristic of the plasma is closely related to the microwave transmission characteristic, concentration and distribution of the surface plasma.
The GeOI transverse solid state plasma pin diode plasma reconfigurable antenna can be formed by arranging and combining GeOI transverse solid state plasma pin diodes according to an array, the solid state plasma pin diodes in the array are controlled to be selectively conducted by the outside, so that the array forms dynamic solid state plasma stripes, has the function of the antenna, has the transmitting and receiving functions on specific electromagnetic waves, and can change the shape and distribution of the solid state plasma stripes through the selective conduction of the solid state plasma pin diodes in the array, thereby realizing the reconfiguration of the antenna, and having important application prospects in the aspects of national defense communication and radar technology.
The process flow of the GeOI-based solid state plasma pin diode prepared according to the present invention will be described in further detail below. In the drawings, the thickness of layers and regions are exaggerated or reduced for convenience of explanation, and the illustrated sizes do not represent actual dimensions.
Example one
Referring to fig. 1, fig. 1 is a schematic structural diagram of a reconfigurable dipole antenna according to an embodiment of the present invention. The dipole antenna comprises a semiconductor substrate GeOI, a Ge-based plasma pin diode antenna arm, a coaxial feeder line and a direct current bias line, wherein the Ge-based plasma pin diode antenna arm is formed by sequentially connecting a plurality of Ge-based plasma pin diodes end to form a plasma pin diode string, please refer to FIG. 2, FIG. 2 is a flow chart of a preparation method of the heterogeneous Ge-based plasma pin diode, and the preparation method of the Ge-based plasma pin diode comprises the following steps:
(a) selecting a GeOI substrate with a certain crystal orientation, and arranging an isolation region in the GeOI substrate;
(b) etching the GeOI substrate to form a P-type groove and an N-type groove, wherein the depth of the P-type groove and the depth of the N-type groove are smaller than the thickness of the top Ge layer of the GeOI substrate;
(c) oxidizing the P-type groove and the N-type groove to enable the inner walls of the P-type groove and the N-type groove to form an oxide layer;
(d) etching the oxide layers on the inner walls of the P-type groove and the N-type groove by using a wet etching process to finish the flattening of the inner walls of the P-type groove and the N-type groove;
(e) filling the P-type groove and the N-type groove, and forming a P-type active area and an N-type active area in the top Ge layer of the GeOI substrate by adopting ion implantation;
(f) generating silicon dioxide on the GeOI substrate; activating impurities in the active region by using an annealing process;
(g) photoetching lead holes in the P-type contact area and the N-type contact area to form leads; passivating and photoetching PAD to form the Ge-based plasma pin diode.
Among them, the reason why the GeOI substrate is used for the step (a) is that good microwave characteristics are required for the solid-state plasma antenna, and the solid-state plasma pin diode is required to have good isolation characteristics and confinement capability of carriers, i.e., solid-state plasma, in order to satisfy this requirement, and the GeOI substrate is preferably used as the substrate of the solid-state plasma pin diode because it has a pin isolation region that can be conveniently formed with an isolation groove, and silicon dioxide (SiO2) can also confine carriers, i.e., solid-state plasma, in the top layer Ge.
For step (d), the planarization process may include the following steps: oxidizing the P-type groove and the N-type groove to form an oxide layer on the inner walls of the P-type groove and the N-type groove; and etching the oxide layers on the inner walls of the P-type groove and the N-type groove by using a wet etching process to finish the flattening of the inner walls of the P-type groove and the N-type groove. The benefits of this are: the protrusion of the trench sidewall can be prevented from forming an electric field concentration region, causing Pi and Ni junction breakdown.
In an embodiment of the present invention, the plasma pin diode antenna arm includes a first antenna arm and a second antenna arm, and the number of the diode strings of the first antenna arm is the same as that of the diode strings of the second antenna arm, and the diode strings are symmetrically distributed with the coaxial feed line as a symmetry axis.
In one embodiment of the present invention, the dipole antenna comprises:
a first antenna arm (2), a second antenna arm (3) and a coaxial feed line (4) fixed on the semiconductor substrate GeOI (1);
the first antenna arm (2) and the second antenna arm (3) are respectively arranged on two sides of the coaxial feeder (4) and comprise a plurality of plasma pin diode strings, and when the antenna is in a working state, the first antenna arm (2) and the second antenna arm (3) realize the adjustment of the length of the antenna arms according to the connection and disconnection of the plurality of plasma pin diode strings.
Further, in an embodiment of the invention, the plasma pin diodes in the plasma pin diode string comprise a P + region (27), an N + region (26) and an intrinsic region (22), and further comprise a first metal contact region (23) and a second metal contact region (24); wherein the content of the first and second substances,
the first metal contact area (23) is electrically connected with the P + area (27) and the anode of the direct current bias voltage respectively, and the second metal contact area (24) is electrically connected with the N + area (26) and the cathode of the direct current bias voltage respectively, so that all plasma pin diodes of the corresponding plasma pin diode string are in a forward conduction state after the direct current bias voltage is applied to the corresponding plasma pin diode string.
In one embodiment of the present invention, an isolation region is provided within the GeOI substrate, comprising:
(a1) forming a first protective layer on the surface of the GeOI substrate;
specifically, the first protective layer includes a first silicon oxide (SiO2) layer and a first silicon nitride (SiN) layer; the forming of the first protection layer includes: generating silicon dioxide (SiO2) on the surface of the GeOI substrate to form a first silicon dioxide (SiO2) layer; silicon nitride (SiN) is grown on the surface of the first silicon oxide (SiO2) layer to form a first silicon nitride (SiN) layer. The method has the advantages that the stress of silicon nitride (SiN) is isolated by utilizing the loose characteristic of silicon dioxide (SiO2) so that the stress cannot be conducted into the top Ge layer, and the stability of the performance of the top Ge layer is ensured; based on the high selection ratio of silicon nitride (SiN) to Ge in dry etching, the silicon nitride (SiN) is used as a masking film of the dry etching, and the process is easy to realize. Of course, it is to be understood that the number of layers of the protective layer and the material of the protective layer are not limited herein as long as the protective layer can be formed.
(a2) Forming a first isolation region pattern on the first protection layer by utilizing a photoetching process;
(a3) etching the first protective layer and the GeOI substrate at the designated position of the first isolation region pattern by using a dry etching process to form an isolation groove, wherein the depth of the isolation groove is more than or equal to the thickness of the top Ge layer of the GeOI substrate;
(a4) filling the isolation trench to form the isolation region of the Ge-based plasma pin diode.
Further, on the basis of the above embodiment, the first protective layer includes a first silicon dioxide layer and a first silicon nitride layer; accordingly, step (a1) includes:
(a11) generating silicon dioxide on the surface of the GeOI substrate to form a first silicon dioxide layer;
(a12) and generating silicon nitride on the surface of the first silicon dioxide layer to form a first silicon nitride layer.
Further, on the basis of the above embodiment, the step (b) includes:
(b1) forming a second protective layer on the surface of the GeOI substrate;
specifically, the second protective layer includes a second silicon oxide (SiO2) layer and a second silicon nitride (SiN) layer; the forming of the second protective layer includes: generating silicon dioxide (SiO2) on the surface of the GeOI substrate to form a second silicon dioxide (SiO2) layer; and generating silicon nitride (SiN) on the surface of the second silicon dioxide (SiO2) layer to form a second silicon nitride (SiN) layer. The benefits of this are similar to the effect of the first protective layer and will not be described in further detail here.
(b2) Forming a second isolation region pattern on the second protective layer by utilizing a photoetching process;
(b3) and etching the second protective layer and the GeOI substrate at the designated position of the second isolation region pattern by using a dry etching process to form the P-type groove and the N-type groove.
The depth of the P-type groove and the N-type groove is larger than the thickness of the second protective layer and smaller than the sum of the thickness of the second protective layer and the thickness of Ge of the top layer of the GeOI substrate; preferably, the distance between the bottoms of the P-type trench and the N-type trench and the bottom of the top Ge of the GeOI substrate is 0.5-30 microns, so that a generally-considered deep groove is formed, and an P, N region with uniform impurity distribution and high doping concentration and a sharp Pi and Ni junction can be formed when the P-type active region and the N-type active region are formed, so that the i-region plasma concentration is favorably improved.
Further, on the basis of the above embodiment, the second protective layer includes a second silicon oxide layer and a second silicon nitride layer; accordingly, step (b1) includes:
(b11) generating silicon dioxide on the surface of the GeOI substrate to form a second silicon dioxide layer;
(b12) and generating silicon nitride on the surface of the second silicon dioxide layer to form a second silicon nitride layer.
Further, on the basis of the above embodiment, the step (e) includes:
(e1) filling the P-type groove and the N-type groove with polycrystalline SiGe;
(e2) after the GeOI substrate is subjected to planarization processing, a polycrystalline SiGe layer is formed on the GeOI substrate;
(e3) photoetching the polycrystalline SiGe layer, and respectively injecting P-type impurities and N-type impurities into the positions of the P-type groove and the N-type groove by adopting a method of ion implantation with glue to form a P-type active region and an N-type active region and simultaneously form a P-type contact region and an N-type contact region;
(e4) removing the photoresist;
(e5) and removing the polycrystalline SiGe layer outside the P-type contact region and the N-type contact region by wet etching.
The preparation method of the heterogeneous Ge-based plasma pin diode provided by the invention has the following advantages:
(1) the germanium material used by the pin diode can effectively improve the solid plasma concentration of the pin diode due to the characteristics of high mobility and long carrier life;
(2) the pin diode adopts a heterojunction structure, as the I area is germanium, the carrier mobility is high, the forbidden bandwidth is narrow, the P, N area is filled with polycrystal SiGe to form the heterojunction structure, and the forbidden bandwidth of the SiGe material is larger than that of the germanium, so that high injection ratio can be generated, and the performance of the device is improved;
(3) due to the characteristic of poor thermal stability of oxide GeO of the germanium material used by the pin diode, the process of flattening the side walls of the deep grooves of the P region and the N region can be automatically completed in a high-temperature environment, and the preparation method of the material is simplified.
(4) The pin diode adopts an etching-based deep groove medium isolation process, so that the breakdown voltage of the device is effectively improved, and the influence of leakage current on the performance of the device is inhibited.
Example two
Referring to fig. 3 a-3 r, fig. 3 a-3 r are schematic diagrams of a method for manufacturing a heterogeneous Ge-based plasma pin diode according to an embodiment of the present invention, which is described in detail by taking the example of manufacturing a GeOI-based solid-state plasma pin diode with a channel length of 22nm (a length of a solid-state plasma region is 100 μm) as an example on the basis of the first embodiment, and the specific steps are as follows:
step 1, a substrate material preparation step:
(1a) as shown in FIG. 3a, a GeOI substrate sheet 101 with a (100) crystal orientation, a p-type doping type and a doping concentration of 1014cm-3 is selected, and the thickness of top Ge is 50 μm;
(1b) as shown in fig. 3b, a first SiO2 layer 201 with a thickness of 40nm is deposited on the GeOI substrate by Chemical Vapor Deposition (CVD);
(1c) depositing a first Si3N4/SiN layer 202 with the thickness of 2 mu m on the substrate by adopting a chemical vapor deposition method;
(2a) as shown in fig. 3c, an isolation region is formed on the protection layer by a photolithography process, and the isolation region first Si3N4/SiN layer 202 is wet-etched to form an isolation region pattern; forming a deep isolation groove 301 with the width of 5 microns and the depth of 50 microns in the isolation region by adopting dry etching;
(2b) as shown in fig. 3d, depositing SiO 2401 to fill the deep isolation trench by CVD;
(2c) as shown in fig. 3e, the first Si3N4/SiN layer 202 and the first SiO2 layer 201 are removed by Chemical Mechanical Polishing (CMP) to make the surface of the GeOI substrate flat;
(3a) as shown in fig. 3f, two layers of material were deposited successively on the substrate by CVD, the first layer being a 300nm thick second SiO2 layer 601 and the second layer being a 500nm thick second Si3N4/SiN layer 602;
(3b) as shown in fig. 3g, deep grooves in P, N region are etched, and the second Si3N4/SiN layer 602 and the second SiO2 layer 601 in P, N region are wet-etched to form a P, N region pattern; adopting dry etching to form deep grooves 701 with the width of 4 mu m and the depth of 5 mu m in the P, N area, wherein the length of the grooves in the P, N area is determined according to the application condition in the prepared antenna;
(3c) as shown in fig. 3h, the inner wall of the oxidation tank is oxidized to form an oxidation layer 801 at 850 ℃ for 10 minutes, so that the inner wall of the P, N zone tank is flat;
(3d) as shown in fig. 3i, the oxide layer 801 on the inner wall of the trench is removed P, N by a wet etching process.
Step 4, P, N contact zone preparation step:
(4a) as shown in fig. 3j, poly SiGe1001 is deposited in the P, N trench by CVD and the trench is filled;
(4b) as shown in fig. 3k, CMP is used to remove the surface poly SiGe1001 and the second Si3N4/SiN layer 602, so as to make the surface flat;
(4c) as shown in fig. 3l, a layer of poly SiGe1201 with a thickness of 200-500 nm is deposited on the surface by CVD;
(4d) as shown in fig. 3m, photoetching an active region of a P region, performing P + implantation by adopting a method of ion implantation with photoresist to ensure that the doping concentration of the active region of the P region reaches 0.5 multiplied by 1020cm < -3 >, removing the photoresist and forming a P contact 1301;
(4e) photoetching an N-region active region, performing N + implantation by adopting a photoresist-carrying ion implantation method to ensure that the doping concentration of the N-region active region is 0.5 multiplied by 1020cm < -3 >, removing the photoresist and forming an N contact 1302;
(4f) as shown in fig. 3n, wet etching is used to etch away the poly SiGe1201 outside the P, N contact region, forming P, N contact region;
(4g) as shown in FIG. 3o, SiO21501 is deposited on the surface by CVD method, and the thickness is 800 nm;
(4h) annealing at 1000 ℃ for 1 minute to activate the ion implanted impurities and drive in the impurities in the poly SiGe;
step 5, forming a PIN diode:
(5a) as shown in fig. 3p, wiring holes 1601 are lithographed at the P, N contact regions;
(5b) as shown in fig. 3q, sputtering metal on the surface of the substrate, alloying at 750 ℃ to form a metal silicide 1701, and etching off the metal on the surface;
(5c) sputtering metal on the surface of the substrate, and photoetching a lead;
(5d) as shown in FIG. 3r, Si3N4/SiN is deposited to form a passivation layer 1801, and the PAD is photoetched to form a PIN diode as a material for preparing a solid state plasma antenna.
In the present embodiment, the above various process parameters are illustrated, and the modifications made by the conventional means of those skilled in the art are all within the scope of the present application.
According to the pin diode applied to the dipole antenna, firstly, the used germanium material improves the solid plasma concentration of the pin diode due to the characteristics of high mobility and long carrier life; in addition, a P area and an N area of the Ge-based pin diode adopt a polycrystalline SiGe inlaying process based on etched deep groove etching, the process can provide abrupt junction pi and ni junctions, and can effectively improve the junction depths of the pi junctions and the ni junctions, so that the controllability of the concentration and distribution of solid plasma is enhanced, and the preparation of a high-performance plasma antenna is facilitated; secondly, due to the characteristic of poor thermal stability of the oxide GeO of the germanium material, the flattening treatment of the side walls of the deep grooves of the P region and the N region can be automatically completed in a high-temperature environment, so that the preparation method of the material is simplified; and thirdly, the GeOI-based pin diode applied to the solid-state plasma reconfigurable antenna, which is prepared by the invention, adopts an etching-based deep groove dielectric isolation process, so that the breakdown voltage of the device is effectively improved, and the influence of leakage current on the performance of the device is inhibited.
EXAMPLE III
Referring to fig. 4, fig. 4 is a schematic view of a device structure of a heterogeneous Ge-based plasma pin diode according to an embodiment of the present invention. The heterogeneous Ge-based plasma pin diode is manufactured by the above-mentioned manufacturing method as shown in fig. 1, specifically, the Ge-based plasma pin diode is manufactured on a GeOI substrate 301, and a P region 304, an N region 305 and an I region laterally located between the P region 304 and the N region 305 of the pin diode are all located within a top layer Ge302 of the GeOI substrate. The pin diode can be isolated by using STI deep trenches, that is, an isolation trench 303 is respectively disposed outside the P region 304 and the N region 305, and a depth of the isolation trench 303 is greater than or equal to a thickness of the top layer Ge 302.
In summary, the principle and the implementation of the solid-state plasma pin diode and the method for manufacturing the same according to the present invention are explained herein by using specific examples, and the above description of the examples is only used to help understanding the method and the core idea of the invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention, and the scope of the present invention should be subject to the appended claims.
Claims (7)
1. A method for manufacturing a heterogeneous Ge-based plasma pin diode of a dipole antenna is characterized in that the dipole antenna comprises a semiconductor substrate GeOI, a Ge-based plasma pin diode antenna arm, a coaxial feeder line and a direct current bias line, the Ge-based plasma pin diode antenna arm is formed by sequentially connecting a plurality of Ge-based plasma pin diodes end to form a plasma pin diode string, and the method for manufacturing the Ge-based plasma pin diode comprises the following steps:
(a) selecting a GeOI substrate with a (100) crystal direction, and arranging an isolation region in the GeOI substrate, wherein the thickness of top layer Ge is 50 μm, and the depth of the isolation region is more than or equal to that of the top layer Ge of the GeOI substrate;
(b) etching the GeOI substrate to form a P-type groove and an N-type groove, wherein the depth of the P-type groove and the depth of the N-type groove are smaller than the thickness of the top Ge layer of the GeOI substrate, and the distance between the bottom of the P-type groove and the bottom of the N-type groove and the bottom of the top Ge layer of the GeOI substrate is 0.5-30 mu m;
(c) processing at 850 ℃ for 10 minutes, and oxidizing the P-type groove and the N-type groove to form an oxide layer on the inner walls of the P-type groove and the N-type groove;
(d) etching the oxide layers on the inner walls of the P-type groove and the N-type groove by using a wet etching process to finish the flattening of the inner walls of the P-type groove and the N-type groove;
(e) depositing polycrystalline SiGe in the P-type groove and the N-type groove by adopting a CVD (chemical vapor deposition) process, filling the P-type groove and the N-type groove, forming a P-type active area and an N-type active area in the top layer Ge of the GeOI substrate by adopting ion implantation, and simultaneously forming a P-type contact area and an N-type contact area, wherein the doping concentrations of the P-type active area and the N-type active area are both 0.5 × 1020cm-3；
(f) Generating silicon dioxide on the GeOI substrate; activating impurities in the active region by using an annealing process;
(g) photoetching lead holes in the P-type contact area and the N-type contact area to form leads; passivating and photoetching PAD to form the Ge-based plasma pin diode;
the plasma pin diode antenna arm comprises a first antenna arm and a second antenna arm, the number of diode strings of the first antenna arm is the same as that of diode strings of the second antenna arm, and the diode strings are symmetrically distributed by taking the coaxial feeder line as a symmetry axis;
the dipole antenna includes:
a first antenna arm (2), a second antenna arm (3) and a coaxial feed line (4) fixed on the semiconductor substrate GeOI (1);
the first antenna arm (2) and the second antenna arm (3) are respectively arranged on two sides of the coaxial feeder (4) and comprise a plurality of plasma pin diode strings, and when the antenna is in a working state, the first antenna arm (2) and the second antenna arm (3) realize the adjustment of the length of the antenna arms according to the connection and disconnection of the plurality of plasma pin diode strings.
2. A method of manufacturing as claimed in claim 1, characterized in that a plasma pin diode in the plasma pin diode string comprises a P + region (27), an N + region (26) and an intrinsic region (22), and further comprises a first metal contact region (23) and a second metal contact region (24); wherein the content of the first and second substances,
the first metal contact area (23) is electrically connected with the P + area (27) and the anode of the direct current bias voltage respectively, and the second metal contact area (24) is electrically connected with the N + area (26) and the cathode of the direct current bias voltage respectively, so that all plasma pin diodes are in a forward conduction state after the direct current bias voltage is applied to the corresponding plasma pin diode strings.
3. The method of claim 1, wherein providing isolation regions within the GeOI substrate comprises:
(a1) forming a first protective layer on the surface of the GeOI substrate;
(a2) forming a first isolation region pattern on the first protection layer by utilizing a photoetching process;
(a3) etching the first protective layer and the GeOI substrate at the designated position of the first isolation region pattern by using a dry etching process to form an isolation groove, wherein the depth of the isolation groove is more than or equal to the thickness of the top Ge layer of the GeOI substrate;
(a4) filling the isolation trench to form the isolation region of the Ge-based plasma pin diode.
4. The method according to claim 3, wherein the first protective layer comprises a first silicon dioxide layer and a first silicon nitride layer; accordingly, step (a1) includes:
(a11) generating silicon dioxide on the surface of the GeOI substrate to form a first silicon dioxide layer;
(a12) and generating silicon nitride on the surface of the first silicon dioxide layer to form a first silicon nitride layer.
5. The method of claim 4, wherein step (b) comprises:
(b1) forming a second protective layer on the surface of the GeOI substrate;
(b2) forming a second isolation region pattern on the second protective layer by utilizing a photoetching process;
(b3) and etching the second protective layer and the GeOI substrate at the designated position of the second isolation region pattern by using a dry etching process to form the P-type groove and the N-type groove.
6. The manufacturing method according to claim 5, wherein the second protective layer includes a second silicon oxide layer and a second silicon nitride layer; accordingly, step (b1) includes:
(b11) generating silicon dioxide on the surface of the GeOI substrate to form a second silicon dioxide layer;
(b12) and generating silicon nitride on the surface of the second silicon dioxide layer to form a second silicon nitride layer.
7. The method of claim 6, wherein step (e) comprises:
(e1) filling the P-type groove and the N-type groove with polycrystalline SiGe;
(e2) after the GeOI substrate is subjected to planarization processing, a polycrystalline SiGe layer is formed on the GeOI substrate;
(e3) photoetching the polycrystalline SiGe layer, and respectively injecting P-type impurities and N-type impurities into the positions of the P-type groove and the N-type groove by adopting a method of ion implantation with glue to form a P-type active region and an N-type active region and simultaneously form a P-type contact region and an N-type contact region;
(e4) removing the photoresist;
(e5) and removing the polycrystalline SiGe layer outside the P-type contact region and the N-type contact region by wet etching.
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