CN106098552A - A kind of semi-conductor discrete device CSP encapsulation technology - Google Patents
A kind of semi-conductor discrete device CSP encapsulation technology Download PDFInfo
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- 238000005516 engineering process Methods 0.000 title claims abstract description 28
- 238000005538 encapsulation Methods 0.000 title claims abstract description 21
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 239000004642 Polyimide Substances 0.000 claims abstract description 39
- 229920001721 polyimide Polymers 0.000 claims abstract description 39
- 239000000463 material Substances 0.000 claims abstract description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 31
- 229910052681 coesite Inorganic materials 0.000 claims description 28
- 229910052906 cristobalite Inorganic materials 0.000 claims description 28
- 239000000377 silicon dioxide Substances 0.000 claims description 28
- 229910052682 stishovite Inorganic materials 0.000 claims description 28
- 229910052905 tridymite Inorganic materials 0.000 claims description 28
- 239000010410 layer Substances 0.000 claims description 24
- 238000001259 photo etching Methods 0.000 claims description 15
- 239000011248 coating agent Substances 0.000 claims description 14
- 238000000576 coating method Methods 0.000 claims description 14
- 238000004528 spin coating Methods 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 12
- 238000007747 plating Methods 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 10
- 238000009792 diffusion process Methods 0.000 claims description 9
- 230000003647 oxidation Effects 0.000 claims description 8
- 238000007254 oxidation reaction Methods 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 7
- 238000005240 physical vapour deposition Methods 0.000 claims description 6
- 238000004806 packaging method and process Methods 0.000 claims description 5
- 238000007373 indentation Methods 0.000 claims description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- 239000004952 Polyamide Substances 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 238000001459 lithography Methods 0.000 claims description 3
- 230000011218 segmentation Effects 0.000 claims description 3
- 239000002344 surface layer Substances 0.000 claims description 3
- 238000003466 welding Methods 0.000 claims description 3
- 230000004888 barrier function Effects 0.000 claims description 2
- 238000001035 drying Methods 0.000 claims description 2
- 238000009713 electroplating Methods 0.000 claims description 2
- 150000002466 imines Chemical class 0.000 claims description 2
- GNFTZDOKVXKIBK-UHFFFAOYSA-N 3-(2-methoxyethoxy)benzohydrazide Chemical compound COCCOC1=CC=CC(C(=O)NN)=C1 GNFTZDOKVXKIBK-UHFFFAOYSA-N 0.000 claims 1
- 238000001312 dry etching Methods 0.000 claims 1
- 238000002360 preparation method Methods 0.000 claims 1
- 238000001039 wet etching Methods 0.000 claims 1
- 238000001465 metallisation Methods 0.000 abstract description 3
- 239000002365 multiple layer Substances 0.000 abstract description 3
- 238000002161 passivation Methods 0.000 abstract description 3
- 230000010354 integration Effects 0.000 abstract description 2
- 230000005855 radiation Effects 0.000 abstract 1
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000018109 developmental process Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 229920002647 polyamide Polymers 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 1
- 238000010923 batch production Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/293—Organic, e.g. plastic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present invention relates to the chip scale package field of semiconductor device, be specially a kind of semi-conductor discrete device CSP encapsulation technology.The present invention uses polyimide material to realize integration passivation encapsulation, it is not necessary to special bonding sealed in unit, and has more preferable insulating properties, high temperature resistant, radiation hardness, and thermal resistance is little waits premium properties；Use the inverted structure without lead-in wire and multiple-layer metallization technology, make to encapsulate electric capacity and drop to 0.5 1pF from 1 3pF of lead-in wire bonding, lead-in inductance drops to 0.5 1.5nH from 2 4nH, owing to using upside-down mounting radiator structure, thermal resistance also will drop to the half of original positive assembling structure, so that encapsulation performance is greatly promoted, and the volume weight of PIN diode is made to reduce.
Description
Technical field
The present invention relates to the chip scale package field of semiconductor device, particularly related to chip-scale CSP encapsulation technology and ground
The method studied carefully, is specially a kind of semi-conductor discrete device CSP encapsulation technology.
Background technology
It is whole information technology at current information-intensive society, integrated circuit and novel semiconductor device and sensor
Basis, is the most important mark of a national development level.For smart mobile phone, GSP equipment, digital camera, media play
In device, the portable type electronic product such as notebook computer and panel computer, game machine, medical treatment and health care facility, and industrial instrument
Load switching civilian PIN microwave diode, technology is the most ripe, and manufacturer is more.But it is as individual's mobile device
Development, the requirement for semiconductor device volume and installation dimension is more and more higher.
Existing PIN diode theory is built upon the One Dimension Analysis model on vertical table-board architecture basics, and actually
Be widely used in the PIN diode of mobile communication etc. due to resistance to pressure request relatively low, parasitic capacitance is less demanding and batch production
Technology consider, general use two exits all in the planar structure on surface, and this structure run through more deeply owing to existing
The N+ diffusion region of epitaxial layer, current path is longer, thus parasitic series resistance is relatively big, and between P+ diffusion region and two N+ diffusion regions
Spacing, relatively big for flowing through I type district CURRENT DISTRIBUTION relation, if spacing is excessive, current path increases will make dead resistance increase
Greatly, die area is excessive affects cost.Traditional method is to use surface mount package technology, the occupy-place of the diode of this technology
Area, pin-pitch and whole height, be not sufficient to tackle latest generation portable electronic system and design the space witnessed
Restricted problem.
Summary of the invention
For above-mentioned existing problems or deficiency, for realizing integrative packaging, encapsulation performance in PIN diode manufacturing process
It is greatly promoted.The invention provides a kind of semi-conductor discrete device CSP encapsulation technology.
This semi-conductor discrete device CSP encapsulation technology, its technology path utilizes polyimides polyimide material to seal
Dress passivation and the multiple-layer metallization technology of employing paster lead-in wire.
Detailed process is as follows:
A, at the upper first forward epitaxial diposition CVD of N+ type substrate (N+SUB) to obtain the high resistant epitaxial layer N-epi of 10-15um,
Doping content 0.9 × 1014cm3～1.1 × 1014cm3, then go out Si by CVD growth, then Si is carried out oxidation draw SiO2,N
+ SUB, N-epi and SiO2Length identical；N+SUB length L is 250-350um, and thickness W1 is 110-130um；N-epi thickness
W2 is 10-15um, SiO2Thickness W3 is 0.9-1.1um.
B, photoetching P+ district, expansion boron:
Photoetching and diffusion technique is utilized to prepare P+ district, distance SiO2Layer left border 28-32um, a length of 60-100um,
The degree of depth is 1.3-1.7um, and concentration is 0.9 × 1019cm3～1.1 × 1019cm3, obtain the SiO above it simultaneously2Breach.
C, photoetching N+ district:
Use the oxidation technology of step a, prepare SiO2Fill up the SiO above P+ district2Breach；Then photoetching and diffusion are used
Technique prepares N+ district, away from SiO2Layer right side boundary 17-23um, length is identical with P+ district, the degree of depth equal to W2, concentration 0.9 ×
1019cm3～1.1 × 1019cm3, obtain the SiO above N+ district simultaneously2Breach.
D, the oxidation technology of employing step a, prepare SiO2Fill up the SiO above N+ district2Breach；Then lithography fair lead i.e. P
SiO above+district and N+ district2Relief area, then use physical vapour deposition (PVD) (PVD), above P+ district and N+ district, deposit Al, make
It fills full SiO2Indentation, there, and to SiO2Upper strata.
P+ district deposit Al is beyond SiO2The thickness W4 of layer is 1.3-1.7um, distance left border 20-25um, length 100-
120um；N+ district deposit Al is beyond SiO2The thickness of layer is equal to W4, distance right side boundary 10-15um, length 100-120um, P+ district
Al is non-intersect for the deposit of deposit Al with N+ district.
E, etch-deposition Al obtain the groove of 0.1-0.2um；After having etched drying, deposit 0.8-successively at Al surface layer
The W/Au of 1.2um thickness, and the Cu of 2.7-3.2um thickness；Wherein, W/Au layer is as adhesion layer and barrier layer, and Cu is as leading
Electric layer.
F, polyimides spin coating, etching.
The substrate top surface spin-on polyimide coating obtained in step e is smooth, then to P+ district and N+ to whole coating
The polyimide coating of space above, district performs etching；
Polyimide coating after etching is 13-17um beyond the thickness above Cu layer, in left border length L1For 23-
27um, in right side boundary length L2For 18-22um；
Length L is etched above P+ districtPFor etching length L above 60-100um, N+ districtNFor 60-100um, between the two distance
L3, L1+L2+L3+LP+LN=L, L3＞ 0.
G, polyimides secondary spin coating thicken, and plating thickeies Cu, and finally plating Sn is to make external pads:
First at LPAnd LNTop plating Cu, makes the aspect ratio both sides polyimides height 2-5um of Cu；Then at L1、L2And L3
The polyimides of spin coating same thickness above polyimide coating；The aspect ratio now polyamides electroplating Sn, Sn above Cu is sub-
Amine height 4-10um；The pt of 2～3um, the finally polyimides of spin coating 15um～25um below pt is sputtered again below N+SUB.
Further, present invention additionally comprises step h, carve deep trouth with DISC scribing machine or wide laser scribing and reach lining
The end, refilling polyimides as lateral protection, photoetching reserves plating welding hole and i.e. electroplates Sn part；Again by special DISC or laser
Scribing machine completes segmentation packaging.
Described polyimide material is light-sensitive polyimide.
The CSP encapsulation technology research method of the present invention, makes the volume weight of PIN diode reduce, and uses polyimides material
Material realizes integration passivation encapsulation, it is not necessary to special bonding sealed in unit, and has more preferable insulating properties, high temperature resistant, resistance to spoke
Penetrating, thermal resistance is little waits premium properties.Use the inverted structure without lead-in wire and multiple-layer metallization technology so that encapsulation electric capacity is from lead-in wire nation
Fixed 1-3pF drops to 0.5-1pF, and lead-in inductance drops to 0.5-1.5nH from 2-4nH, owing to using upside-down mounting radiator structure, and heat
Resistance is also by dropping to the half of original positive assembling structure, so that encapsulation performance is greatly promoted.
Accompanying drawing explanation
Fig. 1 is integrated chip processing and the chip size packages techniqueflow schematic diagram of embodiment；
Reference: N+SUB length-L, etches length-L above P+ districtP, above N+ district, etch length-LN, LPWith LNIt
Between distance L3, N+SUB thickness-W1, N-epi thickness-W2, SiO2Thickness-W3, polyimide layer-I of spin coating for the first time, second
Polyimide layer-II of secondary spin coating, the polyimides-IV of lateral protection.
Detailed description of the invention
By following example the description that combines its accompanying drawing, it is further appreciated by purpose and the feature of its invention.
The CSP chip dimension encapsulation method of the present invention will be described in further detail below.Described CSP chip size
Being embodied as combining shown in Fig. 1 and include of encapsulation:
A, on N+SUB first forward epitaxial diposition (CVD) to obtain the high resistant epitaxial layer N-epi of 12um, doping content 1.0
×1014cm3, then grow Si by Chemical Vapor-Phase Epitaxy deposit (CVD), then Si aoxidized, draw SiO2, L=
300um, W1=120um, W2=12um, W3=1um；
B, photoetching P+ district, expand boron. and i.e. use photoetching and diffusion technique to obtain on the left of distance border at 30um, a length of
80um, thickness 3um, concentration 1.0 × 1019cm3P+ district and P+ district above SiO2Breach；
C, photoetching N+ district.Use the oxidation technology in step a, utilize SiO2Fill up the SiO above P+ district2Indentation, there, then
Use photoetching and diffusion technique away from SiO2Layer obtains 80um length, 12um thickness at 20um on the right side of border, and concentration is 1.0 ×
1019cm3N+ district and the SiO of top2Breach；
Oxidation technology in d, employing step a, utilizes SiO2Fill up the SiO above P+ district2Indentation, there, lithography fair lead, adopt
It is plated in SiO with vacuum evaporation2Top deposit Al, W4=1.5um, 24um, a length of 110um on the left of distance border, distance border
The Al of right side 14um, a length of 110um and the full SiO of filling2Breach；
E, use plasma etching, carry out etch aluminum and obtain the groove of 0.1um；Etch successfully dry after at aluminum surface layer successively
Deposit obtains the Cu of W/Au, the 3um thickness of 1um thickness；
F, the substrate upper surface spin coating light-sensitive polyimide coating obtained in step e are smooth, then to P+ to whole coating
The light-sensitive polyimide coating of district and space above, N+ district performs etching；
Light-sensitive polyimide coating after etching is 15um beyond the thickness above Cu layer, in left border length L1=
26um, in right side boundary length L2=20um；
Length L is etched above P+ districtPLength L is etched above=80um, N+ districtN=80um, between the two distance L3=
94um。
G, light-sensitive polyimide secondary spin coating thicken, and plating thickeies Cu, and finally plating Sn is to make external pads.
First at LPAnd LNTop plating Cu, makes the aspect ratio both sides light-sensitive polyimide height 2.4um of Cu；Then at L1、L2
And L3The light-sensitive polyimide of spin coating same thickness above light-sensitive polyimide；Above Cu electroplate Sn, Sn aspect ratio this
Time light-sensitive polyimide height 5um；The pt of 2.5um, the finally photosensitive polyamides of spin coating 20um below pt is sputtered again below N+SUB
Imines.
H, carve deep trouth reach substrate with DISC scribing machine or wide laser scribing, refill light-sensitive polyimide as side
Protection, photoetching reserves plating welding hole；Segmentation packaging is completed again by special DISC or laser scribing means.
After having encapsulated, drawing these packaging and testing, this encapsulation electric capacity drops to 0.8pF from the 2pF of lead-in wire bonding, lead-in wire
Inductance is dropped to below 1nH by 3nH.
Claims (4)
1. a semi-conductor discrete device CSP encapsulation technology, detailed process is as follows:
A, on the N+ i.e. N+SUB of type substrate first forward epitaxial diposition CVD to obtain the high resistant epitaxial layer N-epi of 10-15um, doping
Concentration 0.9 × 1014cm3～1.1 × 1014cm3, then go out Si by CVD growth, then Si is carried out oxidation draw SiO2,N+
SUB, N-epi and SiO2Length identical；N+SUB length L is 250-350um, and thickness W1 is 110-130um；N-epi thickness W2
For 10-15um, SiO2Thickness W3 is 0.9-1.1um；
B, photoetching P+ district, expansion boron:
Photoetching and diffusion technique is utilized to prepare P+ district, distance SiO2Layer left border 28-32um, a length of 60-100um, the degree of depth is
1.3-1.7um, concentration is 0.9 × 1019cm3～1.1 × 1019cm3, obtain the SiO above it simultaneously2Breach；
C, photoetching N+ district:
Use the oxidation technology of step a, prepare SiO2Fill up the SiO above P+ district2Breach；Then photoetching and diffusion technique are used
Preparation N+ district, away from SiO2Layer right side boundary 17-23um, length is identical with P+ district, and the degree of depth is equal to W2, concentration 0.9 × 1019cm3~
1.1×1019cm3, obtain the SiO above N+ district simultaneously2Breach；
D, the oxidation technology of employing step a, prepare SiO2Fill up the SiO above N+ district2Breach；Then lithography fair lead i.e. P+ district
With the SiO above N+ district2Relief area, then use physical vapour deposition (PVD) PVD, above P+ district and N+ district, deposit Al so that it is fill out
It is full of SiO2Indentation, there, and to SiO2Upper strata；
P+ district deposit Al is beyond SiO2The thickness W4 of layer is 1.3-1.7um, distance left border 20-25um, length 100-120um；
N+ district deposit Al is beyond SiO2The thickness of layer is equal to W4, distance right side boundary 10-15um, length 100-120um, P+ district deposit Al
Non-intersect with N+ district deposit Al；
E, etch-deposition Al obtain the groove of 0.1-0.2um；After having etched drying, deposit 0.8-successively at Al surface layer
The W/Au of 1.2um thickness, and the Cu of 2.7-3.2um thickness；Wherein, W/Au layer is as adhesion layer and barrier layer, and Cu is as leading
Electric layer；
F, polyimides spin coating, etching:
The substrate top surface spin-on polyimide coating obtained in step e is smooth to whole coating, then empty to P+ district and N+ district
Polyimide coating above between performs etching；
Polyimide coating after etching is 13-17um beyond the thickness above Cu layer, in left border length L1For 23-27um,
In right side boundary length L2For 18-22um；
Length L is etched above P+ districtPFor etching length L above 60-100um, N+ districtNFor 60-100um, between the two distance L3, L1
+L2+L3+LP+LN=L, L3＞ 0；
G, polyimides secondary spin coating thicken, and plating thickeies Cu, and finally plating Sn is to make external pads:
First at LPAnd LNTop plating Cu, makes the aspect ratio both sides polyimides height 2-5um of Cu；Then at L1、L2And L3Polyamides
The polyimides of spin coating same thickness above imines coating；The aspect ratio now polyimides electroplating Sn, Sn above Cu is high
4-10um；The pt of 2～3um, the finally polyimides of spin coating 15um～25um below pt is sputtered again below N+SUB.
2. semi-conductor discrete device CSP encapsulation technology as claimed in claim 1, it is characterised in that: described etch-deposition Al uses
Wet etching or dry etching.
3. semi-conductor discrete device CSP encapsulation technology as claimed in claim 1, it is characterised in that: described polyimide material is
Light-sensitive polyimide.
4. semi-conductor discrete device CSP encapsulation technology as claimed in claim 1, it is characterised in that: after step g, also include one
Individual step h；
Step h, carve deep trouth reach substrate with DISC scribing machine or wide laser scribing, refill polyimides and protect as side
Protecting, photoetching reserves plating welding hole and i.e. electroplates Sn part；Segmentation packaging is completed again by special DISC or laser scribing means.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106783599A (en) * | 2016-12-20 | 2017-05-31 | 西安科技大学 | Make the preparation method of the heterogeneous Ge bases plasma pin diodes of dipole antenna |
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|---|---|---|---|---|
| CN101393926A (en) * | 2008-11-10 | 2009-03-25 | 吉林华微电子股份有限公司 | Bipolar transistor power device having P zone and low doping separation manufacturing method thereof |
| CN104538374A (en) * | 2015-01-08 | 2015-04-22 | 电子科技大学 | Chip scale package PIN diode and manufacturing method thereof |
| CN104952936A (en) * | 2014-03-25 | 2015-09-30 | 国家电网公司 | Fast recovery diode and manufacturing method thereof |
-
2016
- 2016-07-18 CN CN201610562746.0A patent/CN106098552A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101393926A (en) * | 2008-11-10 | 2009-03-25 | 吉林华微电子股份有限公司 | Bipolar transistor power device having P zone and low doping separation manufacturing method thereof |
| CN104952936A (en) * | 2014-03-25 | 2015-09-30 | 国家电网公司 | Fast recovery diode and manufacturing method thereof |
| CN104538374A (en) * | 2015-01-08 | 2015-04-22 | 电子科技大学 | Chip scale package PIN diode and manufacturing method thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106783599A (en) * | 2016-12-20 | 2017-05-31 | 西安科技大学 | Make the preparation method of the heterogeneous Ge bases plasma pin diodes of dipole antenna |
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