CN101517718A - Plastic packaged device with die interface layer - Google Patents
Plastic packaged device with die interface layer Download PDFInfo
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- CN101517718A CN101517718A CNA2006800397984A CN200680039798A CN101517718A CN 101517718 A CN101517718 A CN 101517718A CN A2006800397984 A CNA2006800397984 A CN A2006800397984A CN 200680039798 A CN200680039798 A CN 200680039798A CN 101517718 A CN101517718 A CN 101517718A
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- resilient coating
- bond pad
- tube core
- dielectric constant
- loss factor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3192—Multilayer coating
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3164—Partial encapsulation or coating the coating being a foil
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
- H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
- H01L23/4334—Auxiliary members in encapsulations
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- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
The invention provides a structure and method for plastic encapsulated semiconductor devices having a buffer layer of low dielectric constant and/or low loss tangent material separating the die surface from the plastic encapsulation. Semiconductor wafers with substantially completed SC die (42) are coated with the buffer layer (52). The buffer layer is patterned to expose the die bonding pads (44) but leave the buffer layer over some or all of the other die metallization. The die are then separated, mounted on a lead-frame or other support, wire bonded or otherwise coupled to external leads, and encapsulated. The plastic encapsulation (47) surrounds the die and the buffer layer, providing a solid structure. The buffer layer reduces the parasitic capacitance, cross-talk and loss between metallization regions on the die. An optional sealing layer may also be provided at the wafer stage between the buffer layer and the plastic encapsulation to mitigate any buffer layer porosity.
Description
Technical field
The present invention relates generally to semiconductor device, and more specifically, relate to plastic packaging semiconductor device with die interface layer.
Background technology
Semiconductor (SC) device usually is encapsulated in the moulding plastics.Moulding plastics around and the protection semiconductor element, support engages lead and outside lead and provide durability and shock resistance to device.Plastic packaged device is widely used.Fig. 1 shows the diagrammatic cross-sectional view of simplification of the moulding plastics encapsulation that comprises semiconductor (SC) tube core 22 20 of prior art.SC tube core 22 expediently but and optionally be installed on the radiator 23.Metal Contact zone 24-1,24-2 (by being designated as 24 jointly) is provided on SC tube core 22, and outside lead 26-1,26-2 (by being designated as 26 jointly) engage by lead or other means 25-1,25-2 (by being designated as 25 jointly) are coupled to SC tube core 22.Conductor on the die surfaces 32 and interconnection (for example, metal routing) 31 also is illustrated.Plastic encapsulant 27 is around interior section 28-1,28-2 (by the being designated as 28 jointly) moulding of SC tube core 22, conductor 31, wire bond 24, lead joint 25, outside lead 26, thus in this example, the lower surface 21 of radiator 23 keeps exposing on the downside of encapsulation 20, but having exposed surface 21 is not to be necessary.Although be widely used such as Plastic Package illustrated in fig. 1 and equivalents, it is subjected to the puzzlement of many shortcomings as known in the art and restriction.One of them is, around SC tube core 22 and go between 25 and 28 and the Plastic Package 27 that covers conductor 31 than air or vacuum, have remarkable higher dielectric constant ε
eWith loss factor δ
eFor example, the normally used plastic encapsulant that is used for semiconductor device usually has 3.5～5.0 DIELECTRIC CONSTANT
e, and, have 0.005～0.015 loss factor δ for the frequency range of being paid close attention to
eThis enough causes significant performance degradation, particularly under high frequency and high-pressure situations.Fringe field 29 (producing when applying voltage) extends in the plastic encapsulant 27 between the multiple conductor 31 and 24 on the surface 32 of SC tube core 22.This has caused encapsulating capacitive coupling (for example, " crosstalking ") and power loss (for example, heat dissipation) in 27.This is along with the DIELECTRIC CONSTANT of encapsulation 27
eWith loss factor δ
eIncrease and increase.This is crosstalked and loss is unfavorable.
In the prior art; capacitive coupling that is associated with the fringe field that extends to SC tube core outside and loss alleviate or avoid; its method is; for example: (i) on tube core, use the Faraday shield (not shown); and/or (ii) use the pottery or the metallic packaging of hollow; it provides air or vacuum space on the tube core sensing surface with conductor 24,31, and also engages and inner package lead around lead usually.Faraday shield has limited fringing field, but owing to need extra conductor and mask layer, so this is to be cost with extra die complexity.Vacuum or airspace package have been described among Fig. 2, and it shows the encapsulation 30 of hollow, and it has around the air of tube core 32 or vacuum space 37.Tube core 32 for example is installed in, metal, pottery or above the plastic-substrates 33-1, outside lead 36-1,36-2 (by being designated as 36 jointly) are attached to this plastic-substrates 33-1.Lead engages or other connection 35-1,35-2 (by being designated as 35 jointly) are coupled to bond pad 34-1,34-2 on the tube core 32 (by being designated as 34 jointly) interior section 38-1, the 38-2 (by being designated as 38 jointly) of package lead 36-1,36-2 (by being designated as 36 jointly).Top cover 33-2 is placed in above the interior section 38 of substrate 34, tube core 32, lead joint or other connections 35 and package lead 36.Around tube core 22, has air or vacuum space 37 means that fringe field 39 does not contact with any encapsulating material.Therefore, avoided by the coupling capacitance that causes with plastic encapsulant that die surfaces contacts with multiple conductor and/or the increase of loss.The DIELECTRIC CONSTANT of air or vacuum
oWith loss factor δ
oTherefore lower, and make and crosstalk and the dielectric loss minimum.Yet the encapsulation of this hollow is expensive more and usually durable not as Plastic Package.If the acceleration force that the device of finishing experience is big, then lead joint or other connections 35 may break away from.
Therefore, continue to need improved semiconductor device and method, it provides the encapsulation related capacitive cross-talk with minimizing and the plastic packaged device of loss.Therefore, it is desirable to, the improved semiconductor device with Plastic Package is provided, the material that contacts with die surfaces of this Plastic Package has lower DIELECTRIC CONSTANT
B1And/or loss factor δ
B1In addition, it is desirable to, improved plastic encapsulant, structure and method allow to form the firm basically structure around semiconductor element, die leads and wire bonds, so that mechanically durable encapsulation is provided.Further it is desirable to, the improved device that uses existing manufacturing technology to realize, perhaps it can easily be added to typical semiconductor device manufacturing line, only needs the trickle modification to manufacturing process thus.And, further it is desirable to, can obtain these advantages at low cost.By following detailed and claims, with the technical field and the background technology of front, other desired characteristics of the present invention and characteristic will be conspicuous in conjunction with the accompanying drawings.
Description of drawings
Hereinafter will the present invention be described in conjunction with following accompanying drawing, identical in the accompanying drawings numeral components identical, and
Fig. 1 shows the diagrammatic cross-sectional view of simplification of the moulding plastics packaging that comprises semiconductor (SC) tube core of prior art;
Fig. 2 shows the diagrammatic cross-sectional view of simplification of the hollow packaging that comprises semiconductor (SC) tube core of prior art;
Fig. 3 shows the diagrammatic cross-sectional view of the simplification of the moulding plastics packaging that comprises semiconductor (SC) tube core according to an embodiment of the invention;
Fig. 4 shows the diagrammatic cross-sectional view of simplification of a part of SC tube core of Fig. 3, and it shows further details;
Fig. 5 shows the diagrammatic cross-sectional view of a part of semiconductor wafer in a series of simplification of different fabrication stages, wherein the SC tube core of the type that illustrates in the shop drawings 3～4 on this semiconductor wafer;
Fig. 6 shows according to a part of semiconductor wafer of another embodiment diagrammatic cross-sectional view in a series of simplification of different fabrication stages, wherein the SC tube core of the type of explanation in the shop drawings 3～4 on this semiconductor wafer;
Fig. 7 shows according to a part of semiconductor wafer of another embodiment diagrammatic cross-sectional view in a series of simplification of different fabrication stages, wherein the SC tube core of the type of explanation in the shop drawings 3～4 on this semiconductor wafer;
Fig. 8 shows the flow chart according to the simplification of the embodiment of Fig. 5, and it has illustrated the method for plastic encapsulated semiconductor (SC) device that is used to form the die interface resilient coating with low electric capacity and loss;
Fig. 9 shows the flow chart according to the simplification of the embodiment of Fig. 6, and it has illustrated the method for plastic encapsulated semiconductor (SC) device that is used to form the die interface resilient coating with low electric capacity and loss; And
Figure 10 shows the flow chart according to the simplification of the embodiment of Fig. 7, and it has illustrated the method for plastic encapsulated semiconductor (SC) device that is used to form the die interface resilient coating with low electric capacity and loss.
Embodiment
Following detailed only is exemplary in itself, and its purpose is not to be restriction the present invention or application of the present invention and use.And, the clearly statement or the hard-core purpose of any theory of indirect suggestion in the technical field of front, background technology, description of drawings or the following detailed.
In order to make explanation simply clear, description of drawings general make, and the description of well-known features and technology and details may be omitted, to avoid unnecessarily making the present invention smudgy.In addition, the element in the accompanying drawing there is no need to draw to scale.For example, the size in some element or zone may be exaggerated with respect to other elements or zone among the figure, to assist to improve the understanding to embodiments of the invention.
Term " first " in specification and the claim, " second ", " the 3rd ", " 4th " etc. can be used for distinguishing similar element, there is no need to be used to describe specific order or chronological order.The term that should be appreciated that use like this can exchange under suitable environment, and embodiments of the invention described herein thus for example, can be operated under the order that is different from explanation herein or describes in addition.And, the inclusion that term " comprises ", " having " and any version thereof are used to contain nonexcludability, the technology, method, object or the device that comprise series of elements thus there is no need to be limited to these elements, but can comprise clearly do not list or be other intrinsic elements for this technology, method, object or device.
Term in specification and the claim " left side ", " right side ", " interior ", " outward ", " preceding ", " back ", " on ", D score, " top ", " end ", " top ", " following ", " top ", " below " etc. be used for purpose of description, there is no need to be used to describe permanent relative position.The term that should be appreciated that use like this can exchange under suitable environment, and embodiments of the invention described herein thus for example, can be operated under the orientation that is different from explanation herein or describes in addition.Be defined as using the direct or indirect connection of electric or non-electric means herein as the term " coupling " that uses.Should comprise any supporting construction of semiconductor element that one or more independently or interconnection can be installed as the term " lead frame " that uses herein, and can be metal, plastics pottery, glass or its combination.Should comprise the semiconductor device of any classification and configuration as the term " semiconductor element " that uses and abridge " SC tube core " herein, no matter individual devices or such as the complex assemblies of the device in the integrated circuit, the perhaps semiconductor device of any other configuration.As the term " lead joint " that herein uses and " wire bonds " should comprise with the package lead electrical couplings to the SC tube core contact area and/or any means of bond pad, be not limited only to use lead etc.The non-limiting example of other electrical couplings means is beam lead, solder bump, metal plastic band etc.Wait as " metal interconnected " on the term semiconductor element that uses herein and should broadly explain, and comprise the conductor of any material, be not limited only to metal material with " metallic conductor ".The non-limiting example of the conductor material of this variation is doped semiconductor, semimetal, sandwich construction etc.
Fig. 3 shows the diagrammatic cross-sectional view of the simplification of the moulding plastics packaging 40 that comprises semiconductor (SC) tube core 42 according to an embodiment of the invention.Device 40 comprises SC tube core or device 42, its expediently but and optionally be installed on the radiator 43 and by Plastic Package 47 around (except the lower surface 41 of possible radiator 43).47-1 illustrates as outline line, and encapsulation 47 can center on radiator 43, except its lower surface 41.Replacedly, 47-2 illustrates as outline line, and Plastic Package 47 can center on radiator 43 fully.Arbitrary configuration all is useful, and is not important for the present invention.Metallic conductor and interconnection 51 have been described on SC tube core 42.The upper surface 50 of tube core 42 and conductor 51 are that 53 resilient coating 52 separates with encapsulation 47 by thickness, than the DIELECTRIC CONSTANT of encapsulating material 47
eWith loss factor δ
e, this resilient coating 52 has lower DIELECTRIC CONSTANT
B1And/or loss factor δ
B1Tube core 42 has connection (for example, bond pad) 44-1, the 44-2 (by being designated as 44 jointly) on the upper surface 50 of tube core 42.The transverse side 42S of tube core 42 has stopped the upper surface 50 of tube core.Lead engages or other connection 45-1,45-2 (by being designated as 45 jointly) are coupled to interior section 48-1, the 48-2 (by being designated as 48 jointly) of outside lead 46-1,46-2 (by being designated as 46 jointly) with bond pad 44, so that the external electrical coupling at tube core 42 is provided.Usually, bond pad 44 substantial lateral are positioned at the outside of resilient coating 52, that is, resilient coating 52 does not significantly cover wire bonds or goes between 45 attached bond pad 44 parts.The element 41,42,43,44,45,46 and 48 of device 40 is similar with the element 21,22,23,24,25,26 and 28 of device 20 on function.The fringe field 49 that is associated with conductor 51 on the die surfaces 50 is basically by low ε
B1And/or δ
B1Resilient coating 52.Device 40 and 20 difference be, the encapsulation 47 of device 40 does not contact with conductor 51 on the surface 50 of SC tube core 42 basically.Surface 50 and conductor 51 are subjected to low ε
B1And/or δ
B1Resilient coating 52 protection and 47 separate by itself and encapsulation.
Low ε
B1And/or δ
B1Resilient coating 52 need be chemically stable and electric and chemically compatible with the surface 50 and the conductor 51 of SC tube core 42 so that can not bother the operation of SC tube core 42.The example of the material of applicable category be Sol-Gels, Aero-Gels, spin-coating glass and such as PTFE,
Multiple organic material with polyimides.Another kind of useful material is low-loss, low-density CVD oxide material, and it is called as " carbonado " in the art.By Midland, the SiLK that the Dow Chemical Corporation of MI makes
TMIt is another example of suitable material.These materials are known in the art.In order to be effectively, the DIELECTRIC CONSTANT of these materials
B1And/or loss factor δ
B1Need be lower than the DIELECTRIC CONSTANT of encapsulating material 47
eAnd/or loss factor δ
eUsually, the DIELECTRIC CONSTANT of layer 52
B1Advantageously should be less than about 3.5, be less than or equal to expediently about 3.0, and preferably be less than or equal to about 2.8, and loss factor δ
B1Less than about 0.005.Depend on the selection of the material of resilient coating 52, DIELECTRIC CONSTANT
B1Perhaps loss factor δ
B1Perhaps these both can be than the ε of encapsulation 47
eAnd/or δ
eReduce.Reduce DIELECTRIC CONSTANT
B1Reduced and crosstalked.Reduce loss factor δ
B1Reduced power loss.Arbitrary result all is favourable.It is desirable to ε
B1And δ
B1All be reduced, but this is dispensable, and statement " low ε
B1And/or δ
B1" and " low ε
B1And/or δ
B1" should comprise than the ε of encapsulation 47
eAnd/or δ
eThe ε that reduces
B1Perhaps δ
B1, perhaps ε
B1And δ
B1
Fig. 4 shows the diagrammatic cross-sectional view of simplification of part 60 SC tube cores 42 of the amplification of Fig. 3, and it shows further details.In this example, metallic region on the surface 50 of SC tube core 42 or conductor 51-1 and 51-3 (for example, the source electrode of MOS device and/or drain electrode connect) are that thickness is 54 sandwich construction, and it is higher than metallic region 51-2 (for example, grid connects).Fringe field 49 can extend between source electrode and drain electrode connection 51-1 and grid connection 51-2.This is common situation in the MOS device, particularly for about 400MHz or higher frequency applications.Has low-k ε
B1And/or low loss factor δ
B1Resilient coating 52 have enough thickness 53, fringing field 49 is located substantially in the resilient coating 52 thus, but not is positioned at above the Plastic Package 47.Encapsulate 47 situation than fringing field 49 by part, this has reduced owing to give birth to electrode-electric electrode capacitance and/or the loss of signal that heat causes.Than the prior art device 20 of Fig. 1, lower electric capacity has reduced crosstalking between this electrode.Should be noted that resilient coating 52 is not the interlayer dielectric that the different conductor layer is separated, but be positioned at this conductor layer outside, so that it is separated with encapsulation 47.
The resilient coating 52 of Fig. 4 can be that thickness is 53 homogeneous strata, perhaps can be structure sheaf, and it has all low ε described above
B1And/or δ
B1Thickness be the lower part 52-1 of 53-1, this lower part 52-1 is that the sealant of 53-2 covers by thickness.Some advanced low-k materials is a porous more, and it may allow moisture to enter.The moisture porosity of resilient coating 52-1 is not desirable.Therefore, it is desirable to provide the optional sealant 52-2 of the outer surface 55 (for example, top surface and side surface) that covers resilient coating 52-1, reduce thus or avoid moisture to see through the risk on surface 50.The example that is applicable to the material of optional sealant 52-2 is CVD deposit SiO
2, polyimides, Parylene etc.The other method that produces sealant 52-2 is to develop in the home position to form sealant 52-2, its method is, make a layer 52-1 be exposed to plasma or other catalyst, impel for example crosslinked or other chemical changes of generation, so that the part 52-2 of layer 52 to be provided, it is impermeable for moisture or other pollutants basically.Whether need sealant 52-2 to depend on the material selection of resilient coating 52-1 and encapsulating material 47, the moisture sensitivity of tube core 42 and the environmental specification that packaging 40 expections are satisfied.These conditions will change with situation, and within those skilled in the art's ability.One skilled in the art should appreciate that need how to determine whether sealant 52-2.Although understand the use of sealant 52-2 specifically in the device portions 60 of Fig. 4, the sealing layer also can be regarded as the part of resilient coating 52 of the device 40 of Fig. 3.
Fig. 5 shows the diagrammatic cross-sectional view of wafer substrate 82 in a plurality of simplification of different fabrication stage 80-1,80-2,80-3,80-4,80-5,80-6 (by being designated as 80 jointly), wherein on this wafer substrate 82 simultaneously a plurality of SC tube core 42-1 of the type of explanation in the shop drawings 3～4,42-2,42-3 ... 42-N (by being designated as 42 jointly).Bond pad 44 and metal interconnected or conductor 52 are positioned on the upper surface 50 of tube core 42 of wafer 82.Stage 80-1 illustrated following wafer 82 the processing stage situation, wherein semiconductor device (for example, tube core 42) fully by multiple doped region, interconnecting conductor 51 and in surface 50 or the bond pad 44 that on surface 50, provides form, but wafer 82 be not divided into yet independently tube core 42-1,42-2,42-3 ... 42-N.This processing is traditional.In stage 80-2, will hang down ε
B1And/or δ
B1Thickness be that 53 resilient coating 52 is applied to surface 50, and be applied to conductor 51 and above the bond pad 44.Basically whole surperficial 50 coated with buffer layer 52 simultaneously ideally of wafer 82.This can realize that the material with resilient coating 52 in this spin coating proceeding is dispensed into surface 50 expediently by for example spin coating proceeding, makes wafer 82 with quite high speed rotation then, so that dispense material flow in the uniform basically thin layer of thickness.Yet, also can use other means that resilient coating 52 is provided.Nonrestrictive example is vacuum deposition, sputter, chemical vapor deposition, silk screen printing etc.This program is known in the art.Identical technology can also be used to apply Fig. 4 and optional sealant 52-2 illustrated in fig. 7.The resilient coating 52 of Fig. 5 can comprise sealant 52-2, as being pointed out by dotted line 79.On wafer 82 all provide the uniform resilient coating 52 of thickness and (alternatively) sealant 52-2 above a plurality of tube cores 42 simultaneously, are the remarkable advantages of technology of the present invention.
In stage 80-3, by any means easily deposit or formation mask layer 60 on resilient coating 52.Photoresist is the example of the mask material that is suitable for.Photoresist is known with the method that applies photoresist in the art.In stage 80-4, in mask layer 60, form opening 62,62 ', the part 64,64 ' of the resilient coating 52 that is positioned at bond pad 44 tops is exposed.In the zone 91 on the right half part of stage 80-4,80-6, opening 62 is not capped bond pad 44, and in the zone 93 on the left-half of stage 80-4,80-6, opening 62 ' is not capped bond pad 44 and the saw street between tube core 42-1 and 42-2 94.In zone 91, the part 96 of the resilient coating 52 above the saw street 94 keeps, and removes the buffer layer part in the zone 93 simultaneously.Depend on the specific wafer configuration that the designer selects, arbitrary configuration all is useful.Should be included in any space that be used for wafer be divided into individual dice that wafer on provide as the term " saw street " that uses herein, and be not limited to sawing or be used to carry out any other the specific means and the method for this known function.In stage 80-5, by for example, etching or other convenient means as known in the art, remove the part 64,64 ' of resilient coating 52, make bond pad 44 and the bond pad 44 tube core 42-1 and 42-2 between of zone in 91 add that saw street 94 exposes basically thus, and make tube core 42-1,42-2 between the bond pad 44,42-3 ... the part 66 of the resilient coating 52 that the surface of 42-N 50 is top is without disturbance.In optional stage 80-6, can remove mask layer 60.This is easily, but dispensable.Resilient coating 52 can solidify after stage 80-2 or after the stage 80-6, and arbitrary selection all is more easily.It is preferred solidifying after stage 80-6, but dispensable.After stage 80-6, can use subsequently means as known in the art along saw street 94 with wafer 82 be cut into discrete individual dice 42-1,42-2,42-3 ... 42-N, can use standard techniques then, such as injection or transfer molding, these individual dice are installed in the suitable lead frame that provided and the encapsulation 47 (referring to Fig. 3～4).The advantage of above-described technology 80 is that resilient coating 52 is formed on the tube core 42 with wafer scale,, is applied to all component pipe cores of wafer basically simultaneously that is.This is desirable and economy.If sealant 52-1 (being pointed out by dotted line 79) formed or was formed a part of resilient coating 52-2 by a part of resilient coating 52-2 before stage 80-3, then as can in stage 80-6, seeing, the upper surface 76 of resilient coating 52 is sealed, but the sidewall 77 of the resilient coating 52 adjacent with bond pad 44 is not covered by sealant 52-2.Yet resilient coating 52 is normally extremely thin than its lateral dimension, and the area that enters via sidewall 77 of moisture (entering the thickness that area=bond pad girth multiply by layer 52) is very little so that can ignore thus.But, as explaining, even so little risk also can be avoided in conjunction with Fig. 6～7.
Fig. 6 shows according to the wafer substrate 82 of another embodiment diagrammatic cross-sectional view in a plurality of simplification of different fabrication stage 80 '-1,80 '-2,80 '-3,80 '-4,80 '-5,80 '-6,80 '-7 (by being designated as 80 ' jointly), wherein on this wafer substrate 82 simultaneously a plurality of SC tube core 42-1 of the type of explanation in the shop drawings 3～4,42-2,42-3 ... 42-N (by being designated as 42 jointly).Stage 80 '-1～80 '-6, the similar stage 80-1～80-6 with Fig. 5 was identical basically, but did not have sealant among Fig. 5, and was incorporated herein by reference in conjunction with being described in herein of Fig. 5.The situation that zone 91 has illustrated the part 96 that wherein keeps the resilient coating 52 on the saw street 94, and zone 93 has illustrated that part 96 wherein is removed and makes by opening 64 ' situation of saw street 94 exposures between tube core 80-1 and the tube core 80-2.In the stage 80 '-7 of Fig. 6, by for example, after the stage 80 '-6, make wafer 82 be exposed to plasma or other catalyst or reactant, impel the crosslinked or sclerosis of outer surface region of resilient coating 52, reducing its porosity and/or permeability, on the upper surface 76 of buffer layer part 52 and side surface 77, form sealant or regional 52-2 about moisture or other pollutants.The part that is not capped of resilient coating 52 is marked by reference number 52-1, and the part that is not capped (being sealant) of layer 52 is marked by reference number 52-2.By this mode, the upper surface 76 of resilient coating 52 and side surface 77 are invaded sealed at for example moisture.Do not need extra mask step.
Fig. 7 shows wafer substrate 82 according to another embodiment in the different fabrication stage 80 "-1～80 " diagrammatic cross-sectional view of a plurality of simplification of-10 (are designated as 80 jointly "), wherein on this wafer substrate 82 simultaneously a plurality of SC tube core 42-1 of the type of explanation in the shop drawings 3～4,42-2,42-3 ... 42-N (by being designated as 42 jointly).Stage 80 "-1～80 "-6 the similar stage 80-1～80-6 with Fig. 5 is identical basically, and do not have sealant among Fig. 5, and be incorporated herein by reference in conjunction with being described in herein of Fig. 5.In zone 91, bond pad 44 is exposed, and in zone 93, bond pad 44 and saw street 94 are exposed, as described previously.In the stage 80 of Fig. 7 " in-7, on resilient coating 52-1, that is, on the upper surface 76 ' and side surface 77 ' of resilient coating 52-1, deposit sealant 52-2 conformally basically.Many known technologies can be used for forming sealant 52-2, such as but not limited to, chemical vapor deposition (CVD), evaporation, sputter, spin coating, silk screen printing etc., it uses one or more encapsulants in the previously described multiple encapsulant.In the stage 80 " in-8, on sealant 52-2, for example form the mask layer 70 of photoresist or other etch mask material.In the stage 80 " in-9, in mask layer 70, form opening 72,72 '.In zone 91, opening 72 extends on the core 44 ' of bond pad 44, thus in the stage 80 " in-10; mask open 72 can be used for removing the part 74 of the sealant 52-2 above the core 44 ' of bond pad 44, stays sidewall 77 ' and the sealant 52-2 above the upper surface 76 ' of resilient coating 52-1.In zone 93, opening 72 ' is in the core 44 ' of bond pad 44 and extension above the saw street 94, thus in the stage 80 " in-10; mask open 72 ' can be used for removing the part 74 ' of core 44 ' and the sealant 52-2 above the saw street 94, stays sidewall 77 ' and the sealant 52-2 above the upper surface 76 ' of resilient coating 52-1.Can realize that then on other exposed surface 76 ' and 77 ', resilient coating 52-1 is subjected to the protection of the sealant 52-2 of conformal basically simultaneously at lead joint or other connections of the core 44 ' of bond pad 44.What should comprise the bond pad 44 that exposes by sealant 52-2 herein as the term " core " that uses can realize any zone that lead engages or other external electrical connect, and is not limited only to the central area of pad, although it is not excluded.Depend on the wafer configuration that the designer selects, can use arbitrary mask configuration of explanation in the zone 91,93, difference is, in zone 91, stay the resilient coating on the saw street 94, and in zone 93, as the part of the technology that resilient coating 52-1 and sealant 52-2 are provided, it is removed.
In Fig. 5～7, orderly treatment step 80-1...80-6; 80 '-1...80 '-7 and 80 "-1...80 "-10 mask has been described wherein and has removed step makes bond pad 44 exposures by resilient coating 52 (with sealant 52-2) situation, but this is not to be restrictive, and other zones of the die surfaces of supportive conductors 51 can and not remove the step exposure by this mask yet.At this mask and removing in the step process, for example, can also make the part of wafer 82, for example the residing saw street 94 of scribing lattice or other tube core separated regions exposes, as explanation in the zone 93.This provides a plurality of tube cores, and it has resilient coating 52 (having or do not have sealant 52-2) on surface conductor 51, but does not have resilient coating 52 on bond pad 44 or horizontal tube core side 42S.This result is for example illustrating among Fig. 3.
Fig. 8 shows the flow chart of simplification, and it has illustrated and has been used to form the low ε that has on the tube core 42
B1And/or δ
B1The method 100 of plastic encapsulated semiconductor (SC) device 40 of resilient coating 52.With reference now to Fig. 5 and 8,, method 100 starts from beginning 102 and initial step 104, and wherein in wafer 82 and/or on the wafer 82 (in being abbreviated as in Fig. 8～10/on) forms tube core 42 (referring to the stage 80-1 of Fig. 5).In the step 106 corresponding to stage 80-2, wafer 82 and (tube core 42) are by low ε
B1And/or δ
B1 Resilient coating 52 cover.As long as the ε of resilient coating 52
B1And δ
B1One of or these both respectively less than the corresponding ε of encapsulation 47
eAnd δ
e, promptly obtained advantage.In subsequent step 108, resilient coating 52 covers (stage 80-3) by mask layer 60.In step 110, to mask layer 60 compositions with the required opening in the resilient coating 52 that bond pad 44 tops are provided (stage 80-4).In step 112, remove resilient coating 52 from bond pad 44 tops, stay conductor and interconnection 51 resilient coating 52 (stage 80-5) on covering surfaces 50 and the remainder of dice 42.In step 114, expediently but and resilient coating 52 is solidified.Mention that in conjunction with the discussion of Fig. 5 curing schedule 114 can be carried out any time after step 106 expediently, so the orderly position of step 114 in method 100 is not to be restrictive only for the purpose of being convenient to explain as the front.The removing in Fig. 8 of mask layer 60 of pointing out among the stage 80-6 as Fig. 5 do not illustrate, and it can be omitted or any time after step 112 carries out.In step 116, the wafer of finishing 82 is cut into discrete individual dice 42, and these a plurality of tube cores, for example, join on lead frame or other supporters, and realize that lead at bond pad 44 engages or other are electrically connected.Lead frame and tube core are ready to encapsulation now, carry out encapsulation in step 118, and wherein mounted, lead tube core that engage, that be coated with resilient coating is closed in (referring to Fig. 3～4) in the encapsulating material 47.Depend on the particular type of package design, can carry out optional step 120, with the finishing lead frame and package lead is formed the shape of its expection.This finishing and formation operation are traditional.Method 100 proceeds to and finishes 122 then.
Fig. 9 shows the flow chart of simplification, and it has illustrated and has been used to form the low ε that has on the tube core 42
B1And/or δ
B1The method 200 of plastic encapsulated semiconductor (SC) device 40 of resilient coating 52.With reference now to Fig. 6 and 9,, method 200 starts from beginning 202 and initial step 204 (stage 80 '-1) and proceed to step 212 (stage 80 '-6).The step 204 of method 200～212 are similar with step 104～112 of the method 100 of Fig. 8.Therefore, the discussion of step 104～112 is incorporated herein by reference herein.In step 214 (stage 80 '-7),, handle the outer surface 76 ', 77 ' of resilient coating 52, to be translated into sealant as describing in conjunction with Fig. 6.The curing schedule 216 of method 200 is similar with the curing schedule 114 of method 100, and is not limited to the particular location pointed out in the sequence of steps of method 200.Depend on the selection of employed material and processing, resilient coating 52-1 and sealant 52-2 can solidify or discrete curing simultaneously.Depend on selected processing, sealant 52-2 can be without any need for discrete curing schedule.One skilled in the art should appreciate that how to depend on selected material and the processing that is used to form resilient coating 52, select to be used to solidify resilient coating 52-1 (with alternatively, sealant 52-2) optimal ordering.The step 218 of method 200～220 and discussion that combine Fig. 6 similar with step 116～120 of method 100 is incorporated herein by reference herein.Method 200 proceeds to and finishes 224 then.
Figure 10 shows the flow chart of simplification, and it has illustrated and has been used to form the low ε that has on the tube core 42
B1And/or δ
B1The method 300 of plastic encapsulated semiconductor (SC) device 40 of resilient coating 52.With reference now to Fig. 7 and 10,, method 300 starts from beginning 302 and initial step 304 (stage 80 "-1) and proceed to step 312 (stage 80 "-6).The step 304 of method 300～312 are similar with step 104～112 of the method 100 of Fig. 8.Therefore, the discussion of step 104～112 is incorporated herein by reference herein.In step 314 (stage 80 "-7), on entire wafer, at least on surface 50, bond pad 44 and above the conductor 51, conformally apply sealant 52-2 basically.In step 316 (stage 80 "-8), sealant 52-2 is by second mask layer 70, and for example, photoresist covers.In step 318 (stage 80 "-9), to mask layer 70 compositions so that the part 74 of the sealant 52-2 of the 44 ' top, central area of bond pad 44 expose.In step 320 (stage 80 "-10), depend on the selected material that is used for sealant 52-2, by any means easily (etching, development and dissolving etc.), remove the part s74 of sealant 52-2 from the central area 44 ' of bond pad 44.In the stage 80 " in-10, the mask of mask layer 70 partly is shown as and is removed, but this is not to be necessary.In step 322, resilient coating 52-1 and sealant 52-2 are solidified.Mention as associated methods 100,200, curing schedule 322 can be carried out in the multiple stage of technology, for resilient coating 52-1, can carry out in any time after applying resilient coating 52-1 and solidify, for sealant 52-2, can carry out in any time after applying sealant 52-2 and solidify.Resilient coating 52-1 and sealant 52-2 can discrete curing or are solidified together, and curing schedule 322 position between step 320 and 324 in the method 300 of Figure 10 is not to be restrictive only for the purpose of being convenient to explain.One skilled in the art should appreciate that how to depend on, for example, the particular combinations of selected material is selected reasonable time or the order of this curing schedule in the process of method 300.Step 324～328 are similar with step 116～120 of the method 100 of Fig. 8, and the discussion of the step 116 of method 100～120 is incorporated herein by reference herein.Method 300 proceeds to and finishes 330 then.
According to first embodiment, a kind of semiconductor device is provided, comprising: support component; Semiconductor element, it has towards outer die surfaces, and this has one or more electric conductors above die surfaces, wherein should be installed on the part support component by the horizontal termination of side surface and this tube core towards outer die surfaces; Plastic Package, it has DIELECTRIC CONSTANT
eWith loss factor δ
e, it is closed to small part support component and tube core; And resilient coating, its DIELECTRIC CONSTANT
B1And/or loss factor δ
B1Be lower than the ε of Plastic Package respectively
eAnd δ
e, it is in Plastic Package with towards between the outer die surfaces, and covers some or all one or more electric conductors, but does not cover side surface basically.In another embodiment, resilient coating has and is lower than about 3.0 DIELECTRIC CONSTANT
B1In another embodiment, resilient coating has and is lower than about 0.005 loss factor δ
B1In another embodiment, this device further comprises the sealant between resilient coating and Plastic Package.In another embodiment, this device further comprises the bond pad on the outer die surfaces, and wherein resilient coating extending above outer die surfaces between the bond pad that is located substantially on the outer die surfaces do not cover bond pad basically.In another embodiment, resilient coating have with respect between bond pad and one or more second lateral surface adjacent with bond pad towards the outer die surfaces first surface of conformal basically.In another embodiment, this device further comprises the first and second lip-deep sealants between resilient coating and Plastic Package of resilient coating.
According to second embodiment, a kind of semiconductor device with outside lead is provided, comprising: semiconductor element, it has first type surface, has interconnecting conductor and the bond pad that is suitable for being coupled to outside lead on this first type surface; Plastic Package, it has first dielectric constant and first loss factor, and this Plastic Package is around one or more of semiconductor element; Resilient coating, it has second dielectric constant and second loss factor, this resilient coating is between the first type surface of Plastic Package and semiconductor element, cover some interconnection at least, be not used for the bond pad areas of bond pad electrical couplings but cover basically to outside lead, and wherein second dielectric constant or second loss factor one of at least less than first dielectric constant or first loss factor of correspondence.According to another embodiment, second dielectric constant and second loss factor are all less than first dielectric constant and first loss factor of correspondence.According to another embodiment, this device further comprises the sealant between resilient coating and Plastic Package.According to another embodiment, the sealing layer is the moisture seal layer.According to another embodiment, second dielectric constant is less than about 2.8.According to another embodiment, second loss factor is less than about 0.005.
According to the 3rd embodiment, a kind of method that semiconductor element is provided is provided, comprising: the SC that comprises tube core is provided wafer, and this tube core has first type surface, has conductive interconnect and bond pad on this first type surface; Use resilient coating to cover some or all first type surface of tube core, the DIELECTRIC CONSTANT of this resilient coating
B1And/or loss factor δ
B1Respectively less than the dielectric constant and/or the loss factor of the material that is used for the Plastic Package tube core; And, expose basically to be used in the zone that tube core is coupled on the bond pad of outside lead, but stay some resilient coating above the conductive interconnect at least the resilient coating composition.According to another embodiment, this method further comprises, the exposed region of bond pad is coupled to outside lead.According to another embodiment, this method further comprises, uses to have DIELECTRIC CONSTANT
eWith loss factor δ
ePlastic Package around the interior section of tube core and outside lead, wherein ε
eGreater than ε
B1Perhaps δ
eGreater than δ
B1, and wherein resilient coating makes at least that some conductive interconnect and Plastic Package separate.According to another embodiment, ε
eGreater than ε
B1And δ
eGreater than δ
B1According to another embodiment, this method further comprises, after pattern step, forms sealant on the outer surface of resilient coating.According to another embodiment, this method further comprises, after forming step, to the sealant composition, basically expose so that being used on the bond pad is coupled to tube core in the zone of outside lead, still stay the sealant above the buffer layer part that covers conductive interconnect at least basically.According to another embodiment, this method further comprises, before step, forms sealant on the outer surface of resilient coating.
Although presented at least one exemplary embodiment in the detailed description in front, will be appreciated that, there are many variation schemes.For example, for resilient coating 52, can use multiple widely than low-k and more low-loss material.One skilled in the art will understand that the principle of instruction also is applicable to this variation scheme herein.On the contrary, preceding detailed description will be provided for the route map easily of realization example embodiment to those skilled in the art.Should be appreciated that under the prerequisite of the scope of the present invention that does not depart from the elaboration of claims and legal equivalents thereof, can carry out the multiple change in element function and the configuration.
Claims (20)
1. semiconductor device comprises:
Support component;
Semiconductor element, it has towards outer die surfaces, has one or more electric conductors on the described die surfaces, is wherein saidly laterally stopped by side surface and described tube core is installed on the part support component towards outer die surfaces;
Plastic Package, it has dielectric constant ∈
eWith loss factor δ
e, it is closed to small part support component and tube core; With
Resilient coating, its dielectric constant ∈
B1And/or loss factor δ
B1Be lower than the ∈ of Plastic Package respectively
eAnd δ
e, it is in Plastic Package with towards between the outer die surfaces, and covers some or all one or more electric conductors, but does not cover side surface basically.
2. device as claimed in claim 1, wherein said resilient coating have and are lower than about 3.0 dielectric constant ∈
B1
3. device as claimed in claim 1, wherein said resilient coating have and are lower than about 0.005 loss factor δ
B1
4. device as claimed in claim 1 further comprises the sealant between resilient coating and Plastic Package.
5. device as claimed in claim 1, wherein said device further comprises the bond pad on the outer die surfaces, and described resilient coating extending above outer die surfaces between the bond pad that is located substantially on the outer die surfaces do not cover bond pad basically.
6. device as claimed in claim 5, wherein said resilient coating has first surface, this first surface with respect between bond pad and one or more second lateral surface adjacent with bond pad towards the conformal basically of outer die surfaces.
7. device as claimed in claim 6 further comprises one of first and second surfaces of resilient coating or this sealant between resilient coating and Plastic Package on both.
8. plastic packaging semiconductor device with outside lead comprises:
Semiconductor element, it has first type surface, has interconnecting conductor and the bond pad that is suitable for being coupled to outside lead on the described first type surface;
Plastic Package, it has first dielectric constant and first loss factor, and described Plastic Package is around one or more of semiconductor element;
Resilient coating, it has second dielectric constant and second loss factor, described resilient coating covers some interconnection at least between the first type surface of Plastic Package and semiconductor element, be not used for the bond pad areas of bond pad electrical couplings to outside lead but cover basically; And
Wherein, second dielectric constant or second loss factor one of at least less than first dielectric constant or first loss factor of correspondence.
9. device as claimed in claim 8, wherein, second dielectric constant and second loss factor are all less than first dielectric constant and first loss factor of correspondence.
10. device as claimed in claim 8 further comprises the sealant between resilient coating and Plastic Package.
11. device as claimed in claim 10, wherein said sealant are the moisture seal layers.
12. device as claimed in claim 8, wherein, second dielectric constant is less than about 2.8.
13. device as claimed in claim 8, wherein, second loss factor is less than about 0.005.
14. the method that semiconductor element is provided comprises:
The SC that comprises tube core is provided wafer, and described tube core has first type surface, has conductive interconnect and bond pad on the described first type surface;
Use resilient coating to cover some or all first type surface of tube core, the dielectric constant ∈ of described resilient coating
B1And/or loss factor δ
B1Respectively less than the dielectric constant and/or the loss factor of the material that is used for the Plastic Package tube core; And
To the resilient coating composition, expose basically to be used in the zone that tube core is coupled on the bond pad of outside lead, but stay some resilient coating above the conductive interconnect at least.
15. method as claimed in claim 14 further comprises, the exposed region of bond pad is coupled to outside lead.
16. method as claimed in claim 15 further comprises, uses to have dielectric constant ∈
eWith loss factor δ
ePlastic Package around the interior section of tube core and outside lead, ∈ at least wherein
eGreater than ε
B1Perhaps δ
eGreater than δ
B1, and wherein said resilient coating makes at least, and some conductive interconnect and Plastic Package separate.
17. method as claimed in claim 16, wherein, ∈
eGreater than ε
B1And δ
eGreater than δ
B1
18. method as claimed in claim 14 further comprises, after covering step, forms sealant on the outer surface of resilient coating.
19. method as claimed in claim 18, further comprise, after forming step, the sealant composition, basically expose so that being used on the bond pad is coupled to tube core in the zone of outside lead, still stay the sealant above the partial buffer layer that covers conductive interconnect at least basically.
20. method as claimed in claim 16 further comprises, before step, forms sealant on the outer surface of resilient coating.
Applications Claiming Priority (3)
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| US11/257,822 | 2005-10-24 | ||
| PCT/US2006/040871 WO2007050422A2 (en) | 2005-10-24 | 2006-10-18 | Plastic packaged device with die interface layer |
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| Publication Number | Publication Date |
|---|---|
| CN101517718A true CN101517718A (en) | 2009-08-26 |
| CN101517718B CN101517718B (en) | 2011-01-26 |
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| CN2006800397984A Active CN101517718B (en) | 2005-10-24 | 2006-10-18 | Plastic packaged device with die interface layer |
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| US (1) | US7432133B2 (en) |
| JP (1) | JP2009513030A (en) |
| CN (1) | CN101517718B (en) |
| TW (1) | TWI470747B (en) |
| WO (1) | WO2007050422A2 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104671188A (en) * | 2013-11-26 | 2015-06-03 | 英飞凌科技股份有限公司 | Semiconductor package with air gap |
| US10224260B2 (en) | 2013-11-26 | 2019-03-05 | Infineon Technologies Ag | Semiconductor package with air gap |
| CN109273418A (en) * | 2018-11-08 | 2019-01-25 | 中国科学院苏州纳米技术与纳米仿生研究所南昌研究院 | A kind of chip-packaging structure and method |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2007050422A3 (en) | 2009-05-14 |
| JP2009513030A (en) | 2009-03-26 |
| TWI470747B (en) | 2015-01-21 |
| CN101517718B (en) | 2011-01-26 |
| US7432133B2 (en) | 2008-10-07 |
| US20070090543A1 (en) | 2007-04-26 |
| WO2007050422A2 (en) | 2007-05-03 |
| TW200731476A (en) | 2007-08-16 |
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