CN106784019B - Ge-based solid-state plasma PiN diode and preparation method thereof - Google Patents
Ge-based solid-state plasma PiN diode and preparation method thereof Download PDFInfo
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- 239000000758 substrate Substances 0.000 claims abstract description 75
- 238000000034 method Methods 0.000 claims abstract description 71
- 238000002955 isolation Methods 0.000 claims abstract description 50
- 239000007787 solid Substances 0.000 claims abstract description 49
- 230000008569 process Effects 0.000 claims abstract description 42
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- 239000010410 layer Substances 0.000 claims description 92
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 39
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 38
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 29
- 239000011241 protective layer Substances 0.000 claims description 29
- 238000001259 photo etching Methods 0.000 claims description 20
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/868—PIN diodes
Abstract
The invention relates to a Ge-based solid plasma PiN diode and a preparation method thereof, wherein the preparation method comprises the following steps: selecting a GeOI substrate with a certain crystal orientation, and arranging an isolation region in the GeOI substrate; etching the GeOI substrate to form a P-type groove and an N-type groove, wherein the depth of the P-type groove and the depth of the N-type groove are smaller than the thickness of the top Ge layer of the GeOI substrate; forming a first P-type active area and a first N-type active area in the P-type groove and the N-type groove by adopting ion implantation; filling the P-type groove and the N-type groove, and forming a second P-type active region and a second N-type active region in the top Ge layer of the GeOI substrate by adopting ion implantation; and forming a lead on the GeOI substrate to complete the preparation of the Ge-based solid-state plasma PiN diode. The embodiment of the invention can prepare and provide the high-performance Ge-based solid plasma PiN diode suitable for forming the solid plasma antenna by utilizing the deep groove isolation technology and the ion implantation process.
Description
Technical Field
The invention relates to the technical field of semiconductor device manufacturing, in particular to a Ge-based solid plasma PiN diode and a preparation method thereof.
Background
At present, the materials adopted by pin diodes applied to plasma reconfigurable antennas at home and abroad are all bulk silicon materials, and the materials have the problem of low intrinsic region carrier mobility, influence on the intrinsic region carrier concentration of the pin diodes and further influence on the solid plasma concentration of the pin diodes; the P region and the N region of the structure are mostly formed by adopting an injection process, and the method requires large injection dosage and energy, has high requirements on equipment and is incompatible with the prior process; and by adopting the diffusion process, although the junction depth is deeper, the areas of the P region and the N region are larger, the integration level is low, the doping concentration is uneven, the electrical performance of the pin diode is influenced, and the controllability of the concentration and the distribution of the solid plasma is poor.
Therefore, it becomes important to select what material and process to fabricate a solid state plasma PiN diode for application in a solid state plasma antenna.
Disclosure of Invention
Therefore, in order to solve the technical defects and shortcomings in the prior art, the invention provides a Ge-based solid-state plasma PiN diode and a preparation method thereof.
Specifically, the embodiment of the present invention provides a method for manufacturing a Ge-based solid state plasma PiN diode, where the Ge-based solid state plasma PiN diode is used for manufacturing a solid state plasma antenna, and the method includes the steps of:
(a) selecting a GeOI substrate with a certain crystal orientation, and arranging an isolation region in the GeOI substrate;
(b) etching the GeOI substrate to form a P-type groove and an N-type groove, wherein the depth of the P-type groove and the depth of the N-type groove are smaller than the thickness of the top Ge layer of the GeOI substrate;
(c) forming a first P-type active area and a first N-type active area in the P-type groove and the N-type groove by adopting ion implantation;
(d) filling the P-type groove and the N-type groove, and forming a second P-type active area and a second N-type active area in the top Ge layer of the GeOI substrate by adopting ion implantation; and
(e) and forming a lead on the GeOI substrate to finish the preparation of the Ge-based solid state plasma PiN diode.
On the basis of the above embodiment, an isolation region is provided in the GeOI substrate, including:
(a1) forming a first protective layer on the surface of the GeOI substrate;
(a2) forming a first isolation region pattern on the first protection layer by utilizing a photoetching process;
(a3) etching the first protective layer and the GeOI substrate at the designated position of the first isolation region pattern by using a dry etching process to form an isolation groove, wherein the depth of the isolation groove is more than or equal to the thickness of the top Ge layer of the GeOI substrate;
(a4) filling the isolation trench to form the isolation region of the Ge-based solid state plasma PiN diode.
On the basis of the above embodiment, the first protective layer includes a first silicon dioxide layer and a first silicon nitride layer; accordingly, step (a1) includes:
(a11) generating silicon dioxide on the surface of the GeOI substrate to form a first silicon dioxide layer;
(a12) and generating silicon nitride on the surface of the first silicon dioxide layer to form a first silicon nitride layer.
On the basis of the above embodiment, the step (b) includes:
(b1) forming a second protective layer on the surface of the GeOI substrate;
(b2) forming a second isolation region pattern on the second protective layer by utilizing a photoetching process;
(b3) and etching the second protective layer and the GeOI substrate at the designated position of the second isolation region pattern by using a dry etching process to form the P-type groove and the N-type groove.
On the basis of the above embodiment, the second protective layer includes a second silicon oxide layer and a second silicon nitride layer; accordingly, step (b1) includes:
(b11) generating silicon dioxide on the surface of the GeOI substrate to form a second silicon dioxide layer;
(b12) and generating silicon nitride on the surface of the second silicon dioxide layer to form a second silicon nitride layer.
On the basis of the above embodiment, the step (c) includes:
(c1) oxidizing the P-type groove and the N-type groove to enable the inner walls of the P-type groove and the N-type groove to form an oxide layer;
(c2) etching the oxide layers on the inner walls of the P-type groove and the N-type groove by using a wet etching process to finish the flattening of the inner walls of the P-type groove and the N-type groove;
(c3) and carrying out ion implantation on the P-type groove and the N-type groove to form a first P-type active area and a first N-type active area, wherein the depth of the first N-type active area to the side wall and the bottom of the N-type groove is smaller than 1 micrometer along the ion diffusion direction, and the depth of the first P-type active area to the side wall and the bottom of the P-type groove is smaller than 1 micrometer along the ion diffusion direction.
On the basis of the above embodiment, the step (c3) includes:
(c31) photoetching the P-type groove and the N-type groove;
(c32) respectively injecting P-type impurities and N-type impurities into the P-type groove and the N-type groove by adopting a method of ion injection with glue to form a first P-type active area and a first N-type active area;
(c33) and removing the photoresist.
On the basis of the above embodiment, the step (d) includes:
(d1) filling the P-type groove and the N-type groove with polycrystalline silicon;
(d2) after the GeOI substrate is subjected to planarization processing, a polycrystalline silicon layer is formed on the GeOI substrate;
(d3) photoetching the polycrystalline silicon layer, and respectively injecting P-type impurities and N-type impurities into the positions of the P-type groove and the N-type groove by adopting a method of ion injection with glue to form a second P-type active region and a second N-type active region and simultaneously form a P-type contact region and an N-type contact region;
(d4) removing the photoresist;
(d5) and removing the polysilicon layer outside the P-type contact region and the N-type contact region by wet etching.
On the basis of the above embodiment, the step (e) includes:
(e1) generating silicon dioxide on the GeOI substrate;
(e2) activating impurities in the active region by using an annealing process;
(e3) photoetching lead holes in the P-type contact area and the N-type contact area to form leads;
(e4) passivating and photoetching PAD to form the Ge-based solid state plasma PiN diode.
In addition, another embodiment of the present invention provides a germanium (Ge) -based solid-state plasma PiN diode for manufacturing a solid-state plasma antenna, where the Ge-based solid-state plasma PiN diode is manufactured by any of the above method embodiments.
Therefore, the embodiment of the invention adopts the polysilicon mosaic process of GeOI deep groove etching based on etching for the P area and the N area of the Ge-based solid plasma PiN diode, and the process can provide abrupt junction pi and ni junctions, effectively improve the junction depths of the pi junction and the ni junction and enhance the controllability of the concentration and distribution of the solid plasma. In addition, the GeOI-based solid-state plasma PiN diode applied to the solid-state plasma reconfigurable antenna, which is prepared by the invention, adopts an etching-based GeOI deep groove medium isolation process, so that the breakdown voltage of the device is effectively improved, and the influence of leakage current on the performance of the device is inhibited. In addition, in the preparation process of conventionally manufacturing the P region and the N region of the solid plasma PiN diode, the P region and the N region are both formed by adopting an injection process, and the method requires larger injection dosage and energy, has high requirements on equipment and is incompatible with the existing process; and by adopting the diffusion process, although the junction depth is deeper, the areas of the P region and the N region are larger, the integration level is low, the doping concentration is uneven, the electrical performance of the solid plasma PiN diode is influenced, and the controllability of the concentration and the distribution of the solid plasma is poor.
Other aspects and features of the present invention will become apparent from the following detailed description, which proceeds with reference to the accompanying drawings. It is to be understood, however, that the drawings are designed solely for purposes of illustration and not as a definition of the limits of the invention, for which reference should be made to the appended claims. It should be further understood that the drawings are not necessarily drawn to scale and that, unless otherwise indicated, they are merely intended to conceptually illustrate the structures and procedures described herein.
Drawings
The following detailed description of embodiments of the invention will be made with reference to the accompanying drawings.
Fig. 1 is a flowchart of a method for manufacturing a Ge-based solid-state plasma PiN diode according to an embodiment of the present invention.
Fig. 2 a-fig. 2s are schematic diagrams of a method for manufacturing a Ge-based solid-state plasma PiN diode according to an embodiment of the invention.
Fig. 3 is a schematic structural diagram of a Ge-based solid-state plasma PiN diode according to an embodiment of the invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
The invention provides a preparation method and a device of a germanium (Ge) -based solid plasma PiN diode suitable for forming a solid plasma reconfigurable antenna. The Ge-based solid plasma PiN diode is a transverse PiN diode formed On the basis of Germanium (GeOI for short) On an insulating substrate, when a direct current bias is applied, a solid plasma consisting of free carriers (electrons and holes) is formed On the surface of direct current, the plasma has a metal-like characteristic, namely has a reflection effect On electromagnetic waves, and the reflection characteristic of the plasma is closely related to the microwave transmission characteristic, concentration and distribution of the surface plasma.
The GeOI transverse solid state plasma PiN diode plasma reconfigurable antenna can be formed by arranging and combining GeOI transverse solid state plasma PiN diodes according to an array, the solid state plasma PiN diodes in the array are controlled to be selectively conducted by the outside, so that the array forms dynamic solid state plasma stripes, has the function of an antenna, has the transmitting and receiving functions on specific electromagnetic waves, and can change the shape and distribution of the solid state plasma stripes through the selective conduction of the solid state plasma PiN diodes in the array, thereby realizing the reconfiguration of the antenna and having important application prospects in the aspects of national defense communication and radar technology.
The process flow of the GeOI-based solid-state plasma PiN diode prepared according to the present invention will be described in further detail below. In the drawings, the thickness of layers and regions are exaggerated or reduced for convenience of explanation, and the illustrated sizes do not represent actual dimensions.
Example one
Referring to fig. 1, fig. 1 is a flow chart of a method for manufacturing a Ge-based solid state plasma PiN diode according to an embodiment of the present invention, the method is suitable for manufacturing a GeOI-based lateral solid state plasma PiN diode, and the GeOI-based lateral solid state plasma PiN diode is mainly used for manufacturing a solid state plasma antenna. The method comprises the following steps:
(a) selecting a GeOI substrate with a certain crystal orientation, and arranging an isolation region in the GeOI substrate;
(b) etching the GeOI substrate to form a P-type groove and an N-type groove, wherein the depth of the P-type groove and the depth of the N-type groove are smaller than the thickness of the top Ge layer of the GeOI substrate;
(c) forming a first P-type active area and a first N-type active area in the P-type groove and the N-type groove by adopting ion implantation;
(d) filling the P-type groove and the N-type groove, and forming a second P-type active region and a second N-type active region in the top Ge layer of the GeOI substrate by adopting ion implantation; and
(e) and forming a lead on the GeOI substrate to complete the preparation of the Ge-based solid-state plasma PiN diode.
Among them, the reason why the GeOI substrate is used for the step (a) is that good microwave characteristics are required for the solid-state plasma antenna, and the solid-state plasma PiN diode is required to have good isolation characteristics and carrier confinement ability, i.e., solid-state plasma, in order to satisfy this requirement, whereas the GeOI substrate is capable of conveniently forming a PiN isolation region, silicon dioxide (SiO), with the isolation trench2) It is also possible to confine the carriers, i.e. the solid plasma, in the top layer Ge, so GeOI is preferably used as the substrate of the solid plasma PiN diode.
In addition, for step (a), providing an isolation region within the GeOI substrate may include the steps of:
(a1) forming a first protective layer on the surface of the GeOI substrate;
specifically, the first protective layer includes a first silicon dioxide (SiO)2) A layer and a first silicon nitride (SiN) layer; the forming of the first protection layer includes: generating silicon dioxide (SiO) on the surface of GeOI substrate2) To form a first silicon dioxide (SiO)2) A layer; in the first silicon dioxide (SiO)2) Silicon nitride (SiN) is generated on the surface of the layer to form a first silicon nitride (SiN) layer. This has the advantage that silicon dioxide (SiO) is used2) The loose characteristic of the silicon nitride (SiN) isolates the stress of the silicon nitride (SiN) so that the stress cannot be conducted into the top Ge layer, and the stability of the performance of the top Ge layer is ensured; based on the high selection ratio of silicon nitride (SiN) to Ge in dry etching, the silicon nitride (SiN) is used as a masking film of the dry etching, and the process is easy to realize. Of course, it is to be understood that the number of layers of the protective layer and the material of the protective layer are not limited herein as long as the protective layer can be formed.
(a2) And forming a first isolation region pattern on the first protective layer by utilizing a photoetching process.
(a3) Etching the first protective layer and the GeOI substrate at the designated position of the first isolation region pattern by using a dry etching process to form an isolation groove, wherein the depth of the isolation groove is more than or equal to the thickness of the top Ge layer of the GeOI substrate; wherein, the depth of the isolation groove is more than or equal to the thickness of the top layer Ge, so that silicon dioxide (SiO) in the subsequent groove is ensured2) And forming complete insulation isolation by connecting the GeOI substrate with the oxide layer of the GeOI substrate.
(a4) And filling the isolation groove to form an isolation region of the Ge-based solid state plasma PiN diode. Wherein the material filling the isolation trench may be silicon dioxide (SiO)2)。
Further, the step (b) may specifically include the steps of:
(b1) forming a second protective layer on the surface of the GeOI substrate;
specifically, the second protective layer includes second silicon dioxide (SiO)2) A layer and a second silicon nitride (SiN) layer; the forming of the second protective layer includes: generating silicon dioxide (SiO) on the surface of GeOI substrate2) To form a second silicon dioxide (SiO)2) A layer; in the second silicon dioxide (SiO)2) Silicon nitride (SiN) is grown on the surface of the layer to form a second silicon nitride (SiN) layer. The benefits of this are similar to the effect of the first protective layer and will not be described in further detail here.
(b2) Forming a second isolation region pattern on the second protective layer by using a photoetching process;
(b3) and etching the second protective layer and the GeOI substrate at the designated position of the second isolation region pattern by using a dry etching process to form a P-type groove and an N-type groove.
And the depth of the P-type groove and the N-type groove is larger than the thickness of the second protective layer and smaller than the sum of the thickness of the second protective layer and the Ge of the top layer of the GeOI substrate. Preferably, the distance between the bottoms of the P-type trench and the N-type trench and the bottom of the top Ge of the GeOI substrate is 0.5-30 microns, so that a generally-considered deep groove is formed, and an P, N region with uniform impurity distribution and high doping concentration and a sharp Pi and Ni junction can be formed when the P-type active region and the N-type active region are formed, so that the i-region plasma concentration is favorably improved.
Further, the step (c) may specifically include the steps of:
(c1) and oxidizing the P-type groove and the N-type groove to form an oxide layer on the inner walls of the P-type groove and the N-type groove.
(c2) And etching the oxide layers on the inner walls of the P-type groove and the N-type groove by using a wet etching process to finish the flattening of the inner walls of the P-type groove and the N-type groove.
Specifically, the planarization process may employ the following steps: oxidizing the P-type groove and the N-type groove to form an oxide layer on the inner walls of the P-type groove and the N-type groove; and etching the oxide layers on the inner walls of the P-type groove and the N-type groove by using a wet etching process to finish the flattening of the inner walls of the P-type groove and the N-type groove. The benefits of this are: the protrusion of the trench sidewall can be prevented from forming an electric field concentration region, causing Pi and Ni junction breakdown.
(c3) And performing ion implantation on the P-type groove and the N-type groove to form a first P-type active area and a first N-type active area, wherein the depth of the first N-type active area to the side wall and the bottom of the N-type groove along the ion diffusion direction is less than 1 micrometer, and the depth of the first P-type active area to the side wall and the bottom of the P-type groove along the ion diffusion direction is less than 1 micrometer.
Specifically, the ion implantation process may be: photoetching a P-type groove and an N-type groove; respectively injecting P-type impurities and N-type impurities into the P-type groove and the N-type groove by adopting a method of ion injection with glue to form a first P-type active area and a first N-type active area; and removing the photoresist.
Wherein the first active region is formed to: forming a layer of uniform heavily doped region on the side wall of the groove, wherein the region is a heavily doped region in the Pi and Ni junction, and the formation of the first active region has the following advantages that the groove is filled with polycrystalline silicon as an electrode for illustration, so that firstly, the uncertainty of performance caused by the superposition of a heterojunction between the polycrystalline silicon and germanium and the Pi and Ni junctions is avoided; secondly, impurities in the polycrystalline silicon can be diffused to the P and N regions more quickly than in the germanium, and the doping concentration of the P and N regions is further improved; thirdly, in the polysilicon process, the cavity is prevented from being formed between the polysilicon and the groove wall due to the uneven growth of the polysilicon, and the cavity can cause poor contact between the polysilicon and the groove wall, thereby affecting the performance of the device.
Further, the step (d) may specifically include the steps of:
(d1) filling the P-type groove and the N-type groove with polycrystalline silicon;
the material filling the trench may also be metal, heavily doped polysilicon germanium or heavily doped silicon, and is preferably polysilicon.
(d2) After the GeOI substrate is subjected to leveling treatment, a polycrystalline silicon layer is formed on the GeOI substrate;
(d3) photoetching a polycrystalline silicon layer, and respectively injecting P-type impurities and N-type impurities into the positions of the P-type groove and the N-type groove by adopting a method of ion injection with glue to form a second P-type active region and a second N-type active region and simultaneously form a P-type contact region and an N-type contact region;
(d4) removing the photoresist;
(d5) and removing the polysilicon layer outside the P-type contact region and the N-type contact region by wet etching.
Further, the step (e) may specifically include the steps of:
(e1) generating silicon dioxide on the GeOI substrate;
(e2) activating impurities in the P-type active region and the N-type active region by using an annealing process;
(e3) photoetching lead holes in the P-type contact area and the N-type contact area to form leads;
(e4) passivation and PAD lithography to form Ge-based solid state plasma PiN diodes.
The preparation method of the Ge-based solid plasma PiN diode provided by the invention has the following advantages:
(1) the germanium material used by the pin diode can effectively improve the solid plasma concentration of the pin diode due to the characteristics of high mobility and long carrier life;
(2) the P area and the N area of the pin diode adopt a polysilicon inlaying process based on etched deep groove etching, the process can provide abrupt junction pi and ni junctions, and can effectively improve the junction depths of the pi junction and the ni junction, so that the concentration and the distribution of solid plasma can be well controlled;
(3) due to the characteristic of poor thermal stability of oxide GeO of the germanium material used by the pin diode, the process of flattening the side walls of the deep grooves of the P region and the N region can be automatically completed in a high-temperature environment, and the preparation method of the material is simplified.
(4) The pin diode adopts an etching-based deep groove medium isolation process, so that the breakdown voltage of the device is effectively improved, and the influence of leakage current on the performance of the device is inhibited.
Example two
Referring to fig. 2 a-2 s, fig. 2 a-2 s are schematic diagrams of a method for fabricating a Ge-based solid-state plasma PiN diode according to an embodiment of the present invention, which is described in detail by taking the fabrication of a GeOI-based solid-state plasma PiN diode with a channel length of 22nm (a length of a solid-state plasma region is 100 μm) as an example on the basis of the first embodiment, and includes the following steps:
step 1, a substrate material preparation step:
(1a) as shown in FIG. 2a, a (100) crystal orientation is selected, the doping type is p-type, and the doping concentration is 1014cm-3The GeOI substrate sheet 101, the thickness of the top layer Ge is 50 μm;
(1b) as shown in FIG. 2b, a first SiO layer with a thickness of 40nm is deposited on the GeOI substrate by Chemical Vapor Deposition (CVD)2A layer 201; by chemical vapor deposition on SiO2Layer-depositing a layer of first Si of 2 μm thickness3N4a/SiN layer 202;
step 2, isolation preparation:
(2a) as shown in fig. 2c, an isolation region is formed on the protection layer by photolithography, and the first Si of the isolation region is wet-etched3N4a/SiN layer 202 forming an isolation region pattern; forming a deep isolation groove 301 with the width of 5 microns and the depth of 50 microns in the isolation region by adopting dry etching;
(2b) depositing SiO by CVD, as shown in FIG. 2d 2401 filling the deep isolation trench;
(2c) as shown in fig. 2e, the first Si on the surface is removed by Chemical Mechanical Polishing (CMP)3N4the/SiN layer 202 and the first SiO2A layer 201, which levels the surface of the GeOI substrate;
step 3, P, N deep groove preparation step:
(3a) as shown in FIG. 2f, two layers of material were deposited successively by CVD, the first layer being a 300nm thick layer of the second SiO2Layer 601, second layer of second Si with a thickness of 600nm3N4a/SiN layer 602;
(3b) as shown in fig. 2g, deep trench is etched in P, N region, and second Si in P, N region is wet etched3N4a/SiN layer 602 and a second SiO2Layer 601 patterned in region P, N; adopting dry etching to form deep grooves 701 with the width of 4 mu m and the depth of 5 mu m in the P, N area, wherein the length of the grooves in the P, N area is determined according to the application condition in the prepared antenna;
(3c) as shown in fig. 2h, the inner wall of the oxidation tank is formed with an oxidation layer 801 by high temperature treatment for 10 minutes at 850 ℃;
(3d) as shown in fig. 2i, the oxide layer 801 on the inner wall of the trench in region P, N is removed by a wet etching process to make the inner wall of the trench in region P, N flat.
Step 4, P, N contact zone preparation step:
(4a) as shown in FIG. 2j, deep trench of P region is etched, and P is performed on the sidewall of the trench of P region by ion implantation with glue+Implanting to form a thin p on the sidewall+ Active region 1001 with concentration of 0.5 × 1020cm-3Removing the photoresist;
(4b) photoetching N-region deep groove, and performing N on the side wall of the N-region groove by adopting a method of ion implantation with glue+Implanting to form a thin n on the sidewall+ Active region 1002 with concentration of 0.5 × 1020cm-3Removing the photoresist;
(4c) as shown in fig. 2k, polysilicon 1101 is deposited in the P, N region by CVD, and the trench is filled;
(4d) as shown in FIG. 2l, the surface polysilicon 1101 and the second Si are removed by CMP3N4a/SiN layer 602 to planarize the surface;
(4e) as shown in fig. 2m, a layer of polysilicon 1301 is deposited on the surface by a CVD method, wherein the thickness of the polysilicon 1301 is 200-500 nm;
(4f) as shown in FIG. 2n, the active region of P region is photoetched, and P is performed by ion implantation with glue+Implanting to make the doping concentration of the active region of the P region reach 0.5 × 1020cm-3Removing the photoresist to form a P contact 1401;
(4g) photoetching N region active region, and performing N by adopting a method of ion implantation with glue+Implanting to make the doping concentration of the N region active region be 0.5 × 1020cm-3Removing the photoresist to form N-contact 1402;
(4h) as shown in fig. 2o, the polysilicon 1301 outside the P, N contact region is etched away by wet etching to form P, N contact region;
(4i) depositing SiO on the surface by CVD method, as shown in FIG. 2p 21601, the thickness is 800 nm;
(4j) annealing at 1000 deg.C for 1 min to activate the ion implanted impurities and drive in the impurities in the poly-germanium;
step 5, forming a PIN diode:
(5a) as shown in fig. 2q, a wire hole 1701 is etched at the P, N contact area;
(5b) as shown in fig. 2r, sputtering metal on the surface of the substrate, alloying at 750 ℃ to form a metal silicide 1801, and etching off the metal on the surface;
(5c) sputtering metal on the surface of the substrate, and photoetching a lead;
(5d) depositing Si as shown in FIG. 2s3N4the/SiN forms a passivation layer 1901, and the PAD is photoetched to form a PIN diode as a material for preparing the solid-state plasma antenna.
In the present embodiment, the above various process parameters are illustrated, and the modifications made by the conventional means of those skilled in the art are all within the scope of the present application.
According to the pin diode applied to the solid-state plasma reconfigurable antenna, firstly, the concentration of the solid-state plasma of the pin diode is improved due to the characteristics of high mobility and long carrier life of the used germanium material; in addition, a P area and an N area of the Ge-based pin diode adopt a polysilicon inlaying process based on etched deep groove etching, the process can provide abrupt junction pi and ni junctions, and can effectively improve the junction depths of the pi junctions and the ni junctions, so that the controllability of the concentration and distribution of solid plasma is enhanced, and the preparation of a high-performance plasma antenna is facilitated; secondly, due to the characteristic of poor thermal stability of the oxide GeO of the germanium material, the flattening treatment of the side walls of the deep grooves of the P region and the N region can be automatically completed in a high-temperature environment, so that the preparation method of the material is simplified; and thirdly, the GeOI-based pin diode applied to the solid-state plasma reconfigurable antenna, which is prepared by the invention, adopts an etching-based deep groove dielectric isolation process, so that the breakdown voltage of the device is effectively improved, and the influence of leakage current on the performance of the device is inhibited.
EXAMPLE III
Referring to fig. 3, fig. 3 is a schematic device structure diagram of a Ge-based solid-state plasma PiN diode according to an embodiment of the invention. The Ge-based solid state plasma PiN diode is manufactured by the above-described manufacturing method as shown in fig. 1, and specifically, the Ge-based solid state plasma PiN diode is manufactured on a GeOI substrate 301, and a P region 305, an N region 306 and an I region laterally located between the P region 305 and the N region 306 of a PiN diode are all located in a top layer Ge302 of the GeOI substrate. The pin diode can be isolated by using STI deep trenches, that is, an isolation trench 303 is respectively disposed outside the P region 305 and the N region 306, and the depth of the isolation trench 303 is greater than or equal to the thickness of the top layer Ge 302. In addition, the P region 305 and the N region 306 may include a thin P-type active region 307 and a thin N-type active region 304, respectively, in the substrate direction.
In summary, the principle and the implementation of the solid-state plasma PiN diode and the method for manufacturing the same according to the present invention are explained herein by using specific examples, and the above description of the examples is only used to help understanding the method and the core concept of the invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention, and the scope of the present invention should be subject to the appended claims.
Claims (8)
1. A preparation method of a Ge-based solid plasma PiN diode is characterized in that the Ge-based solid plasma PiN diode is used for manufacturing a solid plasma antenna, and the preparation method comprises the following steps:
(a) selecting a GeOI substrate with a certain crystal orientation, and arranging an isolation region in the GeOI substrate;
(b) etching the GeOI substrate to form a P-type groove and an N-type groove, wherein the depth of the P-type groove and the depth of the N-type groove are smaller than the thickness of the top Ge layer of the GeOI substrate;
(c) forming a first P-type active area and a first N-type active area in the P-type groove and the N-type groove by adopting ion implantation; the distance between the bottoms of the P-type groove and the N-type groove and the bottom of the top Ge of the GeOI substrate is 0.5-30 microns;
(d) filling the P-type groove and the N-type groove, and forming a second P-type active area and a second N-type active area in the top Ge layer of the GeOI substrate by adopting ion implantation; and
(e) forming a lead on the GeOI substrate to complete the preparation of the Ge-based plasma pin diode, wherein an isolation region is arranged in the GeOI substrate, and the method comprises the following steps:
(a1) forming a first protective layer on the surface of the GeOI substrate;
(a2) forming a first isolation region pattern on the first protection layer by utilizing a photoetching process;
(a3) etching the first protective layer and the GeOI substrate at the designated position of the first isolation region pattern by using a dry etching process to form an isolation groove, wherein the depth of the isolation groove is more than or equal to the thickness of the top Ge layer of the GeOI substrate;
(a4) filling said isolation trench to form said isolation region of said Ge-based plasma pin diode,
the step (c) includes:
(c1) processing at 850 ℃ for 10 minutes, and oxidizing the P-type groove and the N-type groove to form an oxide layer on the inner walls of the P-type groove and the N-type groove;
(c2) etching the oxide layers on the inner walls of the P-type groove and the N-type groove by using a wet etching process to finish the flattening of the inner walls of the P-type groove and the N-type groove;
(c3) and carrying out ion implantation on the P-type groove and the N-type groove to form a first P-type active area and a first N-type active area, wherein the depth of the first N-type active area to the side wall and the bottom of the N-type groove is smaller than 1 micrometer along the ion diffusion direction, and the depth of the first P-type active area to the side wall and the bottom of the P-type groove is smaller than 1 micrometer along the ion diffusion direction.
2. The method of claim 1, wherein the first protective layer comprises a first silicon dioxide layer and a first silicon nitride layer; accordingly, step (a1) includes:
(a11) generating silicon dioxide on the surface of the GeOI substrate to form a first silicon dioxide layer;
(a12) and generating silicon nitride on the surface of the first silicon dioxide layer to form a first silicon nitride layer.
3. The method of claim 1, wherein step (b) comprises:
(b1) forming a second protective layer on the surface of the GeOI substrate;
(b2) forming a second isolation region pattern on the second protective layer by utilizing a photoetching process;
(b3) and etching the second protective layer and the GeOI substrate at the designated position of the second isolation region pattern by using a dry etching process to form the P-type groove and the N-type groove.
4. The production method according to claim 3, wherein the second protective layer includes a second silicon oxide layer and a second silicon nitride layer; accordingly, step (b1) includes:
(b11) generating silicon dioxide on the surface of the GeOI substrate to form a second silicon dioxide layer;
(b12) and generating silicon nitride on the surface of the second silicon dioxide layer to form a second silicon nitride layer.
5. The method of claim 4, wherein step (c3) comprises:
(c31) photoetching the P-type groove and the N-type groove;
(c32) respectively injecting P-type impurities and N-type impurities into the P-type groove and the N-type groove by adopting a method of ion injection with glue to form a first P-type active area and a first N-type active area;
(c33) and removing the photoresist.
6. The method of claim 1, wherein step (d) comprises:
(d1) filling the P-type groove and the N-type groove with polycrystalline silicon;
(d2) after the GeOI substrate is subjected to planarization processing, a polycrystalline silicon layer is formed on the GeOI substrate;
(d3) photoetching the polycrystalline silicon layer, and respectively injecting P-type impurities and N-type impurities into the positions of the P-type groove and the N-type groove by adopting a method of ion injection with glue to form a second P-type active region and a second N-type active region and simultaneously form a P-type contact region and an N-type contact region;
(d4) removing the photoresist;
(d5) and removing the polysilicon layer outside the P-type contact region and the N-type contact region by wet etching.
7. The method of claim 1, wherein step (e) comprises:
(e1) generating silicon dioxide on the GeOI substrate;
(e2) activating impurities in the active region by using an annealing process;
(e3) photoetching lead holes in the P-type contact area and the N-type contact area to form leads;
(e4) passivating and photoetching PAD to form the Ge-based plasma pin diode.
8. A Ge-based solid state plasma PiN diode for use in the fabrication of a solid state plasma antenna, the Ge-based solid state plasma PiN diode being fabricated using the method of any of claims 1-7.
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