CN112993051B - Preparation method of heterogeneous deep-groove Pin array, device and silicon-based reconfigurable stealth antenna - Google Patents

Preparation method of heterogeneous deep-groove Pin array, device and silicon-based reconfigurable stealth antenna Download PDF

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CN112993051B
CN112993051B CN202110176558.5A CN202110176558A CN112993051B CN 112993051 B CN112993051 B CN 112993051B CN 202110176558 A CN202110176558 A CN 202110176558A CN 112993051 B CN112993051 B CN 112993051B
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deep groove
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pin array
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CN112993051A (en
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苏汉
税冬东
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Engineering University of Chinese Peoples Armed Police Force
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/868—PIN diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00—Details of, or arrangements associated with, antennas
    • H01Q1/36—Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q23/00—Antennas with active circuits or circuit elements integrated within them or attached to them
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6661—High-frequency adaptations for passive devices
    • H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device

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Abstract

The invention relates to a preparation method and a device of a heterogeneous deep groove Pin array and a silicon-based reconfigurable stealth antenna, wherein the preparation method comprises the following steps: selecting a GeOI substrate, and doping the GeOI substrate to form a top GeSn region; etching the GeSn area on the top layer of the substrate to form an active area deep groove; flattening the periphery of the active region and forming a P region and an N region by in-situ doping; and forming a GeSn alloy lead on the substrate and connecting the GeSn alloy lead to finish the preparation of the heterogeneous deep groove PiN array suitable for the silicon-based reconfigurable stealth antenna. The heterogeneous deep groove Pin array is prepared by dynamically controlling the content of Sn components in the top layer Ge and introducing GeSn alloy leads.

Description

Preparation method of heterogeneous deep-groove Pin array, device and silicon-based reconfigurable stealth antenna
Technical Field
The invention relates to the technical field of semiconductor materials and device manufacturing, in particular to a preparation method of a heterogeneous deep groove PiN array, a device and a silicon-based reconfigurable stealth antenna.
Background
With the rapid development of communication technology, the requirements of high-performance communication equipment on the integrability, the reconfiguration performance and the stealth performance of an antenna are also higher and higher. However, most of the traditional antenna systems are made of metal, the antenna is switched to the working frequency band of the antenna by controlling the on-off of a pre-built discrete switching device, and the dynamic reconfiguration of the antenna performance is difficult to realize; moreover, the traditional antenna system has a large radar scattering sectional area due to the existence of the metal radiating unit, so that the stealth performance of the antenna is greatly reduced. The silicon-based antenna has the advantages of high integration level, compatibility with the traditional silicon technology and the like, can greatly improve the reconfiguration performance and stealth performance of the antenna, and has wide application prospect in the fields of helicopters and satellite communication. The silicon-based solid-state plasma Pin diode completely replaces metal to be used as a basic radiation unit of the antenna, and the formation and disappearance of the solid-state plasma area are controlled by externally applied bias voltage so that the electrical length of the antenna is dynamically changed, thereby realizing the reconfiguration.
Therefore, how to fabricate a high performance PiN diode array for use in a silicon-based reconfigurable stealth antenna becomes particularly important.
Disclosure of Invention
In order to solve the technical defects and shortcomings in the prior art, the invention provides a preparation method and a device of a heterogeneous deep groove PiN array and a silicon-based reconfigurable stealth antenna.
The technical scheme of the invention is as follows:
a preparation method of a heterogeneous deep groove PiN array comprises the following steps:
(a) Selecting a GeOI substrate, and doping the GeOI substrate to form a top GeSn region;
(b) Etching the GeSn area on the top layer of the substrate to form an active area deep groove;
(c) Flattening the periphery of the active region and forming a P region and an N region by in-situ doping;
(d) And forming a GeSn alloy lead on the substrate and connecting the GeSn alloy lead to finish the preparation of the heterogeneous deep groove PiN array.
Preferably, doping in the GeOI substrate in step (a) forms a top GeSn region, comprising the steps of:
(a1) Photoetching the GeOI substrate;
(a2) Carrying out Sn component doping on the GeOI substrate to form a top GeSn region, and dynamically controlling the content of Sn components in the top Ge to realize the maximum injection ratio of carriers;
(a3) The photoresist is removed.
Preferably, etching the GeSn region on the top layer of the substrate in the step (b) to form an active region deep trench includes the following steps:
(b1) Depositing a layer of silicon nitride on the surface of the GeSn region by using CVD;
(b2) Forming an active region pattern on the silicon nitride layer by using a photolithography process;
(b3) And etching the protective layer and the top GeSn area at the appointed position of the active area pattern by using a dry etching process so as to form an active area deep groove.
Preferably, in the step (c), the periphery of the active region is planarized and the P region and the N region are formed by in-situ doping, including the following steps:
(c1) Flattening the periphery of the active region;
(c2) Forming a P region by utilizing in-situ doping deposition P-type GaAs;
(c3) N-type GaAs is deposited by in-situ doping to form an N region.
Preferably, the planarization process of the periphery of the active area in the step (c 1) includes the following steps:
(c11) Oxidizing the peripheral side walls of the active region to form a layer of silicon dioxide on the peripheral side walls of the active region;
(c12) And etching the oxidation layer on the peripheral side wall of the active region by utilizing a wet etching process to finish planarization of the peripheral side wall of the active region.
Preferably, the P region is formed in step (c 2) by in situ doping deposition of P-type GaAs, comprising the steps of:
(c21) Depositing a layer of silicon dioxide on the surface of the substrate by CVD;
(c22) Forming a P region pattern on the silicon dioxide layer by utilizing a photoetching process;
(c23) Removing the silicon dioxide layer on the P region by utilizing a wet etching process;
(c24) Forming a P region by utilizing in-situ doping deposition P-type GaAs;
(c25) Firstly, flattening the surface of the P region by using a dry etching process, and then removing the silicon dioxide layer on the surface of the substrate by using a wet etching process.
Preferably, the N region is formed in step (c 3) by in situ doping deposition of N-type GaAs, comprising the steps of:
(c31) Depositing a layer of silicon dioxide on the surface of the substrate by CVD;
(c32) Forming an N region pattern on the silicon dioxide layer by utilizing a photoetching process;
(c33) Removing the silicon dioxide layer on the N region by utilizing a wet etching process;
(c34) Forming an N region by utilizing in-situ doping deposition N-type GaAs;
(c35) Firstly, flattening the surface of the N region by using a dry etching process, and then removing the silicon dioxide layer on the surface of the substrate by using a wet etching process.
Preferably, step (d) comprises the steps of:
(d1) Generating silicon dioxide on the substrate;
(d2) Activating impurities in the P region and the N region by using an annealing process;
(d3) Photoetching lead holes in the P area and the N area and forming a GeSn alloy lead by adopting the RPCVD technology;
(d4) And passivating, photoetching PAD and connecting to form the heterogeneous deep groove PiN array.
A heterogeneous deep groove PiN array is prepared by the method.
A silicon-based reconfigurable stealth antenna comprises the heterogeneous deep groove PiN array.
Compared with the prior art, the invention discloses a preparation method and a device of a heterogeneous deep groove PiN array and a silicon-based reconfigurable stealth antenna, and has the following advantages:
the heterogeneous deep groove PiN array is used for forming a silicon-based reconfigurable stealth antenna, and dynamic reconfiguration of the antenna performance is realized by dynamically controlling the on and off of the PiN diode array unit;
the heterogeneous deep groove PiN array dynamically controls the content of Sn component in the top layer Ge, so that the adjustment of the GeSn forbidden band width of the intrinsic region of the diode is realized, and the concentration and the distribution uniformity of solid plasma of the PiN diode can be effectively improved due to the characteristics of large injection ratio and high mobility;
the heterogeneous deep groove Pin array is formed into a GeSn alloy lead wire by adopting the RPCVD technology, so that a metal electrode in a traditional PiN diode is replaced, and the integration level and stealth performance of a silicon-based antenna system are greatly improved;
the P area and the N area of the heterogeneous deep groove PiN array adopt a polysilicon mosaic process based on etching deep groove etching, the process can provide abrupt junction Pi and Ni junction, and can effectively improve junction depth, so that the concentration and the distribution of solid plasma are improved;
the heterogeneous deep-groove PiN array adopts a deep-groove dielectric isolation process, so that the breakdown voltage of the diode is effectively improved, the influence of leakage current on the performance of the device is suppressed, the practicability is high, and the method is worthy of popularization.
Drawings
Fig. 1 is a schematic structural diagram of a silicon-based reconfigurable stealth antenna according to an embodiment of the present invention.
Fig. 2 is a flowchart of a preparation method of a heterogeneous deep groove PiN array according to an embodiment of the present invention.
Fig. 3 a-3 t are schematic diagrams illustrating a method for manufacturing a heterogeneous deep groove PiN array in a silicon-based reconfigurable stealth antenna according to an embodiment of the present invention.
Fig. 4 is a schematic diagram of a device structure of a hetero GeSn-based silicon-based deep trench protection PiN diode according to an embodiment of the present invention.
Fig. 5 is a schematic structural diagram of a heterogeneous deep groove PiN array according to an embodiment of the present invention.
Fig. 6 is a schematic diagram of a silicon-based reconfigurable stealth antenna structure based on a heterogeneous deep groove PiN array according to an embodiment of the present invention.
Description of the embodiments
In order that the above objects, features and advantages of the present invention will be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in appended fig. 1 to 6, but it is to be understood that the invention is not limited to specific embodiments.
The invention provides a preparation method of a heterogeneous deep groove PiN array in a silicon-based reconfigurable stealth antenna, wherein the diode can be a GeSn-based heterogeneous transverse PiN diode formed by doping Sn components On the basis of Germanium (Germanium-On-Insulator, geOI for short) On an insulating substrate, and when DC bias is applied, DC current can form solid plasma composed of free carriers (electrons and holes) On the surface of the solid plasma, and the plasma has a metal-like characteristic, namely has a reflection effect On electromagnetic waves, and the reflection characteristic is closely related to the microwave transmission characteristic, concentration and distribution of surface plasma.
The silicon-based high-integration silicon-based reconfigurable stealth antenna can be formed by a heterogeneous deep groove Pin array, and the array is formed into dynamic solid plasma stripes by utilizing selective conduction of diodes in an external control array, has the functions of an antenna and transmitting and receiving specific electromagnetic waves, and can change the shapes and distribution of the solid plasma stripes by selective conduction of the diodes in the array, so that the antenna is reconfigured, and has important application prospects in the aspects of helicopter and radar technology.
Hereinafter, the process flow of the heterogeneous deep groove PiN array prepared by the present invention will be described in further detail. In the drawings, thicknesses of layers and regions are enlarged or reduced for convenience of description, and the illustrated sizes do not represent actual dimensions.
Examples
Referring to fig. 1, fig. 1 is a schematic diagram of a silicon-based reconfigurable stealth antenna according to an embodiment of the present invention. The silicon-based reconfigurable stealth antenna comprises: a semiconductor substrate 1, a first antenna arm 2, a second antenna arm 3, a first direct current bias line 4, a second direct current bias line 5, a third direct current bias line 6, a fourth direct current bias line 7, a fifth direct current bias line 8, a sixth direct current bias line 9, a seventh direct current bias line 10, an eighth direct current bias line 11, and a coaxial feeder 12; the antenna arm is composed of a plurality of heterogeneous deep groove Pin diode array units.
The silicon-based reconfigurable stealth antenna comprises a first antenna arm and a second antenna arm, wherein the antenna arm comprises a plurality of heterogeneous deep-groove PiN array units, and the reconfiguration of the antenna performance is realized by controlling the on and off of different PiN diode array units; the number of diode array units in other similar systems can be increased or decreased as required by the antenna performance.
The first antenna arm, the second antenna arm, the first direct current offset line, the second direct current offset line, the third direct current offset line, the fourth direct current offset line, the fifth direct current offset line, the sixth direct current offset line, the seventh direct current offset line, the eighth direct current offset line and the coaxial feeder are all manufactured on the semiconductor substrate by adopting a semiconductor process, and the diode antenna arms 2 and 3 are connected through the coaxial feeder 12.
The first antenna arm 2 includes heterogeneous deep groove PiN array units L1, L3 and L5 connected in series, and the second antenna arm 3 includes heterogeneous deep groove PiN array units L2, L4 and L6 connected in series. Different heterogeneous deep groove PiN array units are connected to a direct current bias power supply through direct current bias lines 4, 5, 6, 7, 8, 9, 10 and 11.
Referring to fig. 2, fig. 2 is a flowchart of a method for preparing a heterogeneous deep trench PiN array according to an embodiment of the present invention, where the method for preparing a heterogeneous deep trench PiN diode array includes the steps of:
(a) Selecting a GeOI substrate, and doping the GeOI substrate to form a top GeSn region;
(b) Etching the GeSn area on the top layer of the substrate to form an active area deep groove;
(c) Flattening the periphery of the active region and forming a P region and an N region by in-situ doping;
(d) And forming a GeSn alloy lead on the substrate and connecting the GeSn alloy lead to finish the preparation of the heterogeneous deep groove PiN array suitable for the silicon-based reconfigurable stealth antenna.
The reason why the top GeSn region is doped in the GeOI substrate for step (a) is that the radiation unit diode of the silicon-based solid state plasma antenna needs to have a high concentration of solid state plasma because of its good microwave characteristics. The heterogeneous GeSn-based solid-state plasma PiN diode obtains GeSn alloy with narrower forbidden band width than silicon material by doping Sn component in the top-layer Ge and dynamically controlling the content of the Sn component in the top-layer Ge, thereby further improving the injection ratio of carriers from a source region to an intrinsic region and greatly improving the concentration and distribution uniformity of solid-state plasma in the diode. In addition, the introduction of the buried oxide layer and the deep trench isolation technology further improves the carrier confinement capability, so Sn is doped in the GeOI substrate to form a top GeSn region.
For step (a), doping the GeOI substrate to form a top GeSn region may include the steps of:
(a1) Photoetching the GeOI substrate;
(a2) Carrying out Sn component doping on the GeOI substrate to form a top GeSn region, and dynamically controlling the content of Sn components in the top Ge to realize the maximum injection ratio of carriers;
(a3) The photoresist is removed.
In addition, for the step (b), etching the GeSn region on the top layer of the substrate to form an active region deep trench may include the steps of:
(b1) Depositing a layer of silicon nitride on the surface of the GeSn region by using CVD;
the purpose of depositing the silicon nitride layer is to: after the active region is photoetched, silicon nitride can be used as a mask of the top GeSn layer, so that the GeSn material in the deep groove is etched.
(b2) Forming an active region pattern on the silicon nitride layer by using a photolithography process;
(b3) And etching the protective layer and the top GeSn area at the appointed position of the active area pattern by using a dry etching process so as to form an active area deep groove.
Furthermore, for the step (c), the step of planarizing the periphery of the active region and forming the P region and the N region by in-situ doping may specifically include the following steps:
(c1) Flattening the periphery of the active region;
(c2) Forming a P region by utilizing in-situ doping deposition P-type GaAs;
(c3) Forming an N region by utilizing in-situ doping deposition N-type GaAs;
for step (c 1), planarizing the active region deep trench may specifically include the steps of:
(c11) Oxidizing the peripheral side walls of the active region to form a layer of silicon dioxide on the peripheral side walls of the active region;
(c12) And etching the oxidation layer on the peripheral side wall of the active region by utilizing a wet etching process to finish planarization of the peripheral side wall of the active region.
Furthermore, for step (c 2), the P-region is formed by in-situ doping deposition of P-type GaAs, which may specifically include the steps of:
(c21) Depositing a layer of silicon dioxide on the surface of the substrate by CVD;
(c22) Forming a P region pattern on the silicon dioxide layer by utilizing a photoetching process;
(c23) Removing the silicon dioxide layer on the P region by utilizing a wet etching process;
(c24) Forming a P region by utilizing in-situ doping deposition P-type GaAs;
(c25) Firstly, flattening the surface of the P region by using a dry etching process, and then removing the silicon dioxide layer on the surface of the substrate by using a wet etching process.
For step (c 3), N-type GaAs is deposited by in-situ doping to form an N-region, which may specifically include the steps of:
(c31) Depositing a layer of silicon dioxide on the surface of the substrate by CVD;
(c32) Forming an N region pattern on the silicon dioxide layer by utilizing a photoetching process;
(c33) Removing the silicon dioxide layer on the N region by utilizing a wet etching process;
(c34) Forming an N region by utilizing in-situ doping deposition N-type GaAs;
(c35) Firstly, flattening the surface of the N region by using a dry etching process, and then removing the silicon dioxide layer on the surface of the substrate by using a wet etching process.
For the step (d), forming a GeSn alloy lead on the substrate and connecting to complete the preparation of the heterogeneous deep groove PiN array suitable for the silicon-based reconfigurable stealth antenna, the method specifically comprises the following steps:
(d1) Generating silicon dioxide on the substrate;
(d2) Activating impurities in the P region and the N region by using an annealing process;
(d3) Photoetching lead holes in the P area and the N area and forming a GeSn alloy lead by adopting the RPCVD technology;
(d4) And forming a GeSn alloy lead on the substrate and connecting to complete the heterogeneous deep groove Pin array.
The preparation method of the heterogeneous deep groove Pin array provided by the invention has the following advantages:
(1) The heterogeneous deep groove PiN array is used for forming a silicon-based reconfigurable stealth antenna, and dynamic reconfiguration of antenna performance is realized by dynamically controlling on and off of the PiN diode array unit.
(2) The heterogeneous deep groove Pin array dynamically controls the content of Sn component in the top layer Ge, thereby realizing the adjustment of the GeSn forbidden band width of the diode intrinsic region. Due to the characteristics of large injection ratio and high mobility, the concentration and the distribution uniformity of the solid plasma of the Pin diode can be effectively improved. Another advantage of forming GaAs-GeSn heterojunctions is that the matching of lattice constants between GaAs and GeSn materials is high, with lattice mismatch ratios of only 0.07%, which is beneficial for forming more ideal heterojunctions.
(3) The heterogeneous deep groove Pin array is formed into the GeSn alloy lead wire by adopting the RPCVD technology, replaces the metal electrode in the traditional PiN diode, and greatly improves the integration level and stealth performance of the silicon-based antenna system.
(4) The P area and the N area of the heterogeneous deep groove PiN array adopt a polysilicon mosaic process based on etching deep groove etching, the process can provide abrupt junction Pi and Ni junction, and can effectively improve junction depth, so that the concentration and the distribution of solid plasma are improved.
(5) The heterogeneous deep-groove Pin array adopts a deep-groove dielectric isolation process, so that the breakdown voltage of the diode is effectively improved, and the influence of leakage current on the performance of the device is inhibited.
Examples
Referring to fig. 3a to 3t, fig. 3a to 3t are schematic diagrams illustrating a method for preparing a heterogeneous deep trench PiN array according to an embodiment of the present invention, based on the first embodiment, a deep trench protection PiN diode array with a solid plasma region length of 90 micrometers is prepared, and the intrinsic region length may be between 50 micrometers and 150 micrometers, which specifically includes the following steps:
s10, selecting the GeOI substrate.
Referring to fig. 3a, the crystal orientation of the GeOI substrate 101 may be (100) or (110) or (111), without limitation. The GeOI substrate 101 may be n-type or p-type in doping concentration of, for example, 0.5X104 to 1X 1015cm-3 and the top layer Ge has a thickness of, for example, 30 to 120. Mu.m.
S20, doping the GeOI substrate to form a top GeSn region.
Referring to fig. 3b, the specific implementation may be: and photoetching the GeOI substrate, carrying out Sn component doping on the GeOI substrate to form a top GeSn region 201 on the substrate, wherein the Sn component in the GeSn region is 1-30%, and removing the photoresist.
S30, depositing a layer of silicon nitride on the surface of the top GeSn region.
Referring to fig. 3c, a silicon nitride layer 301 with a thickness of 500-600 nm is deposited on a substrate 101 by chemical vapor deposition (Chemical vapor deposition, CVD for short).
S40, etching the GeSn area on the top layer of the substrate to form an active area deep groove.
Referring to fig. 3d, an active region pattern is formed on the silicon nitride layer by using a photolithography process, and a protection layer and a top GeSn region are etched at a designated position of the active region pattern by using a dry etching process to form an active region deep trench 401.
S50, flattening the periphery of the active area.
Referring to fig. 3e and 3f, the specific implementation may be: oxidizing the peripheral side wall of the active region to form an oxide layer 501 with the thickness of 5-60 nm on the peripheral side wall of the active region, and etching the peripheral side wall oxide layer of the active region by utilizing a wet etching process to finish planarization of the peripheral side wall of the active region.
S60, depositing a layer of silicon dioxide on the surface of the substrate.
Referring to fig. 3g, a layer of silicon dioxide 601 is deposited on the substrate using CVD.
S70, photoetching the silicon dioxide layer.
Referring to fig. 3h, a P-region pattern is formed on the silicon dioxide layer by using a photolithography process, and the silicon dioxide layer on the P-region pattern is removed by using a wet etching process.
S80, forming a P region.
Referring to fig. 3i, the specific implementation may be: and depositing P-type GaAs on the P region pattern on the surface of the substrate by using an in-situ doping method to form a P region 801, and controlling the doping concentration of the P region by controlling the gas flow.
S90, flattening the surface of the substrate.
Referring to fig. 3j, the specific implementation may be: firstly, flattening the surface of the P region by using a dry etching process, and then removing the silicon dioxide layer on the surface of the substrate by using a wet etching process.
S100, depositing a layer of silicon dioxide on the surface of the substrate.
Referring to fig. 3k, the specific implementation may be: a silicon dioxide layer 1001 is deposited on the substrate surface using a CVD method.
S110, photoetching the silicon dioxide layer.
Referring to fig. 3l, forming an N-region pattern on the silicon dioxide layer by using a photolithography process; and removing the silicon dioxide layer on the N region by utilizing a wet etching process.
S120, forming an N region.
Referring to fig. 3m, N-type GaAs is deposited on the N-region pattern on the substrate surface to form an N-region 1201 by in-situ doping, and the doping concentration of the N-region is controlled by controlling the gas flow.
S130, flattening the surface of the substrate.
Referring to fig. 3N, the surface of the N region is flattened by a dry etching process, and then the silicon dioxide layer on the surface of the substrate is removed by a wet etching process.
S140, flattening the surface of the substrate.
Referring to fig. 3o, the silicon nitride layer and the polycrystalline GaAs on the surface of the substrate may be removed by a CMP method, thereby planarizing the surface of the substrate.
S150, depositing silicon dioxide.
Referring to fig. 3p, a layer of silicon dioxide 1501 is deposited on the substrate surface by CVD and the active area trenches are filled.
S160, activating impurities.
Annealing is performed at 950-1150 ℃ for 0.5-2 minutes to activate the ion implanted impurities and drive the impurities in the active region.
S170, photoetching a lead hole in a P, N contact area.
Referring to fig. 3q, a wire hole 1701 is etched in the silicon dioxide layer.
S180, forming a GeSn alloy lead.
Referring to fig. 3r, a GeSn alloy may be formed in the lead hole by using RPCVD technique, and the alloy on the surface may be etched away; and forming a GeSn alloy 1801 on the surface of the substrate by adopting an RPCVD technology to form a lead, wherein the Sn component in the GeSn alloy is 1-30 percent.
S190, passivation treatment and photoetching PAD.
Referring to fig. 3s, a passivation layer 1901 may be formed by depositing silicon nitride, and PAD is etched. Finally, the GaAs-GeSn-GaAs heterogeneous deep groove PiN diode is formed and is used as a material for preparing the high-integration solid-state plasma antenna.
S200, forming a diode array.
Referring to fig. 3t, the heterogeneous deep trench PiN array is formed by sequentially connecting the deep trench protection PiN diodes end to end, so as to form a silicon-based highly integrated reconfigurable basic unit.
Examples
Referring to fig. 4, fig. 4 is a schematic diagram of a device structure of a GaAs-GeSn-GaAs heterogeneous deep trench PiN diode according to an embodiment of the present invention. The silicon-based deep groove protection Pin diode is manufactured by adopting the manufacturing method shown in the figure 2. Specifically, the hetero GeSn-based silicon-based deep trench protection PiN diode is formed on a GeOI substrate 301, and the P-region 303, the N-region 304, and the intrinsic region laterally between the P-region 303 and the N-region 304 of the diode are all located within the top GeSn region 302 of the GeOI substrate.
Referring to fig. 5, fig. 5 is a schematic structural diagram of a heterogeneous deep groove PiN array according to an embodiment of the invention. The heterogeneous deep groove PiN array is formed by sequentially connecting heterogeneous deep groove PiN diodes of a basic radiation unit of the silicon-based solid-state plasma antenna end to end, and a P region and an N region between adjacent diodes are connected with each other to form mutual series connection between the diodes, so that the heterogeneous deep groove PiN array in the silicon-based high-integration silicon-based reconfigurable stealth antenna is finally formed.
Referring to fig. 6, fig. 6 is a schematic diagram of a silicon-based reconfigurable stealth antenna structure based on a heterogeneous deep groove PiN array according to an embodiment of the present invention. The silicon-based reconfigurable stealth antenna comprises: a semiconductor substrate 1, a first antenna arm 2, a second antenna arm 3, a first direct current bias line 4, a second direct current bias line 5, a third direct current bias line 6, a fourth direct current bias line 7, a fifth direct current bias line 8, a sixth direct current bias line 9, a seventh direct current bias line 10, an eighth direct current bias line 11, and a coaxial feeder 12; the antenna arm is composed of a plurality of heterogeneous deep groove Pin diode array units. The silicon-based reconfigurable stealth antenna comprises a first antenna arm and a second antenna arm, wherein the antenna arm comprises a plurality of heterogeneous deep groove PiN array units, and the reconfiguration of the antenna performance is realized by controlling the on and off of different PiN diode array units.
In summary, the invention discloses a preparation method, a device and a silicon-based reconfigurable stealth antenna of a heterogeneous deep groove PiN array, and compared with the prior art, the invention discloses a preparation method, a device and a silicon-based reconfigurable stealth antenna of a heterogeneous deep groove PiN array, and the dynamic reconfiguration of the antenna performance is realized by dynamically controlling the on and off of a PiN diode array unit; the heterogeneous deep groove PiN array dynamically controls the content of Sn component in the top layer Ge, so that the adjustment of the GeSn forbidden band width of the intrinsic region of the diode is realized, and the concentration and the distribution uniformity of solid plasma of the PiN diode can be effectively improved due to the characteristics of large injection ratio and high mobility; another advantage of forming GaAs-GeSn heterojunctions is that the matching of lattice constants between GaAs and GeSn materials is high, with lattice mismatch ratios of only 0.07%, which is beneficial for forming more ideal heterojunctions. The heterogeneous deep groove Pin array is formed into a GeSn alloy lead wire by adopting the RPCVD technology, so that a metal electrode in a traditional PiN diode is replaced, and the integration level and stealth performance of a silicon-based antenna system are greatly improved; the P area and the N area of the heterogeneous deep groove PiN array adopt a polysilicon mosaic process based on etching deep groove etching, the process can provide abrupt junction Pi and Ni junction, and can effectively improve junction depth, so that the concentration and the distribution of solid plasma are improved; the heterogeneous deep-groove PiN array adopts a deep-groove dielectric isolation process, so that the breakdown voltage of the diode is effectively improved, the influence of leakage current on the performance of the device is suppressed, the practicability is high, and the method is worthy of popularization.
The above description of embodiments is only for aiding in the understanding of the method of the present invention and its core ideas; meanwhile, as for those skilled in the art, there are variations in the specific embodiments and the application scope according to the idea of the present invention, and in summary, the present disclosure should not be construed as limiting the present invention, and the scope of the present invention should be defined by the appended claims.
The foregoing disclosure is merely illustrative of some embodiments of the invention, but the embodiments are not limited thereto and variations within the scope of the invention will be apparent to those skilled in the art.

Claims (8)

1. The preparation method of the heterogeneous deep groove PiN array is characterized by comprising the following steps of:
(a) Selecting a GeOI substrate, and doping the GeOI substrate to form a top GeSn region, wherein the GeOI substrate comprises the following steps:
(a1) Photoetching the GeOI substrate;
(a2) Carrying out Sn component doping on the GeOI substrate to form a top GeSn region, and dynamically controlling the content of Sn components in the top Ge to realize the maximum injection ratio of carriers;
(a3) Removing the photoresist;
(b) Etching the GeSn area on the top layer of the substrate to form an active area deep groove;
(c) The periphery of the active region is flattened and doped in situ to form a P region and an N region, which comprises the following steps:
(c1) Flattening the periphery of the active region;
(c2) Forming a P region by utilizing in-situ doping deposition P-type GaAs;
(c3) Forming an N region by utilizing in-situ doping deposition N-type GaAs;
(d) And forming a GeSn alloy lead on the substrate and connecting the GeSn alloy lead to finish the preparation of the heterogeneous deep groove PiN array.
2. The method for preparing a heterogeneous deep trench PiN array according to claim 1, wherein the step (b) of etching the GeSn region on the top layer of the substrate to form an active region deep trench comprises the steps of:
(b1) Depositing a layer of silicon nitride on the surface of the GeSn region by using CVD;
(b2) Forming an active region pattern on the silicon nitride layer by using a photolithography process;
(b3) And etching the protective layer and the top GeSn area at the appointed position of the active area pattern by using a dry etching process so as to form an active area deep groove.
3. The method for preparing a heterogeneous deep trench PiN array according to claim 1, wherein the planarization process of the periphery of the active region in the step (c 1) comprises the following steps:
(c11) Oxidizing the peripheral side walls of the active region to form a layer of silicon dioxide on the peripheral side walls of the active region;
(c12) And etching the oxidation layer on the peripheral side wall of the active region by utilizing a wet etching process to finish planarization of the peripheral side wall of the active region.
4. The method for preparing a heterogeneous deep groove PiN array according to claim 1, wherein the P-region is formed by in-situ doping deposition of P-type GaAs in step (c 2), comprising the steps of:
(c21) Depositing a layer of silicon dioxide on the surface of the substrate by CVD;
(c22) Forming a P region pattern on the silicon dioxide layer by utilizing a photoetching process;
(c23) Removing the silicon dioxide layer on the P region by utilizing a wet etching process;
(c24) Forming a P region by utilizing in-situ doping deposition P-type GaAs;
(c25) Firstly, flattening the surface of the P region by using a dry etching process, and then removing the silicon dioxide layer on the surface of the substrate by using a wet etching process.
5. The method for preparing a heterogeneous deep groove PiN array according to claim 1, wherein the N region is formed by in-situ doping deposition of N-type GaAs in step (c 3), comprising the steps of:
(c31) Depositing a layer of silicon dioxide on the surface of the substrate by CVD;
(c32) Forming an N region pattern on the silicon dioxide layer by utilizing a photoetching process;
(c33) Removing the silicon dioxide layer on the N region by utilizing a wet etching process;
(c34) Forming an N region by utilizing in-situ doping deposition N-type GaAs;
(c35) Firstly, flattening the surface of the N region by using a dry etching process, and then removing the silicon dioxide layer on the surface of the substrate by using a wet etching process.
6. The method for preparing a heterogeneous deep groove PiN array according to claim 1, wherein the step (d) comprises the steps of:
(d1) Generating silicon dioxide on the substrate;
(d2) Activating impurities in the P region and the N region by using an annealing process;
(d3) Photoetching lead holes in the P area and the N area and forming a GeSn alloy lead by adopting the RPCVD technology;
(d4) And passivating, photoetching PAD and connecting to form the heterogeneous deep groove PiN array.
7. A heterogeneous deep groove PiN array produced by the method of any one of claims 1-6.
8. A silicon-based reconfigurable stealth antenna, comprising the heterogeneous deep groove PiN array according to claim 7, further comprising a semiconductor substrate (1), a first antenna arm (2), a second antenna arm (3) and a coaxial feeder (12) which are arranged on the semiconductor substrate (1), wherein the first antenna arm (2) and the second antenna arm (3) are positioned on the same straight line, a gap exists between the first antenna arm (2) and the second antenna arm (3) and are electrically connected through the coaxial feeder (12), the first antenna arm (2) and the second antenna arm (3) comprise a plurality of heterogeneous deep groove PiN arrays which are sequentially arranged and are connected in series, and each heterogeneous deep groove PiN array is electrically connected with a direct current bias power supply.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7603016B1 (en) * 2007-04-30 2009-10-13 The United States Of America As Represented By The Secretary Of The Air Force Semiconductor photonic nano communication link apparatus
CN105789347A (en) * 2016-03-02 2016-07-20 西安电子科技大学 GeSn-GeSi material based heterogeneous phototransistor and fabrication method thereof
CN106785336A (en) * 2016-12-20 2017-05-31 西安电子科技大学 Possesses SiO2The preparation method of the frequency reconfigurable holographic antenna of protective layer
CN106847904A (en) * 2016-12-20 2017-06-13 西安科锐盛创新科技有限公司 For the preparation method of the GaAs/Ge/GaAs heterojunction structure SPiN diode strings of sleeve antenna

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7603016B1 (en) * 2007-04-30 2009-10-13 The United States Of America As Represented By The Secretary Of The Air Force Semiconductor photonic nano communication link apparatus
CN105789347A (en) * 2016-03-02 2016-07-20 西安电子科技大学 GeSn-GeSi material based heterogeneous phototransistor and fabrication method thereof
CN106785336A (en) * 2016-12-20 2017-05-31 西安电子科技大学 Possesses SiO2The preparation method of the frequency reconfigurable holographic antenna of protective layer
CN106847904A (en) * 2016-12-20 2017-06-13 西安科锐盛创新科技有限公司 For the preparation method of the GaAs/Ge/GaAs heterojunction structure SPiN diode strings of sleeve antenna

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