CN113299765B - Preparation method of heterogeneous GeSn-based solid-state plasma Pin diode array with mesa structure and device thereof - Google Patents
Preparation method of heterogeneous GeSn-based solid-state plasma Pin diode array with mesa structure and device thereof Download PDFInfo
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- 229910005898 GeSn Inorganic materials 0.000 title claims abstract description 118
- 238000002360 preparation method Methods 0.000 title claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 70
- 238000011065 in-situ storage Methods 0.000 claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 claims abstract description 14
- 239000004065 semiconductor Substances 0.000 claims abstract description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 89
- 238000000034 method Methods 0.000 claims description 88
- 239000000377 silicon dioxide Substances 0.000 claims description 46
- 235000012239 silicon dioxide Nutrition 0.000 claims description 43
- 238000000151 deposition Methods 0.000 claims description 31
- 239000007787 solid Substances 0.000 claims description 29
- 238000005229 chemical vapour deposition Methods 0.000 claims description 25
- 238000001259 photo etching Methods 0.000 claims description 20
- 238000001039 wet etching Methods 0.000 claims description 20
- 229910045601 alloy Inorganic materials 0.000 claims description 18
- 239000000956 alloy Substances 0.000 claims description 18
- 230000005404 monopole Effects 0.000 claims description 17
- 230000002093 peripheral effect Effects 0.000 claims description 16
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 15
- 238000003491 array Methods 0.000 claims description 15
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 14
- 238000001312 dry etching Methods 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 12
- 230000008021 deposition Effects 0.000 claims description 9
- 238000002347 injection Methods 0.000 claims description 8
- 239000007924 injection Substances 0.000 claims description 8
- 239000012535 impurity Substances 0.000 claims description 6
- 238000000206 photolithography Methods 0.000 claims description 6
- 239000000969 carrier Substances 0.000 claims description 5
- 230000003213 activating effect Effects 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 4
- 230000001590 oxidative effect Effects 0.000 claims description 4
- 229920002120 photoresistant polymer Polymers 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 24
- 229910052710 silicon Inorganic materials 0.000 abstract description 24
- 239000010703 silicon Substances 0.000 abstract description 24
- 230000010354 integration Effects 0.000 abstract description 5
- 239000010410 layer Substances 0.000 description 58
- 238000010586 diagram Methods 0.000 description 9
- 125000005842 heteroatom Chemical group 0.000 description 9
- 238000009826 distribution Methods 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 7
- 238000004891 communication Methods 0.000 description 5
- 230000005540 biological transmission Effects 0.000 description 4
- 238000002955 isolation Methods 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/868—PIN diodes
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
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Abstract
The application relates to the technical field of semiconductor device manufacturing, and discloses a preparation method of a heterogeneous GeSn-based solid-state plasma Pin diode array with a mesa structure and a device thereof, wherein the preparation method of the heterogeneous GeSn-based solid-state plasma PiN diode array with the mesa structure comprises the following steps: selecting a semiconductor GeOI substrate, and doping the GeOI substrate to form a top GeSn region; forming an active region of the mesa on the surface of the GeSn region; forming a P region and an N region in an active region of the mesa by in-situ doping; the preparation method and the device of the heterogeneous GeSn-based solid-state plasma PiN diode array with the mesa structure realize dynamic reconfiguration of antenna performance and greatly improve the integration level and stealth performance of a silicon-based antenna system.
Description
Technical Field
The application relates to the technical field of semiconductor device manufacturing, in particular to a preparation method of a heterogeneous GeSn-based solid-state plasma PiN diode array with a mesa structure and a device thereof.
Background
In modern wireless communication systems, antennas are an integral component of all radio systems as interfaces to the external propagation medium of the system. The antenna is used as a device for radiating and receiving electromagnetic waves, so that the switching between the electromagnetic waves and guided waves on a transmission line is realized: when the antenna is used as a transmitting device, the current with a specific frequency on the transmission line is converted into electromagnetic waves in free space; when the antenna is used as a receiving device, external electromagnetic waves are converted into high-frequency currents on the transmission line. With the rapid progress of modern communications and the increasing closeness of communications with other technologies, the antenna functions and system complexity required by people are also increasing. The silicon-based high-integration reconfigurable antenna based on the solid-state plasma PiN diode has the advantages of flexible reconfiguration technology, high integration characteristic, good stealth performance and the like, so that the antenna can be widely applied to the fields of radar communication, helicopters, high signal-to-noise ratio microwave communication antennas and the like.
Therefore, how to manufacture a high-performance solid-state plasma lateral surface PiN diode for application to a silicon-based high-integration reconfigurable antenna becomes important.
Disclosure of Invention
The application provides a preparation method of a heterogeneous GeSn-based solid-state plasma Pin diode array with a mesa structure and a device thereof, which can solve the problems in the prior art.
The application provides a preparation method of a heterogeneous GeSn-based solid-state plasma Pin diode array with a mesa structure, which comprises the following steps:
the method comprises the following steps:
(a) Selecting a semiconductor GeOI substrate, and doping the GeOI substrate to form a top GeSn region;
(b) Forming an active region of the mesa on the surface of the GeSn region;
(c) Forming a P region and an N region in an active region of the mesa by in-situ doping;
(d) And forming a GeSn alloy lead on the substrate and connecting the GeSn alloy lead to form a heterogeneous GeSn-based solid-state plasma Pin diode array with a mesa structure.
The specific method for doping the GeOI substrate to form the top GeSn region in the step (a) comprises the following steps:
(a1) Photoetching the GeOI substrate;
(a2) Carrying out Sn component doping on the GeOI substrate to form a top GeSn region, and dynamically controlling the content of Sn components in the top Ge to realize the maximum injection ratio of carriers;
(a3) The photoresist is removed.
The step (b) forms an active region of the mesa, and the specific method comprises the following steps:
(b1) Depositing a layer of silicon nitride on the surface of the GeSn region by Chemical Vapor Deposition (CVD);
(b2) Forming a mesa active region pattern on the silicon nitride layer by using a photolithography process;
(b3) And etching the protective layer and the top GeSn area at the appointed position of the active area pattern by using a dry etching process so as to form a mesa active area.
The specific method for forming the P region and the N region by in-situ doping in the step (c) comprises the following steps:
(c1) Flattening the periphery of an active area of the table top;
(c2) Forming a P region on the P region graph on the surface of the substrate by utilizing in-situ doping deposition of P-type AlAs;
(c3) Forming an N region on the N region graph on the surface of the substrate by utilizing in-situ doping deposition of N-type AlAs;
the specific method for performing planarization treatment on the periphery of the active region of the mesa in the step (c 1) includes the following steps:
(c11) Oxidizing the peripheral side walls of the mesa active region to form an oxide layer on the peripheral side walls of the mesa active region;
(c12) And etching the oxidation layer on the peripheral side wall of the mesa active region by utilizing a wet etching process to finish planarization of the peripheral side wall of the mesa active region.
The specific method for forming the P region by in-situ doping and depositing the P-type AlAs in the step (c 2) comprises the following steps:
(c21) Depositing a layer of silicon dioxide on the surface of the substrate by Chemical Vapor Deposition (CVD);
(c22) Forming a P region pattern on the silicon dioxide layer by utilizing a photoetching process;
(c23) Removing silicon dioxide on the P region by utilizing a wet etching process;
(c24) Forming a P region by utilizing in-situ doping deposition of P-type AlAs;
(c25) Firstly, flattening the surface of the P region by using a dry etching process, and then removing silicon dioxide on the surface of the substrate by using a wet etching process.
The specific method for forming the N region by in-situ doping and depositing the N-type AlAs in the step (c 3) comprises the following steps:
(c31) Depositing a layer of silicon dioxide on the surface of the substrate by Chemical Vapor Deposition (CVD);
(c32) Forming an N region pattern on the silicon dioxide layer by utilizing a photoetching process;
(c33) Removing silicon dioxide on the N region by utilizing a wet etching process;
(c34) Forming an N region by utilizing in-situ doping and depositing N-type AlAs;
(c35) Firstly, flattening the surface of the N region by using a dry etching process, and then removing silicon dioxide on the surface of the substrate by using a wet etching process.
The specific method for forming the heterogeneous GeSn-based solid-state plasma Pin diode array with the mesa structure in the step (d) comprises the following steps:
(d1) Generating silicon dioxide on the substrate;
(d2) Activating impurities in the P region and the N region by using an annealing process to form a diode;
(d3) Photoetching lead holes in the P area and the N area, and forming a GeSn alloy lead by adopting ion-body chemical vapor deposition (RPCVD);
(d4) Passivating and photoetching PAD;
(d5) The diodes are connected in series with each other to form a heterogeneous GeSn-based solid state plasma PiN diode array having a mesa structure.
The heterogeneous GeSn-based solid-state plasma PiN diode array with the mesa structure is characterized by being manufactured by the manufacturing method.
A silicon-based reconfigurable monopole antenna comprises a semiconductor substrate GeOI, an antenna arm, a first direct current bias line, a second direct current bias line, a third direct current bias line, a fourth direct current bias line and a coaxial feeder; the antenna arm is connected with the coaxial feeder, the antenna arm is composed of a plurality of heterogeneous GeSn-based solid-state plasma PiN diode arrays with mesa structures, the diode arrays are connected to a direct-current bias power supply through a first direct-current bias line, a second direct-current bias line, a third direct-current bias line and a fourth direct-current bias line, the on and off of the different PiN diode arrays are dynamically controlled through the direct-current feeder, and the dynamic reconstruction of the antenna performance is realized.
Compared with the prior art, the application has the beneficial effects that:
(1) The heterogeneous GeSn-based solid-state plasma PiN diode array with the mesa structure is used for forming a silicon-based reconfigurable monopole antenna, and dynamic reconfiguration of antenna performance is realized by dynamically controlling on and off of the PiN diode array.
(2) The heterogeneous GeSn-based solid-state plasma PiN diode array with the mesa structure realizes the adjustment of the GeSn forbidden band width of the diode intrinsic region by dynamically controlling the content of Sn component in the top layer Ge. Due to the characteristics of large injection ratio and high mobility, the concentration and the distribution uniformity of the solid plasma of the Pin diode can be effectively improved.
(3) The heterogeneous GeSn-based solid-state plasma PiN diode array with the mesa structure is formed into the GeSn alloy lead wire by adopting the RPCVD technology, so that the metal electrode in the traditional PiN diode is replaced, and the integration level and stealth performance of the silicon-based antenna system are greatly improved.
(4) The P region and the N region of the heterogeneous GeSn-based solid-state plasma PiN diode array with the mesa structure adopt a polysilicon mosaic process based on etching deep groove etching, and the process can provide abrupt junction Pi and Ni junction, can effectively improve junction depth and improve concentration and distribution of solid-state plasma.
(5) The heterogeneous GeSn-based solid-state plasma PiN diode array with the mesa structure adopts a deep-slot dielectric isolation process, so that the breakdown voltage of the diode is effectively improved, and the influence of leakage current on the performance of the device is suppressed.
Drawings
Fig. 1 is a schematic diagram of a silicon-based reconfigurable monopole antenna based on a hetero GeSn-based solid-state plasma PiN diode array with a mesa structure according to an embodiment of the present application.
Fig. 2 is a flowchart of a method for manufacturing a heterojunction GeSn-based solid-state plasma PiN diode array with a mesa structure according to an embodiment of the application.
Fig. 3 a-3 u are schematic diagrams illustrating a method for manufacturing a hetero-GeSn-based solid-state plasma PiN diode array with a mesa structure according to an embodiment of the application.
Fig. 4 is a schematic diagram of a device structure of a hetero-GeSn-based solid-state plasma PiN diode with a mesa structure according to an embodiment of the present application.
Fig. 5 is a schematic structural diagram of a hetero GeSn-based solid-state plasma PiN diode array with a mesa structure according to an embodiment of the present application.
Reference numerals of fig. 1 illustrate:
1-semiconductor substrate GeOI, 2-antenna arm, 3-first DC offset line, 4-second DC offset line, 5-third DC offset line, 6-fourth DC offset line, 7-coaxial feeder.
Reference numerals of fig. 3 illustrate:
101-GeOI substrate, 201-GeSn region, 401-active region deep groove, 501-oxide layer, 601-silicon dioxide, 801-P region, 1001-silicon dioxide layer, 1201-N region, 1401-polycrystalline AlAs layer, 1501-silicon dioxide layer, 1801-lead hole, 1901-GeSn alloy and 2001-passivation layer.
Reference numerals of fig. 4 illustrate:
301-silicon nitride layer, 302-top GeSn region, 303-P region, 304-N region.
Detailed Description
One embodiment of the present application will be described in detail below with reference to fig. 1-5, but it should be understood that the scope of the present application is not limited by the embodiment.
The application provides a preparation method of a heterogeneous GeSn-based solid-state plasma Pin diode array with a mesa structure, which is suitable for forming a silicon-based reconfigurable monopole antenna. The PiN diode can be a lateral heterogeneous GeSn-based PiN diode formed by doping Sn components based On Germanium (Germanium-On-Insulator, for short, geOI) On an insulating substrate, wherein when a direct current is applied to the diode, a solid plasma composed of free carriers (electrons and holes) is formed On the surface of the diode by direct current, and the plasma has a metal-like characteristic, namely, has a reflection effect On electromagnetic waves, and the reflection characteristic is closely related to the microwave transmission characteristic, concentration and distribution of surface plasma.
The silicon-based reconfigurable monopole antenna can be formed by arranging and combining heterogeneous GeSn-based solid plasma Pin diode arrays with mesa structures, and utilizes diodes in an external control array to be selectively conducted, so that the array forms dynamic solid plasma stripes and has the functions of an antenna, and has the functions of transmitting and receiving specific electromagnetic waves.
Hereinafter, a process flow of the heterogeneous GeSn-based solid-state plasma PiN diode array with a mesa structure prepared by the present application will be described in further detail. In the drawings, thicknesses of layers and regions are enlarged or reduced for convenience of description, and the illustrated sizes do not represent actual dimensions.
Example 1
Referring to fig. 1, fig. 1 is a schematic diagram of a silicon-based reconfigurable monopole antenna according to an embodiment of the application. The silicon-based reconfigurable monopole antenna includes: a semiconductor substrate GeOI1, an antenna arm 2, a first dc bias line 3, a second dc bias line 4, a third dc bias line 5, a fourth dc bias line 6, and a coaxial feed line 7; the antenna arm 2 is composed of a plurality of heterogeneous GeSn-based solid state plasma PiN diode arrays having mesa structures.
The antenna arm comprises a plurality of heterogeneous GeSn-based solid-state plasma PiN diode arrays with mesa structures, and the reconstruction of the antenna performance is realized by controlling the on and off of the different PiN diode arrays; the number of diode arrays in other similar systems may be increased or decreased as required by the antenna performance.
The antenna arm, the direct current offset line and the coaxial feeder are manufactured on the semiconductor substrate by adopting a semiconductor process, and the diode antenna arm 2 is connected with the coaxial feeder 14. Wherein the antenna arm 2 comprises a series connection of heterogeneous GeSn-based solid state plasma Pin diode arrays L1, L2 and L3 with mesa structures, and different heterogeneous GeSn-based solid state plasma Pin diode arrays with mesa structures are connected to a DC bias power supply through DC bias lines 3, 4, 5 and 6.
Referring to fig. 2, fig. 2 is a flowchart of a method for manufacturing a hetero GeSn-based solid state plasma PiN diode with a mesa structure according to an embodiment of the present application, where the method is suitable for manufacturing a silicon-based solid state plasma PiN diode array, and the diode array is mainly used for manufacturing a silicon-based reconfigurable monopole antenna. The method comprises the following steps:
(a) Selecting a GeOI substrate, and doping the GeOI substrate to form a top GeSn region;
(b) Forming an active region of the mesa;
(c) Forming a P region and an N region by in-situ doping;
(d) And forming a GeSn alloy lead on the substrate and connecting the GeSn alloy lead to finish the preparation of the heterogeneous GeSn-based solid-state plasma Pin diode array with the mesa structure in the silicon-based reconfigurable monopole antenna.
The reason why the top GeSn region is doped in the GeOI substrate for step (a) is that the radiation unit diode of the silicon-based solid state plasma antenna needs to have a high concentration of solid state plasma because of its good microwave characteristics. The heterogeneous GeSn-based solid-state plasma PiN diode obtains GeSn alloy with narrower forbidden band width than silicon material by doping Sn component in the top-layer Ge and dynamically controlling the content of the Sn component in the top-layer Ge, thereby further improving the injection ratio of carriers from a source region to an intrinsic region and greatly improving the concentration and distribution uniformity of solid-state plasma in the diode. In addition, the introduction of the buried oxide layer and the deep trench isolation technology further improves the carrier confinement capability, so Sn is doped in the GeOI substrate to form a top GeSn region.
For step (a), doping the GeOI substrate to form a top GeSn region may include the steps of:
(a1) Photoetching the GeOI substrate;
(a2) Carrying out Sn component doping on the GeOI substrate to form a top GeSn region, and dynamically controlling the content of Sn components in the top Ge to realize the maximum injection ratio of carriers;
(a3) The photoresist is removed.
In addition, for step (b), forming the active region of the mesa may include the steps of:
(b1) Depositing a layer of silicon nitride on the surface of the GeSn region by using CVD;
the purpose of depositing the silicon nitride layer is to: after the mesa active region is etched, the GeSn material in the mesa active region may be etched away using silicon nitride as a mask for the top GeSn layer.
(b2) Forming a mesa active region pattern on the silicon nitride layer by using a photolithography process;
(b3) And etching the protective layer and the top layer GeSn at the appointed position of the active region graph by using a dry etching process so as to form a mesa active region.
Furthermore, for the step (c), the P region and the N region are formed by in-situ doping, which may specifically include the following steps:
(c1) Flattening the periphery of an active area of the table top;
(c2) Forming a P region by utilizing in-situ doping deposition of P-type AlAs;
(c3) And forming an N region by utilizing in-situ doping to deposit N-type AlAs.
For the step (c 1), the planarization treatment of the periphery of the active area of the mesa may specifically include the following steps:
(c11) Oxidizing the peripheral side walls of the mesa active region to form an oxide layer on the peripheral side walls of the mesa active region;
(c12) And etching the oxidation layer on the peripheral side wall of the mesa active region by utilizing a wet etching process to finish planarization of the peripheral side wall of the mesa active region.
Furthermore, for step (c 2), the P-region is formed by depositing P-type AlAs by in-situ doping, which may specifically include the following steps:
(c21) Depositing a layer of silicon dioxide on the surface of the substrate by CVD;
(c22) Forming a P region pattern on the silicon dioxide layer by utilizing a photoetching process;
(c23) Removing silicon dioxide on the P region by utilizing a wet etching process;
(c24) Forming a P region by utilizing in-situ doping deposition of P-type AlAs;
(c25) Firstly, flattening the surface of the P region by using a dry etching process, and then removing silicon dioxide on the surface of the substrate by using a wet etching process.
For step (c 3), N regions are formed by in-situ doping deposited N-type AlAs, which may specifically include the steps of:
(c31) Depositing a layer of silicon dioxide on the surface of the substrate by CVD;
(c32) Forming an N region pattern on the silicon dioxide layer by utilizing a photoetching process;
(c33) Removing silicon dioxide on the N region by utilizing a wet etching process;
(c34) Forming an N region by utilizing in-situ doping and depositing N-type AlAs;
(c35) Firstly, flattening the surface of the N region by using a dry etching process, and then removing silicon dioxide on the surface of the substrate by using a wet etching process.
For the step (d), forming a GeSn alloy lead on the substrate and connecting to complete the preparation of the heterogeneous GeSn-based solid-state plasma PiN diode array with a mesa structure, specifically comprising the following steps:
(d1) Generating silicon dioxide on the substrate;
(d2) Activating impurities in the P region and the N region by using an annealing process;
(d3) Photoetching lead holes in the P area and the N area and forming a GeSn alloy lead by adopting the RPCVD (ion-source chemical vapor deposition) technology;
(d4) Passivating and photoetching PAD;
(d5) And connecting the diodes in series to form a heterogeneous GeSn-based solid-state plasma Pin diode array with a mesa structure in the silicon-based reconfigurable monopole antenna.
In the conventional preparation process for manufacturing the P region and the N region of the solid plasma pin diode, an injection process is adopted for forming the P region and the N region, and the method requires large injection dosage and energy, has high requirements on equipment and is not compatible with the existing process; and by adopting a diffusion process, the junction depth is deeper, but the areas of the P region and the N region are larger, the integration level is low, the doping concentration is uneven, the electrical performance of the solid plasma pin diode is affected, and the controllability of the concentration and the distribution of the solid plasma is poor.
The preparation method of the heterogeneous GeSn-based solid-state plasma Pin diode array with the mesa structure provided by the application has the following advantages:
the heterogeneous GeSn-based solid-state plasma PiN diode array with the mesa structure is used for forming a silicon-based reconfigurable monopole antenna, and dynamic reconfiguration of antenna performance is realized by dynamically controlling on and off of the PiN diode array.
The heterogeneous GeSn-based solid-state plasma PiN diode array with the mesa structure realizes the adjustment of the GeSn forbidden band width of the diode intrinsic region by dynamically controlling the content of Sn component in the top layer Ge. Due to the characteristics of large injection ratio and high mobility, the concentration and the distribution uniformity of the solid plasma of the Pin diode can be effectively improved.
The heterogeneous GeSn-based solid-state plasma PiN diode array with the mesa structure is formed into a GeSn alloy lead wire by adopting the RPCVD technology, so that a metal electrode in a traditional PiN diode is replaced, and the integration level and stealth performance of a silicon-based antenna system are greatly improved.
The P region and the N region of the heterogeneous GeSn-based solid-state plasma PiN diode array with the mesa structure adopt a polysilicon mosaic process based on etching deep groove etching, and the process can provide abrupt junction Pi and Ni junction, can effectively improve junction depth and improve concentration and distribution of solid-state plasma.
The heterogeneous GeSn-based solid-state plasma PiN diode array with the mesa structure adopts a deep-slot dielectric isolation process, so that the breakdown voltage of the diode is effectively improved, and the influence of leakage current on the performance of the device is suppressed.
Example two
Referring to fig. 3a to 3u, fig. 3a to 3u are schematic diagrams illustrating a method for preparing a hetero GeSn-based solid state plasma PiN diode array with a mesa structure according to an embodiment of the present application, wherein the method is based on the first embodiment, and the method further includes the following steps for preparing a hetero GeSn-based solid state plasma PiN diode array with a mesa structure having a solid state plasma region length of 150 micrometers, where the intrinsic region length may be between 50 micrometers and 150 micrometers:
s10, selecting the GeOI substrate.
Referring to FIG. 3a, the GeOI substrate 101 has a crystal orientation of 111, and the GeOI substrate 101 has a doping type of n-type and a doping concentration of 1×10 14 cm -3 The thickness of the top layer Ge is for example 100 μm.
S20, doping the GeOI substrate to form a top GeSn region.
Referring to fig. 3b, the specific implementation may be: and photoetching the GeOI substrate, carrying out Sn component doping on the GeOI substrate to form a top GeSn region 201 on the substrate, wherein the Sn component in the GeSn region is 1-30%, and removing the photoresist.
S30, depositing a layer of silicon nitride on the surface of the top GeSn region.
Referring to fig. 3c, a silicon nitride layer 301 is deposited on the top GeSn region 201 by chemical vapor deposition (Chemical vapor deposition, CVD for short).
S40, etching the GeSn area on the top layer of the substrate to form an active area deep groove.
Referring to fig. 3d, an active region pattern is formed on the silicon nitride layer by using a photolithography process, and the protection layer and the top GeSn region are etched at designated positions of the active region pattern by using a dry etching process to form an active region deep trench 401.
S50, flattening the periphery of the active area of the mesa.
Referring to fig. 3e and 3f, the specific implementation may be: oxidizing the peripheral side wall of the mesa active region to form an oxide layer 501 with the thickness of 5-60 nm on the peripheral side wall of the mesa active region, and etching the peripheral side wall oxide layer of the mesa active region by utilizing a wet etching process to finish planarization of the peripheral side wall of the mesa active region.
S60, depositing a layer of silicon dioxide on the surface of the substrate.
Referring to fig. 3g, a layer of silicon dioxide 601 is deposited on the substrate using CVD.
S70, photoetching the silicon dioxide layer.
Referring to fig. 3h, a P-region pattern is formed on the silicon dioxide layer by using a photolithography process, and the silicon dioxide layer on the P-region pattern is removed by using a wet etching process.
S80, forming a P region.
Referring to fig. 3i, the specific implementation may be: and depositing P-type AlAs on the P region pattern on the surface of the substrate by using an in-situ doping method to form a P region 801, and controlling the doping concentration of the P region by controlling the gas flow.
S90, flattening the surface of the substrate.
Referring to fig. 3j, the specific implementation may be: firstly, flattening the surface of the P region by using a dry etching process, and then removing the silicon dioxide layer on the surface of the substrate by using a wet etching process.
S100, depositing a layer of silicon dioxide on the surface of the substrate.
Referring to fig. 3k, the specific implementation may be: a silicon dioxide layer 1001 is deposited on the substrate surface using a CVD method.
S110, photoetching the silicon dioxide layer.
Referring to fig. 3l, forming an N-region pattern on the silicon dioxide layer by using a photolithography process; and removing the silicon dioxide layer on the N region by utilizing a wet etching process.
S120, forming an N region.
Referring to fig. 3m, N-type AlAs is deposited on the N-region pattern on the substrate surface by using an in-situ doping method to form an N-region 1201, and the doping concentration of the N-region is controlled by controlling the gas flow.
S130, flattening the surface of the substrate.
Referring to fig. 3N, the surface of the N region is flattened by a dry etching process, and then the silicon dioxide layer on the surface of the substrate is removed by a wet etching process.
S140, depositing a polycrystalline AlAs layer.
Referring to fig. 3o, a layer 1401 of polycrystalline AlAs may be deposited in the trench by CVD.
S150, forming a silicon dioxide layer on the surface.
Referring to fig. 3p, a silicon dioxide layer 1501 may be deposited on the surface by CVD to a thickness of 500nm.
S160, flattening the surface.
Referring to fig. 3q, CMP (Common Middle Point) method can be used to remove the surface silicon dioxide and silicon nitride layer to planarize the surface.
S170, activating impurities.
Annealing is performed at 950-1150 ℃ for 0.5-2 minutes to activate the ion implanted impurities and drive the impurities in the active region.
S180, photoetching a lead hole.
Referring to fig. 3r, a lead hole 1801 is etched in the silicon dioxide layer.
S190, forming a lead.
Referring to fig. 3s, a GeSn alloy may be formed in the lead hole by using RPCVD technique, and the alloy on the surface may be etched away; and forming a GeSn alloy 1901 on the surface of the substrate by adopting an RPCVD technology to form a lead, wherein the Sn component in the GeSn alloy is 1-30 percent.
S200, passivation treatment and photoetching PAD.
Referring to fig. 3t, passivation layer 2001 may be formed by depositing silicon nitride, and PAD is etched. And finally forming a heterogeneous GeSn-based solid-state plasma PiN diode with a mesa structure, and taking the heterogeneous GeSn-based solid-state plasma PiN diode as a basic unit for preparing the silicon-based high-integration reconfigurable antenna.
S210, forming a diode array.
Referring to fig. 3u, the hetero GeSn-based solid state plasma PiN diode array with the mesa structure is formed by sequentially connecting the hetero GeSn-based solid state plasma PiN diodes with the mesa structure end to end, so as to form a silicon-based reconfigurable monopole antenna.
In the present embodiment, the above-mentioned various process parameters are exemplified, and the modifications made by the conventional means of those skilled in the art are all within the scope of the present application.
Example III
Referring to fig. 4, fig. 4 is a schematic diagram of a device structure of a hetero-GeSn-based solid-state plasma PiN diode with a mesa structure according to an embodiment of the application. The PiN diode is manufactured by adopting the manufacturing method shown in the figure 1. Specifically, the hetero-GeSn-based solid-state plasma PiN diode with mesa structure is formed on a GeOI substrate 301, and the P-region 303, N-region 304, and intrinsic region laterally between the P-region 303 and the N-region 304 of the PiN diode are all located within the top GeSn region 302 of the substrate.
Referring to fig. 5, fig. 5 is a schematic structural diagram of a hetero GeSn-based solid-state plasma PiN diode array with a mesa structure according to an embodiment of the application. The heterogeneous GeSn-based solid-state plasma PiN diode array with the mesa structure is formed by sequentially connecting PiN diodes of a basic radiation unit of the silicon-based reconfigurable monopole antenna end to end, and a P region and an N region between adjacent diodes are connected with each other so as to form mutual series connection between the diodes, so that the heterogeneous GeSn-based solid-state plasma PiN diode array with the mesa structure in the silicon-based reconfigurable monopole antenna is finally formed.
Referring to fig. 1, fig. 1 is a schematic diagram of a silicon-based reconfigurable monopole antenna based on a hetero GeSn-based solid-state plasma PiN diode array with a mesa structure according to an embodiment of the application. The silicon-based reconfigurable monopole antenna includes: a semiconductor substrate GeOI1, an antenna arm 2, a first dc bias line 3, a second dc bias line 4, a third dc bias line 5, a fourth dc bias line 6, and a coaxial feed line 7; the antenna arm is composed of a plurality of heterogeneous GeSn-based solid-state plasma PiN diode arrays with mesa structures, and the reconstruction of the antenna performance is realized by controlling the on and off of the different PiN diode arrays.
In summary, specific examples are applied herein to illustrate the principles and embodiments of the method for preparing a heterostructure GeSn-based solid state plasma PiN diode array with mesa structure according to the present application, and the above examples are only for helping to understand the method and core ideas of the present application; meanwhile, as for those skilled in the art, there are variations in the specific embodiments and the application scope according to the idea of the present application, and in summary, the present disclosure should not be construed as limiting the present application, and the scope of the present application should be defined by the appended claims.
The foregoing disclosure is merely illustrative of some embodiments of the application, but the embodiments are not limited thereto and variations within the scope of the application will be apparent to those skilled in the art.
Claims (7)
1. The preparation method of the heterogeneous GeSn-based solid-state plasma Pin diode array with the mesa structure is characterized by comprising the following steps of:
(a) Selecting a semiconductor GeOI substrate, and doping the GeOI substrate to form a top GeSn region, wherein the Sn component in the GeSn region is 1% -30%;
(a1) Photoetching the GeOI substrate;
(a2) For the GeOI linerThe bottom is doped with Sn component to form a top GeSn region, and the maximum injection ratio of carriers is realized by dynamically controlling the content of Sn component in the top Ge, wherein the doping type of the GeOI substrate is n type, and the doping concentration is 1 multiplied by 10 14 cm -3 The thickness of the top layer Ge is 100 μm;
(a3) Removing the photoresist;
(b) Forming an active region of the mesa on the surface of the GeSn region;
(b1) Depositing a layer of silicon nitride on the surface of the GeSn region by Chemical Vapor Deposition (CVD);
(b2) Forming a mesa active region pattern on the silicon nitride layer by using a photolithography process;
(b3) Etching the silicon nitride and the top GeSn area at the appointed position of the active area pattern by using a dry etching process so as to form a mesa active area;
(c) Forming a P region and an N region in an active region of the mesa by in-situ doping;
the specific method for forming the P region and the N region by in-situ doping in the step (c) comprises the following steps:
(c1) Flattening the periphery of an active area of the table top;
(c2) Forming a P region on the P region graph on the surface of the substrate by utilizing in-situ doping deposition of P-type AlAs;
(c3) Forming an N region on the N region graph on the surface of the substrate by utilizing in-situ doping deposition of N-type AlAs;
(d) And forming a GeSn alloy lead on the substrate and connecting the GeSn alloy lead to form a heterogeneous GeSn-based solid-state plasma Pin diode array with a mesa structure.
2. The method for preparing the heterostructure GeSn-based solid state plasma PiN diode array with a mesa structure of claim 1, wherein the specific method for performing planarization treatment on the periphery of the active region of the mesa in step (c 1) comprises the following steps:
(c11) Oxidizing the peripheral side walls of the mesa active region to form an oxide layer on the peripheral side walls of the mesa active region;
(c12) And etching the oxidation layer on the peripheral side wall of the mesa active region by utilizing a wet etching process to finish planarization of the peripheral side wall of the mesa active region.
3. The method of fabricating a hetero-GeSn-based solid state plasma PiN diode array with a mesa structure of claim 1, wherein the specific method of forming a P-region by in-situ doping deposition of P-type AlAs in step (c 2) comprises the steps of:
(c21) Depositing a layer of silicon dioxide on the surface of the substrate by Chemical Vapor Deposition (CVD);
(c22) Forming a P region pattern on the silicon dioxide layer by utilizing a photoetching process;
(c23) Removing silicon dioxide on the P region by utilizing a wet etching process;
(c24) Forming a P region by utilizing in-situ doping deposition of P-type AlAs;
(c25) Firstly, flattening the surface of the P region by using a dry etching process, and then removing silicon dioxide on the surface of the substrate by using a wet etching process.
4. The method of fabricating a hetero-GeSn-based solid state plasma PiN diode array with a mesa structure of claim 1, wherein the specific method of forming an N-region by in-situ doping deposited N-type AlAs of step (c 3) comprises the steps of:
(c31) Depositing a layer of silicon dioxide on the surface of the substrate by Chemical Vapor Deposition (CVD);
(c32) Forming an N region pattern on the silicon dioxide layer by utilizing a photoetching process;
(c33) Removing silicon dioxide on the N region by utilizing a wet etching process;
(c34) Forming an N region by utilizing in-situ doping and depositing N-type AlAs;
(c35) Firstly, flattening the surface of the N region by using a dry etching process, and then removing silicon dioxide on the surface of the substrate by using a wet etching process.
5. The method of fabricating a heterostructure GeSn-based solid state plasma PiN diode array of claim 1, wherein the specific method of forming a heterostructure GeSn-based solid state plasma PiN diode array of step (d) comprises the steps of:
(d1) Generating silicon dioxide on the substrate;
(d2) Activating impurities in the P region and the N region by using an annealing process to form a diode;
(d3) Photoetching lead holes in the P area and the N area, and forming a GeSn alloy lead by adopting ion-body chemical vapor deposition (RPCVD);
(d4) Passivating and photoetching PAD;
(d5) The diodes are connected in series with each other to form a heterogeneous GeSn-based solid state plasma PiN diode array having a mesa structure.
6. A heterostructure GeSn-based solid state plasma PiN diode array having a mesa structure, fabricated using the method of any one of claims 1-5.
7. The reconfigurable monopole antenna is characterized by comprising a semiconductor substrate GeOI, an antenna arm, a first direct current bias line, a second direct current bias line, a third direct current bias line, a fourth direct current bias line and a coaxial feeder; the antenna arm is connected with the coaxial feeder, the antenna arm is composed of a plurality of heterogeneous GeSn-based solid-state plasma PiN diode arrays with mesa structures, the diode arrays are connected to a direct-current bias power supply through a first direct-current bias line, a second direct-current bias line, a third direct-current bias line and a fourth direct-current bias line, the on and off of the different PiN diode arrays are dynamically controlled through the direct-current feeder, and the dynamic reconfiguration of the antenna performance is achieved.
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