CN112992676B - Preparation method of AlAs-GeSn-AlAs structure high injection ratio heterogeneous Pin diode and device thereof - Google Patents
Preparation method of AlAs-GeSn-AlAs structure high injection ratio heterogeneous Pin diode and device thereof Download PDFInfo
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
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Abstract
The application relates to the technical field of semiconductor materials and device manufacturing, and discloses a preparation method of a high injection ratio heterogeneous Pin diode with an AlAs-GeSn-AlAs structure and a device thereof, wherein the preparation method comprises the following steps: selecting a GeOI substrate with a certain crystal orientation, and doping the GeOI substrate to form a top GeSn region; a deep groove isolation region is arranged in the GeSn region on the top layer of the substrate; etching the GeSn region to form a P-type groove and an N-type groove; ion implantation is adopted in the P-type groove and the N-type groove to form a P-type active region and an N-type active region; the polycrystalline AlAs is used for filling the P-type groove and the N-type groove, and a GeSn alloy lead is formed on the substrate.
Description
Technical Field
The application relates to the technical field of semiconductor materials and device manufacturing, in particular to a preparation method of a high injection ratio heterogeneous Pin diode with an AlAs-GeSn-AlAs structure and a device thereof.
Background
The solid plasma device transverse PiN diode is used as a basic radiation unit of the silicon-based high-integration reconfigurable antenna, and the plasma concentration and distribution in the intrinsic region directly determine the radiation performance of the antenna. The solid state plasma concentration is also critical to the effect of the diode fabrication process on the carrier mobility within the intrinsic region, in addition to being affected by diode size, carrier transport mechanism, and microwave characteristics. When a direct current bias is applied to the solid plasma Pin diode, direct current can form solid plasma consisting of free carriers (electrons and holes) on the surface of the solid plasma PiN diode, and the plasma has a metalloid characteristic, namely, has reflection and coupling effects on electromagnetic waves, and the reflection characteristic is closely related to the microwave transmission characteristic, concentration and distribution uniformity of the surface solid plasma.
The silicon-based solid-state plasma reconfigurable antenna is composed of Pin diodes, and the quality of the antenna performance is determined by devices. However, conventional silicon-based solid state plasma reconfigurable antennas have low radiation efficiency, limiting their application in modern communication fields. At present, most of diode preparation processes adopt traditional semiconductor process flows, the process method of the diode is not optimized, mobility performance of carriers is reduced, and forbidden band width of carriers in an intrinsic region is reduced, so that microwave characteristics of solid plasmas in the intrinsic region are reduced, radiation performance of a silicon-based solid plasma reconfigurable antenna is influenced, and application of the silicon-based solid plasma reconfigurable antenna in satellite communication, helicopters and anti-interference fields is limited.
Therefore, it is important to select materials and processes to fabricate a high-injection-ratio heterogeneous PiN diode for the silicon-based high-integration reconfigurable antenna.
Disclosure of Invention
The application provides a preparation method of a heterogeneous Pin diode with a high injection ratio of an AlAs-GeSn-AlAs structure and a device thereof, which can improve the mobility performance of carriers and greatly improve the microwave characteristics of solid plasmas in an intrinsic region, thereby greatly improving the radiation efficiency of a silicon-based solid plasma reconfigurable antenna.
The application provides a preparation method of a high injection ratio heterogeneous Pin diode with an AlAs-GeSn-AlAs structure, which comprises the following steps:
(a) Selecting a GeOI substrate with a certain crystal orientation, and doping the GeOI substrate to form a top GeSn region;
(b) A deep groove isolation region is arranged in the GeSn region on the top layer of the substrate;
(c) Etching the GeSn region to form a P-type groove and an N-type groove, wherein the depth of the P-type groove and the N-type groove is smaller than the thickness of the top GeSn region;
(d) Ion implantation is adopted in the P-type groove and the N-type groove to form a P-type active region and an N-type active region;
(d1) Forming a first P type active region and a first N type active region in the P type groove and the N type groove;
(d2) Forming a second P type active region and a second N type active region in the P type trench and the N type trench, wherein the method specifically comprises the following steps:
(d21) Filling the P-type groove and the N-type groove with polycrystalline AlAs;
(d22) After flattening the substrate, forming a polycrystalline AlAs layer on the surface of the substrate;
(d23) Photoetching the polycrystalline AlAs layer, and respectively injecting P-type impurities and N-type impurities into the positions of the P-type groove and the N-type groove by adopting a method of injecting glued ions to form a second P-type active region and a second N-type active region and simultaneously form a P-type contact region and an N-type contact region;
(d24) Removing the photoresist;
(d25) Removing the polycrystalline AlAs layer outside the P-type contact region and the N-type contact region by wet etching;
(e) And forming a GeSn alloy lead on the substrate to finish the preparation of the high-implantation-ratio heterogeneous Pin diode of the AlAs-GeSn-AlAs structure.
The method for doping the GeOI substrate to form the top GeSn region in the step (a) comprises the following steps:
(a1) Photoetching the GeOI substrate;
(a2) Carrying out Sn component doping on the GeOI substrate to form a top GeSn region, and dynamically controlling the content of Sn components in the top Ge to realize the maximum injection ratio of carriers;
(a3) The photoresist is removed.
The method for arranging the deep groove isolation region in the GeSn region on the top layer of the substrate in the step (b) comprises the following steps:
(b1) Forming a protective layer on the surface of the GeSn region;
the protective layer comprises a silicon dioxide layer and a silicon nitride layer, and the forming of the protective layer comprises the following steps:
(b11) Generating a silicon dioxide layer on the surface of the substrate;
(b12) Generating a silicon nitride layer on the surface of the silicon dioxide layer;
(b2) Forming an isolation region pattern on the protective layer by using a photoetching process;
(b3) Etching the protective layer and the substrate at the appointed position of the isolation region graph by utilizing a dry etching process to form an isolation groove, wherein the depth of the isolation groove is greater than or equal to the thickness of a top GeSn region of the substrate;
(b4) Filling the isolation groove to form the isolation region of the Pin diode;
(b5) The substrate is planarized.
The step (c) includes the steps of:
(c1) Forming P-type grooves and N-type groove patterns on the protective layer by utilizing a photoetching process;
(c2) And etching the protective layer and the GeSn region at the appointed position of the groove by utilizing a dry etching process to form the P-type groove and the N-type groove.
The step (d 1) includes the steps of:
(d11) Oxidizing the P-type groove and the N-type groove to form a silicon dioxide oxide layer on the inner walls of the P-type groove and the N-type groove;
(d12) Etching the oxide layers on the inner walls of the P-type groove and the N-type groove by utilizing a wet etching process to finish planarization of the inner walls of the P-type groove and the N-type groove;
(d13) And performing ion implantation on the P-type groove and the N-type groove to form a first P-type active region and a first N-type active region, wherein the first P-type active region is a region with a depth of less than 1 micron from the side wall and the bottom of the P-type groove along the ion diffusion direction, and the first N-type active region is a region with a depth of less than 1 micron from the side wall and the bottom of the N-type groove along the ion diffusion direction.
The ion implantation process in the step (d 13) includes:
(d131) Photoetching the P-type groove and the N-type groove;
(d132) Injecting P-type impurities and N-type impurities into the P-type groove and the N-type groove respectively by adopting a method of injecting glued ions so as to form a first P-type active region and a first N-type active region;
(d133) The photoresist is removed.
The step (e) includes:
(e1) Generating silicon dioxide on the substrate;
(e2) Activating impurities in the active region using an annealing process;
(e3) Photoetching a lead hole in the P-type contact area and the N-type contact area;
(e4) Forming a GeSn alloy lead wire in the lead wire hole by adopting the RPCVD technology;
(e5) And passivating and photoetching PAD to form the high-implantation-ratio heterogeneous Pin diode of the AlAs-GeSn-AlAs structure.
The high injection ratio heterogeneous Pin diode with the AlAs-GeSn-AlAs structure is prepared by adopting the preparation method.
A silicon-based high-integration reconfigurable antenna comprises the high-injection-ratio heterogeneous Pin diode with the AlAs-GeSn-AlAs structure.
Compared with the prior art, the application has the beneficial effects that:
according to the solid-state plasma Pin diode, the carrier mobility performance is improved by introducing the top GeSn region. Meanwhile, the barrier of the AlAs material has a large forbidden bandwidth, and the microwave characteristics of the solid plasma in the intrinsic region can be greatly improved through the AlAs-GeSn-AlAs heterostructure, so that the radiation efficiency of the silicon-based solid plasma reconfigurable antenna is greatly improved.
According to the application, the Pin diode realizes the adjustment of the GeSn forbidden band width of the intrinsic region of the diode by dynamically controlling the content of Sn component in the top layer Ge. Due to the characteristics of large injection ratio and high mobility, the concentration and the distribution uniformity of the solid plasma of the Pin diode can be effectively improved. Another advantage of forming AlAs-GeSn heterojunctions is that the matching of lattice constants between AlAs and GeSn materials is high, with lattice mismatch ratios of only 0.08%, which is advantageous for forming more ideal heterojunctions.
According to the application, the Pin diode is formed into the GeSn alloy lead wire by adopting the RPCVD technology, so that the metal electrode in the traditional PiN diode is replaced, and the integration level and stealth performance of the silicon-based antenna system are greatly improved.
The P region and the N region of the PiN diode adopt a polysilicon mosaic process based on etching deep groove etching, the process can provide abrupt junction Pi and Ni junction, and can effectively improve junction depth, so that the concentration and the distribution of solid plasma are improved.
The Pin diode adopts a deep-groove dielectric isolation process, so that the breakdown voltage of the diode is effectively improved, and the influence of leakage current on the performance of the device is inhibited.
Drawings
Fig. 1 is a flow chart of a method for manufacturing a high-injection-ratio heterogeneous PiN diode with an AlAs-GeSn-AlAs structure according to an embodiment of the present application.
Fig. 2 a-2 t are schematic diagrams of a preparation method of a high injection ratio heterogeneous PiN diode with an AlAs-GeSn-AlAs structure according to an embodiment of the present application.
Fig. 3 is a schematic diagram of a device structure of a high-injection-ratio heterogeneous PiN diode with an AlAs-GeSn-AlAs structure according to an embodiment of the present application.
Reference numerals of fig. 2 illustrate:
101-GeOI substrate, 201-GeSn region, 301-silicon dioxide layer, 302-silicon nitride layer, 401-isolation region, 501-silicon dioxide material, 701-silicon dioxide layer, 702-silicon nitride layer, 801-deep trench, 901-oxide layer, 1001-p+ active region, 1002-active region, 1101-poly AlAs, 1301-poly AlAs layer, 1401-P contact, 1402-N contact, 1601-silicon dioxide layer, 1801-wire hole, 1901-GeSn alloy, 2001-passivation layer.
Reference numerals of fig. 3 illustrate:
301-GeOI substrate, 302-GeSn layer, 303-P region, 304-N region, 305-P type active region, 306-N type active region.
Detailed Description
One embodiment of the present application will be described in detail below with reference to fig. 1-3, but it should be understood that the scope of the present application is not limited by the embodiment.
The application provides a preparation method and a device of a high injection ratio heterogeneous Pin diode suitable for forming an AlAs-GeSn-AlAs structure of a silicon-based high-integration reconfigurable antenna. The high injection ratio heterogeneous Pin diode of the AlAs-GeSn-AlAs structure is based On a Germanium (Germanium-On-Insulator, geOI for short) On an insulating substrate, a transverse heterogeneous GeSn-based Pin diode is formed by doping Sn components, the formation of a solid plasma region in an intrinsic region is controlled by externally applying forward bias voltage, the diode is in a large injection state, and the plasma concentration exceeds 10 18 cm -3 . At this time, the SPiN diode conductanceThe antenna has very high rate and metal-like characteristics, and can replace metal and external electromagnetic waves to be mutually coupled, so that the radiation performance of the antenna is realized.
The silicon-based high-integration solid-state plasma reconfigurable antenna can be formed by arranging and combining heterogeneous Pin diodes with high injection ratio of AlAs-GeSn-AlAs structures according to an array, wherein the optimized PiN diode array unit with high-concentration carriers replaces a metal antenna arm to serve as an antenna basic radiation unit, when forward bias voltage is externally applied, the SPIN diode array units in different areas are conducted, a plasma channel is formed by high-concentration solid-state plasma, and when external electromagnetic waves or high-frequency electric signals are mutually coupled with the carriers, carrier oscillation is caused, so that the radiation and the reception of the electromagnetic waves are realized. The plasma channel is controlled to form different shapes and electric lengths by externally applying bias voltage, so that the reconfigurable performance of the plasma antenna is obtained, and the plasma antenna has important application prospect in aspects of helicopters, communication anti-interference and radar technology.
Hereinafter, the process flow of the high injection ratio heterogeneous PiN diode of the AlAs-GeSn-AlAs structure prepared by the present application will be described in further detail. In the drawings, thicknesses of layers and regions are enlarged or reduced for convenience of description, and the illustrated sizes do not represent actual dimensions.
Example 1
Referring to fig. 1, fig. 1 is a flow chart of a method for manufacturing a high injection ratio heterogeneous PiN diode with an AlAs-GeSn-AlAs structure, which is suitable for manufacturing a GeOI-based lateral solid-state plasma PiN diode, and the high injection ratio heterogeneous PiN diode with the AlAs-GeSn-AlAs structure is mainly used for manufacturing a silicon-based high-integration reconfigurable antenna. The method comprises the following steps:
(a) Selecting a GeOI substrate with a certain crystal orientation, and doping the GeOI substrate to form a top GeSn region;
(b) A deep groove isolation region is arranged in the GeSn region on the top layer of the substrate;
(c) Etching the GeSn region to form a P-type groove and an N-type groove, wherein the depth of the P-type groove and the N-type groove is smaller than the thickness of the top GeSn region;
(d) Ion implantation is adopted in the P-type groove and the N-type groove to form a P-type active region and an N-type active region; and
(e) And forming a GeSn alloy lead on the substrate to finish the preparation of the high-implantation-ratio heterogeneous Pin diode of the AlAs-GeSn-AlAs structure.
The reason why the top GeSn region is doped in the GeOI substrate for step (a) is that the radiation unit diode of the silicon-based solid state plasma antenna needs to have a high concentration of solid state plasma because of its good microwave characteristics. The high injection ratio heterogeneous Pin diode of the AlAs-GeSn-AlAs structure dynamically controls the content of Sn component in the top-layer Ge by doping the Sn component in the top-layer Ge to obtain GeSn alloy with a forbidden band width which is much narrower than that of AlAs material, so that the injection ratio of carriers from a source region to an intrinsic region is further improved, and the concentration and distribution uniformity of solid plasma in the diode are greatly improved. Another advantage of forming AlAs-GeSn heterojunctions is that the matching of lattice constants between AlAs and GeSn materials is high, with lattice mismatch ratios of only 0.08%, which is advantageous for forming more ideal heterojunctions. In addition, the introduction of the buried oxide layer and the deep trench isolation technology further improves the carrier confinement capability, so Sn is doped in the GeOI substrate to form a top GeSn region.
For step (a), doping the GeOI substrate to form a top GeSn region may include the steps of:
(a1) Photoetching the GeOI substrate;
(a2) Carrying out Sn component doping on the GeOI substrate to form a top GeSn region, and dynamically controlling the content of Sn components in the top Ge to realize the maximum injection ratio of carriers;
(a3) The photoresist is removed.
Furthermore, for the step (b), a deep trench isolation region is disposed in the GeSn region on the top layer of the substrate, which specifically includes the following steps:
(b1) Forming a protective layer on the surface of the GeSn region;
specifically, the protective layer includes a silicon dioxide (SiO 2) layer and a silicon nitride (SiN) layer, and the forming of the protective layer includes: generating a silicon dioxide layer on the surface of the GeSn region of the substrate; and generating a silicon nitride layer on the surface of the silicon dioxide layer. The method has the advantages that the stress of the silicon nitride is isolated by utilizing the loose property of the silicon dioxide, so that the silicon nitride cannot be conducted into the top GeSn area, and the stability of the performance of the top GeSn area is ensured; based on the high selectivity ratio of silicon nitride and germanium in dry etching, the silicon nitride is used as a masking film for dry etching, so that the process is easy to realize. Of course, it is understood that the number of layers of the protective layer and the material of the protective layer are not limited herein as long as the protective layer can be formed.
(b2) Forming an isolation region pattern on the protective layer by using a photoetching process;
(b3) Etching the protective layer and the substrate at the appointed position of the isolation region graph by utilizing a dry etching process to form an isolation groove, wherein the depth of the isolation groove is greater than or equal to the thickness of a top GeSn region of the substrate;
the depth of the isolation groove is larger than or equal to the thickness of the top GeSn region, and the advantage of the isolation groove is that silicon dioxide in the subsequent groove is connected with the buried oxide layer of the GeOI substrate to form complete insulation isolation of the diode device, so that lateral diffusion of carriers among the devices is prevented.
(b4) Filling the isolation groove to form the isolation region of the Pin diode;
(b5) The substrate is planarized.
Further, for step (c), the following steps may be specifically included:
(c1) Forming a protective layer on the surface of the substrate;
specifically, the protective layer comprises a silicon dioxide layer and a silicon nitride layer, and the forming of the protective layer comprises the following steps: generating a silicon dioxide layer on the surface of the GeSn region of the substrate; and generating a silicon nitride layer on the surface of the silicon dioxide layer. The benefits of this are similar to the function of the protective layer above and will not be described in detail here.
(c2) Forming P-type grooves and N-type groove patterns on the protective layer by utilizing a photoetching process;
(c3) And etching the protective layer and the GeSn region at the appointed position of the groove by utilizing a dry etching process to form the P-type groove and the N-type groove.
The depth of the P-type groove and the N-type groove is larger than the thickness of the protective layer and smaller than the sum of the thicknesses of the protective layer and the top GeSn region. Preferably, the distance between the bottoms of the P-type groove and the N-type groove and the bottom of the top GeSn region is 5-25 micrometers, so that a generally-considered deep groove is formed, and a P, N region with uniform impurity distribution and high doping concentration and a steep Pi and Ni junction can be formed when the P-type active region and the N-type active region are formed, so that the plasma concentration of the intrinsic region can be improved.
Further, for step (d), the following steps may be specifically included:
(d1) Forming a first P type active region and a first N type active region in the P type groove and the N type groove;
specifically, the process of forming the first active region may be: oxidizing the P-type groove and the N-type groove to form an oxidation layer on the inner wall of the groove, flattening the groove by utilizing a wet etching process, and performing ion implantation on the P-type groove and the N-type groove to form the first P-type active region and the first N-type active region.
Among them, the flattening treatment has the following advantages: the protrusion of the trench sidewall can be prevented from forming an electric field concentration region, causing Pi and Ni junction breakdown. The ion implantation process may be: photoetching a P-type groove and an N-type groove; injecting P-type impurities and N-type impurities into the P-type groove and the N-type groove respectively by adopting a method of injecting glued ions so as to form a first P-type active region and a first N-type active region; the photoresist is removed. The first P-type active region and the first N-type active region are regions with a depth of less than 1 micron from the side wall and the bottom of the groove along the ion diffusion direction.
The first active region is formed for the purpose of: forming a layer of uniform heavy doped region on the side wall of the groove, wherein the region is a heavy doped region in a Pi and Ni junction, and the formation of the first active region has the following advantages that firstly, the phenomenon that a heterojunction between polycrystalline AlAs and GeSn coincides with the Pi and Ni junction and the performance uncertainty is caused is avoided; secondly, in the polycrystalline AlAs process, a cavity is prevented from being formed between the polycrystalline AlAs and the groove wall due to the non-uniformity of the growth of the polycrystalline AlAs, and the cavity can cause poor contact between the polycrystalline AlAs and the side wall, so that the performance of the device is affected.
(d2) Forming a second P type active region and a second N type active region in the P type groove and the N type groove;
specifically, the process of forming the second active region may be: filling the P-type groove and the N-type groove with polycrystalline AlAs; after flattening the substrate, forming a polycrystalline AlAs layer on the surface of the substrate; photoetching the polycrystalline AlAs layer, and respectively injecting P-type impurities and N-type impurities into the positions of the P-type groove and the N-type groove by adopting a method of injecting colloid ions so as to form a second P-type active region and a second N-type active region and simultaneously form a P-type contact region and an N-type contact region; removing the photoresist; and removing the polycrystalline AlAs layer outside the P-type contact region and the N-type contact region by wet etching.
Further, for step (e), the following steps may be specifically included:
(e1) Generating silicon dioxide on the substrate;
(e2) Activating impurities in the active region using an annealing process;
(e3) Photoetching a lead hole in the P-type contact area and the N-type contact area;
(e4) Forming a GeSn alloy lead wire in the lead wire hole by adopting the RPCVD technology;
(e5) And passivating and photoetching PAD to form the high-implantation-ratio heterogeneous Pin diode of the AlAs-GeSn-AlAs structure.
The preparation method of the high injection ratio heterogeneous Pin diode with the AlAs-GeSn-AlAs structure provided by the application has the following advantages:
according to the solid-state plasma Pin diode, the carrier mobility performance is improved by introducing the top GeSn region. Meanwhile, the barrier of the AlAs material has a large forbidden bandwidth, and the microwave characteristics of the solid plasma in the intrinsic region can be greatly improved through the AlAs-GeSn-AlAs heterostructure, so that the radiation efficiency of the silicon-based solid plasma reconfigurable antenna is greatly improved.
The Pin diode realizes the adjustment of the GeSn forbidden band width of the diode intrinsic region by dynamically controlling the content of Sn component in the top layer Ge. Due to the characteristics of large injection ratio and high mobility, the concentration and the distribution uniformity of the solid plasma of the Pin diode can be effectively improved. Another advantage of forming AlAs-GeSn heterojunctions is that the matching of lattice constants between AlAs and GeSn materials is high, with lattice mismatch ratios of only 0.08%, which is advantageous for forming more ideal heterojunctions.
The Pin diode is formed into a GeSn alloy lead wire by adopting the RPCVD technology, replaces a metal electrode in the traditional PiN diode, and greatly improves the integration level and stealth performance of the silicon-based antenna system.
The P area and the N area of the PiN diode adopt a polysilicon mosaic process based on etching deep groove etching, the process can provide abrupt junction Pi and Ni junction, and can effectively improve junction depth, so that the concentration and distribution of solid plasma are improved.
The Pin diode adopts a deep-groove dielectric isolation process, so that the breakdown voltage of the diode is effectively improved, and the influence of leakage current on the performance of the device is inhibited.
Example two
Referring to fig. 2a to fig. 2t, fig. 2a to fig. 2t are schematic diagrams illustrating a preparation method of a hetero-PiN diode with high injection ratio of AlAs-GeSn-AlAs structure according to an embodiment of the present application, based on the first embodiment, the preparation method is described in detail by taking the hetero-PiN diode with high injection ratio of AlAs-GeSn-AlAs structure with an intrinsic region length of 80 micrometers (the intrinsic region length may be between 50 micrometers and 150 micrometers) as an example, and the specific steps are as follows:
s10, selecting the GeOI substrate.
Referring to fig. 2a, the crystal orientation of the GeOI substrate 101 may be (100) or (110) or (111), without limitation. In addition, the GeOI substrate 101 may be doped n-type or p-type, and has a doping concentration of, for example, 0.5X10 14 ～0.5×10 15 cm -3 The thickness of the top layer Ge is, for example, 30 to 120 μm.
S20, doping the GeOI substrate to form a top GeSn region.
Referring to fig. 2b, the specific implementation may be: and photoetching the GeOI substrate, carrying out Sn component doping on the GeOI substrate to form a top GeSn region 201 on the substrate, wherein the Sn component in the GeSn region is 1-30%, and removing the photoresist.
S30, forming a protective layer on the surface of the GeSn region.
Referring to fig. 2c, two layers of materials may be continuously grown on the top GeSn region 201 by chemical vapor deposition (Chemical vapor deposition, CVD for short), wherein the first layer may be a silicon dioxide layer 301 with a thickness of 500-600 nm, and the second layer may be a silicon nitride layer 302 with a thickness of 0.5-2 μm. The method has the advantages that the stress of the silicon nitride is isolated by utilizing the loose property of the silicon dioxide, so that the silicon nitride cannot be conducted into the top GeSn area, and the stability of the performance of the top GeSn material is ensured; based on the high selectivity ratio of silicon nitride and germanium in dry etching, the silicon nitride is used as a masking film for dry etching, so that the process is easy to realize.
S40, photoetching the isolation region.
Referring to fig. 2d, isolation regions are formed on the passivation layer by a photolithography process. The specific method comprises the following steps: etching the silicon nitride layer by a wet etching process to form an isolation region pattern, and then forming an isolation region 401 with a width of 5-10 μm and a depth of 30-125 μm by dry etching; in the step, the isolation region is formed by adopting a deep groove isolation technology, and the advantage of the deep groove isolation technology is that the depth of the groove is larger than or equal to the thickness of the top GeSn layer, so that the connection between silicon dioxide in the subsequent groove and silicon dioxide on the substrate is ensured, and the complete insulation isolation of the device is formed.
S50, filling the isolation groove.
Referring to fig. 2e, after the isolation region is etched, a CVD method is used to deposit a silicon dioxide material 501 to fill the deep trench, so as to form the isolation region of the PiN diode.
S60, flattening the surface.
Referring to fig. 2f, the surface silicon dioxide layer and the silicon nitride layer are removed by chemical mechanical polishing (Chemical Mechanical Polishing, CMP for short) to planarize the surface.
S70, forming a protective layer on the surface of the substrate.
Referring to fig. 2g, the specific implementation may be: two layers of materials are continuously grown on a substrate by a CVD method, wherein the first layer is a silicon dioxide layer 701 with the thickness of 500-600 nm, and the second layer is a silicon nitride layer 702 with the thickness of 0.5-2 mu m.
S80, photoetching the P-type groove and the N-type groove.
Referring to fig. 2h, the specific implementation may be: etching the P, N area groove pattern by a wet method, and etching the P, N area silicon nitride layer by a wet method to form a P, N area pattern; by dry etching, deep grooves 801 having a width of 2 to 10 μm and a depth of 2 to 15 μm are formed. The purpose of etching the deep trench 801 is to: a P, N region with uniform impurity distribution and high doping concentration and a steep Pi and Ni junction are formed, so that the plasma concentration of the intrinsic region is improved.
S90, carrying out groove flattening treatment.
Referring to fig. 2i and fig. 2j, the specific implementation may be: oxidizing the substrate to form an oxide layer 901 with the thickness of 5-60 nm on the inner wall of the groove, and wet etching the oxide layer 901 of the groove to smooth the inner wall of the groove. The smooth purpose of slot inner wall is: the protrusion of the sidewall is prevented from forming an electric field concentration region, causing breakdown of Pi and Ni junctions.
S100, forming a first active region.
Referring to fig. 2k, the specific implementation may be: photoetching a P region groove, and carrying out p+ injection on the side wall of the P region groove by adopting a method of carrying out ion injection with glue so as to form a thin p+ active region 1001 in the side wall, wherein the concentration reaches 0.1-8 multiplied by 10 20 cm -3 Removing the photoresist when the thickness reaches 0.1-1 mu m; photoetching an N-region deep groove, and carrying out n+ implantation on the side wall of the N-region groove by adopting a method of ion implantation with glue to form a thin n+ active region 1002 in the side wall, wherein the concentration reaches 0.1-8 multiplied by 10 20 cm -3 The thickness reaches 0.1-1 mu m, and the photoresist is removed.
S110, filling polycrystalline AlAs.
Referring to fig. 2l, a poly-AlAs 1101 is deposited in the P, N trenches by CVD and the trenches are filled as contact electrodes.
S120, flattening the surface.
Referring to fig. 2m, a CMP process may be used to remove the surface poly AlAs and silicon nitride layer to planarize the surface.
S130, growing a polycrystalline AlAs layer.
Referring to fig. 2n, a polycrystalline AlAs layer 1301 may be deposited on the surface using CVD to a thickness of 300-600 nm.
S140, forming a second active region.
Referring to fig. 2o, the specific implementation may be: photoetching a P region groove, and carrying out p+ injection by adopting a rubberized ion injection method to ensure that the doping concentration of an active region of the P region reaches 0.1-8 multiplied by 10 20 cm -3 Removing the photoresist to form a P contact 1401; photoetching an N region groove, and carrying out n+ implantation by adopting ion implantation with glue to ensure that the doping concentration of an N region active region is 0.1-8 multiplied by 10 20 cm -3 The photoresist is removed and an N-contact 1402 is formed.
S150, forming a P/N contact region.
Referring to fig. 2p, a wet etch may be used to etch away poly AlAs outside the P, N contact region to form a P, N contact region.
S160, silicon dioxide is formed on the surface of the substrate.
Referring to fig. 2q, a silicon dioxide layer 1601 may be deposited on the surface of the substrate by CVD to a thickness of 500-800 nm.
S170, activating impurities.
Annealing is carried out for 0.5 to 2 minutes at 950 to 1150 ℃ so that the ion implanted impurities activate and push the impurities in the polycrystalline AlAs.
And S180, photoetching a lead hole in a P, N contact area.
Referring to fig. 2r, a lead hole 1801 is etched in the silicon dioxide layer.
And S190, forming a GeSn alloy lead.
Referring to fig. 2s, a GeSn alloy may be formed in the lead hole by using RPCVD technique, and the alloy on the surface may be etched away; and forming GeSn alloy 1901 on the surface of the substrate by adopting the RPCVD technology to form a lead. The Sn component in the GeSn alloy is, for example, 1% to 30%.
S200, passivation treatment and photoetching PAD.
Referring to fig. 2t, a passivation layer 2001 may be formed by depositing silicon nitride, and PAD is etched. Finally, the high injection ratio heterogeneous Pin diode with the AlAs-GeSn-AlAs structure is formed and is used for preparing the silicon-based high-integration stealth antenna.
In the present embodiment, the above-mentioned various process parameters are exemplified, and the modifications made by the conventional means of those skilled in the art are all within the scope of the present application.
The high injection ratio heterogeneous Pin diode applied to the AlAs-GeSn-AlAs structure of the silicon-based high-integration stealth antenna prepared by the application is characterized in that firstly, the content of Sn component in the top layer Ge is dynamically controlled by using GeSn material, so that the adjustment of the GeSn forbidden band width of the intrinsic region of the diode is realized, the injection ratio and the carrier mobility of carriers from a source region to the intrinsic region are further improved, the concentration and the distribution uniformity of solid-state plasmas in the diode are improved, and the performance of the silicon-based solid-state plasma high-integration antenna is greatly improved; secondly, the metal electrode in the traditional pin diode is replaced by the GeSn alloy electrode formed by adopting the RPCVD technology, so that the influence of solid plasma on the radiation performance of the antenna and the integration level and stealth performance of the antenna system are greatly improved, and the silicon-based solid plasma has wide application prospect in the miniaturized, integrated and intelligent directions of a communication system; in addition, the P region and the N region of the diode adopt an etching-based polysilicon mosaic process, the process can provide abrupt junction Pi and Ni junction, and can effectively improve the junction depth of the Pi and Ni junction, so that the concentration and distribution controllability of solid plasma are enhanced, and the preparation of a high-performance plasma antenna is facilitated; meanwhile, the preparation of the high injection ratio heterogeneous Pin diode with the AlAs-GeSn-AlAs structure adopts a deep-slot dielectric isolation process, so that the breakdown voltage of the diode is effectively improved, and the influence of leakage current on the performance of the device is inhibited.
Example III
Referring to fig. 3, fig. 3 is a schematic diagram of a device structure of a high-injection-ratio heterogeneous PiN diode with AlAs-GeSn-AlAs structure according to an embodiment of the application. The high-implantation-ratio heterogeneous PiN diode is manufactured by the manufacturing method shown in fig. 1, specifically, the high-implantation-ratio heterogeneous PiN diode with the AlAs-GeSn-AlAs structure is manufactured on a GeOI substrate 301, and a P region 303, an N region 304 and an intrinsic region laterally located between the P region 303 and the N region 304 of the diode are all located in a top GeSn layer 302 of the substrate. The PiN diode adopts a deep trench isolation technology, i.e., a deep trench isolation region 307 is disposed outside the P region 303 and the N region 304, and the depth of the isolation trench 307 is greater than or equal to the thickness of the top GeSn layer 302. In addition, the P region 303 and the N region 304 may respectively include a thin P-type active region 305 and a thin N-type active region 306 along the carrier diffusion direction.
From the above, according to the embodiment of the application, the Sn component is doped in the top layer Ge of the heterogeneous Pin diode with the high injection ratio of the AlAs-GeSn-AlAs structure, and the GeSn alloy with the energy gap being much narrower than that of the AlAs material is obtained by dynamically controlling the content of the Sn component in the top layer Ge, so that the injection ratio of carriers from the source region to the intrinsic region is further improved, and the concentration and the distribution uniformity of solid plasmas in the diode are improved. In addition, the mobility of carriers in the intrinsic region can be further improved by introducing the GeSn material, so that the performance of the silicon-based solid-state plasma high-integration antenna is greatly improved. Another advantage of forming AlAs-GeSn heterojunctions is that the matching of lattice constants between AlAs and GeSn materials is high, with lattice mismatch ratios of only 0.08%, which is advantageous for forming more ideal heterojunctions. The electrodes in the traditional silicon-based antenna pin diode are prepared from metal, and the existence of the metal electrodes can greatly influence the radar scattering cross section of the antenna system, so that the stealth characteristic of the communication system is reduced. Meanwhile, the interaction between the plasma region and electromagnetic waves is greatly influenced by the existence of the large metal electrode, so that the influence of solid plasma on the radiation performance of the antenna is weakened, and the development of silicon-based solid plasma in the directions of miniaturization, integration and intellectualization is limited. According to the embodiment of the application, the RPCVD technology is adopted to form the GeSn alloy lead, so that the metal electrode in the traditional diode is replaced, and the integration level and stealth performance of the antenna system are greatly improved. In addition, the use of the GeOI deep trench dielectric isolation process and the ion implantation process based on etching also improves the performance of the solid-state plasma Pin diode.
In summary, specific examples are applied herein to illustrate the principles and embodiments of the high-injection-ratio heterogeneous PiN diode with AlAs-GeSn-AlAs structure and the method for manufacturing the same, and the above examples are only used to help understand the method and core idea of the application; meanwhile, as for those skilled in the art, there are variations in the specific embodiments and the application scope according to the idea of the present application, and in summary, the present disclosure should not be construed as limiting the present application, and the scope of the present application should be defined by the appended claims.
The foregoing disclosure is merely illustrative of some embodiments of the application, but the embodiments are not limited thereto and variations within the scope of the application will be apparent to those skilled in the art.
Claims (8)
1. The preparation method of the high injection ratio heterogeneous Pin diode with the AlAs-GeSn-AlAs structure is characterized by comprising the following steps of:
(a) Selecting a GeOI substrate with a certain crystal orientation, and doping the GeOI substrate to form a top GeSn region;
(b) A deep groove isolation region is arranged in the GeSn region on the top layer of the substrate;
(c) Etching the GeSn region to form a P-type groove and an N-type groove, wherein the depth of the P-type groove and the N-type groove is smaller than the thickness of the top GeSn region;
(d) Ion implantation is adopted in the P-type groove and the N-type groove to form a P-type active region and an N-type active region;
(e) Forming a GeSn alloy lead on a substrate to finish the preparation of the high injection ratio heterogeneous Pin diode of the AlAs-GeSn-AlAs structure;
the method for doping the GeOI substrate to form the top GeSn region in the step (a) comprises the following steps:
(a1) Photoetching the GeOI substrate;
(a2) Carrying out Sn component doping on the GeOI substrate to form a top GeSn region, and dynamically controlling the content of Sn components in the top Ge to realize the maximum injection ratio of carriers;
(a3) Removing the photoresist;
the Pin diode realizes the adjustment of the GeSn forbidden band width of the intrinsic region of the diode by dynamically controlling the content of Sn component in the top layer Ge;
said step (d) comprises the steps of:
(d1) Forming a first P type active region and a first N type active region in the P type groove and the N type groove;
(d2) Forming a second P type active region and a second N type active region in the P type groove and the N type groove;
the step (d 2) specifically includes the following steps:
(d21) Filling the P-type groove and the N-type groove with polycrystalline AlAs;
(d22) After flattening the substrate, forming a polycrystalline AlAs layer on the surface of the substrate;
(d23) Photoetching the polycrystalline AlAs layer, and respectively injecting P-type impurities and N-type impurities into the positions of the P-type groove and the N-type groove by adopting a method of injecting glued ions to form a second P-type active region and a second N-type active region and simultaneously form a P-type contact region and an N-type contact region;
(d24) Removing the photoresist;
(d25) And removing the polycrystalline AlAs layer outside the P-type contact region and the N-type contact region by wet etching.
2. The method for preparing the high implantation ratio heterogeneous PiN diode with the AlAs-GeSn-AlAs structure according to claim 1, wherein the method for disposing the deep trench isolation region in the top GeSn region of the substrate in the step (b) comprises the following steps:
(b1) Forming a protective layer on the surface of the GeSn region;
the protective layer comprises a silicon dioxide layer and a silicon nitride layer, and the forming of the protective layer comprises the following steps:
(b11) Generating a silicon dioxide layer on the surface of the substrate;
(b12) Generating a silicon nitride layer on the surface of the silicon dioxide layer;
(b2) Forming an isolation region pattern on the protective layer by using a photoetching process;
(b3) Etching the protective layer and the substrate at the appointed position of the isolation region graph by utilizing a dry etching process to form an isolation groove, wherein the depth of the isolation groove is greater than or equal to the thickness of a top GeSn region of the substrate;
(b4) Filling the isolation groove to form the isolation region of the Pin diode;
(b5) The substrate is planarized.
3. The method for manufacturing the high implantation ratio heterogeneous PiN diode of the AlAs-GeSn-AlAs structure according to claim 2, wherein the step (c) comprises the steps of:
(c1) Forming P-type grooves and N-type groove patterns on the protective layer by utilizing a photoetching process;
(c2) And etching the protective layer and the GeSn region at the appointed position of the groove by utilizing a dry etching process to form the P-type groove and the N-type groove.
4. The method for manufacturing the high implantation ratio heterogeneous PiN diode of the AlAs-GeSn-AlAs structure according to claim 1, wherein the step (d 1) comprises the steps of:
(d11) Oxidizing the P-type groove and the N-type groove to form a silicon dioxide oxide layer on the inner walls of the P-type groove and the N-type groove;
(d12) Etching the oxide layers on the inner walls of the P-type groove and the N-type groove by utilizing a wet etching process to finish planarization of the inner walls of the P-type groove and the N-type groove;
(d13) And performing ion implantation on the P-type groove and the N-type groove to form a first P-type active region and a first N-type active region, wherein the first P-type active region is a region with a depth of less than 1 micron from the side wall and the bottom of the P-type groove along the ion diffusion direction, and the first N-type active region is a region with a depth of less than 1 micron from the side wall and the bottom of the N-type groove along the ion diffusion direction.
5. The method for manufacturing the high implantation ratio heterogeneous PiN diode of the AlAs-GeSn-AlAs structure according to claim 4, wherein the ion implantation process in the step (d 13) comprises:
(d131) Photoetching the P-type groove and the N-type groove;
(d132) Injecting P-type impurities and N-type impurities into the P-type groove and the N-type groove respectively by adopting a method of injecting glued ions so as to form a first P-type active region and a first N-type active region;
(d133) The photoresist is removed.
6. The method for preparing the high implantation ratio heterogeneous PiN diode of the AlAs-GeSn-AlAs structure according to claim 1, wherein the step (e) comprises:
(e1) Generating silicon dioxide on the substrate;
(e2) Activating impurities in the active region using an annealing process;
(e3) Photoetching a lead hole in the P-type contact area and the N-type contact area;
(e4) Forming a GeSn alloy lead wire in the lead wire hole by adopting the RPCVD technology;
(e5) And passivating and photoetching PAD to form the high-implantation-ratio heterogeneous Pin diode of the AlAs-GeSn-AlAs structure.
7. A high-injection-ratio heterogeneous PiN diode of AlAs-GeSn-AlAs structure, for use in the fabrication of silicon-based highly integrated reconfigurable antennas, prepared by the method of any one of claims 1-6.
8. A silicon-based highly integrated reconfigurable antenna comprising the AlAs-GeSn-AlAs structured high-implantation-ratio heterogeneous PiN diode of claim 7.
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| US7603016B1 (en) * | 2007-04-30 | 2009-10-13 | The United States Of America As Represented By The Secretary Of The Air Force | Semiconductor photonic nano communication link apparatus |
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