CN112993052B - Heterogeneous GeSn-based solid-state plasma Pin diode with mesa structure and preparation method thereof - Google Patents
Heterogeneous GeSn-based solid-state plasma Pin diode with mesa structure and preparation method thereof Download PDFInfo
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- 229910005898 GeSn Inorganic materials 0.000 title claims abstract description 81
- 238000002360 preparation method Methods 0.000 title claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 61
- 238000011065 in-situ storage Methods 0.000 claims abstract description 22
- 239000007787 solid Substances 0.000 claims abstract description 20
- 239000000969 carrier Substances 0.000 claims abstract description 19
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 13
- 239000000956 alloy Substances 0.000 claims abstract description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 86
- 238000000034 method Methods 0.000 claims description 67
- 230000008569 process Effects 0.000 claims description 52
- 239000000377 silicon dioxide Substances 0.000 claims description 43
- 235000012239 silicon dioxide Nutrition 0.000 claims description 43
- 229910052710 silicon Inorganic materials 0.000 claims description 24
- 239000010703 silicon Substances 0.000 claims description 24
- 238000001039 wet etching Methods 0.000 claims description 20
- 238000000151 deposition Methods 0.000 claims description 17
- 238000001259 photo etching Methods 0.000 claims description 17
- 230000002093 peripheral effect Effects 0.000 claims description 16
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 14
- 238000004519 manufacturing process Methods 0.000 claims description 14
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 14
- 238000001312 dry etching Methods 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 8
- 238000005516 engineering process Methods 0.000 claims description 6
- 239000012535 impurity Substances 0.000 claims description 6
- 238000002347 injection Methods 0.000 claims description 6
- 239000007924 injection Substances 0.000 claims description 6
- 238000000206 photolithography Methods 0.000 claims description 6
- 230000003213 activating effect Effects 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 4
- 125000005842 heteroatom Chemical group 0.000 claims description 4
- 230000001590 oxidative effect Effects 0.000 claims description 4
- 229920002120 photoresistant polymer Polymers 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 3
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- 238000009826 distribution Methods 0.000 abstract description 7
- 238000009792 diffusion process Methods 0.000 abstract description 5
- 230000007723 transport mechanism Effects 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 52
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 20
- 238000004891 communication Methods 0.000 description 6
- 230000010354 integration Effects 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000005855 radiation Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000007123 defense Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
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- 230000004048 modification Effects 0.000 description 1
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- 238000006467 substitution reaction Methods 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/868—PIN diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/6606—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
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Abstract
The invention discloses a heterogeneous GeSn-based solid-state plasma PiN diode with a mesa structure and a preparation method thereof. Selecting a GeOI substrate, and doping the GeOI substrate to form a top GeSn region; forming an active region of the mesa; forming a P region and an N region by in-situ doping; and forming a GeSn alloy lead on the substrate to finish the preparation of the heterogeneous GeSn-based solid-state plasma Pin diode with the mesa structure. The P region and the N region of the diode active region are subjected to intrinsic region bottom by introducing the mesa structure, so that the longitudinal diffusion distance of carriers is greatly reduced, the attenuation of the carriers in the intrinsic region is weakened, the concentration and the distribution uniformity of the carriers in the solid plasma PiN diode can be greatly improved, meanwhile, the transport mechanism of the carriers in the intrinsic region is improved by introducing the top GeSn region, and the forbidden band width of the intrinsic region is adjustable by dynamically controlling the content of Sn components in the top Ge.
Description
Technical Field
The invention relates to the technical field of semiconductor device manufacturing, in particular to a heterogeneous GeSn-based solid-state plasma Pin diode with a mesa structure and a preparation method thereof.
Background
The modern communication system has stronger requirements on miniaturization and integration, and the antenna serving as an electromagnetic wave radiation and receiving device in the communication system plays an important role in system performance measurement standard, so that the complexity of the antenna system is reduced, the operation is convenient, the weight and the physical size of the antenna system are reduced, and the communication system is promoted to develop towards miniaturization and integration by combining with a modern semiconductor preparation process on the basis of realizing multi-directional polarization, multi-working frequency range and multi-application function. The conventional metal antenna gradually cannot meet the requirements of a modern communication system due to the defects of large volume, poor reconstruction performance, low integration level and the like. Under the background, the novel solid-state plasma antenna has the advantages of high integration level, flexible reconfiguration, good stealth performance and the like, so that the novel solid-state plasma antenna greatly draws attention of researchers at home and abroad and becomes a hotspot in the field of antenna research. The diode is used as a basic radiation unit of the silicon-based antenna, and the antenna performance reconstruction is realized through the on-off of the dynamic control unit array, so that the diode can be widely applied to the fields of various reconnaissance, early warning and countermeasure radars, spaceborne, airborne and missile antennas, helicopter antennas, high signal-to-noise ratio microwave communication antennas and the like.
The current solid-state plasma PIN diode has a large longitudinal diffusion distance of carriers, so that the attenuation of the carriers in an intrinsic region is serious, and therefore, the invention provides the high-performance solid-state plasma transverse surface PIN diode which can be applied to a silicon-based high-integration reconfigurable antenna and a preparation method thereof.
Disclosure of Invention
The invention aims to overcome the problems in the prior art and provide a heterogeneous GeSn-based solid-state plasma PiN diode with a mesa structure and a preparation method thereof, wherein the P region and the N region of an active region of the diode are provided with the bottom of an intrinsic region through the introduction of the mesa structure of the diode, the longitudinal diffusion distance of carriers is greatly shortened, the attenuation of the carriers in the intrinsic region is weakened, the concentration and the distribution uniformity of the carriers in the solid-state plasma PiN diode can be greatly improved, meanwhile, the introduction of a GeSn region on the top layer improves the transport mechanism of the carriers in the intrinsic region, and the energy gap of the intrinsic region is adjustable through dynamically controlling the content of Sn components in the Ge on the top layer.
The invention aims at providing a preparation method of a heterogeneous GeSn-based solid-state plasma Pin diode with a mesa structure, which comprises the following steps:
(a) Selecting a GeOI substrate, and doping the GeOI substrate to form a top GeSn region;
(b) Forming an active region of the mesa;
(c) Forming a P region and an N region by in-situ doping, wherein the specific steps are as follows;
(c1) Flattening the periphery of an active area of the table top;
(c2) Forming a P region by utilizing in-situ doped and deposited P-type silicon;
(c3) Forming an N region by utilizing in-situ doped and deposited N-type silicon;
(d) And forming a GeSn alloy lead on the substrate to finish the preparation of the heterogeneous GeSn-based solid-state plasma Pin diode with the mesa structure.
Preferably, step (a) comprises:
(a1) Photoetching the GeOI substrate;
(a2) Carrying out Sn component doping on the GeOI substrate to form a top GeSn region, and dynamically controlling the content of Sn components in the top Ge to realize the maximum injection ratio of carriers;
(a3) The photoresist is removed.
Preferably, step (b) comprises:
(b1) Depositing a layer of silicon nitride on the surface of the GeSn region by using CVD;
(b2) Forming a mesa active region pattern on the silicon nitride layer by using a photolithography process;
(b3) And etching the protective layer and the top GeSn area at the appointed position of the active area pattern by using a dry etching process so as to form a mesa active area.
Preferably, step (c 1) comprises:
(c11) Oxidizing the peripheral side walls of the mesa active region to form an oxide layer on the peripheral side walls of the mesa active region;
(c12) And etching the oxidation layer on the peripheral side wall of the mesa active region by utilizing a wet etching process to finish planarization of the peripheral side wall of the mesa active region.
Preferably, step (c 2) comprises:
(c21) Depositing a layer of silicon dioxide on the surface of the substrate by CVD;
(c22) Forming a P region pattern on the silicon dioxide layer by utilizing a photoetching process;
(c23) Removing silicon dioxide on the P region by utilizing a wet etching process;
(c24) Forming a P region by utilizing in-situ doped and deposited P-type silicon;
(c25) Firstly, flattening the surface of the P region by using a dry etching process, and then removing silicon dioxide on the surface of the substrate by using a wet etching process.
Preferably, step (c 3) comprises:
(c31) Depositing a layer of silicon dioxide on the surface of the substrate by CVD;
(c32) Forming an N region pattern on the silicon dioxide layer by utilizing a photoetching process;
(c33) Removing silicon dioxide on the N region by utilizing a wet etching process;
(c34) Forming an N region by utilizing in-situ doped and deposited N-type silicon;
(c35) Firstly, flattening the surface of the N region by using a dry etching process, and then removing silicon dioxide on the surface of the substrate by using a wet etching process.
Preferably, step (d) comprises:
(d1) Generating silicon dioxide on the substrate;
(d2) Activating impurities in the P region and the N region by using an annealing process;
(d3) Photoetching lead holes in the P area and the N area and forming a GeSn alloy lead by adopting the RPCVD technology;
(d4) The PAD is passivated and photoetched to form the heterogeneous GeSn-based solid state plasma Pin diode with a mesa structure.
The second purpose of the invention is to provide a heterogeneous GeSn-based solid-state plasma Pin diode with a mesa structure, which is used for manufacturing a silicon-based high-integration solid-state plasma antenna.
Compared with the prior art, the invention has the beneficial effects that: the invention can prepare and provide the heterogeneous GeSn-based solid-state plasma PiN diode with the mesa structure, which is suitable for forming the silicon-based high-integration reconfigurable antenna, and the P area and the N area of the diode active area are provided with the bottom of the intrinsic area by introducing the mesa structure, so that the longitudinal diffusion distance of carriers is greatly shortened, the attenuation of the carriers in the intrinsic area is reduced, and the concentration and the distribution uniformity of the carriers in the solid-state plasma PiN diode can be greatly improved. Meanwhile, the introduction of the top GeSn region improves the transport mechanism of carriers in the intrinsic region, and the forbidden bandwidth of the intrinsic region is adjustable by dynamically controlling the content of Sn components in the top Ge.
Drawings
Fig. 1 is a flowchart of a method for manufacturing a heterojunction GeSn-based solid-state plasma PiN diode with a mesa structure according to an embodiment of the invention.
Fig. 2 a-2 t are schematic diagrams illustrating a method for manufacturing a hetero-GeSn-based solid-state plasma PiN diode with a mesa structure according to an embodiment of the invention.
Fig. 3 is a schematic diagram of a device structure of a hetero-GeSn-based solid-state plasma PiN diode with a mesa structure according to an embodiment of the present invention.
Detailed Description
Specific embodiments of the present invention will be described in detail below with reference to fig. 1-3, but it should be understood that the scope of the present invention is not limited by the specific embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The invention provides a heterogeneous GeSn-based solid-state plasma PiN diode with a mesa structure and a preparation method thereof, and provides a heterogeneous GeSn-based solid-state plasma PiN diode with a mesa structure and a preparation method thereof, which are suitable for forming a solid-state plasma reconfigurable antenna. The PiN diode can be a lateral heterogeneous GeSn-based PiN diode formed by doping Sn components based On Germanium (Germanium-On-Insulator, for short, geOI) On an insulating substrate, wherein when a direct current is applied to the diode, a solid plasma composed of free carriers (electrons and holes) is formed On the surface of the diode by direct current, and the plasma has a metal-like characteristic, namely, has a reflection effect On electromagnetic waves, and the reflection characteristic is closely related to the microwave transmission characteristic, concentration and distribution of surface plasma.
The solid-state plasma reconfigurable antenna can be formed by arranging and combining heterogeneous GeSn-based solid-state plasma PiN diodes with a mesa structure according to an array, utilizes the diodes in an external control array to be selectively conducted, enables the array to form dynamic solid-state plasma stripes, has the functions of an antenna and transmitting and receiving specific electromagnetic waves, and can change the shapes and distribution of the solid-state plasma stripes through the selective conduction of the diodes in the array, thereby realizing the reconfiguration of the antenna and having important application prospects in the aspects of helicopters, national defense communication and radar technology.
Hereinafter, the process flow of the heterogeneous GeSn-based solid-state plasma PiN diode with a mesa structure prepared by the present invention will be described in further detail. In the drawings, thicknesses of layers and regions are enlarged or reduced for convenience of description, and the illustrated sizes do not represent actual dimensions.
Example 1
Referring to fig. 1, fig. 1 is a flowchart of a method for manufacturing a hetero GeSn-based solid state plasma PiN diode with a mesa structure according to an embodiment of the present invention, where the method is suitable for manufacturing a silicon-based solid state plasma PiN diode, and the diode is mainly used for manufacturing a silicon-based high-integration reconfigurable antenna. The method comprises the following steps:
(a) Selecting a GeOI substrate, and doping the GeOI substrate to form a top GeSn region;
(b) Forming an active region of the mesa;
(c) Forming a P region and an N region by in-situ doping;
(d) And forming a GeSn alloy lead on the substrate to finish the preparation of the heterogeneous GeSn-based solid-state plasma Pin diode with the mesa structure.
The reason why the top GeSn region is doped in the GeOI substrate for step (a) is that the radiation unit diode of the silicon-based solid state plasma antenna needs to have a high concentration of solid state plasma because of its good microwave characteristics. The heterogeneous GeSn-based solid-state plasma PiN diode obtains GeSn alloy with narrower forbidden band width than silicon material by doping Sn component in the top-layer Ge and dynamically controlling the content of the Sn component in the top-layer Ge, thereby further improving the injection ratio of carriers from a source region to an intrinsic region and greatly improving the concentration and distribution uniformity of solid-state plasma in the diode. In addition, the introduction of the buried oxide layer and the deep trench isolation technology further improves the carrier confinement capability, so Sn is doped in the GeOI substrate to form a top GeSn region.
For step (a), doping the GeOI substrate to form a top GeSn region may include the steps of:
(a1) Photoetching the GeOI substrate;
(a2) Carrying out Sn component doping on the GeOI substrate to form a top GeSn region, and dynamically controlling the content of Sn components in the top Ge to realize the maximum injection ratio of carriers;
(a3) The photoresist is removed.
In addition, for step (b), forming the active region of the mesa may include the steps of:
(b1) Depositing a layer of silicon nitride on the surface of the GeSn region by using CVD;
the purpose of depositing the silicon nitride layer is to: after the mesa active region is etched, the GeSn material in the mesa active region may be etched away using silicon nitride as a mask for the top GeSn layer.
(b2) Forming a mesa active region pattern on the silicon nitride layer by using a photolithography process;
(b3) And etching the protective layer and the top layer GeSn at the appointed position of the active region graph by using a dry etching process so as to form a mesa active region.
Furthermore, for the step (c), the P region and the N region are formed by in-situ doping, which may specifically include the following steps:
(c1) Flattening the periphery of an active area of the table top;
(c2) Forming a P region by utilizing in-situ doped and deposited P-type silicon;
(c3) N-type silicon is deposited by in-situ doping to form an N-region.
For the step (c 1), the planarization treatment of the periphery of the active area of the mesa may specifically include the following steps:
(c11) Oxidizing the peripheral side walls of the mesa active region to form an oxide layer on the peripheral side walls of the mesa active region;
(c12) And etching the oxidation layer on the peripheral side wall of the mesa active region by utilizing a wet etching process to finish planarization of the peripheral side wall of the mesa active region.
Furthermore, for step (c 2), the P-region is formed by in-situ doping deposition of P-type silicon, which may specifically include the steps of:
(c21) Depositing a layer of silicon dioxide on the surface of the substrate by CVD;
(c22) Forming a P region pattern on the silicon dioxide layer by utilizing a photoetching process;
(c23) Removing silicon dioxide on the P region by utilizing a wet etching process;
(c24) Forming a P region by utilizing in-situ doped and deposited P-type silicon;
(c25) Firstly, flattening the surface of the P region by using a dry etching process, and then removing silicon dioxide on the surface of the substrate by using a wet etching process.
For step (c 3), N regions are formed by in-situ doping of the deposited N-type silicon, which may specifically include the steps of:
(c31) Depositing a layer of silicon dioxide on the surface of the substrate by CVD;
(c32) Forming an N region pattern on the silicon dioxide layer by utilizing a photoetching process;
(c33) Removing silicon dioxide on the N region by utilizing a wet etching process;
(c34) Forming an N region by utilizing in-situ doped and deposited N-type silicon;
(c35) Firstly, flattening the surface of the N region by using a dry etching process, and then removing silicon dioxide on the surface of the substrate by using a wet etching process.
For the step (d), forming a GeSn alloy lead on the substrate to complete the preparation of the heterogeneous GeSn-based solid-state plasma PiN diode with a mesa structure, specifically comprising the following steps:
(d1) Generating silicon dioxide on the substrate;
(d2) Activating impurities in the P region and the N region by using an annealing process;
(d3) Photoetching lead holes in the P area and the N area and forming a GeSn alloy lead by adopting the RPCVD technology;
(d4) The PAD is passivated and photoetched to form the heterogeneous GeSn-based solid state plasma Pin diode with a mesa structure.
In the conventional preparation process for manufacturing the P region and the N region of the solid-state plasma PiN diode, an injection process is adopted for forming the P region and the N region, and the method requires large injection dosage and energy, has high requirements on equipment and is not compatible with the existing process; and by adopting a diffusion process, the junction depth is deeper, but the areas of the P region and the N region are larger, the integration level is low, the doping concentration is uneven, the electrical property of the solid plasma PiN diode is affected, and the controllability of the concentration and the distribution of the solid plasma is poor.
The in-situ doping can avoid adverse effects caused by ion implantation and other modes, and the doping concentration of the material can be controlled by controlling the gas flow, so that a steep doping interface is more favorable to be obtained, and better device performance is obtained.
Example two
Referring to fig. 2a to fig. 2t, fig. 2a to fig. 2t are schematic views of a method for preparing a hetero GeSn-based solid state plasma PiN diode with a mesa structure according to an embodiment of the present invention, wherein the method is described in detail based on the first embodiment, taking the hetero GeSn-based solid state plasma PiN diode with a mesa structure with a solid state plasma region length of 100 micrometers as an example, and the intrinsic region length may be between 50 micrometers and 150 micrometers, and the specific steps are as follows:
s10, selecting the GeOI substrate.
Referring to FIG. 2a, the GeOI substrate 101 has a crystal orientation of (100), and the GeOI substrate 101 has a doping type of p-type and a doping concentration of 10 14 cm -3 The thickness of the top layer Ge is for example 60 μm.
S20, doping the GeOI substrate to form a top GeSn region.
Referring to fig. 2b, the specific implementation may be: and photoetching the GeOI substrate, carrying out Sn component doping on the GeOI substrate to form a top GeSn region 201 on the substrate, wherein the Sn component in the GeSn region is 1-30%, and removing the photoresist.
S30, depositing a layer of silicon nitride on the surface of the top GeSn region.
Referring to fig. 2c, a silicon nitride layer 301 is deposited on the top GeSn region 201 by chemical vapor deposition (Chemical vapor deposition, CVD for short).
S40, etching the GeSn area on the top layer of the substrate to form an active area deep groove.
Referring to fig. 2d, an active region pattern is formed on the silicon nitride layer by using a photolithography process, and the protection layer and the top GeSn region are etched at designated positions of the active region pattern by using a dry etching process to form an active region deep trench 401.
S50, flattening the periphery of the active area of the mesa.
Referring to fig. 2e and 2f, the specific implementation may be: oxidizing the peripheral side wall of the mesa active region to form an oxide layer 501 with the thickness of 5-60 nm on the peripheral side wall of the mesa active region, and etching the peripheral side wall oxide layer of the mesa active region by utilizing a wet etching process to finish planarization of the peripheral side wall of the mesa active region.
S60, depositing a layer of silicon dioxide on the surface of the substrate.
Referring to fig. 2g, a layer of silicon dioxide 601 is deposited on the substrate using a CVD process.
S70, photoetching the silicon dioxide layer.
Referring to fig. 2h, a P-region pattern is formed on the silicon dioxide layer by using a photolithography process, and the silicon dioxide layer on the P-region pattern is removed by using a wet etching process.
S80, forming a P region.
Referring to fig. 2i, the specific implementation may be: and depositing P-type silicon on the P region pattern on the surface of the substrate by using an in-situ doping method to form a P region 801, and controlling the doping concentration of the P region by controlling the gas flow.
S90, flattening the surface of the substrate.
Referring to fig. 2j, the specific implementation may be: firstly, flattening the surface of the P region by using a dry etching process, and then removing the silicon dioxide layer on the surface of the substrate by using a wet etching process.
S100, depositing a layer of silicon dioxide on the surface of the substrate.
Referring to fig. 2k, the specific implementation may be: a silicon dioxide layer 1001 is deposited on the substrate surface using a CVD method.
S110, photoetching the silicon dioxide layer.
Referring to fig. 2l, forming an N-region pattern on the silicon dioxide layer by using a photolithography process; and removing the silicon dioxide layer on the N region by utilizing a wet etching process.
S120, forming an N region.
Referring to fig. 2m, N-type silicon is deposited on the N-region pattern on the substrate surface by using an in-situ doping method to form an N-region 1201, and the doping concentration of the N-region is controlled by controlling the gas flow.
S130, flattening the surface of the substrate.
Referring to fig. 2N, the surface of the N region is flattened by a dry etching process, and then the silicon dioxide layer on the surface of the substrate is removed by a wet etching process.
S140, depositing a polysilicon layer.
Referring to fig. 2o, a polysilicon layer 1401 may be deposited in the trench using CVD.
S150, forming a silicon dioxide layer on the surface.
Referring to fig. 2p, a silicon dioxide layer 1501 may be deposited on the surface by CVD to a thickness of 500nm.
S160, flattening the surface.
Referring to fig. 2q, a CMP process may be used to remove the surface silicon dioxide and silicon nitride layers to planarize the surface.
S170, activating impurities.
Annealing is performed at 950-1150 ℃ for 0.5-2 minutes to activate the ion implanted impurities and drive the impurities in the active region.
S180, photoetching a lead hole.
Referring to fig. 2r, a lead hole 1801 is etched in the silicon dioxide layer.
S190, forming a lead.
Referring to fig. 2s, a GeSn alloy may be formed in the lead hole by using RPCVD technique, and the alloy on the surface may be etched away; and forming a GeSn alloy 1901 on the surface of the substrate by adopting an RPCVD technology to form a lead, wherein the Sn component in the GeSn alloy is 1-30 percent.
S200, passivation treatment and photoetching PAD.
Referring to fig. 2t, a passivation layer 2001 may be formed by depositing silicon nitride, and PAD is etched. And finally forming a heterogeneous GeSn-based solid-state plasma PiN diode with a mesa structure, and taking the heterogeneous GeSn-based solid-state plasma PiN diode as a basic unit for preparing the silicon-based high-integration reconfigurable antenna.
Example III
Referring to fig. 3, fig. 3 is a schematic diagram of a device structure of a hetero-GeSn-based solid-state plasma PiN diode with a mesa structure according to an embodiment of the invention. The PiN diode is manufactured by adopting the manufacturing method shown in the figure 1. Specifically, the hetero-GeSn-based solid-state plasma PiN diode with mesa structure is formed on a GeOI substrate 301, and the P-region 303, N-region 304, and intrinsic region laterally between the P-region 303 and the N-region 304 of the PiN diode are all located within the top GeSn region 302 of the substrate.
In summary, specific examples are applied herein to illustrate the principles and embodiments of the present invention, i.e., the heterojunction GeSn-based solid-state plasma PiN diode with mesa structure and the method for manufacturing the same, and the above examples are only used to help understand the method and core idea of the present invention; meanwhile, as for those skilled in the art, there are variations in the specific embodiments and the application scope according to the idea of the present invention, and in summary, the present disclosure should not be construed as limiting the present invention, and the scope of the present invention should be defined by the appended claims.
Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (6)
1. The preparation method of the heterogeneous GeSn-based solid-state plasma PiN diode with the mesa structure is characterized by comprising the following steps of:
(a) Selecting GeOI substrate, doping to form top GeSn region in GeOI substrate, wherein GeOI substrate 101 has crystal orientation of (100), and the GeOI substrate (101) has p-type doping concentration of 10 14 cm -3 The thickness of the top layer Ge is 60 μm; the Sn component in the GeSn area is 1-30 percent; the method comprises the following specific steps of;
(a1) Photoetching the GeOI substrate;
(a2) Carrying out Sn component doping on the GeOI substrate to form a top GeSn region, and dynamically controlling the content of Sn components in the top Ge to realize the maximum injection ratio of carriers;
(a3) Removing the photoresist;
(b) Forming an active region of the mesa;
(c) Forming a P region and an N region by in-situ doping, wherein the specific steps are as follows;
(c1) Flattening the periphery of an active area of the table top;
(c2) Forming a P region by utilizing in-situ doped and deposited P-type silicon;
(c3) Forming an N region by utilizing in-situ doped and deposited N-type silicon;
(d) Forming a GeSn alloy lead on the substrate to finish the preparation of the heterogeneous GeSn-based solid-state plasma Pin diode with the mesa structure;
said step (d) comprises:
(d1) Generating silicon dioxide on the substrate;
(d2) Activating impurities in the P region and the N region by using an annealing process;
(d3) Photoetching lead holes in the P area and the N area and forming a GeSn alloy lead by adopting the RPCVD technology;
(d4) The PAD is passivated and photoetched to form the heterogeneous GeSn-based solid state plasma Pin diode with a mesa structure.
2. The method of fabricating a hetero-GeSn-based solid state plasma PiN diode with a mesa structure of claim 1, wherein step (b) comprises:
(b1) Depositing a silicon nitride layer on the surface of the GeSn region by CVD;
(b2) Forming a mesa active region pattern on the silicon nitride layer by using a photolithography process;
(b3) And etching the silicon nitride layer and the top GeSn region at the appointed position of the active region graph by using a dry etching process so as to form a mesa active region.
3. The method of fabricating a hetero-GeSn-based solid state plasma PiN diode with a mesa structure of claim 1, wherein step (c 1) comprises:
(c11) Oxidizing the peripheral side walls of the mesa active region to form an oxide layer on the peripheral side walls of the mesa active region;
(c12) And etching the oxidation layer on the peripheral side wall of the mesa active region by utilizing a wet etching process to finish planarization of the peripheral side wall of the mesa active region.
4. The method of fabricating a hetero-GeSn-based solid state plasma PiN diode with a mesa structure of claim 1, wherein step (c 2) comprises:
(c21) Depositing a layer of silicon dioxide on the surface of the substrate by CVD;
(c22) Forming a P region pattern on the silicon dioxide layer by utilizing a photoetching process;
(c23) Removing silicon dioxide on the P region by utilizing a wet etching process;
(c24) Forming a P region by utilizing in-situ doped and deposited P-type silicon;
(c25) Firstly, flattening the surface of the P region by using a dry etching process, and then removing silicon dioxide on the surface of the substrate by using a wet etching process.
5. The method of fabricating a hetero-GeSn-based solid state plasma PiN diode with a mesa structure of claim 1, wherein step (c 3) comprises:
(c31) Depositing a layer of silicon dioxide on the surface of the substrate by CVD;
(c32) Forming an N region pattern on the silicon dioxide layer by utilizing a photoetching process;
(c33) Removing silicon dioxide on the N region by utilizing a wet etching process;
(c34) Forming an N region by utilizing in-situ doped and deposited N-type silicon;
(c35) Firstly, flattening the surface of the N region by using a dry etching process, and then removing silicon dioxide on the surface of the substrate by using a wet etching process.
6. A hetero GeSn-based solid state plasma PiN diode with a mesa structure for use in fabricating a highly integrated reconfigurable antenna, the solid state plasma PiN diode being made by the method of any one of claims 1-5.
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