CN112993047B - Heterogeneous GeSn-based deep groove protection Pin diode and preparation method thereof - Google Patents
Heterogeneous GeSn-based deep groove protection Pin diode and preparation method thereof Download PDFInfo
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- 229910005898 GeSn Inorganic materials 0.000 title claims abstract description 93
- 238000002360 preparation method Methods 0.000 title claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 82
- 239000000758 substrate Substances 0.000 claims abstract description 68
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 66
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 66
- 239000010703 silicon Substances 0.000 claims abstract description 66
- 230000008569 process Effects 0.000 claims abstract description 62
- 238000011065 in-situ storage Methods 0.000 claims abstract description 26
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 19
- 239000000956 alloy Substances 0.000 claims abstract description 19
- 238000005530 etching Methods 0.000 claims abstract description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 94
- 239000000377 silicon dioxide Substances 0.000 claims description 47
- 235000012239 silicon dioxide Nutrition 0.000 claims description 47
- 238000000151 deposition Methods 0.000 claims description 24
- 230000002093 peripheral effect Effects 0.000 claims description 20
- 238000001259 photo etching Methods 0.000 claims description 20
- 238000001039 wet etching Methods 0.000 claims description 20
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 15
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 15
- 238000001312 dry etching Methods 0.000 claims description 12
- 238000005516 engineering process Methods 0.000 claims description 9
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- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 230000002349 favourable effect Effects 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 230000005855 radiation Effects 0.000 description 3
- 239000002210 silicon-based material Substances 0.000 description 3
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/868—PIN diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
Abstract
The invention relates to a heterogeneous GeSn-based silicon-based deep groove protection Pin diode and a preparation method thereof, wherein the preparation method comprises the following steps: selecting a GeOI substrate, and doping the GeOI substrate to form a top GeSn region; etching the GeSn area on the top layer of the substrate to form an active area deep groove; flattening the periphery of the deep groove of the active region and forming a P region and an N region by in-situ doping; forming a GeSn alloy lead on the substrate to finish the preparation of the heterogeneous GeSn-based silicon-based deep groove protection Pin diode; according to the invention, by introducing a deep groove isolation process and a Si-GeSn-Si heterostructure, the low power consumption performance of the diode is greatly improved, so that the power consumption of the PiN diode can be reduced by one order of magnitude.
Description
Technical Field
The invention relates to the technical field of semiconductor materials and device manufacturing, in particular to a heterogeneous GeSn-based silicon-based deep groove protection PiN diode and a preparation method thereof.
Background
The modern communication system has stronger requirements on miniaturization and integration, and the antenna serving as an electromagnetic wave radiation and receiving device in the communication system plays an important role in system performance measurement standard, so that the complexity of the antenna system is reduced, the operation is convenient, the weight and the physical size of the antenna system are reduced, and the communication system is promoted to develop towards miniaturization and integration by combining with a modern semiconductor preparation process on the basis of realizing multi-directional polarization, multi-working frequency range and multi-application function. The preparation process of the silicon-based high-integration reconfigurable antenna is compatible with the traditional silicon process, the volume and weight of the antenna are far smaller than those of a metal antenna, the advantages of flexible reconfigurability, good stealth performance, easiness in integration with a modern communication system and the like are achieved, and the silicon-based high-integration reconfigurable antenna has wide application prospects in the fields of helicopters, military communication and wireless terminals. The silicon-based Pin diode is used as a basic radiating unit of the silicon-based high-integration reconfigurable antenna, and a physical structure model, an intrinsic region internal carrier generation mechanism and a solid plasma microwave characteristic research of the silicon-based high-integration reconfigurable antenna play a vital role in the development of solid plasma devices and the silicon-based high-integration reconfigurable antenna. However, due to the disadvantages of low concentration, poor distribution uniformity and the like of solid plasmas in the intrinsic region of the traditional PiN diode, the power consumption of the diode can reach about 0.2W when the diode works normally, and when a plurality of diodes are connected in series to form an array, the overall power consumption is very large, so that the silicon-based high-integration reconfigurable antenna is not beneficial to the development of the silicon-based high-integration reconfigurable antenna in the directions of miniaturization and low power consumption.
Therefore, how to manufacture a high-performance solid-state plasma PiN diode for application to a silicon-based high-integration reconfigurable antenna becomes important.
Disclosure of Invention
Therefore, in order to solve the technical defects and shortcomings in the prior art, the invention provides the heterogeneous GeSn-based silicon-based deep trench protection PiN diode and the preparation method thereof, and the deep trench isolation process and the Si-GeSn-Si heterostructure are introduced, so that the low power consumption performance of the diode is greatly improved, and the power consumption of the PiN diode can be reduced by one order of magnitude.
The first object of the present invention is to provide a method for preparing a hetero GeSn-based silicon-based deep trench protection PiN diode for manufacturing a silicon-based highly integrated reconfigurable antenna, the method comprising the steps of:
(a) Selecting a GeOI substrate, doping Sn in the GeOI substrate, and forming a top GeSn region;
(b) Etching the top GeSn region to form an active region deep groove;
(c) Flattening the peripheral side walls of the deep groove of the active region, forming a P region by utilizing in-situ doping deposition P-type silicon, and forming an N region by utilizing in-situ doping deposition N-type silicon;
(d) And forming a GeSn alloy lead on the substrate to prepare the heterogeneous GeSn-based silicon-based deep groove protection Pin diode.
Preferably, the step (a) specifically includes the following steps:
(a1) Photoetching the GeOI substrate;
(a2) Carrying out Sn component doping on the GeOI substrate to form a top GeSn region, and dynamically controlling the content of Sn components in the top Ge; the Sn component in the GeSn area is 1% -30%;
(a3) The photoresist is removed.
Preferably, the step (b) specifically includes the following steps:
(b1) Depositing a layer of silicon nitride on the surface of the top GeSn region by CVD;
(b2) Forming an active region pattern on the silicon nitride layer by using a photolithography process;
(b3) And etching the silicon nitride layer and the top GeSn region at the appointed position of the active region pattern by using a dry etching process so as to form an active region deep groove.
Preferably, in the step (c), the planarization process of the peripheral sidewall of the deep trench of the active region specifically includes the following steps:
(c11) Oxidizing the peripheral side walls of the active region to form a layer of silicon dioxide on the peripheral side walls of the active region;
(c12) And etching the oxidation layer on the peripheral side wall of the active region by utilizing a wet etching process to finish planarization of the peripheral side wall of the active region.
Preferably, in the step (c), the forming the P region by depositing P-type silicon by in-situ doping specifically includes the following steps:
(c21) Depositing a layer of silicon dioxide on the surface of the substrate by CVD;
(c22) Forming a P region pattern on the silicon dioxide layer by utilizing a photoetching process;
(c23) Removing the silicon dioxide layer on the P region by utilizing a wet etching process;
(c24) Forming a P region by utilizing in-situ doped and deposited P-type silicon;
(c25) Firstly, flattening the surface of the P region by using a dry etching process, and then removing the silicon dioxide layer on the surface of the substrate by using a wet etching process.
Preferably, in the step (c), the forming the N region by in-situ doping and depositing N-type silicon specifically includes the following steps:
(c31) Depositing a layer of silicon dioxide on the surface of the substrate by CVD;
(c32) Forming an N region pattern on the silicon dioxide layer by utilizing a photoetching process;
(c33) Removing the silicon dioxide layer on the N region by utilizing a wet etching process;
(c34) Forming an N region by utilizing in-situ doped and deposited N-type silicon;
(c35) Firstly, flattening the surface of the N region by using a dry etching process, and then removing the silicon dioxide layer on the surface of the substrate by using a wet etching process.
Preferably, step (d) specifically comprises the steps of:
(d1) Generating silicon dioxide on the substrate;
(d2) Activating impurities in the P region and the N region by using an annealing process; the annealing process is 950-1150 ℃ and the annealing time is 0.5-2min;
(d3) Photoetching lead holes in the P area and the N area, forming GeSn alloy in the lead holes by adopting an RPCVD technology, and forming a GeSn alloy lead on the surface of the silicon dioxide layer formed in the step (d 1) by adopting the RPCVD technology;
(d4) And passivating and photoetching PAD to form the heterogeneous GeSn-based silicon-based deep trench protection Pin diode.
The second object of the invention is to provide the heterogeneous GeSn-based silicon-based deep trench protection PiN diode prepared by the preparation method, wherein the heterogeneous GeSn-based silicon-based deep trench protection PiN diode is used for manufacturing a silicon-based high-integration reconfigurable antenna.
The invention has the beneficial effects that:
the invention provides a heterogeneous GeSn-based silicon-based deep groove protection PiN diode, which greatly improves the low power consumption performance of the diode by introducing a deep groove isolation process and a Si-GeSn-Si heterostructure, so that the power consumption of the PiN diode can be reduced by one order of magnitude; sn is doped in the top-layer Ge, and the content of Sn components in the top-layer Ge is dynamically controlled to obtain GeSn alloy with narrower forbidden bandwidth than that of a silicon material, so that the injection ratio of carriers from a source region to an intrinsic region is further improved, and the concentration and distribution uniformity of solid plasma in the diode are greatly improved; the in-situ doping can avoid adverse effects caused by ion implantation and other modes, and the doping concentration of the material can be controlled by controlling the gas flow, so that a steep doping interface is more favorable to be obtained, and better device performance is obtained; the GeSn alloy lead is formed by adopting the RPCVD technology to replace a metal electrode in a traditional diode, so that the integration level and stealth performance of an antenna system are greatly improved, and the application prospect of the antenna system in the fields of helicopters, military communication and wireless terminals is improved.
Other aspects and features of the present invention will become apparent from the following detailed description, which refers to the accompanying drawings. It is to be understood that the drawings are designed solely for purposes of illustration and not as a definition of the limits of the invention, for which reference should be made to the appended claims. It should be further understood that the drawings are not necessarily drawn to scale and that, unless otherwise indicated, they are merely intended to conceptually illustrate the structures and procedures described herein.
Drawings
The following detailed description of specific embodiments of the invention refers to the accompanying drawings.
Fig. 1 is a flowchart of a preparation method of a hetero GeSn-based silicon-based deep trench protection PiN diode according to embodiment 1 of the present invention.
Fig. 2 a-2 s are schematic diagrams of a preparation method of a hetero GeSn-based silicon-based deep trench protection PiN diode according to embodiment 2 of the present invention.
Fig. 3 is a schematic diagram of a device structure of a hetero GeSn-based silicon-based deep trench protection PiN diode according to embodiment 3 of the present invention.
Description of the embodiments
In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to the appended drawings.
The invention provides a heterogeneous GeSn-based silicon-based deep groove protection PiN diode and a preparation method thereof. The diode can be a GeSn-based heterogeneous transverse PiN diode formed by doping Sn components based On Germanium (Germanium-On-Insulator, for short, geOI) On an insulating substrate, and the low-power consumption performance of the diode is greatly improved by introducing a deep trench isolation process and a Si-GeSn-Si heterostructure, so that the power consumption of the PiN diode can be reduced by one order of magnitude; when a direct current is applied to the plasma, direct current can form solid plasmas composed of free carriers (electrons and holes) on the surface of the plasma, and the plasmas have metalloid characteristics, namely, the plasmas have reflection effect on electromagnetic waves, and the reflection characteristics are closely related to the microwave transmission characteristics, concentration and distribution of the surface plasmas.
The silicon-based high-integration reconfigurable antenna can be formed by arranging and combining heterogeneous GeSn-based silicon-based deep groove protection PiN diodes according to an array, utilizes the diodes in an external control array to be selectively conducted, enables the array to form dynamic solid plasma stripes, has the functions of an antenna and transmitting and receiving specific electromagnetic waves, and can change the shapes and distribution of the solid plasma stripes through the selective conduction of the diodes in the array, so that the antenna is reconfigured, and has important application prospects in the aspects of helicopter and radar technology.
Hereinafter, the process flow of the heterogeneous GeSn-based silicon-based deep trench protection Pin diode prepared by the method is further described in detail. In the drawings, thicknesses of layers and regions are enlarged or reduced for convenience of description, and the illustrated sizes do not represent actual dimensions.
Examples
Referring to fig. 1, fig. 1 is a flowchart of a method for manufacturing a hetero GeSn-based silicon-based deep trench protection PiN diode according to an embodiment of the present invention, where the method is applicable to manufacturing a hetero GeSn-based silicon-based deep trench protection PiN diode, and the diode is mainly used for manufacturing a silicon-based high-integration reconfigurable antenna. The method comprises the following steps:
(a) Selecting a GeOI substrate, and doping the GeOI substrate to form a top GeSn region;
(b) Etching the GeSn area on the top layer of the substrate to form an active area deep groove;
(c) Flattening the side wall around the deep groove of the active region and forming a P region and an N region by in-situ doping;
(d) And forming a GeSn alloy lead on the substrate to finish the preparation of the heterogeneous GeSn-based silicon-based deep groove protection Pin diode.
The reason why the top GeSn region is doped in the GeOI substrate for step (a) is that the radiation unit diode of the silicon-based solid state plasma antenna needs to have a high concentration of solid state plasma because of its good microwave characteristics. The heterogeneous GeSn-based solid-state plasma PiN diode obtains GeSn alloy with narrower forbidden band width than silicon material by doping Sn component in the top-layer Ge and dynamically controlling the content of the Sn component in the top-layer Ge, thereby further improving the injection ratio of carriers from a source region to an intrinsic region and greatly improving the concentration and distribution uniformity of solid-state plasma in the diode. In addition, the introduction of the buried oxide layer and the deep trench isolation technology further improves the carrier confinement capability, so Sn is doped in the GeOI substrate to form a top GeSn region.
For step (a), doping the GeOI substrate to form a top GeSn region may include the steps of:
(a1) Photoetching the GeOI substrate;
(a2) Carrying out Sn component doping on the GeOI substrate to form a top GeSn region, and dynamically controlling the content of Sn components in the top Ge to realize the maximum injection ratio of carriers;
(a3) The photoresist is removed.
In addition, for the step (b), etching the GeSn region on the top layer of the substrate to form an active region deep trench may include the steps of:
(b1) Depositing a layer of silicon nitride on the surface of the GeSn region by using CVD;
the purpose of depositing the silicon nitride layer is to: after the active region is photoetched, silicon nitride can be used as a mask of the top GeSn layer, so that the GeSn material in the deep groove is etched.
(b2) Forming an active region pattern on the silicon nitride layer by using a photolithography process;
(b3) And etching the protective layer and the top GeSn area at the appointed position of the active area pattern by using a dry etching process so as to form an active area deep groove.
Furthermore, for the step (c), the step of planarizing the periphery of the active region and forming the P region and the N region by in-situ doping may specifically include the following steps:
(c1) Flattening the side wall around the deep groove of the active region;
(c2) Forming a P region by utilizing in-situ doped and deposited P-type silicon;
(c3) Forming an N region by utilizing in-situ doped and deposited N-type silicon;
for step (c 1), planarizing the active region deep trench may specifically include the steps of:
(c11) Oxidizing the peripheral side walls of the active region to form a layer of silicon dioxide on the peripheral side walls of the deep groove of the active region;
(c12) And etching the oxidation layer on the peripheral side wall of the deep groove of the active region by utilizing a wet etching process so as to finish planarization of the peripheral side wall of the deep groove of the active region.
Furthermore, for step (c 2), the P-region is formed by in-situ doping deposition of P-type silicon, which may specifically include the steps of:
(c21) Depositing a layer of silicon dioxide on the surface of the substrate by CVD;
(c22) Forming a P region pattern on the silicon dioxide layer by utilizing a photoetching process;
(c23) Removing the silicon dioxide layer on the P region by utilizing a wet etching process;
(c24) Forming a P region by utilizing in-situ doped and deposited P-type silicon;
(c25) Firstly, flattening the surface of the P region by using a dry etching process, and then removing the silicon dioxide layer on the surface of the substrate by using a wet etching process.
For step (c 3), N regions are formed by in-situ doping of the deposited N-type silicon, which may specifically include the steps of:
(c31) Depositing a layer of silicon dioxide on the surface of the substrate by CVD;
(c32) Forming an N region pattern on the silicon dioxide layer by utilizing a photoetching process;
(c33) Removing the silicon dioxide layer on the N region by utilizing a wet etching process;
(c34) Forming an N region by utilizing in-situ doped and deposited N-type silicon;
(c35) Firstly, flattening the surface of the N region by using a dry etching process, and then removing the silicon dioxide layer on the surface of the substrate by using a wet etching process.
For the step (d), forming a GeSn alloy lead on the substrate to complete the preparation of the heterogeneous GeSn-based silicon-based deep trench protection PiN diode, specifically comprising the following steps:
(d1) Generating silicon dioxide on the substrate;
(d2) Activating impurities in the P region and the N region by using an annealing process;
(d3) Photoetching lead holes in the P area and the N area and forming a GeSn alloy lead by adopting the RPCVD technology;
(d4) And passivating and photoetching PAD to form the heterogeneous GeSn-based silicon-based deep trench protection Pin diode.
In the conventional preparation process for manufacturing the P region and the N region of the solid-state plasma PiN diode, an injection process is adopted for forming the P region and the N region, and the method requires large injection dosage and energy, has high requirements on equipment and is not compatible with the existing process; and by adopting a diffusion process, the junction depth is deeper, but the areas of the P region and the N region are larger, the integration level is low, the doping concentration is uneven, the electrical property of the diode is affected, and the controllability of the concentration and the distribution of the solid plasma is poor.
The in-situ doping can avoid adverse effects caused by ion implantation and other modes, and the doping concentration of the material can be controlled by controlling the gas flow, so that a steep doping interface is more favorable to be obtained, and better device performance is obtained.
Examples
Referring to fig. 2a to fig. 2s, fig. 2a to fig. 2s are schematic diagrams illustrating a preparation method of a hetero GeSn-based silicon-based deep trench protection PiN diode according to an embodiment of the present invention, wherein on the basis of the first embodiment, a preparation method of a hetero GeSn-based silicon-based deep trench protection PiN diode with a solid plasma region length of 80 microns is described in detail, and the solid plasma region length may be between 50 microns and 150 microns, which includes the following specific steps:
s10, selecting the GeOI substrate.
Referring to fig. 2a, the crystal orientation of the GeOI substrate 101 may be (100) or (110) or (111), without limitation. In addition, the GeOI substrate 101 may be doped n-type or p-type, and has a doping concentration of, for example, 0.5X10 14 ～1×10 15 cm -3 The thickness of the top layer Ge is, for example, 30 to 120 μm.
S20, doping the GeOI substrate to form a top GeSn region.
Referring to fig. 2b, the specific implementation may be: and photoetching the GeOI substrate, carrying out Sn component doping on the GeOI substrate to form a top GeSn region 201 on the substrate, wherein the Sn component in the GeSn region is 1-30%, and removing the photoresist.
S30, depositing a layer of silicon nitride on the surface of the top GeSn region.
Referring to fig. 2c, a silicon nitride layer 301 with a thickness of 500-600 nm is deposited on a substrate 101 by chemical vapor deposition (Chemical vapor deposition, CVD for short).
S40, etching the GeSn area on the top layer of the substrate to form an active area deep groove.
Referring to fig. 2d, an active region pattern is formed on the silicon nitride layer by using a photolithography process, and the protection layer and the top GeSn region are etched at designated positions of the active region pattern by using a dry etching process to form an active region deep trench 401.
S50, flattening the side wall around the deep groove of the active region.
Referring to fig. 2e and 2f, the specific implementation may be: oxidizing the peripheral side wall of the active region deep groove to form an oxide layer 501 with the thickness of 5-60 nm on the peripheral side wall of the active region, and etching the peripheral side wall oxide layer of the active region deep groove by utilizing a wet etching process to finish planarization of the peripheral side wall of the active region deep groove.
S60, depositing a layer of silicon dioxide on the surface of the substrate.
Referring to fig. 2g, a layer of silicon dioxide 601 is deposited on the substrate using a CVD process.
S70, photoetching the silicon dioxide layer.
Referring to fig. 2h, a P-region pattern is formed on the silicon dioxide layer by using a photolithography process, and the silicon dioxide layer on the P-region pattern is removed by using a wet etching process.
S80, forming a P region.
Referring to fig. 2i, the specific implementation may be: by using an in-situ doping method, P-type silicon is deposited on a P-region pattern on the surface of the substrate to form a P-region 801, the doping concentration of the P-region is controlled by controlling the gas flow, and the doping concentration of the P-region is 5 x 10 19 cm -3 ~5*10 20 cm -3 。
S90, flattening the surface of the substrate.
Referring to fig. 2j, the specific implementation may be: firstly, flattening the surface of the P region by using a dry etching process, and then removing the silicon dioxide layer on the surface of the substrate by using a wet etching process.
S100, depositing a layer of silicon dioxide on the surface of the substrate.
Referring to fig. 2k, the specific implementation may be: a silicon dioxide layer 1001 is deposited on the substrate surface using a CVD method.
S110, photoetching the silicon dioxide layer.
Referring to fig. 2l, forming an N-region pattern on the silicon dioxide layer by using a photolithography process; and removing the silicon dioxide layer on the N region by utilizing a wet etching process.
S120, forming an N region.
Referring to fig. 2m, N-type silicon is deposited on the N-region pattern on the substrate surface to form an N-region 1201 by in-situ doping, the doping concentration of the N-region is controlled by controlling the gas flow, and the doping concentration of the N-region is 5×10 19 cm -3 ~5*10 20 cm -3 。
S130, flattening the surface of the substrate.
Referring to fig. 2N, the surface of the N region is flattened by a dry etching process, and then the silicon dioxide layer on the surface of the substrate is removed by a wet etching process.
S140, flattening the surface of the substrate.
Referring to fig. 2o, the silicon nitride layer and the polysilicon on the surface of the substrate may be removed by a CMP method, thereby planarizing the surface of the substrate.
S150, depositing silicon dioxide.
Referring to fig. 2p, a layer of silicon dioxide 1501 is deposited on the substrate surface by CVD and the active area trenches are filled.
S160, activating impurities.
And annealing for 0.5-2 minutes at 950-1150 ℃ to activate the ion implanted impurities and drive the impurities in the active region.
S170, photoetching a lead hole in a P, N contact area.
Referring to fig. 2q, a wire hole 1701 is etched in the silicon dioxide layer.
S180, forming a GeSn alloy lead.
Referring to fig. 2r, a GeSn alloy may be formed in the lead hole by using RPCVD technique, and the alloy on the surface may be etched away; and forming a GeSn alloy 1801 on the surface of the substrate by adopting an RPCVD technology to form a lead, wherein the Sn component in the GeSn alloy is 1-30 percent.
S190, passivation treatment and photoetching PAD.
Referring to fig. 2s, a passivation layer 1901 may be formed by depositing silicon nitride, and PAD is etched. And finally, forming a heterogeneous GeSn-based silicon-based deep groove protection PiN diode which is used for preparing a high-integration solid-state plasma antenna material.
Examples
Referring to fig. 3, fig. 3 is a schematic diagram of a device structure of a hetero GeSn-based silicon-based deep trench protection PiN diode according to an embodiment of the invention. The heterogeneous GeSn-based silicon-based deep groove protection Pin diode is manufactured by adopting the manufacturing method shown in the figure 1. Specifically, the hetero GeSn-based silicon-based deep trench protection PiN diode is formed on a GeOI substrate 301, and the P-region 303, the N-region 304, and the intrinsic region laterally between the P-region 303 and the N-region 304 of the diode are all located within the top GeSn region 302 of the GeOI substrate.
The invention provides a heterogeneous GeSn-based silicon-based deep groove protection PiN diode, which greatly improves the low power consumption performance of the diode by introducing a deep groove isolation process and a Si-GeSn-Si heterostructure, so that the power consumption of the PiN diode can be reduced by one order of magnitude; sn is doped in the top-layer Ge, and the content of Sn components in the top-layer Ge is dynamically controlled to obtain GeSn alloy with narrower forbidden bandwidth than that of a silicon material, so that the injection ratio of carriers from a source region to an intrinsic region is further improved, and the concentration and distribution uniformity of solid plasma in the diode are greatly improved; in the conventional preparation process for manufacturing the P region and the N region of the solid-state plasma PiN diode, an injection process is adopted for forming the P region and the N region, and the method requires large injection dosage and energy, has high requirements on equipment and is not compatible with the existing process; the diffusion process is adopted, the junction depth is deeper, but the areas of the P region and the N region are larger, the integration level is low, the doping concentration is uneven, the electrical property of the diode is affected, the controllability of the concentration and the distribution of solid plasma is poor, the adverse effect caused by ion implantation and other modes can be avoided by adopting in-situ doping, the doping concentration of the material can be controlled by controlling the gas flow, and a steep doping interface is more favorable to be obtained, so that better device performance is obtained; the electrode in the traditional silicon-based antenna Pin diode is prepared from metal, and the existence of the metal electrode can greatly influence the radar scattering cross section of the antenna system, so that the stealth characteristic of the communication system is reduced. Meanwhile, the interaction between a plasma region and electromagnetic waves is greatly influenced by the existence of a large metal electrode, and the influence of solid plasma on the radiation performance of an antenna is weakened, so that the development of silicon-based solid plasma to miniaturization, integration and intellectualization is limited.
In summary, specific examples are applied herein to illustrate the principles and embodiments of the heterojunction GeSn-based silicon-based deep trench protection PiN diode and the method for manufacturing the same, and the above examples are only for helping to understand the method and core ideas of the invention; meanwhile, as for those skilled in the art, there are variations in the specific embodiments and the application scope according to the idea of the present invention, and in summary, the present disclosure should not be construed as limiting the present invention, and the scope of the present invention should be defined by the appended claims.
Claims (8)
1. The preparation method of the heterogeneous GeSn-based deep groove protection PiN diode is characterized by comprising the following steps of:
(a) Selecting a GeOI substrate, doping Sn in the GeOI substrate, and forming a top GeSn region;
the GeOI substrate 101 is doped n-type or p-type with a doping concentration of 0.5X10 14 ～1×10 15 cm -3 The thickness of the top layer Ge is 30-120 mu m;
the step (a) specifically comprises the following steps:
(a1) Photoetching the GeOI substrate;
(a2) Carrying out Sn component doping on the GeOI substrate to form a top GeSn region, and dynamically controlling the content of Sn components in the top Ge to realize the maximum injection ratio of carriers; the Sn component in the GeSn area is 1% -30%;
(a3) Removing the photoresist;
(b) Etching the top GeSn region to form an active region deep groove;
(c) Flattening the peripheral side walls of the deep groove of the active region, forming a P region by utilizing in-situ doping deposition P-type silicon, and forming an N region by utilizing in-situ doping deposition N-type silicon;
(d) And forming a GeSn alloy lead on the substrate to finish the preparation of the heterogeneous GeSn-based deep groove protection Pin diode.
2. The method for preparing the heterogeneous GeSn-based deep trench protection PiN diode according to claim 1, wherein the step (b) specifically comprises the following steps:
(b1) Depositing a layer of silicon nitride on the surface of the top GeSn region by CVD;
(b2) Forming an active region pattern on the silicon nitride layer by using a photolithography process;
(b3) And etching the silicon nitride layer and the top GeSn region at the appointed position of the active region pattern by using a dry etching process so as to form an active region deep groove.
3. The method for preparing the heterogeneous GeSn-based deep trench protection PiN diode according to claim 1, wherein in the step (c), the planarization process of the peripheral sidewall of the deep trench of the active region specifically comprises the following steps:
(c11) Oxidizing the peripheral side walls of the active region to form a layer of silicon dioxide on the peripheral side walls of the active region;
(c12) And etching the oxidation layer on the peripheral side wall of the active region by utilizing a wet etching process to finish planarization of the peripheral side wall of the active region.
4. The method for preparing the heterogeneous GeSn-based deep trench protection PiN diode of claim 1, wherein in the step (c), the forming of the P-region by in-situ doped deposition of P-type silicon comprises the following steps:
(c21) Depositing a layer of silicon dioxide on the surface of the substrate by CVD;
(c22) Forming a P region pattern on the silicon dioxide layer by utilizing a photoetching process;
(c23) Removing the silicon dioxide layer on the P region by utilizing a wet etching process;
(c24) Forming a P region by utilizing in-situ doped and deposited P-type silicon;
(c25) Firstly, flattening the surface of the P region by using a dry etching process, and then removing the silicon dioxide layer on the surface of the substrate by using a wet etching process.
5. The method for preparing the heterogeneous GeSn-based deep trench protection PiN diode of claim 1, wherein in the step (c), the N-region is formed by in-situ doping deposition of N-type silicon, comprising the steps of:
(c31) Depositing a layer of silicon dioxide on the surface of the substrate by CVD;
(c32) Forming an N region pattern on the silicon dioxide layer by utilizing a photoetching process;
(c33) Removing the silicon dioxide layer on the N region by utilizing a wet etching process;
(c34) Forming an N region by utilizing in-situ doped and deposited N-type silicon;
(c35) Firstly, flattening the surface of the N region by using a dry etching process, and then removing the silicon dioxide layer on the surface of the substrate by using a wet etching process.
6. The method for preparing the heterogeneous GeSn-based deep trench protection PiN diode of claim 1, wherein step (d) comprises:
(d1) Generating silicon dioxide on the substrate;
(d2) Activating impurities in the P region and the N region by using an annealing process;
(d3) Photoetching lead holes in the P area and the N area, forming GeSn alloy in the lead holes by adopting an RPCVD technology, and forming a GeSn alloy lead on the surface of the silicon dioxide layer formed in the step (d 1) by adopting the RPCVD technology;
(d4) And passivating and photoetching PAD to form the heterogeneous GeSn-based deep trench protection Pin diode.
7. A heterogeneous GeSn-based deep trench protection PiN diode made according to the method of any one of claims 1-6.
8. The hetero-GeSn-based deep trench protection PiN diode of claim 7, for use in fabricating a highly integrated reconfigurable antenna.
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