CN108767072A - Enhanced cmos sensor light emitting diode structure preparation method - Google Patents
Enhanced cmos sensor light emitting diode structure preparation method Download PDFInfo
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0054—Processes for devices with an active region comprising only group IV elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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Abstract
The invention discloses a kind of enhanced cmos sensor light emitting diode structure preparation methods, it is removed including p-type wafer cleaning and surface oxide layer, oxide layer plated film, mask, oxide layer opens square window and high energy ion beam surface treatment, Si corrodes, mask and oxide layer open square window, n-type doping, oxide layer plated film, mask and oxide layer trepanning, p-type is adulterated, oxide layer corrosion, silicide barrier layer plated film and mask openings, silicide plated film, annealing, remove unreacted silicide and barrier layer, nitration case plated film, oxide layer plated film, mask and open wire contacts hole, metal coating, chemical machinery polishes, oxide layer plated film, mask, oxide layer corrosion and line metal coating.Preparation process of the present invention is simple, can enhance conversion quantum efficiency, reduce cost.
Description
Technical field
It is specifically a kind of enhanced the present invention relates to field of semiconductor manufacture more particularly to field of image sensors
Cmos sensor light emitting diode structure preparation method.
Background technology
Charge is converted into voltage by cmos image chip in Pixel-level, and most function is then integrated into chip.In this way
Institute is functional to be worked by single power supply, and can realize and flexibly read image according to area-of-interest or windowing.
Cmos image sensor substantially be embedded in as analog-to-digital conversion (ADC), correlated-double-sampling (CDS), clock generate,
The system level chips such as voltage-stablizer (System-On-Chip, SOC) functions such as structure or Imaging processing, and before these all
It is that application system level designs the function just having.Present CIS is typically to be given birth to according to the 1P5M techniques from 180nm to recent 55nm
Production allows pixel to design and very high conversion factor is added, convenient for combining row gain to amplify.And then CIS chip substrate biass are steady
Circuit in qualitative difference and chip is more, so carrying more significant noise jamming.
Noise is mainly caused by two factors：1/f flicker noises and thermal noise.In MOS device and each amplifying unit, dodge
Bright noise is the defect that technical matters error generates, the result caused by charge is trapped in gate oxide.Charge passes in and out this
" trap " a bit causes the electric current in transistor channels unstable.These are the adjoint noise drawbacks of assertive evidence technique.For CIS cores
Piece, remove reduce assertive evidence logic circuit noise jamming, promoted pixel region photoelectric conversion process in the quantum efficiency of itself for
It improves signal-to-noise ratio and light sensation sensitivity has very great help.
Quantum efficiency (Quantum efficiency, QE) is the factor for directly affecting imaging sensor photoelectric properties, because
It all can directly lower signal-to-noise ratio (Signal-To-Noise-Ratio, SNR) for any loss of photoelectric conversion efficiency.Its shadow
Sound is various, because when shot noise (square root of signal) is Main Noise Sources, quantum efficiency is not singly signal-to-noise ratio
Dividend (signal), while be also divisor (noise).
The technical matters development that CIS accumulates in terms of quantum efficiency improvement is relatively slow.Physics based on silicon matter is special
Property, longer wavelength can penetrate photosensitive transition zones, it is possible to increase red and near infrared ray using thick epitaxial material
The quantum efficiency of wavelength.
According to Bill's Lambert law (Beer-Lambert law), absorbed energy is closed with the thickness exponentially of medium
Department.High-end CIS is using thicker silicon matter and back-illuminated (back side illumination, BSI) technique to restore high broadband
Quantum efficiency and near infrared ray (near infrared, NIR) susceptibility.However Si epitaxy layer thickness controlled ranges are small and to indigo plant
Light and feux rouges are at reversed quantum efficiency correspondence.
The special graph structuring on the surfaces pixel area photoelectric diode Si be can reduce the reflection of generation incident light improve diffraction and
Scattering probability enhances absorption intensity and then enhances the optimised process gimmick of photoelectric quantum transfer efficiency.
For the quantum efficiency of enhancing, it is desirable that the strong diffraction in c-Si and antireflection effect extend the optical path length in c-Si
Degree, needs harsh and complicated technique to prepare the embedded chamfering Si structures with absolute critical angle on this basis.
The surfaces existing mainstream Si special graph chemical industry skill bottleneck and challenge are as follows：
Random acicular surface with antiradar reflectivity and high-selenium corn efficiency in c-Si；And the CIS pixel packets of fine pith size
Containing random but limited quantity structure, lead to the large deviation of pixel characteristic, such as PRNU (photoresponse nonuniformity), is not suitable for height
The 2D imaging functions of uniform quality.
The absolute critical angle of embedded chamfering Si structures, which is made, harsh causes the complicated of high cost and uniformity of preparation process
It faces big challenge.
In traditional design structure (such as Fig. 1), since si dielectric surfaces are plane, light reflects, only one by reflection
The absorption efficiency of secondary light absorption, light is low, and conversion quantum efficiency is also low.
It is therefore desirable to invent a kind of cmos sensor light emitting diode structure preparation method, enhancing quantum conversion is moved
Efficiency and cost of keeping under strict control simultaneously.
Invention content
The object of the present invention is to provide a kind of enhanced cmos sensor light emitting diode structure preparation methods, can
Enhance conversion quantum efficiency, reduces cost.
To achieve the above object, the present invention provides a kind of enhanced cmos sensor light emitting diode structure preparation side
Method, step include：
(1) RCA ablutions are utilized, by SC-1 cleaning solutions, SC-2 cleaning solutions, SC-3 cleaning solutions, acid and deionized water to P
Type wafer is cleaned, the oxide layer of stripping p-type wafer upper surface；
(2) in the p-type crystal column surface plating oxide layer plated film one for having removed surface oxide layer；
(3) utilize photoresists to oxide layer plated film one into line mask, and cover part in mask surface to have the stone for ironing coating
English glass plate is exposed mask using litho machine, the Mask portion that removal is not ironed coating and covered, also using focusing
Ion beam or focused ion beam are surface-treated the position for eliminating mask, form the window that size is 1.5um × 1.5um
One；
(4) KOH for utilizing a concentration of 10%, corrodes downwards p-type wafer to one position of window, and it is 1-3um's to form depth
Inverted cone type groove；
(5) photoresists is utilized to cover part into line mask, and in mask surface to the oxide layer plated film one of one periphery of window
There is the quartz glass plate for ironing coating, mask is exposed using litho machine, the mask portion that removal is not ironed coating and covered
Point, also the position for eliminating mask is surface-treated using focused ion beam, by the dimension enlargement of window one be 4um ×
4um；
(6) surface of the bottom wall of the window one by energetic ion injection mode after dimension enlargement and inverted cone type groove is noted
Enter arsenic ion, what formation was made of inverted cone-shaped part one and the horizontal component one being connect with one upper end periphery of inverted cone-shaped part
N-type doping layer；
(7) in the inverted cone-shaped part one of n-type doping layer and the surface of horizontal component one plating layer of oxide layer plated film two, oxygen
Change layer plated film two and the oxide layer plated film one of one periphery of window after dimension enlargement is connected as one；
(8) utilize photoresists to oxide layer plated film two into line mask, and cover part in mask surface to have the stone for ironing coating
English glass plate is exposed mask using litho machine, the mask and horizontal component on the surface of removal inverted cone-shaped part one
The Mask portion for not ironed coating and being covered on one surface, also using focused ion beam to eliminating the position carry out table of mask
Surface treatment forms the window two that the size deviated towards inverted cone type groove side is 2.5um × 2.5um；
(9) by energetic ion injection mode the surface and window two of the inverted cone-shaped part one of n-type doping layer bottom
Wall injects boron ion, is formed by inverted conical part two and two structure of horizontal component being connect with two upper end side of inverted cone-shaped part
At p-type doped layer；
(10) by the oxide layer plated film two of two periphery of the window of focused ion beam removal step (8), and in p-type doped layer
The surface of inverted conical part two, the upper surface of the other side of inverted conical part two, the surface of horizontal component two, N-type mix
The surface of the horizontal component one of diamicton and the upper end face of p-type wafer plate one layer of silicide barrier layer plated film, and utilize photosensitive
Glue to the silicide barrier layer plated film on one surface of horizontal component of two offside of horizontal component two and horizontal component into line mask, and
Mask surface, which covers part, the quartz glass plate for ironing coating, is exposed to mask using litho machine, and plating is not ironed in removal
The Mask portion that layer covers, is also surface-treated the position for eliminating mask using focused ion beam, in horizontal component
Two and two offside of horizontal component horizontal component one upper surface be respectively formed size be 0.5um × 0.5um window three；
(11) it is plated in the upper surface of the horizontal component one of two offside of horizontal component two and horizontal component of three bottom of window
Silicide barrier layer plated film, and annealing also utilizes focused ion beam removal horizontal component two and two offside of horizontal component
The silicide barrier layer plated film of the silicide barrier layer plated film peripheral region of the upper surface of horizontal component one and unreacted silication
Object；
(12) it is coated with nitration case on the surface of silicide barrier layer coated surface and silicide barrier layer plated film peripheral region
Plated film, oxide layer plated film three is coated on the surface of nitration case plated film, and silicon is corresponded on oxide layer plated film three by focused ion beam
The position processing of compound barrier layer plated film forms lead contact hole, and lead contact hole penetrates through oxide layer plated film three and nitration case plated film successively
Reach silicide barrier layer coated surface；
(13) metal coating is plated in lead contact hole position at three surface of oxide layer plated film and two；
(14) by chemical-mechanical polishing mathing, the metal coating on three surface of oxide layer plated film is polished, lead at two is left and touches
The metal coating of hole site；
(15) oxide layer plated film four is plated on the metal coating surface of lead contact hole position at three surface of oxide layer plated film and two,
Using photoresists to oxide layer plated film four into line mask, and mask surface cover part have the quartz glass plate for ironing coating, profit
Mask is exposed with litho machine, the Mask portion that removal is not ironed coating and covered, while utilizing focused ion beam pair
The position for eliminating mask is surface-treated, the oxide layer plating at removal two on the upside of metal coating and at two on the outside of metal coating
Film four retains the oxide layer plated film four between metal coating at two, and plates line in the position for eliminating oxide layer plated film four
Metal coating.
As a further improvement on the present invention, the oxide layer plating of the oxide layer plated film one of the step (2), step (7)
Film two, the oxide layer plated film three of step (12), the oxide layer plated film four of step (15) are warm at 300 degree by thin film deposition system
It is deposited under degree, the nitration case plated film of step (12) is deposited by thin film deposition system at a temperature of 250 degree, step
(3), the photoresists of step (5), step (8), step (10) and step (15) are smeared by SC-1B type sol evenning machines.
As a further improvement on the present invention, the SC-1 cleaning solutions of the step (1) are NH4OH/H2O2/H2O, SC-2
Cleaning solution is HCI/H2O2/H2O, SC-3 cleaning solution are H2SO4/H2O2/H2O, acid are HF.
As a further improvement on the present invention, the P-type substrate material of the step (1) is silicon, the thickness of P-type substrate material
Degree is 700um.
As a further improvement on the present invention, the doped chemical of the n-type doping layer of the step (6) is arsenic, and doping is dense
Degree is 3.0 × 1016cm-3, the dosage of doping depth 1.5um, energy E=150keV, arsenic are ND (As)=1.3 × 1013cm–2。
As a further improvement on the present invention, the doped chemical of the p-type doped layer of the step (9) is boron, and doping is dense
Degree is 3.0 × 1016cm-3, the dosage of doping depth 0.25um, energy E=60keV, boron are ND (B)=1.0 × 1013cm–2。
As a further improvement on the present invention, the line metal-plated of the metal coating of the step (13) and step (15)
Film is formed by plating mode, and the line metal coating of step (15) is metallic aluminium or metallic copper, and the metal coating of (13) is
Tungsten.
As a further improvement on the present invention, the silicide barrier layer plated film of the step (11) is cobalt plated film, not instead
The silicide answered is oxide and nitride.
As a further improvement on the present invention, nitrogen is passed through when the step (11) is annealed, annealing temperature is 450 degree.
As a further improvement on the present invention, the operating voltage 30kV of the focused ion beam of the step (10), electric current
40pA；The operating voltage 30kV of the focused ion beam of step (12), electric current 0.23nA；The work of the focused ion beam of step (15)
Voltage 30kV, electric current 0.23nA.
Compared with prior art, enhanced cmos sensor light emitting diode structure preparation method of the invention has
Beneficial effect is as follows：
(1) preparation process is simple, reduces cost, and the Si pixels without obtaining complicated photoetching and etch process force madial wall
The critical angle of profile prepares irregular and periodic structure using simplified technique on the surface silicon (Si), rather than increases
Add silicon (Si) thickness and complicated manufacturing process, scattering, multiple reflections, repeatedly folding are reduced to be realized in crystalline silicon (c-Si)
It penetrates, to extend the optical path length in crystalline silicon (c-Si), improves the absorption of light.
(2) by simple preparation method, inverted cone structure is formed so that Si dielectric surfaces are inclined-plane, and light is by anti-
It penetrates, reflects, then reflect, then reflect, three reflections, three refractions, each incident light at least through the period is absorbed twice, to realize folding
Light is penetrated in pixel region side wall multiple reflections, is repeatedly reflected, and then extend the effective optical path length elongation in silicon (Si) substrate, some
The incident light of angle can be absorbed three times, increase the surface area of light absorption, substantially increase the absorption efficiency of light, to increase
Add quantum efficiency (QE) and sensitivity, increases signal-to-noise ratio；And inverted cone structure can reduce the scattering at edge, simultaneously because
The size of cone is in micron dimension, and the size that the condition that diffraction occurs is barrier is less than wavelength, and the dimension of barrier is got over
Big diffraction phenomena gets over unobvious, so cone can effectively reduce the diffraction of visible light.
(3) this preparation method is also compatible with FSI, BSI and stack CIS and ISP wafer.
By description below and in conjunction with attached drawing, the present invention will become more fully apparent, these attached drawings are for explaining the present invention
Embodiment.
Description of the drawings
Fig. 1 is traditional light emitting diode structural schematic diagram；
Fig. 2 is the light emitting diode structural schematic diagram of the present invention；
Fig. 3 is light emitting diode structure of the present invention and traditional light emitting diode structure photoelectricity conversion testing knot
Fruit comparison diagram；
Fig. 4 is process flow chart one；
Fig. 5 is process flow chart two；
Fig. 6 is process flow chart three；
Fig. 7 is process flow chart four；
Fig. 8 is process flow chart five；
Fig. 9 is process flow chart six；
Figure 10 is process flow chart seven；
Figure 11 is process flow chart eight；
Figure 12 is process flow chart nine；
Figure 13 is process flow chart ten；
Figure 14 is process flow chart 11；
Figure 15 is process flow chart 12；
Figure 16 is process flow chart 13；
Figure 17 is process flow chart 14；
Figure 18 is process flow chart 15；
Figure 19 is integrated artistic flow chart.
Wherein, P-type substrate 1, oxide layer plated film 1, window 1, inverted cone type groove 4, n-type doping layer 5, inverted cone-shaped portion
Divide a 5a, one 5b of horizontal component, oxide layer plated film 26, window 27, p-type doped layer 8, two 8a of inverted conical part, horizontal part
Divide two 8b, silicide barrier layer plated film 9, window 3 10, nitration case plated film 11, oxide layer plated film 3 12, lead contact hole 13, metal
Plated film 14, oxide layer plated film 4 15, line metal coating 16.
Specific implementation mode
The embodiment of the present invention described referring now to the drawings, similar element numbers represent similar element in attached drawing.
Please refer to Fig.2-19, the enhanced cmos sensor light emitting diode structure preparation method, step packet
It includes：
(1) RCA ablutions are utilized, by SC-1 cleaning solutions, SC-2 cleaning solutions, SC-3 cleaning solutions, acid and deionized water to P
Type wafer 1 is cleaned, the oxide layer of 1 upper surface of stripping p-type wafer.P-type wafer material is silicon, the thickness of p-type wafer material
For 700um.SC-1 cleaning solutions are NH4OH/H2O2/H2O, SC-2 cleaning solution are HCI/H2O2/H2O, SC-3 cleaning solution are H2SO4/
H2O2/H2O, acid are HF.On cleaning procedure, the organic contaminations of silicon chip surface are removed first, because organic matter can covering part silicon
Piece surface, to make oxidation film and associated contamination be difficult to remove；Then oxidation film is dissolved, because oxide layer is " to stain
Trap " can also introduce epitaxy defect；The contaminations such as particle, metal are finally removed again, while silicon chip surface being made to be passivated.
It is still typically, so far the wet chemical cleans method most generally used, the stream of the ablution that RCA ablutions, which are a kind of,
Journey and cleaning agent are as follows.
(1)SPM(SC-3)：H2SO4/H2O2/H2120~150 DEG C of SPM of O have very high oxidability, can be by metal oxygen
It is dissolved in cleaning solution after change, and oxidation operation can be generated CO2And H2O.It can remove the weight of silicon chip surface with SPM cleaning silicon chips
Organic contaminations and part metals, but can make organic carbon when organic matter stains especially severe and be difficult to remove.
(2)APM(SC-1)：NH4OH/H2O2/H230~80 DEG C of O is due to H2O2Effect, silicon chip surface has one layer of natural oxygen
Change film (SiO2), it is in hydrophily, liquid can be cleaned between silicon chip surface and particle and is impregnated with.Due to the natural oxidizing layer of silicon chip surface
Si with silicon chip surface is by NH4OH corrodes, therefore the particle for being attached to silicon chip surface is just fallen into cleaning solution, to reach removal
The purpose of particle.In NH4While the corrosion of silicon surfaces OH, H2O2New oxidation film is formed on oxidized silicon chip surface again.
(3)HPM(SC-2)：HCl/H2O2/H265~85 DEG C of O is stained with for removing the metals such as the sodium, iron, magnesium of silicon chip surface
It is dirty.HPM can remove Fe and Zn at room temperature.
(4)HF(DHF)：Therefore the natural oxide film that 20~25 DEG C of DHF of HF (DHF) can remove silicon chip surface is attached to
Metal on natural oxide film will be dissolved in cleaning solution, while DHF inhibits the formation of oxidation film.Therefore it can be easy to
Ground removes the Al, Fe, Zn of silicon chip surface, the metals such as Ni, and DHF can also remove the metal hydroxide being attached on natural oxide film
Object.When being cleaned with DHF, when natural oxide film is corroded, the silicon of silicon chip surface is hardly corroded.
It is cleaned with deionized water (D.I.Water) per between twice cleaning agent, removes residual components.
(2) in 1 surface of the p-type wafer plating oxide layer plated film 1 for having removed surface oxide layer.Oxide layer plated film 1 passes through
Thin film deposition system deposits at a temperature of 300 degree.
(3) utilize photoresists to oxide layer plated film 1 into line mask, and cover part in mask surface to have the stone for ironing coating
English glass plate is exposed mask using litho machine, the Mask portion that removal is not ironed coating and covered, also using focusing
Ion beam FIB is surface-treated the position for eliminating mask, forms the window 1 that size is 1.5um × 1.5um.It is photosensitive
Glue is applied to by SC-1B type sol evenning machines on oxide layer plated film 1.Litho machine uses SUSS MicroTec ' s ELP300 photoetching
Machine, focused ion beam (FIB) use 450 two-beam focused ion beam systems of FEI Helios.At the surface focused ion beam (FIB)
Manage bar part, accelerating potential 30kV, sample processing time 10s, electric current I=80pA, silicon face is after high energy ion beam is handled, silicon
Rough surface, when carrying out silicon corrosion, etching time is shorter, is easy to form cone, by the electricity for controlling high energy ion beam
Pressure, electric current and processing time can be with control surface roughness.
(4) p-type wafer 1 is corroded downwards to one 3 position of window using a concentration of 10% KOH, it is 1-3um's to form depth
Inverted cone type groove 4, etching time 105s-150s.1um depth needs to corrode the 105s times.
(5) photoresists is utilized to cover office into line mask, and in mask surface to the oxide layer plated film 1 of one 3 periphery of window
There is the quartz glass plate for ironing coating in portion, is exposed to mask using litho machine, the mask that removal is not ironed coating and covered
Part is also surface-treated the position for eliminating mask using focused ion beam, is 4um by the dimension enlargement of window 1
×4um.Photoresists are smeared by SC-1B type sol evenning machines on oxide layer plated film 1.Focused ion beam (FIB) is surface-treated condition,
Accelerating potential 15kV, sample processing time 10s, electric current I=80pA.Litho machine uses SUSS MicroTec ' s ELP300 photoetching
Machine, focused ion beam use 450 two-beam focused ion beam systems of FEI Helios.
(6) bottom wall of window one 3 of the high energy implanters by energetic ion injection mode after dimension enlargement is utilized
Inject arsenic ion with the surface of inverted cone type groove 4, formed by one 5a of inverted cone-shaped part and with one upper ends 5a of inverted cone-shaped part
The n-type doping layer 5 that one 5b of horizontal component of periphery connection is constituted.The doped chemical of n-type doping layer 5 is arsenic, doping concentration 3.0
×1016cm-3, the dosage of doping depth 1.5um, energy E=150keV, arsenic are ND (As)=1.3 × 1013cm–2.High energy from
Sub- implanter uses Varian EHP500 ion implantation apparatuses.
(7) layer of oxide layer plated film is plated on the surface of one 5b of one 5a of inverted cone-shaped part and horizontal component of n-type doping layer 5
26, oxide layer plated film 26 and the oxide layer plated film 1 of one 3 periphery of window after dimension enlargement are connected as one.Oxide layer is plated
Film 26 is deposited by thin film deposition system at a temperature of 300 degree.
(8) utilize photoresists to oxide layer plated film 26 into line mask, and cover part in mask surface to have the stone for ironing coating
English glass plate is exposed mask using litho machine, the mask and horizontal part on the surface of one 5a of removal inverted cone-shaped part
The Mask portion for not ironed coating and being covered on point surfaces 5b, also using focused ion beam to eliminate the position of mask into
Row surface treatment forms the window 27 that the size deviated towards 4 side of inverted cone type groove is 2.5um × 2.5um, so as to more
Simply open the lead contact hole 13 of following step.Photoresists are smeared by SC-1B type sol evenning machines on oxide layer plated film 26.It focuses
Ion beam (FIB) is surface-treated condition, accelerating potential 15kV, sample processing time 10s, electric current I=80pA.Litho machine uses
SUSS MicroTec ' s ELP300 litho machines, focused ion beam use 450 two-beam focused ion beam systems of FEI Helios.
(9)) utilize high energy implanters by energetic ion injection mode in the inverted cone-shaped part of n-type doping layer 5
The bottom wall of the surface of one 5a and window 27 injects boron ion, formed by two 8a of inverted conical part and with inverted cone-shaped part two
The p-type doped layer 8 that two 8b of horizontal component of the upper ends 8a side connection is constituted.The doped chemical of p-type doped layer 8 is boron, and doping is dense
Degree is 3.0 × 1016cm-3, the dosage of doping depth 0.25um, energy E=60keV, boron are ND (B)=1.0 × 1013cm–2。
High energy implanters use Varian EHP500 ion implantation apparatuses.
(10) it by the oxide layer plated film 26 of 27 periphery of the window of focused ion beam removal step (8), and is adulterated in p-type
The surface of two 8a of inverted conical part of layer 8, the upper surface of the other side of two 8a of inverted conical part, two 8b of horizontal component table
Face, the surface of one 5b of horizontal component of n-type doping layer 5 and the upper end face of p-type wafer 1 plate one layer of silicide barrier layer plated film 9,
And the silicide on one surfaces 5b of horizontal component of two 8b offsides of two 8b of horizontal component and horizontal component is stopped using photoresists
Layer plated film 9 into line mask, and mask surface cover part have the quartz glass plate for ironing coating, using litho machine to mask carry out
Exposure, the Mask portion that removal is not ironed coating and covered also carry out the position for eliminating mask using focused ion beam
Surface treatment, being respectively formed size in the upper surface of one 5b of horizontal component of two 8b offsides of two 8b of horizontal component and horizontal component is
The window 3 10 of 0.5um × 0.5um.Photoresists are applied to by SC-1B type sol evenning machines on silicide barrier layer plated film 9.It focuses
The operating voltage 30kV of ion beam, processing time 10s, electric current 40pA.Focused ion beam is poly- using 450 two-beams of FEI Helios
Pyrophosphate ion beam system.Litho machine uses SUSS MicroTec ' s ELP300 litho machines.
(11) in the upper of one 5b of horizontal component of two 8b offsides of two 8b of horizontal component of 3 10 bottom of window and horizontal component
Surface plates silicide barrier layer plated film 9 again, and anneals in annealing boiler tube, also focused ion beam is utilized to remove horizontal part
Divide the silicon of 9 peripheral region of silicide barrier layer plated film of the upper surface of one 5b of horizontal component of two 8b offsides of two 8b and horizontal component
Compound barrier layer plated film 9 and unreacted silicide.Silicide barrier layer plated film 9 is cobalt plated film, and unreacted silicide is oxygen
Compound and nitride.Nitrogen is passed through when annealing into annealing boiler tube, annealing temperature is 450 degree, generates CoSi2。
(12) it is coated with nitridation on the surface of 9 peripheral region of silicide barrier layer coated surface 9 and silicide barrier layer plated film
Layer plated film 11, is coated with oxide layer plated film 3 12, by focused ion beam in oxide layer plated film three on the surface of nitration case plated film 11
The position processing that silicide barrier layer plated film 11 is corresponded on 12 forms lead contact hole 13, and lead contact hole 13 penetrates through oxide layer plating successively
Film 3 12 and nitration case plated film 11 reach 9 surface of silicide barrier layer plated film.The operating voltage 30kV of focused ion beam, when processing
Between 10s, electric current 0.23nA.Nitration case plated film 11 is deposited by thin film deposition system at a temperature of 250 degree.Oxide layer plated film
3 12 are deposited by thin film deposition system at a temperature of 300 degree.
(13) metal coating 14 is plated in 13 position of lead contact hole at 3 12 surface of oxide layer plated film and two.Metal coating 14 is logical
Plating mode is crossed to be formed.Metal coating 14 is tungsten.
(14) by chemical-mechanical polishing mathing, the metal coating 14 on 3 12 surface of oxide layer plated film is polished, leaves and draws at two
The metal coating 14 of 13 position of line contact hole.
(15) oxide layer is plated on 14 surface of metal coating of 13 position of lead contact hole at 3 12 surface of oxide layer plated film and two
Plated film 4 15, using photoresists to oxide layer plated film 4 15 into line mask, and mask surface cover part have the stone for ironing coating
English glass plate is exposed mask using litho machine, the Mask portion that removal is not ironed coating and covered, while using poly-
Pyrophosphate ion beam is surface-treated the position for eliminating mask, metal coating 14 at 14 upside of metal coating and two at removal two
The oxide layer plated film 4 15 in outside retains the oxide layer plated film 4 15 between metal coating 14 at two, and is eliminating oxide layer
The position of plated film 4 15 plates line metal coating 16.Oxide layer plated film 4 15 is by thin film deposition system in 300 degree of temperature
Under deposit.Photoresists are applied to by SC-1B type sol evenning machines on oxide layer plated film 4 15.Line metal coating 16 passes through electricity
Plating mode is formed, and line metal coating 16 is metallic aluminium or metallic copper.The operating voltage 30kV of focused ion beam, processing time
10s, electric current 0.23nA.Litho machine uses SUSS MicroTec ' s ELP300 litho machines, focused ion beam to use FEI
450 two-beam focused ion beam systems of Helios.
Fig. 3 is inverted conical silicon array light emitting diode device and traditional planar structure light emitting diode device
The opto-electronic conversion test result figure of part, as can be seen from the figure under the irradiation of same light beam, under identical reversed bias voltage,
Conical silicon array light-emitting diode unit component absorbs light, and the value for being converted into electric current is apparently higher than traditional planar structure.Two
Kind structure is located on Si side by side, and adjacent close, about 5um, it is possible to think that light reaches the total amount phase of sample surfaces
Together.Therefore the difference of electric current is mainly different structure generation.Test result clearly shows that the light of back taper silicon array structure
Absorption efficiency is apparently higher than conventional planar.
Above in association with most preferred embodiment, invention has been described, but the invention is not limited in implementations disclosed above
Example, and modification, equivalent combinations that various essence according to the present invention carry out should be covered.
Claims (10)
1. a kind of enhanced cmos sensor light emitting diode structure preparation method, step include：
(1) RCA ablutions are utilized, by SC-1 cleaning solutions, SC-2 cleaning solutions, SC-3 cleaning solutions, acid and deionized water to p-type crystalline substance
Circle is cleaned, the oxide layer of stripping p-type wafer upper surface；
(2) in the p-type crystal column surface plating oxide layer plated film one for having removed surface oxide layer；
(3) utilize photoresists to oxide layer plated film one into line mask, and cover part in mask surface to have the quartzy glass for ironing coating
Glass plate is exposed mask using litho machine, and the Mask portion that removal is not ironed coating and covered also utilizes focused ion
Beam is surface-treated the position for eliminating mask, forms the window one that size is 1.5um × 1.5um；
(4) KOH for utilizing a concentration of 10%, corrodes downwards p-type wafer to one position of window, forms the rounding that depth is 1-3um
Tapered slot；
(5) it utilizes photoresists to the oxide layer plated film one of one periphery of window into line mask, and covers part in mask surface and iron
The quartz glass plate of coating is exposed mask using litho machine, the Mask portion that removal is not ironed coating and covered, also
The position for eliminating mask is surface-treated using focused ion beam, is 4um × 4um by the dimension enlargement of window one；
(6) arsenic is injected on the surface of the bottom wall of the window one by energetic ion injection mode after dimension enlargement and inverted cone type groove
Ion forms the N-type being made of inverted cone-shaped part one and the horizontal component one being connect with one upper end periphery of inverted cone-shaped part
Doped layer；
(7) in the inverted cone-shaped part one of n-type doping layer and the surface of horizontal component one plating layer of oxide layer plated film two, oxide layer
Plated film two and the oxide layer plated film one of one periphery of window after dimension enlargement are connected as one；
(8) utilize photoresists to oxide layer plated film two into line mask, and cover part in mask surface to have the quartzy glass for ironing coating
Glass plate is exposed mask using litho machine, one table of mask and horizontal component on the surface of removal inverted cone-shaped part one
The Mask portion for not ironed coating and being covered in face also carries out at surface the position for eliminating mask using focused ion beam
Reason forms the window two that the size deviated towards inverted cone type groove side is 2.5um × 2.5um；
(9) it is noted on the surface of the inverted cone-shaped part one of n-type doping layer and the bottom wall of window two by energetic ion injection mode
Enter boron ion, what formation was made of inverted conical part two and the horizontal component two being connect with two upper end side of inverted cone-shaped part
P-type doped layer；
(10) by the oxide layer plated film two of two periphery of the window of focused ion beam removal step (8), and falling in p-type doped layer
The surface of conical portion two, the upper surface of the other side of inverted conical part two, the surface of horizontal component two, n-type doping layer
Horizontal component one surface and p-type wafer upper end face plate one layer of silicide barrier layer plated film, and utilize photoresists pair
The silicide barrier layer plated film on one surface of horizontal component of two offside of horizontal component two and horizontal component is into line mask, and in mask
Locally there is the quartz glass plate for ironing coating in surface cover, mask is exposed using litho machine, removal is not ironed coating and covered
The Mask portion covered is also surface-treated the position for eliminating mask using focused ion beam, in two He of horizontal component
The upper surface of the horizontal component one of two offside of horizontal component is respectively formed the window three that size is 0.5um × 0.5um；
(11) silication is plated in the upper surface of the horizontal component one of two offside of horizontal component two and horizontal component of three bottom of window
Object barrier layer plated film, and anneal, also utilize the level of focused ion beam removal horizontal component two and two offside of horizontal component
The silicide barrier layer plated film and unreacted silicide of the silicide barrier layer plated film peripheral region of the upper surface of part one；
(12) it is coated with nitration case plated film on the surface of silicide barrier layer coated surface and silicide barrier layer plated film peripheral region,
It is coated with oxide layer plated film three on the surface of nitration case plated film, corresponds to silicide resistance on oxide layer plated film three by focused ion beam
The position processing of barrier plated film forms lead contact hole, and lead contact hole penetrates through oxide layer plated film three successively and nitration case plated film reaches silicon
Compound barrier layer coated surface；
(13) metal coating is plated in lead contact hole position at three surface of oxide layer plated film and two；
(14) by chemical-mechanical polishing mathing, the metal coating on three surface of oxide layer plated film is polished, leaves lead contact hole position at two
The metal coating set；
(15) oxide layer plated film four is plated on the metal coating surface of lead contact hole position at three surface of oxide layer plated film and two, utilizes
Photoresists to oxide layer plated film four into line mask, and mask surface cover part have the quartz glass plate for ironing coating, utilize light
Quarter, machine was exposed mask, the Mask portion that removal is not ironed coating and covered, while using focused ion beam to removal
The position of mask is surface-treated, the oxide layer plated film at removal two on the upside of metal coating and at two on the outside of metal coating
Four, retain the oxide layer plated film four between metal coating at two, and line gold is plated in the position for eliminating oxide layer plated film four
Belong to plated film.
2. enhanced cmos sensor light emitting diode structure preparation method as described in claim 1, it is characterised in that：
The oxide layer plated film one of step (2), the oxide layer plated film two of step (7), the oxide layer plated film three of step (12), step
(15) oxide layer plated film four is deposited by thin film deposition system at a temperature of 300 degree, the nitration case plating of step (12)
Film is deposited by thin film deposition system at a temperature of 250 degree, step (3), step (5), step (8), step (10) and step
Suddenly the photoresists of (15) are smeared by SC-1B type sol evenning machines.
3. enhanced cmos sensor light emitting diode structure preparation method as described in claim 1, it is characterised in that：
The SC-1 cleaning solutions of the step (1) are NH4OH/H2O2/H2O, SC-2 cleaning solution are HCI/H2O2/H2O, SC-3 cleaning solution is
H2SO4/H2O2/H2O, acid are HF.
4. enhanced cmos sensor light emitting diode structure preparation method as described in claim 1, it is characterised in that：
The p-type wafer material of the step (1) is silicon, and the thickness of p-type wafer material is 700um.
5. enhanced cmos sensor light emitting diode structure preparation method as described in claim 1, it is characterised in that：
The doped chemical of the n-type doping layer of the step (6) is arsenic, and doping concentration is 3.0 × 1016cm-3, doping depth 1.5um,
Energy is E=150keV, and the dosage of arsenic is ND (As)=1.3 × 1013cm-2。
6. enhanced cmos sensor light emitting diode structure preparation method as described in claim 1, it is characterised in that：
The doped chemical of the p-type doped layer of the step (9) is boron, and doping concentration is 3.0 × 1016cm-3, doping depth 0.25um,
Energy is E=60keV, and the dosage of boron is ND (B)=1.0 × 1013cm-2。
7. enhanced cmos sensor light emitting diode structure preparation method as described in claim 1, it is characterised in that：
The metal coating of the step (13) and the line metal coating of step (15) are formed by plating mode, step (15)
Line metal coating is metallic aluminium or metallic copper, and the metal coating of (13) is tungsten.
8. enhanced cmos sensor light emitting diode structure preparation method as described in claim 1, it is characterised in that：
The silicide barrier layer plated film of the step (11) is cobalt plated film, and unreacted silicide is oxide and nitride.
9. enhanced cmos sensor light emitting diode structure preparation method as described in claim 1, it is characterised in that：
The step (11) is passed through nitrogen when annealing, annealing temperature is 450 degree.
10. enhanced cmos sensor light emitting diode structure preparation method as described in claim 1, feature exist
In：The operating voltage 30kV, electric current 40pA of the focused ion beam of the step (10)；The work of the focused ion beam of step (12)
Make voltage 30kV, electric current 0.23nA；The operating voltage 30kV of the focused ion beam of step (15), electric current 0.23nA.
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