CN102931126A - Method for increasing narrow width effect of MOS (Metal Oxide Semiconductor) device - Google Patents
Method for increasing narrow width effect of MOS (Metal Oxide Semiconductor) device Download PDFInfo
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- CN102931126A CN102931126A CN2011102319018A CN201110231901A CN102931126A CN 102931126 A CN102931126 A CN 102931126A CN 2011102319018 A CN2011102319018 A CN 2011102319018A CN 201110231901 A CN201110231901 A CN 201110231901A CN 102931126 A CN102931126 A CN 102931126A
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Abstract
The invention provides a method for increasing narrow width effect of an MOS (Metal Oxide Semiconductor) device. According to the method provided by the invention, an isolation oxide layer surface layer of a shallow channel isolation structure is implanted with ions, a mixing barrier layer is formed on a contact interface between a semiconductor substrate and the shallow channel isolation structure after rapid annealing, ions in the semiconductor substrate, particularly in a narrow width channel area, are prevented from eroding in the isolation oxide layer of the shallow channel isolation structure, thus the narrow width effect of the MOS device is increased, the distribution of a threshold voltage can be improved, the carrier mobility can be increased, and the parastitism junction capacitance can be reduced.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to a kind of method of the MOS of raising device narrow width effect.
Background technology
Shallow trench isolation is from (Shallow Trench Isolation, STI) have that excellent isolation performance, smooth surface configuration, good anti-locking performance, almost nil field corrode, the characteristics such as less leakage current and junction capacitance, now become the main flow isolation technology of cmos device manufacturing process.
Usually, in cmos device technique, the threshold voltage vt of device increases along with narrowing down of channel width, i.e. narrow width effect (narrow width effect); But in shallow ditch groove separation process, the threshold voltage vt of device roll-offs along with narrowing down of channel width, is called anti-narrow width effect (reverse narrow width effect).Along with the cmos device size is constantly dwindled, particularly enter into 65nm and reach with lower node, anti-narrow width effect has become the key factor of restriction small size device performance.
In present cmos device manufacturing process, the boron ion that active area injects by sti structure edge and Semiconductor substrate inner boundary to the erosion of sti structure and the anisotropy diffusion effect of sti structure initiation active area ion itself, cause the cmos device of follow-up formation that serious anti-narrow width effect is arranged, cause threshold voltage variation large, the device parasitic capacitance increases, and operating rate descends.
Therefore, providing a kind of method that can improve MOS device narrow width effect, is the technical problem that those skilled in the art need to be resolved hurrily.
Summary of the invention
The object of the present invention is to provide a kind of method of the MOS of raising device narrow width effect, the distribution of energy improvement threshold voltage improves carrier mobility, reduces parasitic junction capacitance.
For addressing the above problem, the present invention proposes a kind of method of the MOS of raising device narrow width effect, and the method comprises the steps:
Semiconductor substrate with shallow trench is provided, and described shallow trench inwall is formed with lining oxide layer;
In described shallow trench, fill insulating oxide, and the described insulating oxide of planarization forms fleet plough groove isolation structure;
Form the patterned mask layer that exposes described fleet plough groove isolation structure in described Semiconductor substrate;
Take described patterned mask layer as mask, to the top layer ion of described fleet plough groove isolation structure;
Remove described patterned mask layer and short annealing, in described fleet plough groove isolation structure, form doping blocking layer.
Further, using plasma injects and the top layer ion of injection technology to described fleet plough groove isolation structure that recoil.
Further, when described MOS device was nmos device, the ion that injects to the top layer of described fleet plough groove isolation structure comprised at least a of boron ion, boron fluoride ion and indium ion.
Further, the energy that described boron ion, boron fluoride ion or indium ion inject is 1KeV～50KeV, and dosage is 1E15～1E16/cm
2
Further, when described MOS device was nmos device, the ion that injects to the top layer of described fleet plough groove isolation structure also comprised germanium ion or xenon ion.
Further, the energy of described germanium ion or xenon ion implantation is 1KeV～10KeV, and dosage is 5E14～5E15/cm
2
Further, 800 ℃～1000 ℃ of the temperature of described short annealing, the time is 30min～120min.
Further, 1000 ℃～1300 ℃ of the temperature of described short annealing, the time is 10s～1min, temperature gradient is 50 ℃/s～250 ℃/s.
Further, adopt the described Semiconductor substrate of high-aspect-ratio technique etching to form shallow trench.
Further, form before the shallow trench, also comprise: on described Semiconductor substrate, form successively pad oxide and corrosion barrier layer.
Further, described corrosion barrier layer is silicon nitride layer.
Further, adopt high-aspect-ratio technique in described shallow trench, to fill insulating oxide.
Further, adopt high density plasma chemical vapor deposition technique in described shallow trench, to fill insulating oxide.
Compared with prior art, the method of raising MOS device narrow width effect provided by the invention, by ion in the insulating oxide top layer of described fleet plough groove isolation structure, contact interface at Semiconductor substrate and fleet plough groove isolation structure after the short annealing forms one deck doping blocking layer, stopped in the Semiconductor substrate, particularly the ion erosion in the narrow width channel region is in the insulating oxide of fleet plough groove isolation structure, thereby improve MOS device narrow width effect, the distribution of improvement threshold voltage, improve carrier mobility, reduce parasitic junction capacitance.
Description of drawings
Fig. 1 is the method flow diagram of the raising MOS device narrow width effect of one embodiment of the invention;
Fig. 2 A to 2G is the cross-sectional view of device corresponding to each step in the method for raising MOS device narrow width effect of one embodiment of the invention.
Embodiment
The invention provides a kind of method of the MOS of raising device narrow width effect, the method comprises the steps:
Semiconductor substrate with shallow trench is provided, and described shallow trench inwall is formed with lining oxide layer;
In described shallow trench, fill insulating oxide, and the planarization insulating oxide forms fleet plough groove isolation structure;
Form the patterned mask layer that exposes described fleet plough groove isolation structure in described Semiconductor substrate;
Take described patterned mask layer as mask, to the top layer ion of described fleet plough groove isolation structure;
Remove described patterned mask layer and short annealing, in fleet plough groove isolation structure, form doping blocking layer.
Be described in further detail below in conjunction with the manufacture method of the drawings and specific embodiments to the autoregistration channel MOS transistor of the present invention's proposition.
As shown in Figure 1, present embodiment is finished by step shown in the S101 to S107, is explained in detail below in conjunction with the method for the cross-sectional view shown in Fig. 2 A～2G to above-mentioned raising MOS device narrow width effect.
S101 provides Semiconductor substrate, forms successively pad oxide and corrosion barrier layer on described Semiconductor substrate.
Please refer to Fig. 2 A, Semiconductor substrate 200 is provided, described Semiconductor substrate 200 can be the semi-conducting materials such as silicon, silicon-on-insulator, germanium.Can form pad oxide 201 by thermal oxidation method on Semiconductor substrate 200, described pad oxide 201 can be silica.Afterwards, can adopt low-pressure chemical vapor deposition or plasma ion assisted deposition method to form corrosion barrier layer 202 at pad oxide 201, be used for subsequent etching process neonychium oxide layer 201, described corrosion barrier layer 202 can be silicon nitride.
S102, the described corrosion barrier layer of etching, pad oxide and part semiconductor substrate form shallow trench successively.
Please refer to Fig. 2 B, in this step, spin coating photoresist layer (not shown) at first, more described photoresist layer is carried out exposure imaging after, define the shallow trench figure.Then take patterned photoresist layer as mask, adopt dry etching and high-aspect-ratio technique (HARP) the successively described corrosion barrier layer 202 of etching, pad oxide 201 and part semiconductor substrate 200, to form shallow trench 203a.The shallow trench 203a that adopts high-aspect-ratio technique (HARP) to form, pattern can be V-arrangement wide at the top and narrow at the bottom or inverted trapezoidal, for groove isolation construction before the follow-up formation is to fill insulation oxide to provide good basis.
S103 forms lining oxide layer at described shallow trench inwall.
Please refer to Fig. 2 C, can adopt chemical vapour deposition technique cvd silicon oxide in the shallow trench 203a to form lining oxide layer 204; Also can adopt thermal oxidation method, the silicon materials of the Semiconductor substrate 200 in the oxidation shallow trench 203a form the lining oxide layer 204 that covers described shallow trench inwall.
S104 fills insulating oxide in described shallow trench, the described insulating oxide of planarization forms fleet plough groove isolation structure to described corrosion barrier layer top.
Please refer to Fig. 2 D, can be in the shallow trench 203b that is formed with lining oxide layer 204 deposition conventional be used in shallow trench isolation from insulating material, to obtain to fill up the insulating oxide 203 of shallow trench 203b, for example, insulating material can be made of the oxide that the oxide that is selected from O3-TEOS (tetraethoxysilane), HDP (high-density plasma), SA (inferior atmosphere) CVD forms, and also can be silicon dioxide.Preferably, adopt during filling high-aspect-ratio technique or high density plasma CVD (HDPCVD) technique in described shallow trench, to fill insulating oxide.Then, the described insulating oxide of planarization forms fleet plough groove isolation structure to described corrosion barrier layer 202 tops, and fleet plough groove isolation structure comprises lining oxide layer 204 and fills the also insulating barrier 203 of planarization.
S105 forms the patterned mask layer that exposes described fleet plough groove isolation structure at described corrosion barrier layer.
Please refer to Fig. 2 E, can by spin coating photoresist layer and patterning on described corrosion barrier layer 202, expose the patterned mask layer 205 of described fleet plough groove isolation structure with formation.
S106 is take described patterned mask layer as mask, to the top layer ion of described fleet plough groove isolation structure.
Please refer to Fig. 2 F, take described patterned mask layer 205 as mask, to the top layer ion of described fleet plough groove isolation structure.Preferably, can inject and the top layer ion of injection technology to described fleet plough groove isolation structure that recoil by using plasma.When described MOS device is nmos device, the ion 206a that injects to the top layer of described fleet plough groove isolation structure comprises at least a of boron ion, boron fluoride ion and indium ion, the energy that described boron ion, boron fluoride ion or indium ion inject is 1KeV～50KeV, and dosage is 1E15～1E16/cm
2When described MOS device is nmos device, the ion that injects to the top layer of described fleet plough groove isolation structure also comprises germanium ion or xenon ion, to increase the compression stress of fleet plough groove isolation structure, further improve carrier mobility, reduce parasitic junction capacitance, improve narrow width effect, wherein, the energy of described germanium ion or xenon ion implantation is 1KeV～10KeV, and dosage is 5E14～5E15/cm
2
S107 removes described patterned mask layer and short annealing, forms doping blocking layer in described fleet plough groove isolation structure.
Please refer to Fig. 2 G, remove described patterned mask layer 205 and short annealing, in described fleet plough groove isolation structure, form doping blocking layer 206.The purpose of carrying out short annealing is to make the ion diffusion of injection even, effectively be diffused into the interface of lining oxide layer 204 and Semiconductor substrate 200, so that doping blocking layer 206 can effectively stop in the Semiconductor substrate 200, particularly the ion erosion in the narrow width channel region is in the insulating oxide 203 of fleet plough groove isolation structure, thereby the distribution of improvement threshold voltage, improve carrier mobility, reduce parasitic junction capacitance.Can adopt temperature when carrying out short annealing is that 800 ℃～1000 ℃, time are the mode of 30min～120min, also can temperature 1000 ℃～1300 ℃, and the time is 10s～1min, temperature gradient is the mode of 50 ℃/s～250 ℃/s.
In sum, the method of raising MOS device narrow width effect provided by the invention, by ion in the insulating oxide top layer of described fleet plough groove isolation structure, contact interface at Semiconductor substrate and fleet plough groove isolation structure after the short annealing forms one deck doping blocking layer, stopped in the Semiconductor substrate, particularly the ion erosion in the narrow width channel region is in the insulating oxide of fleet plough groove isolation structure, thereby the distribution of improvement threshold voltage, improve carrier mobility, reduce parasitic junction capacitance.
Obviously, those skilled in the art can carry out various changes and modification to invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (13)
1. a method that improves MOS device narrow width effect is characterized in that, comprising:
Semiconductor substrate with shallow trench is provided, and described shallow trench inwall is formed with lining oxide layer;
In described shallow trench, fill insulating oxide, and the described insulating oxide of planarization forms fleet plough groove isolation structure;
Form the patterned mask layer that exposes described fleet plough groove isolation structure in described Semiconductor substrate;
Take described patterned mask layer as mask, to the top layer ion of described fleet plough groove isolation structure;
Remove described patterned mask layer and short annealing, in described fleet plough groove isolation structure, form doping blocking layer.
2. the method for raising MOS device narrow width effect as claimed in claim 1 is characterized in that, using plasma injects and the top layer ion of injection technology to described fleet plough groove isolation structure that recoil.
3. the method for raising as claimed in claim 2 MOS device narrow width effect, it is characterized in that, when described MOS device was nmos device, the ion that injects to the top layer of described fleet plough groove isolation structure comprised at least a of boron ion, boron fluoride ion and indium ion.
4. the method for raising MOS device narrow width effect as claimed in claim 3 is characterized in that the energy that described boron ion, boron fluoride ion or indium ion inject is 1KeV～50KeV, and dosage is 1E15～1E16/cm
2
5. the method for raising MOS device narrow width effect as claimed in claim 3 is characterized in that, when described MOS device was nmos device, the ion that injects to the top layer of described fleet plough groove isolation structure also comprised germanium ion or xenon ion.
6. the method for raising MOS device narrow width effect as claimed in claim 5 is characterized in that the energy of described germanium ion or xenon ion implantation is 1KeV～10KeV, and dosage is 5E14～5E15/cm
2
7. the method for raising MOS device narrow width effect as claimed in claim 1 is characterized in that, 800 ℃～1000 ℃ of the temperature of described short annealing, and the time is 30min～120min.
8. the method for raising as claimed in claim 1 MOS device narrow width effect is characterized in that, 1000 ℃～1300 ℃ of the temperature of described short annealing, and the time is 10s～1min, temperature gradient is 50 ℃/s～250 ℃/s.
9. the method for raising MOS device narrow width effect as claimed in claim 1 is characterized in that, adopts the described Semiconductor substrate of high-aspect-ratio technique etching to form shallow trench.
10. the method for raising MOS device narrow width effect as claimed in claim 9 is characterized in that, forms before the shallow trench, also comprises:
On described Semiconductor substrate, form successively pad oxide and corrosion barrier layer.
11. the method for raising MOS device narrow width effect as claimed in claim 10 is characterized in that described corrosion barrier layer is silicon nitride layer.
12. the method for raising MOS device narrow width effect as claimed in claim 9 is characterized in that, adopts high-aspect-ratio technique to fill insulating oxide in described shallow trench.
13. the method such as claim 1 or 12 described raising MOS device narrow width effects is characterized in that, adopts high density plasma chemical vapor deposition technique to fill insulating oxide in described shallow trench.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105355598A (en) * | 2015-10-15 | 2016-02-24 | 武汉新芯集成电路制造有限公司 | Method for restraining reverse narrow width effect and manufacturing CMOS |
| CN108767072A (en) * | 2018-05-31 | 2018-11-06 | 广州锋尚电器有限公司 | Enhanced cmos sensor light emitting diode structure preparation method |
| CN109524346A (en) * | 2018-10-19 | 2019-03-26 | 武汉新芯集成电路制造有限公司 | Fleet plough groove isolation structure and its manufacturing method |
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| US20020081797A1 (en) * | 2000-12-21 | 2002-06-27 | Brady Frederick T. | Elimination of narrow device width effects in complementary metal oxide semiconductor (CMOS) devices |
| US20070105336A1 (en) * | 2005-11-10 | 2007-05-10 | Shinji Takeoka | Semiconductor device and method for fabricating the same |
| CN101355055A (en) * | 2007-07-25 | 2009-01-28 | 东部高科股份有限公司 | Flash memory device and method of manufacturing the same |
| US20090189246A1 (en) * | 2008-01-30 | 2009-07-30 | Hsiao-Che Wu | Method of forming trench isolation structures and semiconductor device produced thereby |
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2011
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020081797A1 (en) * | 2000-12-21 | 2002-06-27 | Brady Frederick T. | Elimination of narrow device width effects in complementary metal oxide semiconductor (CMOS) devices |
| US20070105336A1 (en) * | 2005-11-10 | 2007-05-10 | Shinji Takeoka | Semiconductor device and method for fabricating the same |
| CN101355055A (en) * | 2007-07-25 | 2009-01-28 | 东部高科股份有限公司 | Flash memory device and method of manufacturing the same |
| US20090189246A1 (en) * | 2008-01-30 | 2009-07-30 | Hsiao-Che Wu | Method of forming trench isolation structures and semiconductor device produced thereby |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105355598A (en) * | 2015-10-15 | 2016-02-24 | 武汉新芯集成电路制造有限公司 | Method for restraining reverse narrow width effect and manufacturing CMOS |
| CN108767072A (en) * | 2018-05-31 | 2018-11-06 | 广州锋尚电器有限公司 | Enhanced cmos sensor light emitting diode structure preparation method |
| CN108767072B (en) * | 2018-05-31 | 2019-11-08 | 广州锋尚电器有限公司 | Enhanced cmos sensor light emitting diode structure preparation method |
| CN109524346A (en) * | 2018-10-19 | 2019-03-26 | 武汉新芯集成电路制造有限公司 | Fleet plough groove isolation structure and its manufacturing method |
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Application publication date: 20130213 |