CN102110636A - Methods for improving reverse narrow channel effect and manufacturing metal oxide semiconductor (MOS) transistor - Google Patents
Methods for improving reverse narrow channel effect and manufacturing metal oxide semiconductor (MOS) transistor Download PDFInfo
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- CN102110636A CN102110636A CN2009102474181A CN200910247418A CN102110636A CN 102110636 A CN102110636 A CN 102110636A CN 2009102474181 A CN2009102474181 A CN 2009102474181A CN 200910247418 A CN200910247418 A CN 200910247418A CN 102110636 A CN102110636 A CN 102110636A
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Abstract
The invention provides methods for improving a reverse narrow channel effect and manufacturing a metal oxide semiconductor (MOS) transistor. The method for improving the reverse narrow channel effect comprises the following steps of: providing a semiconductor substrate on which shallow trenches are formed in turn; forming a lining oxide layer on the inner wall of each shallow trench; and performing angular ion implantation on the side wall of the shallow trench. By the method, the reverse narrow channel effect of the MOS transistor is effectively improved.
Description
Technical field
The present invention relates to the manufacturing field of semiconductor device, relate in particular to the method for in making MOS transistor technology, improving reversed narrow-path effect.
Background technology
, speed faster device development littler along with semi-conductor industry court, the feature lateral dimension and the degree of depth of semiconductor device reduce gradually, require source/drain electrode and source/drain electrode extension area (Source/Drain Extension) correspondingly to shoal.Current source/drain junction nearly all is with the ion implantation formation of mixing.Along with the size of electronic component is dwindled, as how the technology transistorized source electrode of manufacturing Metal-oxide-semicondutor (MOS) and the drain electrode of millimicron are present and the developing direction of following ion implantation technique.
But along with the shortening of grid length, in ion implantation process, a lot of negative effects that influence the transistor operate as normal have appearred, such as reversed narrow-path effect (RNCE).
Reversed narrow-path effect (RNCE) is meant at shallow trench isolation under (STI, shallow trench isolation) technology, the threshold voltage of device (Vt) with channel width reduce and the effect of successively decreasing.This effect is one of key factor of restriction small size device application.
In conventional at present metal-oxide-semiconductor field effect transistor manufacturing process, 10 (as shown in Figure 1) because caving in can appear in the fleet plough groove isolation structure edge, the size of the active area between the isolation structure is elongated with respect to preliminary dimension.Main transistor (shown in Fig. 2 heavy line) both sides of causing follow-up formation have like this added two parasitic transistors (shown in Fig. 2 frame of broken lines) that threshold voltage is relatively low near Semiconductor substrate and fleet plough groove isolation structure intersection local in parallel, in the main transistor course of work, can produce comparatively serious reversed narrow-path effect, this transistorized threshold voltage can descend.
Because existing small size device (0.18 μ m is following) is easy to generate reversed narrow-path effect in making, and causes threshold voltage variation big, the parasitic junction capacitance of device increases, and operating rate descends.
Summary of the invention
The problem that the present invention solves provides a kind of method of improving reversed narrow-path effect and making MOS transistor, prevents reversed narrow-path effect.
The invention provides a kind of method of improving reversed narrow-path effect, comprising: the Semiconductor substrate that is formed with shallow trench successively is provided, and described shallow trench inwall is formed with lining oxide layer; The shallow trench sidewall is carried out angled ion to be injected.
Optionally, to inject the angle with the Semiconductor substrate vertical direction be 20 °～45 ° for described ion.Described ion implantation energy is smaller or equal to 100Kev, and implantation dosage is smaller or equal to 10
14/ cm
2
The present invention also provides a kind of method of making MOS transistor, comprising: the Semiconductor substrate that is formed with shallow trench successively is provided, and described shallow trench inwall is formed with lining oxide layer; The shallow trench sidewall is carried out angled ion to be injected; In shallow trench, fill full insulating oxide; Remove corrosion barrier layer and pad oxide, form fleet plough groove isolation structure, the zone between the described fleet plough groove isolation structure is an active area; Form gate dielectric layer and grid successively at active area, described gate dielectric layer and grid constitute grid structure; With the grid structure is mask, advances ion and inject formation source/drain electrode extension area in the Semiconductor substrate of grid both sides; After the grid structure both sides form side wall, formation source/drain electrode in the Semiconductor substrate of grid structure and side wall both sides.
Optionally, to inject the angle with the Semiconductor substrate vertical direction be 20 °～45 ° for described ion.Described ion implantation energy is smaller or equal to 100Kev, and implantation dosage is smaller or equal to 10
14/ cm
2
Optionally, described MOS crystal conduction type is the n type, and injecting ion is p type ion.
Optionally, described MOS crystal conduction type is the p type, and injecting ion is n type ion.
Compared with prior art, the present invention has the following advantages: carry out angled ion at the shallow trench sidewall and inject, promptly the sidewall at active area carries out the ion injection, in order to adjust the cut-in voltage of parasitic mos transistor, and then make the cut-in voltage of MOS transistor reach desired value, improve reversed narrow-path effect, the threshold voltage (Vt) that makes device with channel width reduce and the trend of successively decreasing slow down.
Description of drawings
Fig. 1 is the fleet plough groove isolation structure schematic diagram that existing technology forms;
Fig. 2 is the schematic diagram of the generation reversed narrow-path effect MOS transistor of existing technology formation;
Fig. 3 is the embodiment flow chart that the present invention improves reversed narrow-path effect;
Fig. 4 is the embodiment flow chart that the present invention forms MOS transistor;
Fig. 5 to Fig. 8 is that the present invention forms the embodiment schematic diagram that improves reversed narrow-path effect in the MOS transistor technology;
Fig. 9 is the design sketch of the MOS transistor threshold voltage of the present invention and the formation of existing technology with the active area change in size.
Embodiment
Existing technology because depressed phenomenon can appear in the fleet plough groove isolation structure edge that forms, causes the active area size greater than preliminary dimension in making MOS transistor technology.The transistor both sides of causing follow-up formation are near local in parallel two the parasitic transistors that threshold voltage relatively low of Semiconductor substrate with the fleet plough groove isolation structure intersection, in the transistor course of work, can produce comparatively serious reversed narrow-path effect, make reducing of transistorized threshold voltage channel width and speed subtracts.
The invention provides a kind of method of improving reversed narrow-path effect, as shown in Figure 3, execution in step S1 provides the Semiconductor substrate that is formed with shallow trench successively, and described shallow trench inwall is formed with lining oxide layer; Execution in step S2 carries out angled ion to the shallow trench sidewall and injects.
The present invention improves idiographic flow such as Fig. 4 of reversed narrow-path effect in forming the MOS transistor process, execution in step S11 provides the Semiconductor substrate that is formed with shallow trench successively, and described shallow trench inwall is formed with lining oxide layer; Execution in step S12 carries out angled ion to the shallow trench sidewall and injects; Execution in step S13 fills full insulating oxide in shallow trench; Execution in step S14 removes corrosion barrier layer and pad oxide, forms fleet plough groove isolation structure, and the zone between the described fleet plough groove isolation structure is an active area; Execution in step S15 forms gate dielectric layer and grid successively at active area, and described gate dielectric layer and grid constitute grid structure; Execution in step S16 is a mask with the grid structure, advances ion and inject formation source/drain electrode extension area in the Semiconductor substrate of grid both sides; Execution in step S17, after the grid structure both sides form side wall, formation source/drain electrode in the Semiconductor substrate of grid structure and side wall both sides.
The present invention carries out angled ion at the shallow trench sidewall and injects, promptly the sidewall at active area carries out the ion injection, in order to adjust the cut-in voltage of parasitic mos transistor, and then make the cut-in voltage of MOS transistor reach desired value, improve reversed narrow-path effect, the threshold voltage (Vt) that makes device with channel width reduce and the trend of successively decreasing slow down.
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
Fig. 5 to Fig. 8 is that the present invention forms the embodiment schematic diagram that improves reversed narrow-path effect in the MOS transistor technology.As shown in Figure 5, provide Semiconductor substrate 200, wherein Semiconductor substrate 200 can be semi-conducting materials such as silicon, germanium or silicon-on-insulator; Form pad oxide 202 on Semiconductor substrate 200, the method that forms pad oxide 202 is a thermal oxidation method, and the material of pad oxide 202 is specially silica; On pad oxide 202, form corrosion barrier layer 204 with Low Pressure Chemical Vapor Deposition or plasma auxiliary chemical vapor deposition method; the pad oxide 202 that is used for below the protection of subsequent etch process is avoided corrosion; wherein the material of corrosion barrier layer 204 is a silicon nitride, generally adopts chemical vapour deposition technique to form.
Continuation forms photoresist layer (not shown) with reference to figure 5 with spin-coating method on corrosion barrier layer 204, after exposure imaging technology, define the shallow trench figure.With the photoresist layer is mask, along the shallow trench figure, with dry etching method etching corrosion barrier layer 204 and pad oxide 202 to exposing Semiconductor substrate 200; After removing photoresist layer with ashing method, be mask with corrosion barrier layer 204 and pad oxide 202, with dry etching method etching semiconductor substrate 200, form shallow trench.
As shown in Figure 6, adopt the silicon materials of the Semiconductor substrate 200 in the thermal oxidation method oxidation shallow trench, form lining oxide layer 206, the material of described lining oxide layer 206 is a silica.
Continuation is carried out angled ion to the shallow trench sidewall and is injected with reference to figure 6, is about to the active area sidewall between the ion injection shallow trench.In technical process, ion is injected set the wherein sidewall that an angle is injected shallow trench earlier; Adjust direction then, ion is injected in another sidewall of shallow trench again.
In the present embodiment, described ion injects the angle with the Semiconductor substrate vertical direction, and dosage and energy that ion injects are to determine according to the thickness of active area width, corrosion barrier layer 204.
As an example, under the process conditions of 0.18 μ m, the angle of ion injection is 20 °～45 ° usually.Described ion implantation energy is smaller or equal to 100Kev, more than or equal to 10Kev; Ion implantation dosage is smaller or equal to 10
14/ cm
2, more than or equal to 10
8/ cm
2
In the present embodiment, forming the PMOS transistor area, what inject in the Semiconductor substrate 200 of shallow trench sidewall is n type ion.Forming nmos transistor region, what inject in the Semiconductor substrate 200 of shallow trench sidewall is p type ion.When the PMOS transistor area is injected ion, need form photoresist layer at nmos transistor region and cover, when nmos transistor region injects ion, need form photoresist layer in the PMOS transistor area and cover.
As shown in Figure 7, by using high density plasma CVD method (HDPCVD) or high-aspect-ratio technology (HARP, High Aspect Ratio Process) on corrosion barrier layer 204, forms insulating oxide 208, and with the full shallow trench of insulating oxide 208 fillings, the preferred silica of described insulating oxide 208 materials.After having deposited insulating oxide 208, insulating oxide 208 is carried out planarization to exposing corrosion barrier layer 204.Then, remove corrosion barrier layer 204 and pad oxide 202, form fleet plough groove isolation structure with wet etching method.
As shown in Figure 8, form gate dielectric layer 210 and grid 212 successively on the active area Semiconductor substrate 200 between the fleet plough groove isolation structure, described gate dielectric layer 210 constitutes grid structure with grid 212.The concrete technology that forms is: form gate dielectric layer 210 with thermal oxidation method or chemical vapour deposition technique on Semiconductor substrate 200; Then on gate dielectric layer, form polysilicon layer with chemical vapour deposition technique or low-voltage plasma body chemical vapor phase growing or plasma enhanced chemical vapor deposition technology; On polysilicon layer, form photoresist layer, the definition gate pattern; With the photoresist layer is mask, and etch polysilicon layer and gate dielectric layer are to exposing Semiconductor substrate; Photoresist layer is removed in ashing.
Continuation is mask with reference to figure 8 with the grid structure, carries out ion and inject formation source/drain electrode extension area 216 in the Semiconductor substrate 200 of grid structure both sides.Form side wall 214 in the grid structure both sides, the material of described side wall 214 can for a kind of in silica, silicon nitride, the silicon oxynitride or they constitute.With grid structure and side wall 214 is mask, carries out ion and inject formation source/drain electrode 218 in the Semiconductor substrate 200 of grid structure both sides.At last, Semiconductor substrate 200 is carried out annealing in process, make the ions diffusion of injection even.
Fig. 9 is the design sketch of the MOS transistor threshold voltage of the present invention and the formation of existing technology with the active area change in size.As shown in Figure 9, existing technology because depressed phenomenon can appear in the fleet plough groove isolation structure edge that forms, causes the active area size greater than preliminary dimension in making MOS transistor technology; The transistor both sides of causing follow-up formation are near local in parallel two the parasitic transistors that threshold voltage relatively low of Semiconductor substrate with the fleet plough groove isolation structure intersection, in the transistor course of work, can produce comparatively serious reversed narrow-path effect, the threshold voltage (Vt) that makes device with the active area size reduce and successively decrease (square line among the figure).The present invention carries out angled ion at the shallow trench sidewall and injects, promptly the sidewall at active area carries out the ion injection, in order to adjust the cut-in voltage of parasitic mos transistor, and then make the cut-in voltage of MOS transistor reach desired value, the reversed narrow-path effect of making the life better, shown in figure intermediate cam shape line, the threshold voltage of device (Vt) with the active area size reduce and the degree that thereupon descends is slower.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (8)
1. a method of improving reversed narrow-path effect is characterized in that, comprising:
The Semiconductor substrate that is formed with shallow trench successively is provided, and described shallow trench inwall is formed with lining oxide layer;
The shallow trench sidewall is carried out angled ion to be injected.
2. according to the described method of improving reversed narrow-path effect of claim 1, it is characterized in that described ion injects and the angle of Semiconductor substrate vertical direction is 20 °～45 °.
3. according to the described method of improving reversed narrow-path effect of claim 2, it is characterized in that described ion implantation energy is smaller or equal to 100Kev, implantation dosage is smaller or equal to 10
14/ cm
2
4. a method of making MOS transistor is characterized in that, comprising:
The Semiconductor substrate that is formed with shallow trench successively is provided, and described shallow trench inwall is formed with lining oxide layer;
The shallow trench sidewall is carried out angled ion to be injected;
In shallow trench, fill full insulating oxide;
Remove corrosion barrier layer and pad oxide, form fleet plough groove isolation structure, the zone between the described fleet plough groove isolation structure is an active area;
Form gate dielectric layer and grid successively at active area, described gate dielectric layer and grid constitute grid structure;
With the grid structure is mask, advances ion and inject formation source/drain electrode extension area in the Semiconductor substrate of grid both sides;
After the grid structure both sides form side wall, formation source/drain electrode in the Semiconductor substrate of grid structure and side wall both sides.
5. according to the method for the described making MOS transistor of claim 4, it is characterized in that described ion injects and the angle of Semiconductor substrate vertical direction is 20 °～45 °.
6. according to the method for the described making MOS transistor of claim 5, it is characterized in that described ion implantation energy is smaller or equal to 100Kev, implantation dosage is smaller or equal to 10
14/ cm
2
7. according to the method for the described making MOS transistor of claim 6, it is characterized in that described MOS crystal conduction type is the n type, injecting ion is p type ion.
8. according to the method for the described making MOS transistor of claim 6, it is characterized in that described MOS crystal conduction type is the p type, injecting ion is n type ion.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009102474181A CN102110636A (en) | 2009-12-29 | 2009-12-29 | Methods for improving reverse narrow channel effect and manufacturing metal oxide semiconductor (MOS) transistor |
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|---|---|---|---|
| CN2009102474181A CN102110636A (en) | 2009-12-29 | 2009-12-29 | Methods for improving reverse narrow channel effect and manufacturing metal oxide semiconductor (MOS) transistor |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103579078A (en) * | 2012-07-31 | 2014-02-12 | 上海华虹Nec电子有限公司 | Method for restraining reverse narrow channel effect in shallow trench isolation technology |
| CN103579079A (en) * | 2012-07-31 | 2014-02-12 | 上海华虹Nec电子有限公司 | Method for restraining bimodal effect in shallow groove isolation technology |
| CN105244260A (en) * | 2015-10-26 | 2016-01-13 | 武汉新芯集成电路制造有限公司 | Semiconductor structure and preparation method |
| CN109037144A (en) * | 2018-08-01 | 2018-12-18 | 武汉新芯集成电路制造有限公司 | The method for improving diffusion length effect and making MOS transistor |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5960276A (en) * | 1998-09-28 | 1999-09-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Using an extra boron implant to improve the NMOS reverse narrow width effect in shallow trench isolation process |
| US6245639B1 (en) * | 1999-02-08 | 2001-06-12 | Taiwan Semiconductor Manufacturing Company | Method to reduce a reverse narrow channel effect for MOSFET devices |
-
2009
- 2009-12-29 CN CN2009102474181A patent/CN102110636A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5960276A (en) * | 1998-09-28 | 1999-09-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Using an extra boron implant to improve the NMOS reverse narrow width effect in shallow trench isolation process |
| US6245639B1 (en) * | 1999-02-08 | 2001-06-12 | Taiwan Semiconductor Manufacturing Company | Method to reduce a reverse narrow channel effect for MOSFET devices |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103579078A (en) * | 2012-07-31 | 2014-02-12 | 上海华虹Nec电子有限公司 | Method for restraining reverse narrow channel effect in shallow trench isolation technology |
| CN103579079A (en) * | 2012-07-31 | 2014-02-12 | 上海华虹Nec电子有限公司 | Method for restraining bimodal effect in shallow groove isolation technology |
| CN103579079B (en) * | 2012-07-31 | 2016-10-19 | 上海华虹宏力半导体制造有限公司 | The method of double-hump effect in suppression shallow ditch groove separation process |
| CN105244260A (en) * | 2015-10-26 | 2016-01-13 | 武汉新芯集成电路制造有限公司 | Semiconductor structure and preparation method |
| CN109037144A (en) * | 2018-08-01 | 2018-12-18 | 武汉新芯集成电路制造有限公司 | The method for improving diffusion length effect and making MOS transistor |
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Application publication date: 20110629 |