CN107591330B - Method for forming semiconductor structure - Google Patents
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- CN107591330B CN107591330B CN201610531756.8A CN201610531756A CN107591330B CN 107591330 B CN107591330 B CN 107591330B CN 201610531756 A CN201610531756 A CN 201610531756A CN 107591330 B CN107591330 B CN 107591330B
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Abstract
The invention provides a method for forming a semiconductor structure, which comprises the following steps: providing a substrate, wherein the substrate comprises a first transistor area and a second transistor area, and the first transistor area and the second transistor area of the substrate comprise a substrate and a fin part positioned on the substrate; forming a first sacrificial layer on the first transistor area substrate, wherein the surface of the first sacrificial layer is lower than the top surface of the fin part; performing first ion implantation on the first sacrificial layer of the first transistor area; removing the first sacrificial layer after the first ion implantation; and after removing the first sacrificial layer, carrying out annealing treatment. In the annealing process, the first sacrificial layer is removed, and doped ions in the first sacrificial layer cannot diffuse into the fins of the second transistor area, so that the performance of a transistor formed in the second transistor area is not affected. Therefore, the forming method can improve the performance of the semiconductor structure.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a forming method of a semiconductor structure.
Background
With the increase of the integration level of semiconductor devices, the critical dimension of transistors is continuously reduced, and the reduction of the critical dimension means that a larger number of transistors can be arranged on a chip, thereby improving the performance of the devices. However, with the rapid decrease of the transistor size, the thickness of the gate dielectric layer and the operating voltage cannot be changed correspondingly, so that the difficulty of suppressing the short channel effect is increased, and the channel leakage current of the transistor is increased.
The gate of a Fin-Field-Effect Transistor (FinFET) is a fork-shaped 3D structure similar to a Fin. A FinFET channel protrudes out of the surface of a substrate to form a fin part, and a grid electrode covers the top surface and the side wall of the fin part, so that an inversion layer is formed on each side of the channel, and the multi-side control circuit of the fin part can be switched on and switched off. The design can increase the control of the gate to the channel region, thereby well inhibiting the short-channel effect of the transistor. The short channel effect of the fin field effect transistor still exists.
In order to further reduce the influence of the short channel effect on the semiconductor device, the channel leakage current is reduced. One approach is to reduce the possibility of drain-source punch-through and reduce the short channel effect by performing a punch-through prevention implant into the bottom of the fin.
However, the method of forming the semiconductor structure is susceptible to affecting the performance of the formed semiconductor structure.
Disclosure of Invention
The invention solves the problem of providing a method for forming a semiconductor, which can improve the performance of a semiconductor structure.
To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein the substrate comprises a first transistor area and a second transistor area, and the first transistor area and the second transistor area of the substrate comprise a substrate and a fin part positioned on the substrate; forming a first sacrificial layer on the first transistor area substrate, wherein the surface of the first sacrificial layer is lower than the top surface of the fin part; carrying out first ion implantation on the first sacrificial layer; removing the first sacrificial layer after the first ion implantation; and after removing the first sacrificial layer, carrying out annealing treatment.
Optionally, the first sacrificial layer is an anti-reflective coating, a silicon oxide layer, or a silicon nitride layer.
Optionally, before performing ion implantation on the first sacrificial layer in the first transistor region, the method further includes: and forming a second sacrificial layer in the second transistor region, wherein the second sacrificial layer covers the top and the side wall of the fin part of the second transistor region.
Optionally, the first sacrificial layer and the second sacrificial layer are made of the same material.
Optionally, the step of forming the first sacrificial layer and the second sacrificial layer includes: forming an initial sacrificial layer on the first transistor area and the second transistor area, wherein the surface of the initial sacrificial layer is higher than the top surface of the fin part; and removing the initial sacrificial layer with partial thickness of the first transistor area, forming a first sacrificial layer in the first transistor area, and forming a second sacrificial layer in the second transistor area.
Optionally, the process of removing the initial sacrificial layer of the thickness of the first transistor region includes: dry etching or wet etching.
Optionally, the process of forming the initial sacrificial layer includes: a spin-on process or a fluid chemical vapor deposition process.
Optionally, the process of removing the first sacrificial layer includes: ashing process, dry etching or wet etching.
Optionally, after removing the first sacrificial layer, the method further includes: and forming an isolation structure on the first transistor area and the second transistor area, wherein the surface of the isolation structure is lower than the top surface of the fin part, and the thickness of the isolation structure is greater than or equal to that of the first sacrificial layer.
Optionally, the thickness of the first sacrifice is equal to the thickness of the isolation structure.
Optionally, the second transistor region is used for forming a PMOS transistor; further comprising: and carrying out second ion implantation on the second transistor region isolation structure.
Optionally, the first transistor region is used to form an NMOS transistor.
Optionally, the implanted ions of the first ion implantation include: boron ions or boron fluoride ions.
Optionally, the process parameters of the first ion implantation include: the implantation dose is 5.0E12atoms/cm2～1.0E15atoms/cm2(ii) a The implantation energy is 5 KeV-50 KeV.
Optionally, after removing the first sacrificial layer and before forming the isolation structure, the method further includes: forming a third sacrificial layer on the substrate of the second transistor area, wherein the surface of the third sacrificial layer is lower than the top surface of the fin part; performing second ion implantation on the third sacrificial layer; removing the third sacrificial layer after second ion implantation; and after removing the third sacrificial layer, carrying out annealing treatment.
Optionally, the annealing treatment is performed before the isolation structure is formed.
Optionally, the process parameters of the annealing treatment include: the annealing temperature is 900-1100 ℃.
Optionally, the first transistor region is used for forming a PMOS transistor; the second transistor region is used for forming an NMOS transistor.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the method for forming a semiconductor structure of the present invention, a first sacrificial layer is formed on the first transistor area substrate before the first ion implantation is performed. Implanting ions in the first sacrificial layer by the first ion implantation, the implanted ions being capable of diffusing into the fin. And after ion implantation, removing the first sacrificial layer, and then performing annealing treatment, wherein the annealing treatment is used for activating ions diffused into the fin part and enabling the ions in the fin part to be uniformly diffused in the fin part. Moreover, in the annealing process, because the first sacrificial layer is removed, ions implanted in the first sacrificial layer cannot diffuse into the fin part of the second transistor area, and the performance of a transistor formed in the second transistor area is not affected. Therefore, the forming method can improve the performance of the semiconductor structure.
Drawings
FIGS. 1-3 are schematic structural diagrams illustrating steps of a method for forming a semiconductor structure;
fig. 4 to 13 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
The formation method of the semiconductor structure has a plurality of problems, and the performance of the formed semiconductor structure is poor.
Now, with a method for forming a semiconductor structure, the reason for the poor performance of the formed semiconductor structure is analyzed:
research shows that as the size of a fin portion for forming a fin field effect transistor is continuously reduced, a punch through (punch) phenomenon is easily generated at the bottoms of a source region and a drain region formed in the fin portion, and leakage current is generated at the bottoms of the source region and the drain region. To overcome the bottom punch-through phenomenon, one approach is to implant counter ions in the region between the source and drain bottom portions to isolate the source and drain bottom portions.
Fig. 1 to 3 are schematic structural diagrams of steps of a method for forming a semiconductor structure.
Referring to fig. 1, a substrate is provided, the substrate includes: an NMOS region A and a PMOS region B. The NMOS region A and the PMOS region B of the substrate comprise: a substrate 100, a fin 101 on the substrate 100, and a hard mask 110 on top of the fin 101.
With continued reference to fig. 1, isolation structures 102 are formed on the substrate 100 between the fins 101, the isolation structures 102 having a surface lower than the top surface of the fins 101.
Referring to fig. 2, the isolation structure 102 is subjected to a punch-through prevention implantation, and punch-through prevention ions are implanted.
Referring to fig. 3, after the anti-punch-through implantation, an annealing process is performed to activate the anti-punch-through ions.
The punch-through preventing ions in the NMOS region a are boron ions or boron fluoride ions, which are easily lost during annealing, so that the punch-through preventing ions have a high concentration during the process of punch-through implantation. In addition, boron ions or boron fluoride ions have a small atomic weight and a high diffusion rate in annealing treatment. Therefore, in the annealing process, the punch-through preventing ions in the isolation structure 102 between the NMOS region a fin 101 and the PMOS region B fin 101 are easily diffused into the PMOS region B fin 101, so that the bottom of the PMOS region B fin 101 is doped with P-type ions, which easily increases the leakage current of the transistor formed in the PMOS region B, and further affects the performance of the transistor formed in the PMOS region B.
In order to solve the technical problem, the invention provides a method for forming a semiconductor structure, which comprises the following steps: providing a base, wherein the base comprises a substrate and a fin part positioned on the substrate, and the base comprises: a first transistor region and a second transistor region; forming a first sacrificial layer on the first transistor area substrate, wherein the surface of the first sacrificial layer is lower than the top surface of the fin part; carrying out first ion implantation on the first sacrificial layer; removing the first sacrificial layer after the first ion implantation; and after removing the first sacrificial layer, carrying out annealing treatment.
And forming a first sacrificial layer on the first transistor area substrate before the first ion implantation. Implanting ions in the first sacrificial layer by the first ion implantation, the implanted ions being capable of diffusing into the fin. And after ion implantation, removing the first sacrificial layer, and then performing annealing treatment, wherein the annealing treatment is used for activating ions diffused into the fin part and enabling the ions in the fin part to be uniformly diffused in the fin part. Moreover, in the annealing process, because the first sacrificial layer is removed, ions implanted in the first sacrificial layer cannot diffuse into the fin part of the second transistor area, and the performance of a transistor formed in the second transistor area is not affected. Therefore, the forming method can improve the performance of the semiconductor structure.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 4 to 13 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 4, a substrate is provided, the substrate includes: the first transistor area I and the second transistor area II of the substrate include a substrate 200 and a fin 201 on the substrate 200.
Since the punch-through preventing ions of the NMOS transistor are boron ions or boron fluoride ions, which are easily lost during annealing, the punch-through preventing ions have a high concentration during the punch-through preventing implantation. In addition, boron ions or boron fluoride ions have a small atomic weight and a high diffusion rate in annealing treatment. Therefore, boron ions or boron fluoride ions easily diffuse into the PMOS transistor during the annealing process, thereby affecting the performance of the PMOS transistor. Therefore, the present embodiment will be described in detail by taking an example in which an NMOS transistor is formed in the first transistor region I and a PMOS transistor is formed in the second transistor region II. In other embodiments, the first transistor region may also be used to form a PMOS transistor; the second transistor region is used for forming an NMOS transistor.
In this embodiment, the substrate includes: a substrate 200; a fin 201 located in a first transistor region I and a second transistor region II of the substrate 200; a hard mask 202 on top of the fin 201.
The hard mask 202 may protect the top of the fin 201 from ion implantation during subsequent first and second ion implantation processes.
In this embodiment, the forming of the substrate includes: providing an initial substrate; forming a patterned hard mask 202 on the initial substrate; and patterning the initial substrate by taking the hard mask 202 as a mask to form a substrate 200 and a fin part 201 positioned on the substrate 200, wherein the fin part 201 is used for forming a transistor channel.
In this embodiment, the substrate 200 is a silicon substrate. In other embodiments, the substrate may also be a semiconductor substrate such as a germanium substrate, a silicon-on-insulator substrate, or a germanium-on-insulator substrate.
In this embodiment, the fin 201 is made of silicon. In other embodiments, the fin may be made of germanium or silicon germanium.
In this embodiment, the fin 201 is located on the surface of the substrate 200. In other embodiments, an oxide layer may be further disposed between the fin and the substrate.
Referring to fig. 5 to 7, a first sacrificial layer 211 is formed on the first transistor area I substrate 200, wherein a surface of the first sacrificial layer 211 is lower than a top surface of the fin 202.
The first sacrificial layer 211 is used for ion implantation.
In this embodiment, the forming method further includes forming a second sacrificial layer 212 in the second transistor region II, where the second sacrificial layer 212 covers the top and the sidewall of the fin 201 of the second transistor region II.
In this embodiment, in order to simplify the process, the first sacrificial layer 221 and the second sacrificial layer 212 are formed in the same process.
In this embodiment, the steps of forming the first sacrificial layer 211 and the second sacrificial layer 212 are as shown in fig. 5 to 7.
Referring to fig. 5, an initial sacrificial layer 210 is formed on the substrate 200 in the first transistor area I and the second transistor area II, and the surface of the initial sacrificial layer 210 is higher than the top surface of the fin 201.
The initial sacrificial layer 210 is used to form a first sacrificial layer and a second sacrificial layer.
In this embodiment, the material of the initial sacrificial layer 210 is an anti-reflective coating, and specifically, the material of the initial sacrificial layer 210 is an organic anti-reflective coating. In other embodiments, the material of the initial sacrificial layer may also be a silicon oxide layer or a silicon nitride layer.
In this embodiment, the process of forming the initial sacrificial layer 210 includes: and (4) spin coating. In other embodiments, the material of the initial sacrificial layer is silicon oxide or silicon oxynitride, and the material forming the initial sacrificial layer is a fluid chemical vapor deposition process.
Referring to fig. 6 and 7, the initial sacrificial layer 210 is removed to a thickness of a portion of the first transistor area I.
Referring to fig. 6, a first photoresist 213 is formed on the second region II initial sacrificial layer 210.
The first photoresist 213 is used as a mask to etch the initial sacrificial layer 210.
Referring to fig. 7, the initial sacrificial layer 210 is etched using the first photoresist 213 as a mask, so that the surface of the initial sacrificial layer 210 in the first transistor area I (as shown in fig. 6) is lower than the surface of the fin 210, thereby forming a first sacrificial layer 211, and forming a second sacrificial layer 212 in the second transistor area II.
The first sacrificial layer 211 is used for implanting first punch-through ions and doping the first transistor I-fin 201; the second sacrificial layer 212 is used to protect the second transistor region II fin 201 and prevent the first ion implantation from being performed on the second transistor region II fin.
It should be noted that, if the height of the fin 201 exposed by the first sacrificial layer 211 is less than the height of the fin 201 exposed by the subsequently formed isolation structure, the channel after the subsequently formed transistor is doped with the first anti-punch-through ions, which may easily affect the performance of the transistor. Therefore, the height of the fin 201 exposed by the first sacrificial layer 211 is greater than or equal to the height of the fin 201 exposed by the subsequently formed isolation structure. Specifically, in the present embodiment, the height of the fin 201 exposed by the first sacrificial layer 211 is equal to the height of the fin 201 exposed by the subsequently formed isolation structure.
In this embodiment, the initial sacrificial layer 210 is etched by dry etching. The dry etching has anisotropy, good linewidth control and less loss to the sidewall of the fin portion 201. In other embodiments, the initial sacrificial layer may also be etched by wet etching or a combination of dry and wet etching.
In this embodiment, the first sacrificial layer 211 and the second sacrificial layer 212 are both formed by the initial sacrificial layer 210, and thus, the materials of the first sacrificial layer 211 and the second sacrificial layer 212 are the same. Specifically, the material of the first sacrificial layer 211 and the second sacrificial layer 212 is an anti-reflective coating. In other embodiments, the material of the first sacrificial layer and the second sacrificial layer may also be a silicon oxide layer or a silicon nitride layer.
Referring to fig. 8, a first ion implantation is performed on the first transistor area I and the first sacrificial layer 211.
The first ion implantation is for implanting first punch-through preventing ions in the first sacrificial layer 211.
It should be noted that, in the first ion implantation process, the first punch-through preventing ions may diffuse into the first transistor area I fin 201 to dope the first transistor area I fin 201, so as to reduce the probability of punch-through of the source and drain of the transistor formed in the first transistor area I.
In this embodiment, the first transistor region I is used to form an NMOS transistor. Therefore, the first anti-punch-through ions are boron ions or boron fluoride ions. In other embodiments, the first transistor region is used to form a PMOS transistor. Therefore, the first punch-through preventing ions are phosphorus ions or arsenic ions.
If the ion implantation dosage of the first ion implantation is too low, the concentration of the first punch-through preventing ions entering the first region I fin portion 201 is too low, and it is difficult to prevent the source-drain punch-through of the formed transistor; if the ion implantation dose of the first ion implantation is too high, waste of material and energy is easily generated. Therefore, in this embodiment, the ion implantation dose of the first ion implantation is 5.0E12atoms/cm2～1.0E15atoms/cm2。
In this embodiment, the process parameters of the first ion implantation further include: the implantation energy is 5 KeV-50 KeV.
Referring to fig. 9, after the first ion implantation, the first sacrificial layer 211 is removed (as shown in fig. 8).
Removing the first sacrificial layer 211 can prevent the first anti-punch-through ions in the first sacrificial layer 211 in the first transistor region I from diffusing into the second transistor region II fin 201 in the subsequent annealing process, thereby reducing the influence of the first anti-punch-through ions on the performance of the transistor formed in the second transistor region II.
In this embodiment, the second region II has a second sacrificial layer 212, and the forming method further includes: the second sacrificial layer 212 is removed (as shown in fig. 8).
In this embodiment, the second sacrificial layer 212 and the first sacrificial layer 211 are made of the same material. Therefore, the first sacrificial layer 211 and the second sacrificial layer 212 are removed in the same process. Specifically, the first sacrificial layer 211 and the second sacrificial layer 212 are removed by an ashing process, dry etching, or wet etching.
In this embodiment, the second sacrificial layer 212 has a first photoresist 213 thereon. Before removing the second sacrificial layer 212, the forming method further includes: after the first ion implantation, the first photoresist 213 is removed (as shown in fig. 8).
In this embodiment, the first photoresist 213 is removed by an ashing process.
Referring to fig. 10, after removing the first sacrificial layer 211 (as shown in fig. 8), an annealing process is performed.
In this embodiment, the annealing process performed before the second ion implantation is performed is the first annealing process.
The first annealing process is used to further diffuse the first anti-punch-through ions in the first transistor region ipfin 201 and activate the first anti-punch-through ions.
In this embodiment, the process parameters of the annealing treatment include: the annealing temperature is 900-1100 ℃.
In other embodiments, the first annealing process may not be performed, and the annealing process may be performed only after the second ion implantation.
Referring to fig. 11, after removing the first sacrificial layer 211 (as shown in fig. 8), the forming method further includes: an isolation structure 220 is formed on the substrate 200 in the first transistor area I and the second transistor area II, the surface of the isolation structure 220 is lower than the top surface of the fin 201, and the thickness of the isolation structure 220 is greater than or equal to the thickness of the first sacrificial layer 211.
It should be noted that, if the isolation structure 220 is lower than the surface of the first sacrificial layer 211, after a gate structure is formed subsequently, the first punch-through preventing ions enter into a channel of a formed transistor, which easily increases a threshold voltage of the formed transistor, thereby easily affecting transistor performance. Therefore, the thickness of the isolation structure 220 is greater than or equal to the thickness of the first sacrificial layer 211. Specifically, in this embodiment, the surface of the isolation structure 220 is flush with the surface of the first sacrificial layer 211.
In this embodiment, the isolation structure 220 is made of silicon oxide or silicon oxynitride.
The step of forming the isolation structure 220 includes: forming an initial isolation structure on the substrate 200; and etching the initial isolation structure to enable the surface of the initial isolation structure to be lower than the top surface of the fin portion 201, so as to form an isolation structure 220.
It should be noted that, in the embodiment, after the annealing process, the isolation structure 220 is formed, so that the first punch-through preventing ions in the fin portion can be prevented from diffusing into the isolation structure 220 during the annealing process, and thus the punch-through preventing ions can be prevented from entering the second transistor region II fin portion 201 through the isolation structure 220. In other embodiments, the isolation structure may also be formed prior to annealing.
Referring to fig. 12, the forming method further includes: a second ion implantation is performed on the second transistor area II isolation structure 220.
The second ion implantation is used to implant second anti-punch-through ions in the second transistor region II isolation structure 220 and to diffuse the second anti-punch-through ions into the second transistor region II fin 201.
In this embodiment, the second transistor region II is used to form a PMOS transistor, and thus the second punch-through preventing ions are arsenic ions or phosphorous ions.
In this embodiment, the step of performing the second ion implantation on the second transistor area II isolation structure 220 includes: forming a second photoresist 221 on the first transistor area I substrate 200, wherein the surface of the second photoresist 221 is higher than the top surface of the fin 201; performing second ion implantation by using the second photoresist 221 as a mask; after the second ion implantation, the second photoresist 221 is removed.
In this embodiment, after performing the second ion implantation on the second transistor area II isolation structure 220, the forming method further includes: after removing the second photoresist 221, a second annealing process is performed.
In this embodiment, the parameters of the second ion implantation include: the implantation dose is 5.0E12atoms/cm2～1.0E15 atoms/cm2(ii) a The implantation energy is 30 KeV-120 KeV.
Referring to fig. 13, in the present embodiment, after the second annealing process is performed, the forming method further includes: a gate structure 230 is formed across the fin 201, and the gate structure 230 covers a portion of the sidewalls and the top surface of the fin 201.
In this embodiment, after the isolation structure 230 is formed, the second ion implantation is performed, and the process is simple.
In another embodiment, the impact of the second punch-through preventing ions on the performance of the transistor formed by the second transistor region is reduced. The forming method may further include: before the isolation structure is formed, a third sacrificial layer is formed on the substrate of the second transistor area, and the surface of the third sacrificial layer is lower than the surface of the top of the fin portion; performing second ion implantation on the third sacrificial layer; removing the third sacrificial layer after second ion implantation; and after removing the third sacrificial layer, carrying out the annealing treatment. The forming method does not include the first annealing treatment before the second ion implantation is performed.
In summary, in the method for forming a semiconductor structure of the present invention, before the first ion implantation, a first sacrificial layer is formed on the first transistor area substrate. Implanting ions in the first sacrificial layer by the first ion implantation, the implanted ions being capable of diffusing into the fin. And after ion implantation, removing the first sacrificial layer, and then performing annealing treatment, wherein the annealing treatment is used for activating ions diffused into the fin part and enabling the ions in the fin part to be uniformly diffused in the fin part. Moreover, in the annealing process, because the first sacrificial layer is removed, ions implanted in the first sacrificial layer cannot diffuse into the fin part of the second transistor area, and the performance of a transistor formed in the second transistor area is not affected. Therefore, the forming method can improve the performance of the semiconductor structure.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (18)
1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a first transistor area and a second transistor area, and the first transistor area and the second transistor area of the substrate comprise a substrate and a fin part positioned on the substrate;
forming a first sacrificial layer on the first transistor area substrate, wherein the surface of the first sacrificial layer is lower than the top surface of the fin part;
carrying out first ion implantation on the first sacrificial layer;
removing the first sacrificial layer after the first ion implantation;
and after removing the first sacrificial layer, carrying out annealing treatment.
2. The method of claim 1, wherein the first sacrificial layer is an anti-reflective coating, a silicon oxide layer, or a silicon nitride layer.
3. The method of claim 1, wherein prior to the ion implantation of the first sacrificial layer in the first transistor region, the method further comprises: and forming a second sacrificial layer in the second transistor region, wherein the second sacrificial layer covers the top and the side wall of the fin part of the second transistor region.
4. The method of forming a semiconductor structure according to claim 3, wherein the first sacrificial layer and the second sacrificial layer are made of the same material.
5. The method of forming a semiconductor structure of claim 4, wherein the step of forming the first and second sacrificial layers comprises:
forming an initial sacrificial layer on the first transistor area and the second transistor area, wherein the surface of the initial sacrificial layer is higher than the top surface of the fin part;
and removing the initial sacrificial layer with partial thickness of the first transistor area, forming a first sacrificial layer in the first transistor area, and forming a second sacrificial layer in the second transistor area.
6. The method as claimed in claim 5, wherein the step of removing the initial sacrificial layer to a thickness of the first transistor region portion comprises: dry etching or wet etching.
7. The method of forming a semiconductor structure of claim 5, wherein the process of forming the initial sacrificial layer comprises: a spin-on process or a fluid chemical vapor deposition process.
8. The method of forming a semiconductor structure of claim 1, wherein the process of removing the first sacrificial layer comprises: ashing process, dry etching or wet etching.
9. The method of forming a semiconductor structure of claim 1, further comprising, after removing the first sacrificial layer:
and forming an isolation structure on the first transistor area and the second transistor area, wherein the surface of the isolation structure is lower than the top surface of the fin part, and the thickness of the isolation structure is greater than or equal to that of the first sacrificial layer.
10. The method of forming a semiconductor structure of claim 9, wherein a thickness of the first sacrificial layer is equal to a thickness of the isolation structure.
11. The method of forming a semiconductor structure of claim 9, wherein the second transistor region is used to form a PMOS transistor;
further comprising: and carrying out second ion implantation on the second transistor region isolation structure.
12. The method of claim 11, wherein the first transistor region is used to form an NMOS transistor.
13. The method of forming a semiconductor structure of claim 12, wherein the first ion implantation of implanted ions comprises: boron ions or boron fluoride ions.
14. The method of claim 13, wherein the process parameters of the first ion implantation comprise: the implantation dose is 5.0E12atoms/cm2～1.0E15atoms/cm2(ii) a The implantation energy is 5 KeV-50 KeV.
15. The method of forming a semiconductor structure of claim 9, wherein after removing the first sacrificial layer and before forming the isolation structure, further comprising:
forming a third sacrificial layer on the substrate of the second transistor area, wherein the surface of the third sacrificial layer is lower than the top surface of the fin part; performing second ion implantation on the third sacrificial layer;
removing the third sacrificial layer after second ion implantation; and after removing the third sacrificial layer, carrying out annealing treatment.
16. The method of forming a semiconductor structure of claim 9, wherein the annealing is performed prior to forming the isolation structure.
17. The method of claim 1, wherein the process parameters of the annealing process comprise: the annealing temperature is 900-1100 ℃.
18. The method of claim 1, wherein the first transistor region is used to form a PMOS transistor; the second transistor region is used for forming an NMOS transistor.
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