JP2000058869A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2000058869A JP2000058869A JP10229019A JP22901998A JP2000058869A JP 2000058869 A JP2000058869 A JP 2000058869A JP 10229019 A JP10229019 A JP 10229019A JP 22901998 A JP22901998 A JP 22901998A JP 2000058869 A JP2000058869 A JP 2000058869A
- Authority
- JP
- Japan
- Prior art keywords
- region
- semiconductor substrate
- layer
- conductivity type
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 80
- 239000000758 substrate Substances 0.000 claims abstract description 58
- 230000015556 catabolic process Effects 0.000 claims description 15
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 229910052799 carbon Inorganic materials 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 238000009792 diffusion process Methods 0.000 description 12
- 239000012535 impurity Substances 0.000 description 6
- 230000005684 electric field Effects 0.000 description 5
- 241001673391 Entandrophragma candollei Species 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/408—Electrodes ; Multistep manufacturing processes therefor with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は高耐圧半導体装置に
係わり、特にＳＩＰＯＳ ＲＥＳＵＲＦ（Semi-Insulat
ing Polycrystalline Silicon Reduced Surface Fiel
d ）構造の半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high withstand voltage semiconductor device, and more particularly to a SIPOS RESURF (Semi-Insulat).
ing Polycrystalline Silicon Reduced Surface Fiel
d) a semiconductor device having a structure.
【０００２】[0002]
【従来の技術】高耐圧の半導体装置では、接合の形状や
外部電荷の影響などのため、局部的に高い電界が生成さ
れてブレークダウンが発生する。これを防止するため
に、空乏層となる低不純物濃度の半導体領域の表面に多
結晶シリコン層のような半導電性膜であるＳＩＰＯＳ
（Semi-Insulating Polycrystalline Silicon ）層を付
着させる。さらに、表面の電界を安定させるＲＥＳＵＲ
Ｆ（Reduced Surface Field ）構造が使用される。2. Description of the Related Art In a high breakdown voltage semiconductor device, a high electric field is locally generated due to the influence of the shape of a junction or an external charge, so that a breakdown occurs. In order to prevent this, a SIPOS which is a semiconductive film such as a polycrystalline silicon layer is formed on a surface of a semiconductor region having a low impurity concentration serving as a depletion layer.
(Semi-Insulating Polycrystalline Silicon) layer is deposited. Further, RESUR stabilizes the surface electric field.
An F (Reduced Surface Field) structure is used.
【０００３】図５は、従来のＳＩＰＯＳ ＲＥＳＵＲＦ
構造による高耐圧半導体ダイオードの一例を示してい
る。Ｎ型の半導体基板（Ｓｉ基板）５１の表面領域にｐ
+ 型拡散層（アノード層）５２が選択的に形成され、こ
のアノード層５２を取り囲むように低不純物濃度のｐ-
型拡散層（ＲＥＳＵＲＦ層）５３がイオン注入及び拡散
により形成される。このＲＥＳＵＲＦ層５３の外側に所
定の間隔を有し、Ｓｉ基板５１の表面にＥＱＰＲ（Equi
valent Potential Ring ）層と呼ばれるリング状のｎ+
型拡散層（ＥＱＰＲ層）５４が同じくイオン注入及び拡
散により形成される。さらに、表面の電界を安定させる
ために、逆バイアス時に空乏層となるｐ- 型のＲＥＳＵ
ＲＦ層５３及びＮ型のＳｉ基板５１表面に、半導電性膜
（ＳＩＰＯＳ膜）５６が設けられる。このＳＩＰＯＳ膜
５６上には酸化膜５５が設けられる。また、前記アノー
ド層５２上にアノード電極５８が設けられ、前記酸化膜
５５と前記ＥＱＰＲ層５４上にＥＱＰＲ電極５９が設け
られている。さらに、前記Ｓｉ基板５１の裏面にはカソ
ード電極６０が設けられている。FIG. 5 shows a conventional SIPOS RESURF.
1 shows an example of a high breakdown voltage semiconductor diode having a structure. The surface region of the N-type semiconductor substrate (Si substrate) 51 has p
+ -Type diffusion layer (anode layer) 52 is selectively formed, p lightly doped so as to surround the anode layer 52 -
A diffusion layer (RESURF layer) 53 is formed by ion implantation and diffusion. There is a predetermined space outside the RESURF layer 53 and an EQPR (Equip
valent Potential Ring) ring-shaped n +
A type diffusion layer (EQPR layer) 54 is also formed by ion implantation and diffusion. Furthermore, in order to stabilize the electric field on the surface, a p − -type RESU serving as a depletion layer at the time of reverse bias is provided.
A semiconductive film (SIPOS film) 56 is provided on the surfaces of the RF layer 53 and the N-type Si substrate 51. An oxide film 55 is provided on the SIPOS film 56. An anode electrode 58 is provided on the anode layer 52, and an EQPR electrode 59 is provided on the oxide film 55 and the EQPR layer 54. Further, a cathode electrode 60 is provided on the back surface of the Si substrate 51.
【０００４】次に、上記半導体装置のＲＥＳＵＲＦ構造
の動作について説明する。前記アノード電極５８及びカ
ソード電極６０に逆バイアスが印加される場合、ＳＩＰ
ＯＳ膜５６にＥＱＰＲ層５４からアノード電極５８の接
合側に向かって微少電流が流れる。このため、ＳＩＰＯ
Ｓ膜５６にはこの微少電流に基づく電圧降下によって、
ＥＱＰＲ層５４側からアノード電極５８側に向かってそ
の電位が線形的（直線的）に減少する電位勾配が生じ
る。この結果、ＳＩＰＯＳ膜５６はその電位が線形に変
化したフィールドプレートとして機能し、Ｓｉ基板５１
表面の電界を安定させる。Next, the operation of the RESURF structure of the semiconductor device will be described. When a reverse bias is applied to the anode electrode 58 and the cathode electrode 60, SIP
A minute current flows through the OS film 56 from the EQPR layer 54 toward the junction of the anode electrode 58. For this reason, SIPO
The S film 56 has a voltage drop based on this minute current,
A potential gradient occurs in which the potential decreases linearly (linearly) from the EQPR layer 54 toward the anode electrode 58. As a result, the SIPOS film 56 functions as a field plate whose potential changes linearly,
Stabilizes the electric field on the surface.
【０００５】図６は、図５に示された従来の半導体装置
の詳細を示す部分的拡大図である。なお、図５と対応す
る部分には図５と同一符号を付し、説明は省略する。図
６において、アノード層５２とＥＱＰＲ層５４上のＳｉ
基板５１の表面には酸化膜５５ａが設けられ、この酸化
膜５５ａと、アノード層５２とＥＱＰＲ層５４との間の
Ｓｉ基板５１との上にはＳＩＰＯＳ膜５６が設けられて
いる。さらに、このＳＩＰＯＳ膜５６と前記酸化膜５５
ａ上にはＣＶＤ酸化膜５５ｂが設けられている。FIG. 6 is a partially enlarged view showing details of the conventional semiconductor device shown in FIG. Parts corresponding to those in FIG. 5 are denoted by the same reference numerals as in FIG. 5, and description thereof is omitted. In FIG. 6, Si on the anode layer 52 and the EQPR layer 54
An oxide film 55a is provided on the surface of the substrate 51, and a SIPOS film 56 is provided on the oxide film 55a and the Si substrate 51 between the anode layer 52 and the EQPR layer 54. Further, the SIPOS film 56 and the oxide film 55
A CVD oxide film 55b is provided on a.
【０００６】上記構造において、アノード電極５８及び
カソード電極６０に逆バイアスが印加されると、高不純
物濃度のアノード層５２とＥＱＰＲ層５４との間の不純
物濃度の低いＲＥＳＵＲＦ層５３及びＳｉ基板領域５１
において、接合部から両側に空乏層５０が成長する。In the above structure, when a reverse bias is applied to the anode electrode 58 and the cathode electrode 60, the RESURF layer 53 and the Si substrate region 51 having a low impurity concentration between the anode layer 52 having a high impurity concentration and the EQPR layer 54.
, Depletion layers 50 grow on both sides from the junction.
【０００７】[0007]
【発明が解決しようとする課題】ところで、上記のよう
に、ＳＩＰＯＳ膜５６を設けた半導体装置において、高
い逆バイアス電圧が印加された場合、アノード電極５８
あるいはＥＱＰＲ電極５９とＳＩＰＯＳ膜５６の端部と
の間に高い電界が生じ、この間のＣＶＤ酸化膜５５ｂが
破壊される問題が生じている。As described above, in a semiconductor device provided with the SIPOS film 56, when a high reverse bias voltage is applied, the anode electrode 58
Alternatively, a high electric field is generated between the EQPR electrode 59 and the end of the SIPOS film 56, and there is a problem that the CVD oxide film 55b therebetween is broken.
【０００８】本発明者は、この問題について研究した結
果、このような絶縁膜の破壊が次のような現象によるも
のであることを解明した。すなわち、このような半導体
装置において、逆バイアスの印加によって生成される空
乏層５０は逆バイアス電圧が高くなると、図６に破線で
示すように広がり、アノード層５２内及びＥＱＰＲ層５
４内に入り込む。そのため、空乏層５０の幅がＳＩＰＯ
Ｓ膜５６がＳｉ基板５１とコンタクトする幅より広くな
る。従って、空乏層５０内に取り残されたＳＩＰＯＳ膜
５６の両端部に位置するＡ部及びＢ部の電位が安定しな
いため、ＳＩＰＯＳ膜５６のＣ領域及びＤ領域は異常電
位となる。The inventor of the present invention has studied this problem and found that such a breakdown of the insulating film is caused by the following phenomenon. That is, in such a semiconductor device, when the reverse bias voltage is increased, the depletion layer 50 generated by application of the reverse bias expands as shown by a broken line in FIG.
Get inside 4. Therefore, the width of the depletion layer 50 is
The width of the S film 56 is wider than the width in contact with the Si substrate 51. Therefore, since the potentials of the portions A and B located at both ends of the SIPOS film 56 left in the depletion layer 50 are not stable, the C region and the D region of the SIPOS film 56 have an abnormal potential.
【０００９】すなわち、アノード層５２とアノード電極
５８、ＥＱＰＲ層５４とＥＱＰＲ電極５９は同電位であ
る。また、ＳＩＰＯＳ膜５６のＡ部とＣ領域、Ｂ部とＤ
領域は同電位である。しかし、ＳＩＰＯＳ膜５６の端部
は空乏層５０上に位置し、アノード層５２及びＥＱＰＲ
層５４から電気的に分離されたことになる。このため、
アノード電極５８とＳＩＰＯＳ膜５６のＣ領域との間、
及びＥＱＰＲ電極５９とＳＩＰＯＳ膜５６のＤ領域との
間に大きな電位差が生じる。その結果、これらの間にお
いて絶縁破壊が発生するものと考えられる。That is, the anode layer 52 and the anode electrode 58 and the EQPR layer 54 and the EQPR electrode 59 have the same potential. Further, the A portion and the C region of the SIPOS film 56, and the B portion and the D portion
The regions are at the same potential. However, the end of the SIPOS film 56 is located on the depletion layer 50, and the anode layer 52 and the EQPR
It is electrically separated from the layer 54. For this reason,
Between the anode electrode 58 and the C region of the SIPOS film 56,
Also, a large potential difference occurs between the EQPR electrode 59 and the D region of the SIPOS film 56. As a result, it is considered that dielectric breakdown occurs between them.
【００１０】本発明は上記課題を解決するためになされ
たものであり、その目的とするところは、逆バイアス印
加時に、Ｓｉ基板とコンタクトするＳＩＰＯＳ膜の両端
での電位がそれぞれアノード電極、ＥＱＰＲ電極と同電
位となり、絶縁膜破壊を抑制できる半導体装置を提供す
ることにある。SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems. It is an object of the present invention to provide a reverse bias application in which the potentials at both ends of a SIPOS film in contact with a Si substrate are an anode electrode and an EQPR electrode, respectively. Another object of the present invention is to provide a semiconductor device which has the same potential as that of the semiconductor device and can suppress the breakdown of the insulating film.
【００１１】[0011]
【課題を解決するための手段】本発明は、前記目的を達
成するために以下に示す手段を用いている。本発明の半
導体装置は、第１導電型の半導体基板と、前記半導体基
板の表面に選択的に形成された第２導電型の第１の領域
と、前記第１の領域と隣接され、前記第１の領域より低
濃度の第２導電型の第２の領域と、前記第１及び第２の
領域の外側で、かつ前記第２の領域とは所定の間隔を有
する第１導電型の第３の領域と、前記第１の領域と前記
第３の領域との間の前記半導体基板表面に形成された半
導電性膜とを有し、前記半導電性膜の端部は前記第１の
領域及び第３の領域中に、逆バイアスの印加によって発
生した空乏層の領域を越える位置まで延在していること
を特徴とする。The present invention uses the following means to achieve the above object. The semiconductor device according to the present invention includes a semiconductor substrate of a first conductivity type, a first region of a second conductivity type selectively formed on a surface of the semiconductor substrate, and a second region adjacent to the first region. A second region of a second conductivity type having a lower concentration than the first region, and a third region of a first conductivity type outside the first and second regions and having a predetermined distance from the second region. And a semiconductive film formed on the surface of the semiconductor substrate between the first region and the third region, and an end of the semiconductive film is formed in the first region. And a third region extending to a position beyond a region of a depletion layer generated by application of a reverse bias.
【００１２】本発明の半導体装置は、第１導電型の半導
体基板と、前記半導体基板の表面にリング状に形成され
た第２導電型の第１の領域と、前記第１の領域の外側に
隣接され、前記第１の領域より低濃度の第２導電型の第
２の領域と、前記第１及び第２の領域の外側で、かつ前
記第２の領域とは所定の間隔を有する第１導電型の第３
の領域と、前記第１の領域と前記第３の領域との間の前
記半導体基板表面に形成され、端部が前記第１の領域及
び第３の領域中に、逆バイアスの印加によって発生した
空乏層の領域を越える位置まで延在された半導電性膜
と、前記第１の領域の内側に位置する前記半導体基板の
表面に所定間隔離間して形成された第２導電型の第４、
第５の領域と、前記第４、第５の領域内にそれぞれ形成
された第１導電型のソース領域と、これらソース領域の
上方に形成されたゲート電極と、前記半導体基板の裏面
に形成された第１導電型のドレイン領域とを具備するこ
とを特徴とする。A semiconductor device according to the present invention comprises a semiconductor substrate of a first conductivity type, a first region of a second conductivity type formed in a ring shape on the surface of the semiconductor substrate, and a first region of a second conductivity type formed outside the first region. An adjacent second region of a second conductivity type having a lower concentration than the first region, and a first region outside the first and second regions and having a predetermined distance from the second region. Third of conductivity type
Region, and formed on the surface of the semiconductor substrate between the first region and the third region, and an edge is generated in the first region and the third region by application of a reverse bias. A semiconductive film extending to a position beyond the depletion layer region, and a second conductive type fourth and fourth conductive type formed on the surface of the semiconductor substrate located inside the first region at predetermined intervals.
A fifth region, a first conductivity type source region formed in each of the fourth and fifth regions, a gate electrode formed above the source region, and a back surface of the semiconductor substrate. And a drain region of the first conductivity type.
【００１３】本発明の半導体装置は、第１導電型の半導
体基板と、前記半導体基板の表面にリング状に形成され
た第２導電型の第１の領域と、前記第１の領域の外側に
隣接され、前記第１の領域より低濃度の第２導電型の第
２の領域と、前記第１及び第２の領域の外側で、かつ前
記第２の領域とは所定の間隔を有する第１導電型の第３
の領域と、前記第１の領域と前記第３の領域との間の前
記半導体基板表面に形成され、端部が前記第１の領域及
び第３の領域中に、逆バイアスの印加によって発生した
空乏層の領域を越える位置まで延在された半導電性膜
と、前記第１の領域の内側に位置する前記半導体基板の
表面に所定間隔離間して形成された第２導電型の第４、
第５の領域と、前記第４、第５の領域内にそれぞれ形成
された第１導電型のエミッタ領域と、これらエミッタ領
域の上方に形成されたゲート電極と、前記半導体基板の
裏面に形成された第２導電型のコレクタ領域とを具備す
ることを特徴とする。A semiconductor device according to the present invention comprises a semiconductor substrate of a first conductivity type, a first region of a second conductivity type formed in a ring shape on a surface of the semiconductor substrate, and a first region of a second conductivity type outside the first region. An adjacent second region of a second conductivity type having a lower concentration than the first region, and a first region outside the first and second regions and having a predetermined distance from the second region. Third of conductivity type
Region, and formed on the surface of the semiconductor substrate between the first region and the third region, and an edge is generated in the first region and the third region by application of a reverse bias. A semiconductive film extending to a position beyond the depletion layer region, and a second conductive type fourth and fourth conductive type formed on the surface of the semiconductor substrate located inside the first region at predetermined intervals.
A fifth region, a first conductivity type emitter region formed in each of the fourth and fifth regions, a gate electrode formed above these emitter regions, and a back surface of the semiconductor substrate. And a collector region of the second conductivity type.
【００１４】また、前記半導電性膜が前記半導体基板と
直接接触する部分の幅は、ブレークダウン直前の前記空
乏層の幅より広いこととする。また、前記半導電性膜は
シリコンに酸素、窒素、炭素のいずれか１つ以上を添加
したものである。また、前記半導電性膜の抵抗率は１０
7 〜１０13Ω・ｃｍである。The width of a portion where the semiconductive film is in direct contact with the semiconductor substrate is wider than the width of the depletion layer immediately before breakdown. The semiconductive film is formed by adding one or more of oxygen, nitrogen, and carbon to silicon. Further, the resistivity of the semiconductive film is 10
7 to 10 13 Ω · cm.
【００１５】[0015]
【発明の実施の形態】本発明の実施の形態を以下に図面
を参照して説明する。 ［第１の実施例］図１は、本発明の半導体装置の接合終
端構造を示す詳細図である。Embodiments of the present invention will be described below with reference to the drawings. First Embodiment FIG. 1 is a detailed view showing a junction termination structure of a semiconductor device according to the present invention.
【００１６】第１の実施例では、Ｎ型の半導体基板１１
の表面に４００ｎｍの熱酸化膜を形成した後、この半導
体基板１１の表面に第１のｐ+ 型の拡散層（アノード
層）１２が選択的に形成される。このアノード層１２を
取り囲むように隣接した位置に、不純物として例えばボ
ロンを注入して拡散させ、前記アノード層１２より低濃
度の第２のｐ- 型の拡散層（ＲＥＳＵＲＦ層）１３が形
成される。次に、前記アノード層１２とＲＥＳＵＲＦ層
１３を取り囲み、かつ前記ＲＥＳＵＲＦ層１３とは所定
の間隔を有する位置に、不純物として例えばヒ素を注入
してｎ+ 型拡散層（ＥＱＰＲ層）１４が形成される。次
に、半導体基板１１の表面にＣＶＤ（ Chemical Vapor
Deposition）法により４００ｎｍの酸化膜１５が形成さ
れる。以上の工程は、図５の従来技術の装置と同様であ
る。In the first embodiment, the N-type semiconductor substrate 11
After a 400 nm thermal oxide film is formed on the surface of the semiconductor substrate 11, a first p + -type diffusion layer (anode layer) 12 is selectively formed on the surface of the semiconductor substrate 11. For example, boron is implanted and diffused as an impurity at an adjacent position so as to surround the anode layer 12 to form a second p − -type diffusion layer (RESURF layer) 13 having a lower concentration than the anode layer 12. . Next, for example, arsenic is implanted as an impurity at a position surrounding the anode layer 12 and the RESURF layer 13 and at a predetermined distance from the RESURF layer 13 to form an n + type diffusion layer (EQPR layer) 14. You. Next, CVD (Chemical Vapor) is applied to the surface of the semiconductor substrate 11.
A 400 nm oxide film 15 is formed by a Deposition method. The above steps are the same as those of the prior art apparatus shown in FIG.
【００１７】次に、酸化膜１５を半導体装置（アノード
層と半導体基板間）に逆バイアスを印加した時に発生す
る空乏層１０の広がりよりも広く除去する。空乏層１０
の広がりは想定される最大のバイアス電圧に対して、シ
ミュレーションにより算出される。その後、半導体基板
１１表面に半導電性膜（ＳＩＰＯＳ膜）１６が形成され
る。このとき、ＳＩＰＯＳ膜１６の両端は酸化膜１５上
に位置する。また、半導電性膜の抵抗率は１０7 〜１０
13Ω・ｃｍであることが好ましい。次に、前記ＳＩＰＯ
Ｓ膜１６をアノード層１２及びＥＱＰＲ層１４上の酸化
膜１５上を終端として、アノード層１２とＥＱＰＲ層１
４間との部分に残すようにエッチングする。その後、全
面にＣＶＤ法により１μｍのＣＶＤ酸化膜１７が形成さ
れる。次に、アノード層１２及びＥＱＰＲ層１４をそれ
ぞれ露出するようにＣＶＤ酸化膜１７が除去される。そ
の後、全面にアルミニウム（Ａｌ）膜が形成される。次
に、Ａｌ膜を選択的にエッチングし、アノード電極１８
及びＥＱＰＲ電極１９が形成される。最後に、半導体基
板１１裏面に、Ａｌを用いてカソード電極２０が形成さ
れる。Next, the oxide film 15 is removed more widely than the extent of the depletion layer 10 generated when a reverse bias is applied to the semiconductor device (between the anode layer and the semiconductor substrate). Depletion layer 10
Is calculated by simulation for the assumed maximum bias voltage. Thereafter, a semiconductive film (SIPOS film) 16 is formed on the surface of the semiconductor substrate 11. At this time, both ends of the SIPOS film 16 are located on the oxide film 15. The resistivity of the semiconductive film is 10 7 to 10
It is preferably 13 Ω · cm. Next, the SIPO
The S film 16 is terminated on the oxide film 15 on the anode layer 12 and the EQPR layer 14, and the anode layer 12 and the EQPR layer 1 are terminated.
Etching is performed so as to remain in the portion between the four spaces. Thereafter, a 1 μm CVD oxide film 17 is formed on the entire surface by the CVD method. Next, the CVD oxide film 17 is removed so as to expose the anode layer 12 and the EQPR layer 14, respectively. Thereafter, an aluminum (Al) film is formed on the entire surface. Next, the Al film is selectively etched to form the anode electrode 18.
And an EQPR electrode 19 are formed. Finally, the cathode electrode 20 is formed on the back surface of the semiconductor substrate 11 using Al.
【００１８】上記構造の半導体装置によれば、ＳＩＰＯ
Ｓ膜１６の領域が空乏層１０の広がりよりも広く形成さ
れている。このため、高い逆バイアス電圧が印加されて
もＳＩＰＯＳ膜１６のＥ領域及びＦ領域はそれぞれアノ
ード層１２、ＥＱＰＲ層１４と電位が等しい。そのた
め、ＳＩＰＯＳ膜１６のＧ領域及びＨ領域はそれぞれア
ノード電極１８、ＥＱＰＲ電極１９と同電位となり、前
記従来技術の装置で問題となった絶縁破壊が生じること
はない。According to the semiconductor device having the above structure, the SIPO
The region of the S film 16 is formed wider than the depletion layer 10. Therefore, even when a high reverse bias voltage is applied, the E region and the F region of the SIPOS film 16 have the same potential as the anode layer 12 and the EQPR layer 14, respectively. Therefore, the G region and the H region of the SIPOS film 16 have the same potential as the anode electrode 18 and the EQPR electrode 19, respectively, and the dielectric breakdown which is a problem in the prior art device does not occur.
【００１９】従って、従来の構造に比べ非常に安定した
半導体装置となり、従来構造で発生したアノード電極１
８及びＥＱＰＲ電極１９とＳＩＰＯＳ膜１６のＧ領域及
びＨ領域間の絶縁膜破壊を抑制できる。Therefore, the semiconductor device is very stable as compared with the conventional structure, and the anode electrode 1 generated in the conventional structure can be obtained.
8 and the insulating film between the G region and the H region of the EQPR electrode 19 and the SIPOS film 16 can be suppressed.
【００２０】［第２の実施例］図２、図３は、本発明を
ＭＯＳトランジスタに応用した第２の実施例を示してい
る。図３は、図２の３−３線に沿った断面図である。[Second Embodiment] FIGS. 2 and 3 show a second embodiment in which the present invention is applied to a MOS transistor. FIG. 3 is a sectional view taken along line 3-3 in FIG.
【００２１】この第２の実施例は、半導体基板２１の表
面に、ｐ+ 型のベース層３１が形成され、このベース層
３１内にｎ+ 型のソース層３２が形成されている。この
ソース層３２の上方にはソース電極３３が設けられ、こ
のソース電極３３上にはゲート電極３４が設けられてい
る。また、半導体基板２１裏面にはｎ+ 型のドレイン層
３５が形成され、このドレイン層３５の裏面にはドレイ
ン電極３６が設けられている。In the second embodiment, a p + -type base layer 31 is formed on the surface of a semiconductor substrate 21, and an n + -type source layer 32 is formed in the base layer 31. A source electrode 33 is provided above the source layer 32, and a gate electrode 34 is provided on the source electrode 33. An n + -type drain layer 35 is formed on the back surface of the semiconductor substrate 21, and a drain electrode 36 is provided on the back surface of the drain layer 35.
【００２２】このようなＭＯＳトランジスタを、高耐圧
化するため、トランジスタとして機能する領域を囲んで
リング状のｐ+ 型の領域２２が形成され、これがソース
電極３３と共に接地される。このｐ+ 型の領域２２を取
り囲んで低不純物濃度のｐ−型の拡散層２３が形成され
る。さらに、その外側に間隔を隔ててリング状のｎ＋型
の領域２４が形成されている。また、半導体基板２１の
底部には、ｎ+ 型のドレイン層３５が形成され、このド
レイン層３５はドレイン電極３６と接続されている。こ
の構造は、領域２２が図１に示すアノード層１２に相当
し、拡散層２３がＲＥＳＵＲＦ層１３に相当し、領域２
４がＥＱＰＲ層１４に相当する構造となっている。In order to increase the breakdown voltage of such a MOS transistor, a ring-shaped p + -type region 22 is formed surrounding a region functioning as a transistor, and is grounded together with a source electrode 33. A p − -type diffusion layer 23 having a low impurity concentration is formed surrounding the p + -type region 22. Further, a ring-shaped n + -type region 24 is formed outside the region at an interval. An n + -type drain layer 35 is formed on the bottom of the semiconductor substrate 21, and the drain layer 35 is connected to a drain electrode 36. In this structure, the region 22 corresponds to the anode layer 12 shown in FIG. 1, the diffusion layer 23 corresponds to the RESURF layer 13, and the region 2
4 has a structure corresponding to the EQPR layer 14.
【００２３】領域２２と２４の間の半導体基板２１の表
面に半導電性膜２６が形成される。この半導電性膜２６
は本発明を適用して、空乏層の広がりよりも広い位置で
領域２２、２４内に延在するように形成される。この
後、図示せぬ絶縁膜及び電極が形成される。このような
構成とすることより、第１の実施例と同様に絶縁膜の破
壊を防止できる。A semiconductive film 26 is formed on the surface of the semiconductor substrate 21 between the regions 22 and 24. This semiconductive film 26
Is formed so as to extend into the regions 22 and 24 at a position wider than the spread of the depletion layer by applying the present invention. Thereafter, an insulating film and electrodes (not shown) are formed. With such a configuration, breakdown of the insulating film can be prevented as in the first embodiment.
【００２４】［第３の実施例］図４は、本発明をＩＧＢ
Ｔ構造に応用した第３の実施例を示している。図４にお
いて、図２、図３と同一部分には同一符号を付し、異な
る部分について説明する。[Third Embodiment] FIG. 4 shows an IGB according to the present invention.
9 shows a third embodiment applied to a T structure. 4, the same parts as those in FIGS. 2 and 3 are denoted by the same reference numerals, and different parts will be described.
【００２５】図４に示すように、半導体基板２１の表面
に、ｐ+ 型のベース層３１が形成され、このベース層３
１内にｎ+ 型のエミッタ層３２が形成されている。この
エミッタ層３２上にはエミッタ電極３３が設けられ、こ
のエミッタ電極３３上にはゲート電極３４が設けられて
いる。また、半導体基板２１裏面にはｐ+ 型のコレクタ
層４５が形成され、このコレクタ層４５の裏面にはコレ
クタ電極３６が設けられている。ここで、ｐ+ 型のコレ
クタ層４５は、半導体基板２１の裏面にｎ+ 型の領域を
形成し、このｎ+ 型の領域の裏面にｐ+ 型の領域を形成
したものでもよい。As shown in FIG. 4, ap + type base layer 31 is formed on the surface of a semiconductor substrate 21.
An n + -type emitter layer 32 is formed in 1. An emitter electrode 33 is provided on the emitter layer 32, and a gate electrode 34 is provided on the emitter electrode 33. A p + -type collector layer 45 is formed on the back surface of the semiconductor substrate 21, and a collector electrode 36 is provided on the back surface of the collector layer 45. Here, the p + -type collector layer 45 is an n + -type region is formed on the back surface of the semiconductor substrate 21, it may be made by forming a p + -type region on the back surface of the n + -type region.
【００２６】上記構造のＩＧＢＴにおいても、高耐圧化
のために第２の実施例と同様な構造が設けられており、
この実施例によっても第１、第２の実施例と同様に、絶
縁膜の破壊を抑制できる。In the IGBT having the above structure, a structure similar to that of the second embodiment is provided to increase the breakdown voltage.
According to this embodiment, similarly to the first and second embodiments, the breakdown of the insulating film can be suppressed.
【００２７】なお、本発明は、上記実施形態に限定され
るものではない。例えば、半導電性膜は、実施例で述べ
たようにシリコンに酸素を添加したＳＩＰＯＳ膜以外
に、シリコンに窒素、炭素のいずれか１つ以上を添加し
たものであってもよい。また、前記半導電性膜が基板と
直接接触する部分の幅は、ブレークダウン直前の前記空
乏層の幅より広ければよい。その他、本発明は、その要
旨を逸脱しない範囲で、種々変形して実施することが可
能である。The present invention is not limited to the above embodiment. For example, the semiconductive film may be formed by adding one or more of nitrogen and carbon to silicon, in addition to the SIPOS film obtained by adding oxygen to silicon as described in the embodiment. The width of the portion where the semiconductive film is in direct contact with the substrate may be wider than the width of the depletion layer immediately before breakdown. In addition, the present invention can be variously modified and implemented without departing from the gist thereof.
【００２８】[0028]
【発明の効果】以上説明したように本発明によれば、半
導体基板とコンタクトする半導電性膜の領域を、半導体
装置に逆バイアスを印加したときに発生する空乏層の領
域よりも広く形成するため、Ａｌ電極と半導電性膜間の
絶縁膜破壊を抑制することが可能な半導体装置を提供で
きる。As described above, according to the present invention, the region of the semiconductive film in contact with the semiconductor substrate is formed wider than the region of the depletion layer generated when a reverse bias is applied to the semiconductor device. Therefore, it is possible to provide a semiconductor device capable of suppressing breakdown of an insulating film between an Al electrode and a semiconductive film.
【図面の簡単な説明】[Brief description of the drawings]
【図１】本発明に係わる半導体装置のダイオード構造を
示す断面図。FIG. 1 is a sectional view showing a diode structure of a semiconductor device according to the present invention.
【図２】本発明に係わる半導体装置のＭＯＳトランジス
タ構造を示す平面図。FIG. 2 is a plan view showing a MOS transistor structure of the semiconductor device according to the present invention.
【図３】図２の３−３線に沿った断面図。FIG. 3 is a sectional view taken along line 3-3 in FIG. 2;
【図４】本発明に係わる半導体装置のＩＧＢＴ構造を示
す断面図。FIG. 4 is a sectional view showing an IGBT structure of a semiconductor device according to the present invention.
【図５】従来技術による半導体装置の断面図。FIG. 5 is a sectional view of a conventional semiconductor device.
【図６】従来技術による半導体装置の接合終端構造の断
面図。FIG. 6 is a cross-sectional view of a junction termination structure of a semiconductor device according to a conventional technique.
１０…空乏層、 １１、２１…半導体基板（Ｓｉ基板）、 １２、２２…アノード層、 １３、２３…ｐ- 型拡散層（ＲＥＳＵＲＦ層）、 １４、２４…ｎ+ 型拡散層（ＥＱＰＲ層）、 １５…酸化膜、 １６、２６…半導電性膜（ＳＩＰＯＳ膜）、 １７…ＣＶＤ酸化膜、 １８…アノード電極、 １９…ＥＱＰＲ電極、 ２０…カソード電極、 ３１…ベース層、 ３２…エミッタ層、 ３３…エミッタ電極、 ３４…ゲート電極、 ３５…ｎ+ 型コレクタ層、 ３６…コレクタ電極、 ４５…ｐ+ 型コレクタ層。10 ... depletion layer, 11, 21 ... semiconductor substrate (Si substrate), 12, 22 ... anode layer, 13, 23 ... p - -type diffusion layer (RESURF layer), 14, 24 ... n + -type diffusion layer (EQPR layer) Reference numeral 15: oxide film 16, 26: semiconductive film (SIPOS film), 17: CVD oxide film, 18: anode electrode, 19: EQPR electrode, 20: cathode electrode, 31: base layer, 32: emitter layer, Reference numeral 33 denotes an emitter electrode, 34 denotes a gate electrode, 35 denotes an n + -type collector layer, 36 denotes a collector electrode, and 45 denotes a p + -type collector layer.
Claims (6)
の第１の領域と、 前記第１の領域と隣接され、前記第１の領域より低濃度
の第２導電型の第２の領域と、 前記第１及び第２の領域の外側で、かつ前記第２の領域
とは所定の間隔を有する第１導電型の第３の領域と、 前記第１の領域と前記第３の領域との間の前記半導体基
板表面に形成された半導電性膜とを有し、 前記半導電性膜の端部は前記第１の領域及び第３の領域
中に、逆バイアスの印加によって発生した空乏層の領域
を越える位置まで延在していることを特徴とする半導体
装置。A first conductivity type semiconductor substrate; a second conductivity type first region selectively formed on a surface of the semiconductor substrate; and a first region adjacent to the first region; A second region of a second conductivity type having a lower concentration than the region, and a third region of the first conductivity type outside the first and second regions and having a predetermined distance from the second region And a semiconductive film formed on the surface of the semiconductor substrate between the first region and the third region, wherein an end of the semiconductive film is formed in the first region and the third region. 3. The semiconductor device according to claim 3, wherein the semiconductor device extends to a position beyond a region of a depletion layer generated by application of a reverse bias.
型の第１の領域と、 前記第１の領域の外側に隣接され、前記第１の領域より
低濃度の第２導電型の第２の領域と、 前記第１及び第２の領域の外側で、かつ前記第２の領域
とは所定の間隔を有する第１導電型の第３の領域と、 前記第１の領域と前記第３の領域との間の前記半導体基
板表面に形成され、端部が前記第１の領域及び第３の領
域中に、逆バイアスの印加によって発生した空乏層の領
域を越える位置まで延在された半導電性膜と、 前記第１の領域の内側に位置する前記半導体基板の表面
に所定間隔離間して形成された第２導電型の第４、第５
の領域と、 前記第４、第５の領域内にそれぞれ形成された第１導電
型のソース領域と、 これらソース領域の上方に形成されたゲート電極と、 前記半導体基板の裏面に形成された第１導電型のドレイ
ン領域とを具備することを特徴とする半導体装置。2. A semiconductor substrate of a first conductivity type; a first region of a second conductivity type formed in a ring shape on a surface of the semiconductor substrate; and a first region adjacent to the outside of the first region; A second region of a second conductivity type having a lower concentration than the first region, and a third region of a first conductivity type outside the first and second regions and having a predetermined distance from the second region. Formed on the surface of the semiconductor substrate between the first region and the third region, and an edge is formed in the first and third regions by applying a reverse bias. A semiconductive film extending to a position beyond a region of a depletion layer; a fourth conductive type of fourth conductive type formed on a surface of the semiconductor substrate located inside the first region at a predetermined interval. Fifth
A source region of the first conductivity type formed in each of the fourth and fifth regions; a gate electrode formed above the source region; and a second electrode formed on the back surface of the semiconductor substrate. A semiconductor device comprising a drain region of one conductivity type.
型の第１の領域と、 前記第１の領域の外側に隣接され、前記第１の領域より
低濃度の第２導電型の第２の領域と、 前記第１及び第２の領域の外側で、かつ前記第２の領域
とは所定の間隔を有する第１導電型の第３の領域と、 前記第１の領域と前記第３の領域との間の前記半導体基
板表面に形成され、端部が前記第１の領域及び第３の領
域中に、逆バイアスの印加によって発生した空乏層の領
域を越える位置まで延在された半導電性膜と、 前記第１の領域の内側に位置する前記半導体基板の表面
に所定間隔離間して形成された第２導電型の第４、第５
の領域と、 前記第４、第５の領域内にそれぞれ形成された第１導電
型のエミッタ領域と、 これらエミッタ領域の上方に形成されたゲート電極と、 前記半導体基板の裏面に形成された第２導電型のコレク
タ領域とを具備することを特徴とする半導体装置。3. A semiconductor substrate of a first conductivity type, a first region of a second conductivity type formed in a ring shape on a surface of the semiconductor substrate, and a first region adjacent to the outside of the first region, A second region of a second conductivity type having a lower concentration than the first region, and a third region of a first conductivity type outside the first and second regions and having a predetermined distance from the second region. Formed on the surface of the semiconductor substrate between the first region and the third region, and an edge is formed in the first and third regions by applying a reverse bias. A semiconductive film extending to a position beyond a region of a depletion layer; a fourth conductive type of fourth conductive type formed on a surface of the semiconductor substrate located inside the first region at a predetermined interval. Fifth
A first conductive type emitter region formed in each of the fourth and fifth regions; a gate electrode formed above these emitter regions; and a second conductive region formed on the back surface of the semiconductor substrate. A semiconductor device comprising: a two-conductivity-type collector region.
接触する部分の幅は、ブレークダウン直前の前記空乏層
の幅より広いことを特徴とする請求項１乃至請求項３記
載の半導体装置。4. The semiconductor device according to claim 1, wherein a width of a portion where said semiconductive film directly contacts said semiconductor substrate is wider than a width of said depletion layer immediately before breakdown. .
素、炭素のいずれか１つ以上を添加したものであること
を特徴とする請求項１乃至請求項３記載の半導体装置。5. The semiconductor device according to claim 1, wherein said semiconductive film is formed by adding at least one of oxygen, nitrogen, and carbon to silicon.
13Ω・ｃｍであることを特徴とする請求項１乃至請求項
３記載の半導体装置。6. The resistivity of the semiconductive film is 10 7 to 10
The semiconductor device according to claim 1, wherein the resistance is 13 Ω · cm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10229019A JP2000058869A (en) | 1998-08-13 | 1998-08-13 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10229019A JP2000058869A (en) | 1998-08-13 | 1998-08-13 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000058869A true JP2000058869A (en) | 2000-02-25 |
Family
ID=16885487
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10229019A Abandoned JP2000058869A (en) | 1998-08-13 | 1998-08-13 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000058869A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008124362A (en) * | 2006-11-15 | 2008-05-29 | Mitsubishi Electric Corp | Semiconductor device and manufacturing method thereof |
| JP2010267767A (en) * | 2009-05-14 | 2010-11-25 | Mitsubishi Electric Corp | Semiconductor device and method of manufacturing the same |
| JP2012182302A (en) * | 2011-03-01 | 2012-09-20 | Toyota Motor Corp | Semiconductor device |
-
1998
- 1998-08-13 JP JP10229019A patent/JP2000058869A/en not_active Abandoned
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008124362A (en) * | 2006-11-15 | 2008-05-29 | Mitsubishi Electric Corp | Semiconductor device and manufacturing method thereof |
| JP2010267767A (en) * | 2009-05-14 | 2010-11-25 | Mitsubishi Electric Corp | Semiconductor device and method of manufacturing the same |
| JP2012182302A (en) * | 2011-03-01 | 2012-09-20 | Toyota Motor Corp | Semiconductor device |
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