JP3189456B2 - SOI semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an SOI (silicon on silicon) in which a semiconductor layer is separated via a dielectric serving as an insulating layer.
The present invention relates to a semiconductor device having an insulator (insulator) structure, and more particularly to a configuration of an SOI semiconductor device including an element isolation structure between element formation regions when a dielectric isolation substrate is used.

[0002]

2. Description of the Related Art In a MOS / IC or the like, the capacitance at a junction or the like is greatly reduced to improve switching characteristics.
Semiconductor devices configured by a separation method such as S (silicon on sapphire) or SOI (silicon on insulator) have been developed. Further, in an integrated circuit device having such a structure, the inside of the semiconductor layer is electrically isolated from the semiconductor islands in order to prevent the interference of the operations of the constituent circuit portions while increasing the degree of integration. It is common to separate into regions. That is, each semiconductor island region is used as an element formation region, and circuit elements such as transistors and diodes, and further, circuit portions are divided into these structures, and these circuit portions are electrically connected to each other by a wiring film.

Conventionally, a junction isolation method has been frequently used for element isolation in such an element formation region. However, since this junction isolation method utilizes the reverse bias characteristic of a pn junction, the junction isolation method is not used. Is not reliable. In addition, since unnecessary transistors and diodes are parasitic between semiconductor regions, unexpected troubles such as a latch-up phenomenon and malfunctions may occur during operation of the integrated circuit.

[0004] Therefore, a dielectric isolation method for separating the inside of a semiconductor substrate by a dielectric has been widely adopted. SOI
In the case of employing the dielectric isolation method in a semiconductor device having a structure, a dielectric which is an insulator is provided in a semiconductor layer which is a substrate, and the separated dielectric isolation substrate is used. In some cases, the semiconductor layer of the dielectric isolation substrate is formed of a polycrystalline silicon layer. Here, a case in which a dielectric isolation substrate is manufactured using a bonded substrate obtained by bonding two semiconductor substrates will be described.

First, as shown in FIG. 23A, an etching mask layer 5 is formed on the surface of a semiconductor layer 53 (semiconductor substrate) formed on a semiconductor support substrate 51 via an insulating film 52.
Then, dry etching is performed using a fluorine-based mixed gas to open a region where a separation groove is to be formed.

Next, as shown in FIG. 23B, anisotropic plasma etching is performed from the window opening of the etching mask layer 54 using a fluorine-based mixed gas to reach the insulating film 52. A groove 55 is formed. Here, the width of the separation groove 55 is 2 to 8 μm, and the depth thereof is 10 to 40 μm.

Next, after removing the etching mask layer 54, as shown in FIG. 23C, the surface side of the semiconductor layer 53 is placed in a steam atmosphere at about 1150 ° C. for about 100 minutes.
By thermal oxidation, a side wall insulating film 56 having a thickness of about 1 μm is formed on the side wall of the isolation groove 55. At this time, the insulating film 56a is also formed on the surface side of the semiconductor layer 53 outside the isolation groove 55.

Next, as shown in FIG.
By the VD method, a polycrystalline semiconductor layer 57 (filling layer) is deposited on the surface side of the semiconductor layer 53 to bury the inside of the separation groove 55. At this time, a polycrystalline semiconductor layer 5 7 a are deposited on the surface side of the outside of the semiconductor layer 53 of the isolation groove 55.

Next, as shown in FIG. 24A, the surface side of the semiconductor layer 53 is etched back or polished,
Removing an external polycrystalline semiconductor layer 5 7 a separation groove 55.

Thereafter, as shown in FIG.
When the insulating film 56a outside the isolation groove 55 was removed using dilute hydrofluoric acid, the semiconductor layer 53 was separated into elements by the isolation groove 55 including the sidewall insulating film 56 and the polycrystalline semiconductor layer 57 and the insulating film 52. A dielectric isolation substrate 50 having a semiconductor island region is formed.

Then, as shown in FIG. 24C, first diodes 59a, npn transistors 59b, and MOSFETs 59 are formed in element forming regions 50a, 50b, 50c, and 50d as semiconductor island regions formed in the semiconductor layer 53.
The integrated circuit is formed by forming c and the second diode 59d.

[0012]

In an SOI semiconductor device using such a dielectric isolation substrate, in order to improve the reliability of a circuit formed in an element formation region and to improve the breakdown voltage, The problem is how to set the potentials of the semiconductor supporting substrate and the filling layer.

For example, when an integrated circuit is formed using the conventional dielectric isolation substrate 50, the element formation regions 50a to 50a
In the isolation trench 55 surrounding 50 d, the fluctuation of the potential of the polycrystalline semiconductor layer 57 inside it affects the potential distribution of the element formation regions 50 a to 50 d via the sidewall insulating film 56.
For this reason, n formed in the element formation regions 50a to 50d
There is a problem that device characteristics of semiconductor devices such as the pn transistor 59b and the MOSFET 59c fluctuate.

The potential of the isolation groove 55 fluctuates under the influence of the potential of the semiconductor element formed in the adjacent element formation regions 50a to 50d. Influence of potential on semiconductor elements. This may cause a problem that the semiconductor elements mutually change element characteristics.

Therefore, conventionally, as shown in FIGS. 25 and 26, an electrode for defining the potential of the supporting substrate is provided on the back surface of the semiconductor supporting substrate and is fixed to the ground potential so as to suppress the potential fluctuation of the semiconductor supporting substrate. ing. FIG. 25 shows an example of an integrated circuit device using the above-described bonded substrate. A back surface electrode (support substrate potential defining electrode) 66 is provided on the back surface of the semiconductor support substrate 51, and a ground potential 67 is applied. . FIG. 26 shows an example of an integrated circuit device having a structure in which a main body is constituted by a polycrystalline silicon layer. A back electrode 76 is provided on the back surface of a supporting substrate 71 made of polycrystalline silicon, and a ground potential 67 is applied. Have been. Incidentally, reference numeral 72 denotes an insulating film, 73 denotes a semiconductor layer, and 75 denotes an isolation groove.

However, in the integrated circuit device having the structure shown in FIGS. 25 and 26, the insulating films 52 and 72 for separating the semiconductor layers 53 and 73 into the element forming regions and the side wall insulating film 56 have a withstand voltage of 1 μm. In order to further improve the withstand voltage, the thickness of the insulating film must be 1 μm or more, which is not realistic considering the time required for growing the insulating film. Although the isolation breakdown voltage between elements can be improved by forming a buried diffusion layer between the insulating films 52 and 72 and the semiconductor layers 53 and 73, the formation of the buried diffusion layer requires high-temperature and long-time heat treatment. , The buried diffusion layer is
3 and the element formation region becomes narrower. As described above, in the integrated circuit device using the conventional dielectric isolation substrate, there is a limit in improving the isolation breakdown voltage between elements.

On the other hand, in terms of withstand voltage, the SOI semiconductor device has a problem that it is difficult to achieve a high withstand voltage due to its small thickness of the semiconductor layer. For example, consider a device in which a diode is formed in the element formation region 50 as shown in FIG. FIG.
Is an n-type semiconductor layer 53 in the element formation region 50.
Then, a high concentration impurity is introduced through a window of the insulating film 56a to
⁺ Type cathode layer 62 and p ⁺ type anode layer 6
3 are formed, and a cathode electrode 64 and an anode electrode 65 are connected to the respective layers by aluminum electrodes. A back electrode 66 is provided on the back surface of the silicon support substrate 51 opposite to the insulating film 52 formed of the silicon oxide film , and a ground potential 67 is applied. The thickness of the supporting substrate 51 is 500 μm, the thickness of the insulating film 52 is 1 μm, and the thickness of the semiconductor layer 53 is 30 μm.

FIG. 28 shows a semiconductor layer 53 sandwiched between the anode layer 63 and the cathode layer 62 when a positive potential is applied to the cathode electrode 64 with the anode electrode 65 set to the ground potential (see FIG. 27). , Ab)
Are shown. The potential is 201, 20
When the positive potential is applied to the cathode layer 62, the equipotential lines 201a extend from the interface between the anode layer 63 and the insulating film 52 and the semiconductor layer 53 to the inside of the semiconductor layer 53, respectively. , 201b spread. Further, when a high potential is applied to the cathode layer 62, equipotential lines are connected in a region between the anode layer 63 and the insulating film 52, and equipotential lines are concentrated in a region between the cathode layer 62 and the insulating film 52. Further, when a high potential is applied to the cathode layer 62, the density of equipotential lines between the cathode layer 62 and the insulating film 52 is further increased, causing avalanche breakdown.

As described above, in the SOI semiconductor device shown in FIG. 27, most of the equipotential lines are concentrated on the semiconductor layer 53 interposed between the cathode layer 62 and the insulating film 52, and the vicinity of the cathode layer 62 Voltage breakdown occurs. If the semiconductor layer 53 is made thicker, the breakdown voltage can be improved, but the junction capacitance, which is an advantage of SOI, cannot be kept low, and the manufacturing time and cost increase.

The increase in the breakdown voltage of the semiconductor element formed in the element formation region has a considerable influence on the high integration and low on-resistance (high current output) of the SOI semiconductor device. This is to ensure the required breakdown voltage of the high breakdown voltage element.
It is necessary to set the drift length widely according to the required withstand voltage, which is caused by an increase in the element area. For example,
In the SOI semiconductor device shown in FIG. 29, an n-type buffer layer 97 is formed at one end of the surface of an n-type semiconductor layer 93, and a p ⁺ -type collector layer 98 is further provided in the buffer layer 97. Is formed. A collector electrode 89 is conductively connected to the collector layer 98 to form a collector region C. At the other end of the surface of the semiconductor layer 93, a p-type emitter layer 94, a p ⁺ -type contact layer 95 formed in the emitter layer 94, and an end portion of the contact layer 95 to the emitter layer 94 are formed. And an n ⁺ -type source layer 96. Then, the contact layer 95
Thus, an emitter electrode 87 is conductively connected to a part of the surface of the source layer 96 to form an emitter region E. G is a gate region for controlling the operation of the present device, and extends over the source layer 96, the emitter layer 94, and the semiconductor layer 93, with the gate electrode 8 provided via the gate oxide film 90.
8. Thus, in the semiconductor layer 93 of the present device, a lateral IGBT (lateral insulated gate bipolar transistor) is constructed by the collector region C, the emitter region E, and the gate region G. In order for the lateral IGBT having such a configuration to have a high withstand voltage structure, it is necessary to ensure a drift length L, which is the distance between the collector region C and the emitter region E, wider than a value that satisfies the required withstand voltage. To satisfy, the drift length L
Is set to 30 μm. Further, in order to ensure the withstand voltage of the high withstand voltage element, the thickness of the semiconductor layer 93 needs to be larger than the drift length L, and the thickness of the semiconductor layer 93 is also 3
It is set to 0 μm. The supporting substrate 91 (thickness 5)
A back surface electrode 99 is provided on the back surface opposite to the insulating film 92 (thickness: 2 μm) and a ground potential 67 is applied.

As described above, in the SOI semiconductor device having the above configuration, a wide drift length L and a semiconductor layer 93 thicker than the drift length L are required to satisfy the required breakdown voltage. Increasing the thickness of the semiconductor layer 93 has a problem that it is difficult to keep the junction capacitance low, as described above. The technical limit is about 30 μm in thickness. Further, the wide drift length L causes an increase in element isolation region width, thereby reducing the degree of integration of elements, and also causes a decrease in current output due to an increase in on-resistance.

In view of the above problems, an object of the present invention is to realize an SOI semiconductor device having high withstand voltage and high reliability by controlling the potential of a region surrounding an element formation region. I have.

[0023]

Means for Solving the Problems To solve the above-mentioned problems, the first feature of the SOI semiconductor device according to the present invention is as follows.
Means comprises: a semiconductor layer formed on a front surface side of a semiconductor substrate via a first insulating film;
An isolation groove formed through the insulating film to reach the semiconductor substrate to form an island-shaped element formation region in the semiconductor layer; a second insulating film formed on a side wall of the isolation groove; And a filling layer that is electrically conductively connected to the semiconductor substrate.
A filling layer potential regulating electrode to which a predetermined potential is applied is conductively connected to at least one of the semiconductor substrate and the filling layer, and two or more diffusion layers are formed in the element forming region. is, the predetermined potential, the potential between the two or more potential applied to the diffusion layer, the separation groove element formed territory
A semi-conductive area is formed between adjacent separation grooves.
A peripheral semiconductor region, which is a non-element formation region of the body layer, is formed.
A predetermined potential is applied to this peripheral semiconductor region.
The surrounding area potential regulating electrode to which
Characterized in that that.

In the SOI semiconductor device according to the present invention,
The second means is a first insulating film on the front side of the semiconductor substrate.
-Type semiconductor layer formed through
Penetrates the first insulating film from the front side of the semiconductor substrate and reaches the semiconductor substrate
Formed on the n-type semiconductor layer to form an island-shaped n-type element formation region.
Isolation groove forming an area, and formed on the side wall of the isolation groove
The second insulating film and the inside of the isolation trench are filled into the semiconductor substrate.
A semiconductor substrate and a filling layer having a filling layer for conductive connection
Apply a predetermined potential to at least one side of
The electrode for defining the potential of the filling layer to be connected is conductively connected, and the n-type
Two or more diffusion layers are formed in the element formation region.
At least one of the diffusion layers is p-type and the semiconductor substrate
The predetermined potential applied to the entire surface of the substrate is the maximum potential applied to the diffusion layer.
It is characterized by a high potential . The isolation groove is the element formation area
A semiconductor is formed between each adjacent isolation groove.
A peripheral semiconductor region as a non-element formation region of the layer is formed.
In this peripheral semiconductor region, a predetermined potential is applied to this region.
Make sure that the electrode for defining the potential in the surrounding area to be applied is conductively connected.
Is desirable.

A third measure taken in the SOI semiconductor device according to the present invention includes a semiconductor layer formed on a surface side of a semiconductor substrate via a first insulating film, and a first layer formed from a surface side of the semiconductor layer. An isolation groove formed to reach the insulating film to form an island-shaped element formation region in the semiconductor layer, a second insulating film formed on a side wall of the isolation groove, and a filling layer filled in the isolation groove. has a separation groove is formed in each element formation region
Te, between each isolation trench adjacent, non-element forming region serving around the semiconductor region of the semiconductor layer is formed, the peripheral
In the semiconductor region, a region to which a predetermined potential is to be applied is applied to this region.
Characterized in that the surrounding area potential regulating electrode is conductively connected.
I do . A predetermined voltage is applied to the packed bed filled in the separation groove.
The electrode for defining the potential of the packed layer to be applied
Is desirable. A predetermined potential is applied to the semiconductor substrate.
It is desirable that the substrate electrode to which
No. The predetermined potential is applied to the semiconductor element in the element formation region.
Potential equal to one of the potentials
Is desirable. A predetermined potential is formed in the element formation region.
Of the high-voltage semiconductor elements in the output stage
The potential is equivalent to the potential applied to the application side electrode.
desirable.

In the SOI semiconductor device according to the present invention,
The fourth means is that an insulating film is interposed on the front side of the semiconductor substrate.
Having a semiconductor layer formed by
In an SOI semiconductor device having a diffusion layer of
The substrate electrode that can apply a predetermined potential to the entire body substrate is conductive
This predetermined potential is applied to the diffusion layer.
A potential between two or more potentials of the SOI semiconductor device
Is about half the maximum withstand voltage. Book
Fifth means taken in SOI semiconductor device according to the invention
Is formed on the surface side of the semiconductor substrate via an insulating film.
A semiconductor layer having two or more diffusion layers
In the SOI semiconductor device to be used, the entire semiconductor substrate is
A substrate electrode to which a predetermined potential can be applied is conductively connected.
And the predetermined potential is two or more applied to the diffusion layer.
, Which is the highest of the potentials. 2 above
The above diffusion layer consists of multiple islands where the semiconductor layer is dielectrically separated.
Is desirably formed in the element formation region .

In the SOI semiconductor device according to the present invention,
The sixth means is that an insulating film is interposed on the front side of the semiconductor substrate.
The semiconductor layer formed by the dielectric is separated into multiple islands
It becomes an element formation area, and a horizontal element
The horizontal element is formed in the other element forming area while the element is formed.
SOI semiconductor on which a control element for controlling the SOI is formed
A predetermined potential is applied to the entire semiconductor substrate
The possible substrate electrodes are conductively connected, and this predetermined potential
Is the highest of the potentials applied to the lateral elements.
And features. Two or more diffusion layers are formed in the element formation region.
And a predetermined potential is applied to two or more voltages applied to the diffusion layer.
It is desirable that the potential be between the potentials. The predetermined potential is S
The potential is almost half of the maximum withstand voltage of the OI semiconductor device.
desirable. The predetermined potential is the highest potential applied to the diffusion layer
It is desirably an intermediate potential between the first potential and the lowest potential .

In the SOI semiconductor device according to the present invention,
The seventh means is that a first insulating film is provided on the front side of the semiconductor substrate.
Semiconductor layer formed through
Through the first insulating film to reach the semiconductor substrate.
Separation to form island-shaped device formation region in semiconductor layer
A groove, a second insulating film formed on a side wall of the separation groove,
Filling that fills the inside of the separation groove and conductively connects to the semiconductor substrate
And at least one of the semiconductor substrate and the filling layer.
On one side, there is also a packed bed electrode to which a predetermined potential is to be applied.
The position defining electrode is conductively connected, and 2
The above diffusion layer is configured and applied to the entire semiconductor substrate.
The predetermined potential is between two or more potentials applied to the diffusion layer.
Potential, which is approximately half of the maximum withstand voltage of the SOI semiconductor device.
Is a potential. Further, the SO according to the present invention
The eighth measure taken in the semiconductor device is a semiconductor substrate.
Semiconductor layer formed on the surface side of the semiconductor via a first insulating film
Through the first insulating film from the surface side of the semiconductor layer.
An island-shaped element is formed on the semiconductor layer until it reaches the semiconductor substrate.
Isolation grooves that form the element formation regions, and
The second insulating film formed and the semiconductor filled with the inside of the isolation groove.
A filling layer conductively connected to the semiconductor substrate;
And at least one of the packed layers
The filling layer potential regulating electrode to which the potential is to be applied is conductively connected.
In the element formation region, two or more diffusion layers are formed,
A predetermined potential applied to the entire conductor substrate is applied to the diffusion layer.
Intermediate potential between the highest and lowest applied potential
It is characterized by . In the SOI semiconductor device according to the present invention
A ninth measure taken is to form an insulating film on the front side of the semiconductor substrate.
A semiconductor layer formed through the
In an SOI semiconductor device having an upper diffusion layer,
A board electrode capable of applying a predetermined potential is applied to the entire conductor board.
This predetermined potential is applied to the diffusion layer.
It is an intermediate potential between the highest potential and the lowest potential
And

In the present invention, the SOI semiconductor device is not limited to a semiconductor device using an SOI substrate, but a dielectric isolation in which a semiconductor layer as an element formation region is separated by a dielectric serving as an insulator. It refers to a semiconductor device having a structure.

[0030]

In the semiconductor device having the dielectric isolation structure according to the present invention in which the above first means is employed, the isolation groove extends from the surface of the semiconductor layer to the semiconductor substrate through the first insulating film. Since the formed filling layer inside the separation groove is conductively connected to the semiconductor substrate, all the separation grooves are in the same potential state as the semiconductor substrate. Therefore, the potential of the filling layer inside the separation groove is fixed at the potential of the semiconductor substrate and does not fluctuate.
The semiconductor element formed in the element formation region is not affected by the fluctuation of the potential. Further, since the influence of the potential of the semiconductor element formed in the element formation region does not affect the potential of the filling layer inside the separation groove, the potential between the semiconductor elements in the element formation region adjacent to each other via the separation groove is low. Do not affect each other. That is, in the present invention, the element formation region is electrostatically shielded by the semiconductor substrate and the filling layer that are conductively connected, so that the element characteristics of the semiconductor element are stabilized and a highly reliable SOI semiconductor device can be realized. In addition, since the filling layer potential regulating electrode is conductively connected to the back surface side of the semiconductor substrate or the like, a predetermined potential can be applied to the filling layer via the semiconductor substrate, and the potential of any of the filling layers can be reduced. Since the potential is fixed at a predetermined potential, the potential of the filling layer inside the separation groove does not fluctuate, and the semiconductor elements do not influence each other via the separation groove, so that the element characteristics are further stabilized. Similarly , the third means also
Surrounding the semiconductor region is formed between the isolation trench isolation trench adjacent formed for each element formation region and the surrounding region the potential regulating electrode in this region is connected electrically conductive, element forming regions each other, Since the elements are separated by the peripheral semiconductor region in addition to the isolation groove, and the potential of the peripheral semiconductor region is fixed at a predetermined potential, potential interference between semiconductor elements in adjacent element forming regions. And stabilization of device characteristics is remarkable. Further, since the predetermined potential is set to a potential between two or more potentials applied to the diffusion layer, the withstand voltage performance can be improved.

In the second means, the filling layer potential regulating
The predetermined potential applied to the electrode is the lowest potential applied to the diffusion layer
Or, because it is not a low potential but the highest potential, the semiconductor substrate
Feel that the whole and the packed bed are specified at their highest potential
Function as a plate, applying the lowest potential to the p-type diffusion layer
In the reverse bias state, the first facing the p-type diffusion layer
An electron storage layer is formed at the interface between the first insulating film and the second insulating film.
And the electric field strength rises sharply at the interface
In this way, the reverse bias potential is
The electric field intensity in the element formation region can be moderated.
The breakdown voltage of the device built in the device formation region
The width can be improved. In addition, the fifth and sixth means
Has the same effect.

In the fourth means, the voltage is applied to the substrate electrode.
The predetermined potential is not the minimum potential or the low potential,
Since the potential is almost half of the maximum withstand voltage of the conductor device, semiconductor
The entire substrate is set at a potential of approximately half of its maximum withstand voltage
Acts as a field plate and occurs in the semiconductor layer
End of the equipotential line that is approximately half of the highest withstand voltage in the potential distribution
Passes through the semiconductor substrate, causing the
The potential distribution is based on equipotential lines that are approximately half of the maximum withstand voltage.
The distribution is regulated between the highest potential side and the lowest potential side. this
Therefore, the intervals between the equipotential lines generated in the semiconductor layer are reduced.
Greatly improves the withstand voltage of devices built into the semiconductor layer
Can be The same operation is performed in the seventh means.
Use effect.

According to an eighth means, the filling layer potential regulating
The predetermined potential applied to the electrode is not the lowest potential or low potential.
The highest and lowest potentials applied to the diffusion layer in the element formation region
Since this is an intermediate potential with respect to the potential,
The filling layer has a field plate defined at its intermediate potential and
Functioning as a potential distribution in the element formation region.
The end of the equipotential line of the intermediate potential passes through the semiconductor substrate
Therefore, the potential distribution generated in the element formation region
Is divided into the highest potential side and the lowest potential side based on
Be regulated. Therefore, an equipotential generated in the element formation region
Since the spacing between lines becomes sparse, it was built in the element formation area
The withstand voltage of the element can be greatly improved. The ninth
The same operation and effect can be obtained by the means described above.

As described above, when the element formation region or the periphery of the semiconductor layer is set to the intermediate potential, the element formation region or the semiconductor layer has a gap between the diffusion layer and the semiconductor substrate, the filling layer or the surrounding semiconductor region. It is possible to divide the density of the expanding equipotential lines by the intermediate potential. Therefore, the density of equipotential lines, that is, the concentration of the electric field can be reduced, and the withstand voltage performance can be improved. Further, by applying the intermediate potential, the potential applied to the insulating layers (first and second insulating films) surrounding the element formation region can be reduced, and the apparent breakdown voltage between elements can be improved. High dielectric strength elements can be applied to dielectric isolation. If the intermediate potential is a potential between two or more potentials applied to two or more diffusion layers, an effect of improving withstand voltage can be obtained. Furthermore, by applying a difference between the maximum applied voltages of two or more potentials as an intermediate potential, that is, a potential that is substantially half of the maximum withstand voltage, the density of equipotential lines can be equalized, and a substantially maximum withstand voltage characteristic is obtained. It becomes possible. In addition, by applying to the semiconductor substrate a potential equal to the high voltage application electrode side potential of the high breakdown voltage element formed in the element formation region of the semiconductor layer, the electric field strength increases at the interface between the semiconductor layer and the insulating film, Withstand voltage can be provided inside the insulating film. Therefore, it is possible to suppress the expansion of the depletion layer in the thickness direction of the semiconductor layer, and it is possible to improve the breakdown voltage in the thickness direction of the semiconductor layer. Therefore,
Since the required breakdown voltage can be secured with a thin semiconductor layer,
The device can be made thinner. In addition, as the thickness of the semiconductor layer is reduced, the time and cost required for forming a substrate such as a separation groove can be reduced, and the width of the separation groove can be reduced, so that the degree of integration of the device can be improved. .

[0035]

Next, an embodiment of the present invention will be described with reference to the accompanying drawings.

Embodiment 1 FIG. 1 is a schematic sectional view showing a part of an SOI semiconductor device having a dielectric isolation structure according to Embodiment 1 of the present invention.

In this figure, the semiconductor device 1 of the present example has
A semiconductor element is formed in an element formation region having an SOI structure using the dielectric isolation substrate 2, thereby forming an integrated circuit. The dielectric isolation substrate 2 includes a semiconductor support substrate 3 serving as a first silicon substrate and the semiconductor support substrate 3.
An n-type semiconductor layer 5, which is a second silicon substrate, bonded to the substrate via a silicon oxide film 4 (first insulating film);
The semiconductor layer 5 is formed from the surface side of the semiconductor layer 5 until it reaches the semiconductor support substrate 3 through the silicon oxide film 4.
A trench 6 for isolating elements into island-shaped element forming regions 5a, 5b, 5c, 5d, a sidewall insulating film 7 (second insulating film) as a silicon oxide film formed on the side wall of the separating trench 6, Polycrystalline semiconductor layer 8 (filled layer), which is a polycrystalline silicon film filled in isolation trench 6 and conductively connected to semiconductor support substrate 3
And Here, each element formation region 5a of the semiconductor layer 5
5d include a first diode 9a, an npn transistor 9b, a MOSFET 9c, and a second diode 9d.
And the like, and each wiring layer 15 is conductively connected to these semiconductor elements via connection holes of the interlayer insulating film 14. On the other hand, the semiconductor support substrate 3
A filling layer potential regulating electrode 10 serving as a back surface electrode for applying a predetermined potential to the polycrystalline semiconductor layer 8 inside each separation groove 6 via the semiconductor support substrate 3 is formed on the back side of the semiconductor substrate 3.

Since the semiconductor device 1 having such a structure has a dielectric isolation structure, the operation is reliable and stable. Particularly, a circuit requiring high operation reliability, a high voltage signal and a high frequency signal are required. In addition to the advantage that the semiconductor device is not affected by ambient potential fluctuations, the device characteristics of the semiconductor device are stable. That is, since the isolation groove 6 is formed from the surface of the semiconductor layer 5 to the semiconductor support substrate 3, any of the polycrystalline semiconductor layers 8 inside the isolation groove 6 is conductively connected to the semiconductor support substrate 3. Therefore, each of the separation grooves 6 is in the same potential state as the semiconductor supporting substrate 3 and the potential is hardly fluctuated. Therefore, the element formation region 5
npn transistors 9b, MOS formed in a to 5d
The semiconductor element such as the FET 9 c is hardly affected by the potential change of the polycrystalline semiconductor layer 8, and the influence of the potential change of the semiconductor element does not affect the potential of the polycrystalline semiconductor layer 8. There is no potential interference between the semiconductor elements in the corresponding element formation region. Also, the semiconductor support substrate 3
Since the filling layer potential regulating electrode 10 is conductively connected to the back side of the semiconductor device, a predetermined potential can be applied from the filling layer potential regulating electrode 10 to fix the potential of the polycrystalline semiconductor layer 8. For this reason, the potential of the separation groove 6 does not fluctuate, and there is no potential interference between the semiconductor elements in the element formation regions adjacent to each other via the separation groove 6. Therefore, each semiconductor element has stable element characteristics. Therefore, in an integrated circuit or the like configured in the SOI semiconductor device having such a structure, it is possible to achieve high reliability important for a logic device and the like.

An example of a method for manufacturing the dielectric isolation substrate 2 among the methods for manufacturing the semiconductor device 1 having such a configuration will be described with reference to FIGS. FIG.
3D and FIGS. 3A to 3C are process cross-sectional views showing a part of the method for manufacturing the dielectric isolation substrate 2.

First, as shown in FIG. 2A, an acceleration voltage of 120 keV is applied to the semiconductor layer 5 as one of the two silicon wafers as the semiconductor layer 5 and the semiconductor support substrate 3. Dose amount is 3.5 × 10 ¹⁴ c
Arsenic is ion-implanted under the condition of m− ² , and thermal oxidation is performed for about 5 hours in a steam atmosphere at a temperature of about 1200 ° C. to form a silicon oxide film 4 having a thickness of 2 μm. Subsequently, the wafer as the semiconductor layer 5 and the semiconductor support substrate 3
In a state in which the wafer is brought into contact through the silicon oxide film 4 as a heat treatment for 2 hours in an N ₂ atmosphere (about 110
0 ° C.) to form an SOI wafer, and then thermally oxidize for about 40 minutes in a steam atmosphere at a temperature of about 1100 ° C. to form a 0.5 μm thick semiconductor layer 5 on the surface side. A thermal oxide film 11 is formed. Subsequently, a first mask layer 12 is formed to a thickness of about 1 μm on the thermal oxide film 11, and a second mask layer 13 is formed to a thickness of about 1 μm on the surface side.
Here, as the first mask layer 12, a mixed gas of helium gas and about 20% silane gas is used, the temperature is about 400 ° C., the time is about 80 minutes, and the reduced pressure condition is about 40 minutes.
A polycrystalline silicon film formed by a thermal CVD method under the conditions of Pa and a gas flow rate of about 250 cc / min was used. On the other hand, as the second mask layer 13, about 2
Using a mixed gas of 0% silane gas and oxygen gas,
The temperature is about 400 ° C, the time is about 80 minutes, and the reduced pressure condition is about 9
0Pa, the gas flow rate of the mixed gas of SiH ₄ / He is about 4
00 cc / min, the gas flow rate of oxygen gas is about 60 cc / min.
A silicon oxide film formed by a thermal CVD method under min conditions was used. In addition, as the second mask layer 13,
A silicon oxide film obtained by thermally oxidizing the polycrystalline silicon film used as the first mask layer 12 can also be used.

Next, a resist pattern is formed on the second mask layer 13 by photolithography.
As shown in (b), the second mask layer 13 on the surface of the separation groove forming region 6a is removed by a reactive ion etching method using a fluorine-based mixed gas, and further a chlorine-based mixed gas or a fluorine-based mixed gas is used. By reactive ion etching method or plasma etching method using a system mixed gas,
First mask layer 1 on the surface of separation groove formation planned region 6a
2 is removed, and the thermal oxide film 11 on the surface of the separation groove forming region 6a is removed by a fluorine-based reactive ion etching method, and the separation groove forming region 6a is opened.

Next, as shown in FIG. 2C, using the second mask layer 13 as a mask, the semiconductor layer 5 is subjected to a plasma etching method using a mixed gas of sulfur hexafluoride and oxygen. The depth reaching the silicon oxide film 4 is 3
A separation groove 6 of 0 to 50 μm is formed. Here, the separation groove 6
Is 2 to 8 μm. At this time, the second mask layer 1
3 is also etched by about 0.8 μm.

Next, as shown in FIG. 2D, thermal oxidation is performed for about 150 minutes in a steam atmosphere at a temperature of about 1100 ° C., so that a silicon A sidewall insulating film 7 serving as an oxide film is formed. At this time, the first mask layer 13 on the surface side of the semiconductor layer 5 is also oxidized to a thickness of about 0.6 μm.

Next, as shown in FIG. 3A, the silicon oxide film 4 on the bottom 6b of the separation groove 6 is removed by a fluorine-based reactive ion etching method, and the separation groove 6 is semi-conductive. It reaches the substrate 3. At this time, the semiconductor layer 5
Is removed, the first mask layer 12 is exposed, and the first mask layer 12 is also etched by about 0.1 μm.

Next, as shown in FIG. 3B, the inside of the separation groove 6 is filled with a polycrystalline semiconductor layer 8 as polycrystalline silicon formed by a thermal CVD method. As a result, at the bottom 6 b of the isolation groove 6, the polycrystalline semiconductor layer 8 is brought into a state of being conductively connected to the semiconductor support substrate 3. Here, the conditions for forming the polycrystalline semiconductor layer 8 are the same as those for forming the first mask layer 11. However, the processing time is about 540 minutes. At this time, a polycrystalline semiconductor layer 8a having a thickness of about 9 μm is formed on the surface of the first mask layer 12.

Next, as shown in FIG. 3C, the unnecessary polycrystalline semiconductor layer 8a and the first mask layer 12 outside the isolation trench 6 are removed by fluorine-based plasma etching or polishing. Then, the thermal oxide film 11 is removed with diluted hydrofluoric acid. As a result, the polycrystalline semiconductor layer 8 inside the isolation trench 6
And the semiconductor support substrate 3 are in contact with each other at the bottom 6b of the isolation groove 6, while the semiconductor layer 5 is isolated by the silicon oxide film 4 and the isolation groove 6 including the side wall insulating film 7 and the polycrystalline semiconductor layer 8 as a filling layer. The dielectric isolation substrate 2 including the formed element formation regions 5a to 5d is formed.

Thereafter, the element formation region 5 of the semiconductor layer 5 is formed.
As shown in FIG. 1, semiconductor elements such as a first diode 9a, an npn transistor 9b, a MOSFET 9c, and a second diode 9d are formed for the elements a to 5d. Then, each wiring layer 15 is conductively connected to the semiconductor element. Further, a filling layer potential regulating electrode 10 for applying a predetermined potential to the polycrystalline semiconductor layer 8 inside each separation groove 6 is formed on the back side of the semiconductor supporting substrate 3 through the semiconductor supporting substrate 3. Thus, the SOI semiconductor device 1 having the dielectric isolation structure is manufactured.

Embodiment 2 FIG. 4 is a schematic sectional view of an SOI semiconductor device using a dielectric isolation substrate according to Embodiment 2 of the present invention, and FIG. 5 is a schematic plan view thereof.

In these figures, the semiconductor device 2 of this example is shown.
The dielectric isolation substrate 22 used in Example 1 includes a semiconductor support substrate 23 as a silicon substrate and a silicon oxide film 24 on the surface side thereof.
N-type semiconductor layer 2 formed via (first insulating film)
5 and the silicon oxide film 2 from the surface side of the semiconductor layer 25.
4, the isolation trenches 26a, 26 forming island-shaped element formation regions 25a, 25b in the semiconductor layer 25.
b, sidewall oxide films 27a and 27b (second insulating films), which are silicon oxide films formed on the sidewalls of the isolation trenches 26a and 26b, and a polycrystalline silicon film filled inside the isolation trenches 26a and 26b. And polycrystalline semiconductor layers 28a and 28b (filled layers).

In the semiconductor device 21 of this embodiment,
The separation grooves 26a and 26b are formed around each of the element forming regions 25a and 25b, and are electrically independent from the adjacent separation grooves. That is, the isolation groove 26a isolates the element formation region 25a, while the isolation groove 26b isolates the element formation region 25b. As a result, the semiconductor layer 2 is located between the adjacent isolation grooves 26a and 26b.
5 are non-element forming region serving around the semiconductor region 29 is formed, in the semiconductor device 2 of the present embodiment, the surface side of the peripheral semiconductor region 29, peripheral region potential regulating to be applied a predetermined potential in this region The electrode 33 is electrically conductively connected through a connection hole of the interlayer insulating film 32. Here, the separation grooves 26a,
Since 26b is formed for each of the element formation regions 25a and 25b, the peripheral semiconductor region 29 is conductive around any of the element formation regions 25a and 25b on the semiconductor layer 25. Therefore, the peripheral region potential regulating electrode 33 is conductively connected to any one of the peripheral semiconductor regions 29, and is in a state of being conductively connected to any of the peripheral semiconductor regions 29.

Further, the npn transistor 30 is formed in the element formation region 25a, while the npn transistor 30 is formed in the element formation region 25a.
A MOSFET 31 is formed in 5b, and a collector electrode 30b is conductively connected to a collector region 30a of the npn transistor 30 via a connection hole in the interlayer insulating film 32. This collector electrode 30b
Is also electrically connected to the polycrystalline semiconductor layer 28a inside the isolation groove 26a for isolating the element forming region 25a through the connection hole of the interlayer insulating film 32, thereby lowering the potential of the polycrystalline semiconductor layer 28a. It is a filling layer potential regulating electrode which is set to the same potential as the collector potential of the npn transistor 30. On the other hand, the drain electrode 31 is connected to the drain region 31a of the MOSFET 31 through the connection hole of the interlayer insulating film 32.
b is conductively connected, and the drain electrode 31 b is further connected to the element forming region 25 through a connection hole of the interlayer insulating film 32.
b is also electrically connected to the polycrystalline semiconductor layer 28b inside the isolation trench 26b separating the elements, and serves as a filling layer potential regulating electrode that makes the potential of the polycrystalline semiconductor layer 28b the same as the drain potential of the MOSFET 31. ing.

[0052] In the semiconductor device 2 1 with such a configuration, separation grooves 26a, 26b are element formation regions 25a, 25
b, each adjacent separation groove 26 is formed.
A peripheral semiconductor region 29 which is a non-element formation region of the semiconductor layer 25 is formed between a and 26b. Therefore, each of the element formation regions 25a and 25b is separated from each other by the separation grooves 26a and
Since the element is separated by the peripheral semiconductor region 29 in addition to the element isolation by 26b, the withstand voltage (isolation voltage) between the element formation regions 25a and 25b is high. For example, if the structure of this example is adopted for a conventional semiconductor device corresponding to 500 V, an isolation voltage of 700 V or more can be obtained. Moreover, the npn transistor 30 and the MOSFE
Semiconductor elements such as T31 do not affect each other due to potential fluctuation and do not interfere with each other. In any of the regions, the surrounding semiconductor regions 29 are at the same potential, so that the polycrystalline semiconductor layers 28a, 28 inside the isolation trenches 26a, 26b.
8b does not change unnecessarily. Further, in this example, the potential of the peripheral semiconductor region 29 is fixed to the potential applied via the peripheral region potential fixing electrode 33, so that the potential between the semiconductor elements formed in the element formation regions 25a and 25b is reduced. Thus, the element characteristics are further stabilized without affecting the potential. In addition, the separation groove 26
In the polycrystalline semiconductor layer 28a of FIG.
The collector potential of the applied, since the polycrystalline semiconductor layer 28b of the isolation trench 26b is in a state in which the drain potential of the MOSFET31 is applied, corresponding to the potential state of these semiconductor devices, polycrystalline semiconductor layer 28a , 28b fluctuate under predetermined conditions and are relatively fixed. Therefore, the fluctuation in the potential of the polycrystalline semiconductor layers 28a and 28b does not disturb the potential distribution in the element formation regions 25a and 25b, and there is no interference between the semiconductor elements. Therefore, stabilization of the device characteristics of the semiconductor device is remarkable. As described above, also in the present embodiment, the potential around the element formation region can be stabilized, and the reliability of the circuit formed on the SOI semiconductor device can be increased as in the first embodiment. .

The method of manufacturing the semiconductor device 1 having such a configuration is the same as that of the conventional method of manufacturing a semiconductor device described with reference to FIGS. It can be easily formed only by changing the pattern and changing the formation pattern of the electrode layer and the wiring layer for each semiconductor element.

The structure of the peripheral semiconductor region 29 employed in the semiconductor device 21 having the dielectric isolation structure of the second embodiment is combined with the structure of the semiconductor device 1 having the dielectric isolation structure of the first embodiment. A separation groove reaching the semiconductor substrate from the surface side of the layer, a filling layer potential defining electrode for fixing the potential of the polycrystalline semiconductor layer (filling layer), and a peripheral region potential defining electrode for defining the potential of the peripheral semiconductor region. May be configured.

Third Embodiment FIG. 6A is a schematic sectional view of an SOI semiconductor device using a dielectric isolation substrate according to a third embodiment of the present invention, and FIG. 6B is a schematic plan view thereof.

In these figures, the dielectric isolation substrate 42 of the semiconductor device 41 having the dielectric isolation structure of the present embodiment has a silicon oxide film on the front surface side of the semiconductor support substrate 43, similarly to the semiconductor device of the first embodiment. An n-type semiconductor layer 45 serving as a second silicon substrate bonded via a 44 (first insulating film), and reaches the semiconductor support substrate 43 through the silicon oxide film 44 from the surface side of the semiconductor layer 45. And the island-shaped element formation regions 45a and 45b are formed in the semiconductor layer 45.
Separation grooves 46a and 46b forming the
Side wall oxide films 47a, 47 formed on the side walls of a, 46b
b (second insulating film) and polycrystalline semiconductor layers 48a and 48b (filling layers), which are polycrystalline silicon films filled in the isolation grooves 46a and 46b and conductively connected to the semiconductor support substrate 43.
And Here, each element formation region 4 of the semiconductor layer 44
5a and 45b include an npn transistor 49a and M
OSFETs 49b are respectively formed. On the back side of the semiconductor support substrate 43, the polycrystalline semiconductor 4 inside each of the isolation grooves 46 a and 46 b is interposed via the semiconductor support substrate 43.
A filling layer potential regulating electrode 70 for applying a prescribed potential to 8a and 48b is formed.

Further, in the semiconductor device 41 of this example, the isolation grooves 46a and 46b are formed in the element forming regions 45a and 4b.
It is formed around every 5b and is in an electrically independent state. That is, the isolation groove 46a isolates the element formation region 45a, while the isolation groove 46b isolates the element formation region 45b. A peripheral semiconductor region 71, which is a non-element formation region of the semiconductor layer, is formed between the adjacent isolation grooves 46a and 46b. On the surface side of the peripheral semiconductor region 71, an interlayer insulating film 72 is formed. A peripheral region potential defining electrode 73 to which a predetermined potential is to be applied to the peripheral semiconductor region 71 is conductively connected via the connection hole. Here, the isolation grooves 46a and 46b are formed in the element formation region 45.
a, 45b, the peripheral semiconductor region 7
Reference numeral 1 denotes any one of the element forming regions 45a, 4a on the semiconductor layer 45.
5B, the peripheral region potential regulating electrode 73 can be conductively connected to the peripheral semiconductor region 71 only at one place, and the potential of the entire peripheral semiconductor region 71 can be fixed. .

In the semiconductor device 41 having such a configuration, as in the semiconductor device of the first embodiment, the separation grooves 46a, 4
Polycrystalline semiconductor layers 48a, 48b filled inside 6b
Are conductively connected to the semiconductor support substrate 43 and are in the same potential state as the semiconductor support substrate 43, and the potential does not change. In addition, the influence of the potential fluctuation of the semiconductor elements formed in the element formation regions 45a and 45b is affected by the separation grooves 46a and 46b.
Therefore, the device characteristics of the other semiconductor device are not changed via the device, and the device characteristics are stabilized. In addition, a potential is applied via the filling layer potential defining electrode 70, and the potential of each of the polycrystalline semiconductor layers 48 and 48b is fixed.
Since the potential of the adjacent semiconductor elements does not affect each other, the element characteristics are further stabilized.

Moreover, in this embodiment, the element formation region 4
5a, 4 5 b is between the two rows of the separation grooves 46a, 46b
And the surrounding semiconductor region 71, the withstand voltage between them is high, and there is no potential interference between the semiconductor elements. Further, since a predetermined potential can be applied to the peripheral semiconductor region 71 via the peripheral region potential fixing electrode 73, the potential of the peripheral semiconductor region 71 is fixed at a predetermined potential, and the potential fluctuation of the peripheral semiconductor region 71 is changed. There is no. Therefore, the stabilization of the device characteristics of the semiconductor device is remarkable.

In each of the embodiments, the dielectric isolation substrate is manufactured from the bonded substrate. However, the present invention is not limited to this, and the dielectric isolation substrate may be manufactured from a substrate having a semiconductor layer deposited on the front surface side of the semiconductor substrate. Also, the type of semiconductor element formed in the element formation region is a property to be designed according to the type of integrated circuit formed in the semiconductor device, and the like.
There is no limitation on the type. Further, as the filling layer, a single crystal semiconductor layer, an amorphous semiconductor layer, a conductive material layer, or the like can be employed in addition to the polycrystalline semiconductor layer.

Embodiment 4 In the above embodiment, the semiconductor supporting substrate surrounding the element forming region, the polycrystalline semiconductor layer serving as the filling layer, or the peripheral semiconductor region serving as the non-element forming region is formed by a predetermined method. By fixing the potential, the characteristics of the element formed in the element formation region are stabilized. By setting the predetermined potential to an intermediate potential between a plurality of potentials applied to the elements, the withstand voltage between the elements can be improved. In this embodiment,
Description will be made based on the case where the semiconductor supporting substrate is set at the intermediate potential. It goes without saying that not only the semiconductor substrate but also the case where the filling layer and the surrounding semiconductor region are set at an intermediate potential is the same.

FIG. 7 shows an SOI semiconductor device using the dielectric isolation substrate described above with reference to FIG. 27, in which a diode is formed in the element formation region 50. In the device of this embodiment, phosphorus and boron, which are high-concentration impurities, are ion-implanted into the n-type semiconductor layer 53 in the element formation region 50 from the window of the insulating film 56a, and the n ⁺ -type cathode layer 6 is formed.
2 and a p ⁺ type anode layer 63 are formed. Further, a cathode electrode 64 and an anode electrode 65 are connected to each layer by an aluminum electrode, and a back surface electrode 66 is provided on the back surface of the support substrate 51 made of silicon. Therefore, the SOI semiconductor device of this example has a horizontal diode. Note that the insulating film 52 is made of a silicon oxide film , and the impurity concentration of the semiconductor layer 53 is 1 × 10 ¹⁴ cm ⁻³ . The thickness of the insulating film 52 is 1 μm, the thickness of the semiconductor layer 53 is 30 μm, and the distance between the cathode layer 62 and the anode layer 63 is 7 μm.
0 μm.

FIG. 8 shows the semiconductor device of this example in which the semiconductor layer 53 sandwiched between the anode layer 63 and the cathode layer 62 when a positive potential is applied to the cathode electrode 64 with the anode electrode 65 as the ground potential. (Indicated by ab) is shown. Anode electrode 65 and cathode electrode 64
Is the same as that of the conventional semiconductor device shown in FIG. However, in this example, a positive potential is applied to the back electrode 66 to which a ground potential has been applied conventionally. Accordingly, when the positive potential applied to the cathode electrode 64 is gradually increased, the equipotential lines are maintained between the anode layer 63 and the insulating film 52 until the potential of the cathode electrode 64 becomes equal to the potential of the back electrode 66. Distributed. When the potentials of the cathode electrode 64 and the back electrode 66 become equal, the equipotential lines 202 of the potential pass through the insulating film 52 and reach the support substrate 51.

Further, when the potential applied to the cathode electrode 64 is increased, the equipotential line having a higher potential is further divided by the equipotential line 202 which is the potential of the back electrode 66 and the cathode layer 62 and the insulating film 52. Spread between. If the conventional anode electrode 65 and the back electrode 66 which is also the ground potential, equipotential lines was distributed between the absolute Enmaku 52 and cathode layer 62. On the other hand, in the semiconductor device of this example, an equipotential line between the potential applied to the anode electrode 65 and the potential applied to the back electrode 66 is formed between the anode layer 63 and the insulating film 52. On the other hand, the equipotential lines between the potential applied to the back electrode 66 and the potential applied to the cathode electrode 62 correspond to the cathode layer 62 and the insulating film 52.
Distributed between Therefore, conventionally, the cathode layer 62 directly under
The equipotential lines are distributed also becomes possible to disperse directly under the anode layer 63, the density of the equipotential lines can be greatly relaxed. This means that the electric field immediately below the cathode layer 62 has been alleviated, thereby preventing avalanche breakdown and improving the withstand voltage performance near the cathode layer 62.

When the potential difference applied between the cathode electrode 64 and the anode electrode 65 is known, a potential that is substantially half of that, that is, an arithmetic average potential, is applied to the back surface electrode, so that the portion immediately below the anode layer 63 and the cathode layer 62 are applied. It is possible to evenly distribute the equipotential lines directly below. Therefore, by applying such a potential to the back surface electrode, it is possible to set the breakdown voltage characteristics of the semiconductor device of this example to substantially the maximum. In the above description, the anode electrode 65 is set at the ground potential. However, the back electrode 66 may be set at the ground potential.
, A negative potential opposite to that of the cathode electrode 64 may be applied.

The above description is based on the semiconductor support substrate 51 for simplicity.
The relationship between the element formed in the element formation layer 53 and the potential set around the element formation layer 53 is described with attention paid only to (1). However, not only the semiconductor support substrate 51 but also the semiconductor device in which the separation groove or the peripheral semiconductor region is formed as shown in the first to third embodiments.

FIG. 9 shows a case of a semiconductor device in which the separation groove 6 is formed. In the conventional semiconductor device in which a separation groove is formed as shown in FIG. 24, the separation groove is separated from the support substrate, and even when an intermediate potential is applied to the support substrate, the filling layer in the separation groove is the same as the anode electrode. When the ground potential is reached, the equipotential lines spread from the interface between the side wall insulating film of the isolation trench and the semiconductor layer, and the equipotential lines are dense between the cathode layer and the isolation trench in the vicinity thereof. Therefore, dielectric breakdown occurs in this portion.

However, in the semiconductor device shown in FIG. 9, the insulating film 4 at the bottom of the isolation groove 6 has been removed.
The filling layer 8 separated by the side wall insulating film 7 is in electrical contact with the support substrate 3. Therefore, the potential of the filling layer 8 is the same as that of the support substrate 3. Therefore, as described above, by setting the potential of the support substrate 3 to an intermediate potential between the potential of the anode electrode 65 and the potential of the cathode electrode 64, the potential of the filling layer 8 also becomes the intermediate potential. Therefore, a cathode electrode 64 is provided between the cathode layer 62 and the side wall insulating film 7.
Only the equipotential lines between the potential and the intermediate potential are expanded, and the concentration of the electric field is reduced. Thus, the separation groove 6
Also in the SOI semiconductor device in which is formed, by setting the potential of the filling layer 8 and the supporting substrate 3 formed around the semiconductor layer 5 as the element forming layer to the intermediate potential, the characteristic of the element formed in the element forming layer can be improved. Stabilization is achieved, and furthermore, the withstand voltage characteristics can be improved.

FIG. 10 shows the relationship between the substrate potential applied to the back electrode 66 and the withstand voltage performance of the element formed in the element formation region, using the results of an experiment conducted on the semiconductor device having the structure shown in FIG. It is. It is understood that, when the substrate potential is increased, the electric field concentration between the element and the supporting substrate is reduced, and the withstand voltage of the element is improved. In addition, by applying a high substrate potential, it is difficult to improve the breakdown voltage performance conventionally.
It can be seen that high breakdown voltage characteristics can be obtained also in the OI semiconductor device.

In the semiconductor device shown in FIG.
By connecting the filling layer 8 to the support substrate 3, the filling layer 8
Although the same intermediate potential as that of the supporting substrate 3 is applied to the filling layer, even if the filling layer is insulated from the supporting substrate 3, the same effect as described above can be obtained by connecting an electrode capable of applying the intermediate potential to the filling layer. Can be obtained. Also, even in the case where the peripheral semiconductor region is provided in addition to the isolation trench, by setting the potential of the peripheral semiconductor region to an intermediate potential, the reliability of the device characteristics is improved and the withstand voltage characteristics are improved. It is possible to Furthermore, in the above description, the description is made based on the semiconductor device in which the diode is formed in the element formation region. However, it is needless to say that a similar effect can be obtained even when an element such as a transistor is formed. .

[Embodiment 5] FIG. 11 shows a structure of S which can improve the isolation breakdown voltage between elements.
An OI semiconductor device is shown. FIG. 11 shows an SOI semiconductor device using the dielectric isolation substrate (filled support substrate) 71 described above with reference to FIG.
In each of a to 71c, an npn transistor is formed. In the device of the present example, a V-shaped groove is formed by performing anisotropic etching from the front surface side on a silicon-made n-type substrate having a crystal plane orientation (100) to be the semiconductor layer 73, thereby forming a separation groove 75. After oxidizing the surface of the substrate on which the separation groove 75 has been formed to form a thermal oxide film serving as the insulating film 72, a thick polycrystalline silicon layer 71 is deposited on the insulating film 72. At this time, the separation groove 75 is filled with the polycrystalline silicon layer 71. Subsequently, when the n-type substrate is polished from the back surface side until the tip of the separation groove 75 is exposed, the separation groove 75 is divided into island regions, and the filled support substrate (polycrystalline silicon layer) 71 is formed by the insulating film 72. An element forming region which is dielectrically isolated from the substrate is obtained. The n-type substrate is turned upside down to obtain a dielectric isolation substrate 71 shown in FIG. Phosphorus and boron ions are implanted into the element formation regions 71a to 71c of the dielectric isolation substrate 71 thus formed to form a p-type base layer 81, an n ⁺ -type emitter layer 82, and an n ⁺ -type collector. A layer 83 is formed to build an npn transistor.
Further, on the back surface of the dielectric isolation substrate 71, a back electrode 76 is provided.
Is installed.

In the semiconductor device of this embodiment, the potential applied to the back electrode 76 is an intermediate potential of a plurality of potentials applied to the device, that is, each element formed in the element formation region. Is a potential of an arithmetic average of a maximum value and a minimum value of a plurality of potentials applied to the pixel. For example, when a maximum voltage of 600 V is applied to the element 101 formed in the element formation region 71b and a minimum voltage of 0 V is applied to the element 102 formed in the adjacent element formation region 71a, Is 600V
And 300V which is an intermediate voltage between 0V and 0V. Therefore, the maximum voltage applying element 101 and the minimum voltage applying element 10
2 is 600 V , the insulating film 72 between the maximum voltage applying element 101 and the dielectric isolation substrate 71.
b, the minimum voltage applying element 102 and the dielectric separation substrate 7
1, the voltage applied to the insulating film 72a is 300 V, which is almost half the withstand voltage of the insulating film 72 having a thickness of 1 μm. Can be achieved. Of course, the isolation breakdown voltage between the elements can be improved. Here, the back electrode 7
In the case of a semiconductor device having a structure in which a voltage of 600 V is applied to the rear surface electrode 6, 600 V
V can be set to 1200 V, which is obtained by adding 600 V to the withstand voltage of the insulating film 72 having a thickness of 1 μm, and the withstand voltage characteristic of the device can be set to the maximum.

Embodiment 6 FIG. 12 is a cross-sectional view showing a configuration of an SOI semiconductor device using a dielectric isolation substrate according to Embodiment 6 of the present invention. Semiconductor layer 5 formed
3 denotes a plurality of element forming regions 51a to 51
1c. The p-type base layer 84 and the p-type base layer 84 are implanted into the element formation region 51b by ion implantation of phosphorus and boron.
An n ⁺ -type emitter layer 85 and an n ⁺ -type collector layer 86 are formed, and an npn transistor is constructed. Also in the semiconductor device of this example, the semiconductor support substrate 51
A back surface electrode 66 is provided on the back surface, and an intermediate potential of a plurality of potentials applied to the present device is applied to the back surface electrode 66. Further, in the semiconductor device of this example,
Since the potential of the semiconductor supporting substrate 51 and the potential of the filling layer 57 are independent from each other, the filling layer 57 is not shown when the thickness of the insulating film 52 and the thickness of the sidewall insulating film 56 are equal to 1 μm. The filling layer potential regulating electrode applies an intermediate potential of potentials applied to adjacent devices via one isolation groove 55 among all devices formed on the semiconductor supporting substrate 51. Of course, the potential applied to the semiconductor support substrate 51 may be equivalent to the potential applied to the filling layer 57. In the case where either the insulating film 52 or the sidewall insulating film 56 has a thickness of 1 μm or more and has a sufficient withstand voltage for a voltage applied to the element, it is not necessary to apply the voltage, and the ground potential or the like is not required. It may be fixed.

In the semiconductor device having such a configuration,
By applying an intermediate potential to the semiconductor support substrate 51 and the filling layer 57, the voltage applied to the insulating film 52 and the sidewall insulating film 56 surrounding the element formation region can be reduced, and the apparent breakdown voltage between elements can be improved. Can be. Accordingly, since the withstand voltage of the device is sufficiently ensured, the element characteristics can be stabilized, and the dielectric isolation of the high withstand voltage element can be applied.

Then, as shown in FIG.
If the potential of the semiconductor supporting substrate 51 and the potential of the filling layer 57 are set to the same potential by removing the insulating film 52 at the bottom of the
Since the application of the intermediate potential to 7 is achieved by the back electrode 66 and the filling layer potential defining electrode is not required, the surface of the semiconductor layer 53 can be integrated.

Seventh Embodiment Next, a seventh embodiment of the present invention will be described with reference to FIGS.

14 to 16 are cross-sectional views showing the structure of an SOI semiconductor device using a dielectric isolation substrate according to Embodiment 7 of the present invention.
High breakdown voltage elements such as a GBT (FIG. 14), a lateral MOSFET (FIG. 15), and a lateral diode (FIG. 16) are formed.

The SOI semiconductor device shown in FIG. 14 has a high withstand voltage formed in the semiconductor layer 93 and includes a collector region C, an emitter region E and a gate region G, similarly to the SOI semiconductor device described above with reference to FIG. Is formed, and the configuration thereof is substantially the same as that of the SOI semiconductor device shown in FIG. 29. Therefore, the common portions are denoted by the same reference numerals and description thereof is omitted.

In the SOI semiconductor device shown in FIG. 15, a lateral MOSFET is formed in a semiconductor layer 93 by a drain region D, a source region S and a gate region G. That is, the drain region D is formed by the n-type buffer layer 107 at one end of the surface of the n-type semiconductor layer 93 and the n ⁺ -type drain layer 108 formed in the buffer layer 107.
And a drain electrode 113 is conductively connected to the drain layer 108. On the other hand, on the other end of the surface of the semiconductor layer 93, a p-type base layer 104,
The source region S is formed by the p ⁺ -type contact layer 105 formed therein and the n ⁺ -type source layer 106 formed from the end of the contact layer 105 to the base layer 104. A source electrode 111 is conductively connected to a part of the source layer 106. Then, from the end of the source layer 106, the base layer 1
A gate electrode 112 extending over the semiconductor layer 93 and the semiconductor layer 93 is provided via a gate oxide film 110.

The SOI semiconductor device shown in FIG.
An n ⁺ -type cathode layer 120 is formed at one end of the surface of the n-type semiconductor device 119, and a p ⁺ -type anode layer 121 is formed at the other end of the semiconductor layer 119 to form a high breakdown voltage lateral diode. I have. A cathode electrode 122 is electrically connected to the cathode layer 120, and an anode electrode 123 is electrically connected to the anode layer 121.

It should be noted that in the SOI semiconductor device according to the present embodiment, the back electrode 99 provided on the back surface of the support substrate 91 is provided with a high withstand voltage element (lateral IGBT, MOSFET and MOSFET) formed in the semiconductor layer. diode)
In that the potential of the support substrate 91 is set to the high voltage application electrode side potential.
That is, in the SOI semiconductor device shown in FIG.
Collector electrode 89 which is a high voltage application electrode of a horizontal IGBT
And the back electrode 99 are connected by external wiring.
Further, in the device shown in FIG.
In the apparatus shown in FIG. 16, the cathode electrode 122 and the back electrode 99 are both connected by external wiring.

FIG. 17 shows the horizontal diode shown in FIG.
The distribution of equipotential lines in the semiconductor layer 119 when a high potential is applied to 22 is shown. The distribution diagram of the equipotential lines was obtained by simulation.
The thickness of the insulating film 92 is 2 μm, the drift length L between the cathode layer 120 and the anode layer 121 is 30 μm, the voltage applied to the cathode electrode 122 is 300 V, and the equipotential lines 1
24 is plotted in 30V units. Due to the above-described bias, the lateral diode having the above-described configuration is in a reverse bias state, so that a depletion layer expands from the junction between the anode layer 121 and the semiconductor layer 119, and the equipotential lines are
And the insulating film 92. The equipotential line extends to the insulating film 92 side.

FIG. 18 shows the distribution of the electron concentration inside the lateral diode when a high voltage is applied. In FIG. 18, at the interface between the semiconductor layer 119 and the insulating film 92, an accumulation layer 125 in an electron accumulation state is provided.
Are formed. Since the potential of the supporting substrate 91 increases when a high potential equal to the cathode potential of the diode is applied to the accumulation layer 125, electrons that are majority carriers in the semiconductor layer 119 are attracted to the supporting substrate 91, This is caused by accumulation at the interface with the insulating film 92. The formation of such an accumulation layer 125 is schematically shown in FIG.
9 can be represented. In FIG. 19, the energy band 126 (conduction band lower edge 128,
The intrinsic Fermi level 130 and the lower edge of the forbidden band 131) are bent downward at the interface between the insulating film 92 and the energy band 127 due to the application of a high potential to the support substrate 91. The electrons 132 above the conduction band lower edge 128 are
It is attracted to the (insulating film 92) side and accumulates at the bent portion of the band, forming an accumulation layer 125 for electrons 132.
Note that in FIG. 19, reference numeral 129 denotes an energy band indicating the Fermi level of the semiconductor layer 119;
Is a hole. The storage layer 125 thus formed
Particularly, the supporting substrate 91 with respect to the potential of the semiconductor layer 119.
Layer 1 immediately below the anode layer 121 where the potential rise is large.
It easily occurs at the interface between the insulating film 19 and the insulating film 92.

FIG. 20 shows the distribution of the electric field intensity immediately below the anode layer 121 in such a diode. A cathode electrode 122 of a diode is provided on the support substrate 91.
Is applied to the interface between the semiconductor layer 119 and the insulating film 92, in particular, the region immediately below the anode layer 121, as described above.
25 are formed. Thereby, as shown in FIG.
At the interface between the semiconductor layer 119 immediately below the anode layer 121 and the insulating film 92, the electric field strength sharply increases, and a potential can be provided inside the insulating film 92. As a result, the expansion of the depletion layer in the semiconductor layer 119 region between the anode layer 121 and the insulating film 92 can be suppressed, and the withstand voltage in the thickness direction of the semiconductor layer 119 can be improved. Accordingly, the thickness of the semiconductor layer 119 can be reduced while maintaining the withstand voltage of the high-withstand voltage element such as the diode having the above structure, so that the thickness of the SOI semiconductor device can be reduced.

FIG. 21 shows the relationship between the thickness of the semiconductor layer and the element breakdown voltage in the SOI semiconductor device. In the figure, a line A indicates a change in element withstand voltage due to a change in the thickness of the semiconductor layer 119 of the SOI semiconductor device according to the present embodiment (the SOI semiconductor device shown in FIG. 16), and a line B is provided on the support substrate. 9 shows the relationship between the thickness of the semiconductor layer and the element breakdown voltage in a comparative example (conventional) SOI semiconductor device in which the ground potential is applied to the back electrode. Note that the SOI semiconductor device of the comparative example shown by line B has the same configuration as the device shown in FIG. 16 except that the potential applied to the back electrode is different. In the figure, when the thickness of the semiconductor layer is 10 μm,
The device breakdown voltage of the device of the comparative example shown by the line B is about 100 V, whereas the device breakdown voltage of the SOI semiconductor device according to the present example shown by the line A is about 280 V. This value (280V)
Means that the semiconductor layer thickness of the SOI semiconductor device of the comparative example is 30 μm.
It is further higher than the element withstand voltage (about 170 V) at m, and it can be seen that in the SOI semiconductor device of this embodiment, the withstand voltage in the thickness direction of the semiconductor layer is remarkably improved. Therefore, according to the SOI semiconductor device of this example, the device withstand voltage can be ensured even if the semiconductor layer is thin, so that if the device withstand voltage is about 250 V, the thickness of the semiconductor layer is smaller than that of the conventional device. 2
It can be as thin as 0 μm or more.

As described above, in the SOI semiconductor device according to the present embodiment, by applying to the supporting substrate a potential equal to the high voltage application electrode side potential of the high breakdown voltage element formed in the semiconductor layer, , The breakdown voltage in the thickness direction of the semiconductor layer can be improved, and the device can be made thinner. This is also applied to a power IC in which a high-current output element and its control circuit are formed in a semiconductor layer divided into a plurality of element formation regions by separation grooves. One example is shown in FIG. In this figure, an n-type semiconductor layer 93 formed on a supporting substrate 91 via an insulating film 92 is divided into a plurality of element formation regions by an isolation groove 136, and one region is shown in FIG. A high breakdown voltage horizontal IGBT 134 is formed.
In the area adjacent to T134, the control circuit section CM
An OS 135 is formed. The CMOS 135 is formed on one end of the surface of the semiconductor layer 93 which is dielectrically isolated, and is provided on the surface side of the p ⁺ type source layer 137 and the drain layer 139 and the semiconductor layer 93 extending over the source layer 137 and the drain layer 139. A p-channel MOSFET formed of a gate electrode 141 and an n ⁺ -type source layer 144 and a drain layer 145 formed in a p-type well layer 138 diffused at the other end of the surface of the semiconductor layer 93.
N-channel MOS composed of gate and gate electrode 141
It is constituted by an FET. Also, the source layer 13
7, 144, a source electrode 140 is provided.
Drain electrodes 142 are conductively connected to 9, 145, respectively.

Also in the SOI semiconductor device (power IC) having such a configuration, the collector electrode 89 of the horizontal IGBT 134 at the output stage and the back electrode 99 are connected by external wiring, and the potential of the support substrate 91 is changed to the potential of the collector electrode 89. By setting the same potential as that described above, the insulating film 92 can have a withstand voltage, and the withstand voltage in the thickness direction of the semiconductor layer 93 can be secured. Can be created. Note that CMOS
In 135, the potential of the semiconductor layer 93 is fixed by the source potential.
There is no effect on the device characteristics of the CMOS 135 due to the same potential as the collector electrode 89 of the BT 134.

[0088]

According to the first and third means, the separation groove is provided.
Is formed for each element formation region and between adjacent isolation grooves.
A peripheral semiconductor region is formed in the
Since the defining electrodes are conductively connected, the element forming regions
Means that the device is isolated by the surrounding semiconductor region in addition to the isolation groove.
And the potential of the surrounding semiconductor region is fixed at a predetermined potential.
In the device state, the semiconducting
No potential interference between body elements and stable element characteristics
Is remarkable. Furthermore, a predetermined potential is applied to the diffusion layer.
Is set to a potential between two or more potentials
Withstand voltage performance can be improved.

In the second means, the filling layer potential regulating
The predetermined potential applied to the electrode is the lowest potential applied to the diffusion layer
Or, because it is not a low potential but the highest potential, the semiconductor substrate
Feel that the whole and the packed bed are specified at their highest potential
Function as a plate, applying the lowest potential to the p-type diffusion layer
In the reverse bias state, the first facing the p-type diffusion layer
An electron storage layer is formed at the interface between the first insulating film and the second insulating film.
And the electric field strength rises sharply at the interface
In this way, the reverse bias potential is
The electric field intensity in the element formation region can be moderated.
The breakdown voltage of the device built in the device formation region
The width can be improved. In addition, the fifth and sixth means
Has the same effect.

In the fourth means, a voltage is applied to the substrate electrode.
The predetermined potential is not the minimum potential or the low potential,
Since the potential is almost half of the maximum withstand voltage of the conductor device, semiconductor
The entire substrate is set at a potential of approximately half of its maximum withstand voltage
Acts as a field plate and occurs in the semiconductor layer
End of the equipotential line that is approximately half of the highest withstand voltage in the potential distribution
Passes through the semiconductor substrate, causing the
The potential distribution is based on equipotential lines that are approximately half of the maximum withstand voltage.
The distribution is regulated between the highest potential side and the lowest potential side. this
Therefore, the intervals between the equipotential lines generated in the semiconductor layer are reduced.
Greatly improves the withstand voltage of devices built into the semiconductor layer
Can be The same operation is performed in the seventh means.
Use effect.

In the eighth means, the filling layer potential regulating
The predetermined potential applied to the electrode is not the lowest potential or low potential.
The highest and lowest potentials applied to the diffusion layer in the element formation region
Since this is an intermediate potential with respect to the potential,
The filling layer has a field plate defined at its intermediate potential and
Functioning as a potential distribution in the element formation region.
The end of the equipotential line of the intermediate potential passes through the semiconductor substrate
Therefore, the potential distribution generated in the element formation region
Is divided into the highest potential side and the lowest potential side based on
Be regulated. Therefore, an equipotential generated in the element formation region
Since the spacing between lines becomes sparse, it was built in the element formation area
The withstand voltage of the element can be greatly improved. The ninth
The same operation and effect can be obtained by the means described above.

[0092]

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing a main part of an SOI semiconductor device having a dielectric isolation structure according to a first embodiment of the present invention.

2A to 2D are process cross-sectional views showing a part of a method for manufacturing an SOI semiconductor device using the dielectric isolation substrate shown in FIG.

3A to 3C are cross-sectional views showing a part of a step performed after the step shown in FIG. 2 in the method of manufacturing the semiconductor device shown in FIG. 1;

FIG. 4 is a schematic sectional view showing a main part of an SOI semiconductor device using a dielectric isolation substrate according to a second embodiment of the present invention.

FIG. 5 is a schematic plan view showing a main part of the semiconductor device shown in FIG. 4;

FIG. 6A is a schematic sectional view showing a main part of an SOI semiconductor device using a dielectric isolation substrate according to a third embodiment of the present invention,
(B) is a schematic plan view thereof.

FIG. 7 is a sectional view illustrating a configuration of an SOI semiconductor device according to a fourth embodiment of the present invention.

FIG. 8 is an explanatory diagram showing a distribution of equipotential lines when an intermediate potential is applied to a supporting substrate in the semiconductor device shown in FIG.

FIG. 9 is a cross-sectional view illustrating a configuration of an SOI semiconductor device in which an isolation groove is formed in a fourth embodiment of the present invention.

FIG. 10 is a graph showing a relationship between a withstand voltage characteristic and a substrate potential of a semiconductor device according to a fourth embodiment.

FIG. 11 is a cross-sectional view illustrating a configuration of an SOI semiconductor device according to a fifth embodiment of the present invention.

FIG. 12 is a sectional view illustrating a configuration of an SOI semiconductor device according to a sixth embodiment of the present invention.

FIG. 13 is a cross-sectional view illustrating a configuration of an SOI semiconductor device in which a support substrate and a filling layer are connected in Example 6 of the present invention.

FIG. 14 is a sectional view illustrating a configuration of an SOI semiconductor device according to a seventh embodiment of the present invention.

FIG. 15 is a sectional view illustrating a configuration of an SOI semiconductor device according to a seventh embodiment of the present invention.

FIG. 16 is a sectional view illustrating a configuration of an SOI semiconductor device according to a seventh embodiment of the present invention.

FIG. 17 is an explanatory diagram showing a distribution of equipotential lines inside the element when a reverse voltage is applied in the semiconductor device shown in FIG. 16;

18 is an explanatory diagram showing a distribution of electron concentration inside the element when a reverse voltage is applied in the semiconductor device shown in FIG.

FIG. 19 is an explanatory diagram illustrating formation of a storage layer at an interface between a semiconductor layer and an insulating film.

20 is an explanatory diagram showing a distribution of electric field intensity immediately below an anode layer in the semiconductor device shown in FIG.

FIG. 21 is a graph showing the relationship between the thickness of a semiconductor layer and the withstand voltage of an element.

FIG. 22 is a cross-sectional view showing a configuration of a power IC in which the semiconductor device shown in FIG. 14 is integrated together with its control circuit unit.

FIGS. 23A to 23D are cross-sectional views showing a part of a method for manufacturing a semiconductor device having a conventional dielectric isolation structure.

24A to 24C are process cross-sections showing a part of a process performed after the process shown in FIG. 23 in the conventional method of manufacturing a semiconductor device having a dielectric isolation structure. FIG.

FIG. 25 is a cross-sectional view showing a configuration of an integrated circuit device using a conventional bonded substrate (SOI substrate).

FIG. 26 is a cross-sectional view showing an integrated circuit device having a structure in which a main body is formed by a conventional polycrystalline silicon layer.

FIG. 27 is a cross-sectional view showing a configuration of a conventional SOI semiconductor device.

FIG. 28 is an explanatory diagram showing a distribution of equipotential lines when a ground potential is applied to a support substrate in the semiconductor device shown in FIG. 27;

FIG. 29 is a cross-sectional view showing a configuration of a conventional SOI semiconductor device.

[Explanation of symbols]

1, 21, 41 ... semiconductor device 2, 22, 42 ... dielectric isolation substrate 3, 23, 43 ... semiconductor support substrate (semiconductor substrate) 4, 24, 44 ... silicon oxide film 5, 25, 45 ... semiconductor layers 5a, 5b, 5c, 5d, 25a, 25b, 45a, 4
5b: Element formation area 6, 26a, 26b, 46a, 46b: Separation groove 7, 27a, 27b, 47a, 47b: Side wall insulating film (second insulating film) 8, 28a, 28b, 48a , 48b ... polycrystalline semiconductor layer (filled layer) 10, 70 ... electrode for defining filling layer potential 29, 71 ... peripheral semiconductor region 30b ... emitter electrode (electrode for defining filling layer potential) 31b ..Drain electrode (filling layer potential defining electrode) 33 ... Ambient region potential defining electrode 61 ... Aluminum electrode 62 ... Cathode layer 63 ... Anode layer 64 ... Cathode electrode 65 ... Anode electrode 66 ... Back electrode 201-203 ... Equipotential line

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/762 H01L 27/12

Claims (18)

(57) [Claims] A semiconductor layer formed on a front surface side of the semiconductor substrate via a first insulating film; and a semiconductor layer formed from the front surface side of the semiconductor layer through the first insulating film to reach the semiconductor substrate. An isolation groove forming an island-shaped element formation region in the semiconductor layer; a second insulating film formed on a side wall of the isolation groove; and filling the isolation groove and electrically connecting to the semiconductor substrate. and a filling layer, said semiconductor substrate and on at least one side of said packed bed, it is packed layer potential defining electrode to be applied a predetermined potential is conductively connected to the element forming region Two or more diffusion layers are formed, the predetermined potential is a potential between two or more potentials applied to the diffusion layer, and the separation groove is formed in the element formation region.
It is formed for each area, between the adjacent separation grooves,
A peripheral semiconductor region, which is a non-element formation region of the semiconductor layer, is formed.
In this peripheral semiconductor region, predetermined
The electrode for defining the potential in the surrounding area where the potential is to be applied is conductively connected.
SOI wherein a is. 2. An n-type semiconductor layer formed on a surface side of a semiconductor substrate via a first insulating film, and the semiconductor substrate penetrating from the surface side of the n-type semiconductor layer through the first insulating film. , An isolation groove which forms an island-shaped n-type element formation region in the n-type semiconductor layer, a second insulating film formed on a side wall of the isolation groove, and is filled in the isolation groove. wherein and a filling layer connected conductive to the semiconductor substrate, wherein on at least one side of the semiconductor substrate and the filling layer, it is predetermined filling layer potential regulating electrode to be applied potentials connects conductive Te In the n-type element formation region, two or more diffusion layers are formed, and at least one of the diffusion layers is p-type, and the predetermined potential applied to the entire semiconductor substrate is A highest potential applied to the diffusion layer. That SOI semiconductor device. 3. The semiconductor device according to claim 2, wherein the isolation groove is formed for each of the element formation regions, and a peripheral semiconductor region, which is a non-element formation region of the semiconductor layer, is formed between the adjacent isolation grooves. An SOI semiconductor device characterized in that a peripheral region potential defining electrode to which a predetermined potential is applied is electrically connected to the peripheral semiconductor region. 4. A semiconductor layer formed on a surface side of a semiconductor substrate via a first insulating film, and an island formed on the semiconductor layer from the surface side of the semiconductor layer to reach the first insulating film. An isolation groove for forming an element-shaped element forming region, a second insulating film formed on a side wall of the isolation groove, and a filling layer filling the interior of the isolation groove. A peripheral semiconductor region that is formed for each region and is a non-element formation region of the semiconductor layer is formed between adjacent isolation trenches, and a predetermined potential is applied to this peripheral semiconductor region to this region. An SOI semiconductor device, wherein an electrode for defining a peripheral region potential to be applied is conductively connected. 5. The method according to claim 4, wherein a filling layer potential defining electrode to which a predetermined potential is applied is conductively connected to the filling layer filled in the separation groove.
OI semiconductor device. 6. The SOI semiconductor device according to claim 4, wherein a substrate electrode capable of applying a predetermined potential is conductively connected to said semiconductor substrate. 7. The semiconductor device according to claim 5, wherein the predetermined potential is a potential equivalent to any one of potentials applied to a semiconductor element in the element formation region. SOI semiconductor device. 8. The method according to claim 7, wherein the predetermined potential is
An SOI semiconductor device characterized in that the potential is equal to a potential applied to a high-voltage application side electrode of a high breakdown voltage semiconductor element in an output stage among semiconductor elements formed in the element formation region. 9. A surface side of the semiconductor substrate has a semiconductor layer formed via an insulating film, the SOI semiconductor device 2 or more diffusion layers is formed on the semiconductor layer, the entirety of the semiconductor substrate predetermined and potential are capable of applying the substrate electrodes are conductively connected, the potential this predetermined, I potential der between two or more of the potential applied to the diffusion layer, the SOI half
An SOI semiconductor device, wherein the potential is substantially half of the maximum withstand voltage of the conductor device . 10. A surface side of the semiconductor substrate has a semiconductor layer formed via an insulating film, the SOI semiconductor device 2 or more diffusion layers is formed on the semiconductor layer, the entirety of the semiconductor substrate An SOI semiconductor device, wherein a substrate electrode to which a predetermined potential can be applied is conductively connected, and the predetermined potential is the highest potential among two or more potentials applied to the diffusion layer. 11. The SOI semiconductor device according to claim 10, wherein the two or more diffusion layers are formed in a plurality of island-shaped element formation regions in which the semiconductor layer is dielectrically separated. 12. A semiconductor layer formed on a front surface side of a semiconductor substrate via an insulating film is dielectrically separated to form a plurality of island-shaped element formation regions, and a horizontal element is formed in one of the element formation regions. And a control element for controlling the horizontal element is formed in the other element formation region.
In the I semiconductor device, a substrate electrode to which a predetermined potential can be applied is conductively connected to the entire semiconductor substrate , and the predetermined potential is a highest potential among potentials applied to the lateral element. SOI semiconductor device characterized by the above-mentioned. 13. The device according to claim 4, wherein two or more diffusion layers are formed in the element formation region, and the predetermined potential is applied to the two or more diffusion layers. An SOI semiconductor device, which has a potential between the potentials. 14. The SOI semiconductor device according to claim 13, wherein the predetermined potential is a potential that is substantially half of the highest withstand voltage of the SOI semiconductor device. 15. The SOI semiconductor device according to claim 13, wherein the predetermined potential is an intermediate potential between a highest potential and a lowest potential applied to the diffusion layer. 16. A first insulating film on the surface side of the semiconductor substrate
Between the semiconductor layer formed through and the surface side of this semiconductor layer
Through the first insulating film to reach the semiconductor substrate
To form an island-shaped element formation region in the semiconductor layer.
And a second groove formed on a side wall of the separation groove.
An insulating film, the semiconductor substrate being filled in the separation groove;
And a filling layer conductively connected to the semiconductor substrate and
At least one of the packed layers has a predetermined
The potential regulating electrode to which the potential of
And two or more diffusion layers are formed in the element formation region.
The predetermined potential applied to the entire semiconductor substrate.
Is a potential between two or more potentials applied to the diffusion layer.
And a voltage of approximately half of the maximum withstand voltage of the SOI semiconductor device.
SOI semiconductor device, characterized in that: 17. A first insulating film on the surface side of the semiconductor substrate
Half formed through The conductor layer and the surface side of this semiconductor layer
Through the first insulating film to reach the semiconductor substrate
To form an island-shaped element formation region in the semiconductor layer.
And a second groove formed on a side wall of the separation groove.
An insulating film, the semiconductor substrate being filled in the separation groove;
And a filling layer conductively connected to the semiconductor substrate and
At least one of the packed layers has a predetermined
The potential regulating electrode to which the potential of
And two or more diffusion layers are formed in the element formation region.
The predetermined potential applied to the entire semiconductor substrate.
Is a value between the highest potential and the lowest potential applied to the diffusion layer.
An SOI semiconductor device, which has an inter-potential. 18. A semiconductor device, comprising: an insulating film provided on a surface side of a semiconductor substrate;
Having a semiconductor layer formed by
In the SOI semiconductor device in which the diffusion layer is formed,
A board electrode capable of applying a predetermined potential is applied to the entire conductor board.
The predetermined potential is imprinted on the diffusion layer.
That the applied potential is intermediate between the highest potential and the lowest potential.
SOI semiconductor device characterized by the above-mentioned.