JPH04123456A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To provide a low-cost, high-voltage, high-current and reliable integrated circuit by depositing a heavily-doped layer, with a smaller resistivity than single-crystal semiconductor, entirely on the sides and bottom of a semiconductor island, and forming a refractory metal silicide layer with a further low resistivity on the bottom. CONSTITUTION:A high-melting metal silicide layer 5 is deposited on an n<+> layer 2 of a substrate. A silicon dioxide film 4 is formed on a single-crystal substrate 3. The two substrates are joined under normal temperature and pressure in such a manner that the silicide layer 5 and the silicon dioxide film 4 are in contact. After a high-temperature heat treatment, there are provided an n<+> layer 6 for a collector contact, and a diffused layer 7 for base and emitter. The layer 6 is divided by providing isolation trenches 9 to obtain a plurality of single-crystal islands. After an n<+> film 10 is formed on each side of the isolation trenches, silicon dioxide 41 is deposited, and polyimide 11 is applied and baked. In this manner, the trenches are filled.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device and a method for manufacturing the same, and in particular,
The present invention relates to a dielectric-separated large current capacity semiconductor device and a manufacturing method thereof.

[Prior art] As a conventional technology regarding a dielectrically isolated semiconductor device,
For example, JP-A-54-23388, JP-A-62-
A technique described in Japanese Patent No. 232965 and the like is known.

This prior art relates to a dielectrically isolated semiconductor device with a large current capacity, which is formed by bonding a supporting base made of polycrystalline silicon to a semiconductor single crystal substrate via an insulating film.

Further, as a conventional technique related to a method of manufacturing this type of semiconductor device, for example, a technique described in Japanese Patent Application Laid-Open No. 71580/1983 is known.

This prior art relates to a method in which a support substrate and an active element substrate are bonded and integrated, and then a plurality of semiconductor single crystal islands are formed.

[Problems to be Solved by the Invention] In the semiconductor device according to the above-mentioned prior art, the spread of the depletion layer in the lateral direction, which occurs when a reverse voltage is applied to the active element formed within the semiconductor single crystal island, extends to the side wall of the single crystal island. There is no consideration given to the fact that the electric field collides directly with the insulating film of the device, causing concentration of the electric field in this portion, and this poses a problem in that it is difficult to increase the withstand voltage of the device.

Further, in the semiconductor device according to the prior art, when the active element formed in the semiconductor single crystal island is, for example, a transistor, the collector resistance is determined by the resistivity of the silicon substrate material. The problem is that it is not possible to make it smaller.

Furthermore, in the semiconductor device according to the prior art, if the coefficient of thermal expansion of the resin material filled in the isolation trench is significantly different from the coefficient of thermal expansion of the adjacent semiconductor single crystal island, supporting substrate, etc. Heat treatment at about 150° C. to 400° C. causes peeling or cracking in this portion, which poses a problem in that reliability cannot be improved.

Furthermore, in manufacturing a semiconductor device according to the above-mentioned prior art, bonding is performed using an adhesive in order to bond the support base and the semiconductor single crystal island, but the coefficient of thermal expansion of this adhesive is different from that of the support base and the semiconductor single crystal island. The coefficient of thermal expansion is not exactly the same as that of a semiconductor single crystal island.

Therefore, in the semiconductor device according to the prior art, the active element formed after bonding is formed by performing a high temperature heat treatment process of about soo'c to 1200°C several times, so that the entire substrate is curved during the heat treatment. In this case, in the photolithography process for forming active elements, element pattern misalignment occurs, resulting in a decrease in the uniformity of active element characteristics, and furthermore, the formation of elements with internal stress. This poses a problem in that it is difficult to improve reliability and yield.

Furthermore, the above-described manufacturing method requires special steps such as applying an adhesive and baking, and has the problem of high manufacturing cost.

On the other hand, the manufacturing method according to the prior art disclosed in Japanese Unexamined Patent Publication No. 48-71580 is a method of pasting SiO on the mirror-polished surfaces of both substrates and then applying heat and pressure. However, this method has the problem that since the oxide film surfaces are bonded together, it is not possible to lower the resistance of the bottom surface of an active element to be formed in the future to form a large-capacitance element.

On the other hand, the semiconductor single crystal islands in the three prior art techniques described above are limited to silicon substrates having crystal plane orientations of (100) or (001). That is, in the prior art, etching is performed using a KOH aqueous solution that can perform high-speed etching only in the (100) or (001) crystal plane orientation. The shape of the separation groove formed by this etching method is an inverted triangular shape in which the angle between the substrate surface and the side wall of the etched surface is always 54.7 degrees.

Therefore, in the semiconductor device and device manufacturing method according to the prior art, the area required for separation is large, and the separation area occupies a large amount of the entire semiconductor substrate, which makes it difficult to improve the degree of integration of the integrated circuit device. This has the problem of increasing the chip area and chip cost.

SUMMARY OF THE INVENTION An object of the present invention is to solve the problems of the prior art, and to provide a low-cost, highly reliable, high-voltage, large-current semiconductor integrated circuit device and its manufacturing method.

[Means for Solving the Problems] According to the present invention, the above object is to arrange a highly concentrated impurity layer having a resistance value lower than that of the semiconductor single crystal island material over the entire side surface and bottom surface of the semiconductor single crystal island; By arranging a silicon compound layer of a high melting point metal whose resistance value is even lower than that of the high concentration impurity layer, and without using an adhesive to bond the supporting substrate and the semiconductor single crystal island, the surface of the supporting substrate can be bonded. This is achieved by using a method of directly bonding the silicon oxide surface and the silicon compound layer surface of the high melting point metal. Furthermore, the above purpose is to separate each single crystal island from each other by forming trench-structured grooves by dry etching, etc., and to fill the grooves with a material having a coefficient of thermal expansion of 2 to 8×10 = “K”. This is achieved by using a polyimide resin within the range of .

[Function] The high-concentration impurity layer placed on the side surface of each single-crystal island has a channel stopper or an electric field relaxation effect when the depletion layer of a high voltage element expands laterally, and also serves as a collector current path. will have a role.

On the other hand, the highly concentrated impurity layer at the bottom of each single crystal island functions as follows.

The barrier height (barrier hide) of the high melting point metal silicon compound itself in contact with high concentration impurities is 0.4 to 0.8e.
Due to the high v, a Schottky barrier is formed in contact with a normal silicon single crystal, making it impossible to form an ohmic contact, but the high concentration impurity layer does not aggravate such 1lff problems. is prevented.

According to the literature, for example, silicon compounds of high melting point metals are
o In the case of Si□, the barrier hydride is approximately 0.55ev, and if the contact resistance is to be 1Ωd, the impurity concentration on the contact silicon surface must be 2XIO"am-" or more. If the substrate to be used is N-, its impurity concentration is approximately 2 to 3 x 10"cyn-"
Therefore, it is impossible to form an ohmic contact.

Furthermore, the resistance of a high melting point metal silicon compound layer is extremely low (100~140 μΩcm), and by placing such a high melting point metal silicon compound layer on the bottom surface of a single crystal island, active elements can be In the case of a transistor, the collector resistance can be reduced, and a large current element can be formed.

As a result, the present invention can provide a device having a current capacity approximately three times as large as that of a conventional device without a refractory metal silicide layer in a transistor having the same shape. This means, conversely, that in order to obtain a device with the same current capacity, the device of the present invention having a silicon compound layer of a refractory metal can be housed in one-third the area of the prior art.

In addition, by using a low thermal tensile polyimide with a thermal tensile coefficient in the range of 2 to 8 x 10-K as the resin material filled into the separation groove, the semiconductor located on the periphery of the separation groove can be The thermal expansion coefficient of the single crystal island is 2.4XlO-"K-',
In addition, since the high-melting point metal silicide partially exposed on the side wall of the separation groove is about 6 to 8 x 10-", the thermal expansion coefficients of these two types can be made almost equal, and therefore the A required after forming the separation groove is 150℃~4℃ generated during wiring formation
Even by heat treatment at about 50° C., peeling, cracking, etc. do not occur.

[Example 1] Hereinafter, an example of a semiconductor device and a method for manufacturing the same according to the present invention will be described in detail with reference to the drawings.

FIG. 1 is a sectional view showing the structure of a semiconductor device according to an embodiment of the present invention, FIGS. 2 to 4 are sectional views of each step explaining the manufacturing process, and FIGS. FIG. 1 is a plan view of a semiconductor device according to an embodiment. 1 to 4, 1 is a semiconductor single crystal substrate, 2.10 is a high concentration impurity layer, 3 is a supporting substrate, 4 is a SiO film, 5 is a high melting point metal silicide layer, and 6 is a high melting point metal silicide layer. 03 layer, 9 is a separation groove, and 11 is a polyimide resin.

One embodiment of the present invention includes a semiconductor single crystal substrate l and a supporting base 3.
It is constructed by pasting together. FIG. 1 shows this bonded state.

The semiconductor single crystal substrate 1 is a silicon single crystal of n- conductivity type. This substrate 1 contains an impurity such as As and has a low resistance n+ high concentration impurity layer 2 and a high melting point metal silicide layer 5 whose resistance value is even lower than this n゛ high concentration impurity layer 2.
is formed.

In addition, the surface of the semiconductor single crystal substrate 1 is coated with oxidation, photolithography, etching,
It is formed by methods such as ion implantation, diffusion, and CvD.

Separation grooves 9 for separating each single crystal island from the support substrate 810. It is provided so as to penetrate through the film 4 and the high melting point metal silicide layer 5 and further reach the support base 3. On the side wall of this separation groove 9, an n3 high concentration phase 10 is provided in the semiconductor single crystal substrate in a portion in contact with the side wall, and a Si
A film 41 is formed.

Moreover, this separation groove 9 has Mo exposed on the side surface of the separation groove.
The polyimide resin 11 has a low coefficient of thermal expansion (2 to 8 x 10-"K-') that is approximately equal to the coefficient of thermal expansion (6-8 x 10-"K-') of the high-melting point metal silicide layer 5 made of Si. Insulated and filled.

Note that the filling of the low thermal expansion polyimide resin material 1 can be carried out by the commonly used spin coating method, so it is not necessary to use the epitaxial method or CVD method, which requires high manufacturing costs, as in the case of using polycrystalline silicon. It can be easily done without relying on the above.

Moreover, as mentioned above, the polyimide resin 11 with low thermal expansion
Since the coefficient of thermal expansion of is close to that of the high melting point metal silicide layer 5 that is partially exposed on the side surface of the isolation groove, peeling does not occur in this part, and the reliability of the semiconductor device can be improved. I can do it.

By the way, in the embodiment of the present invention, when the separation groove 9 is formed by etching, it is necessary to perform etching to a predetermined depth, but there is a problem in that the criterion for determining the etching depth is difficult. That is, in one embodiment of the present invention, when the bottom surface of the separation groove 9 reaches the bottom of the high melting point metal silicide layer 5, the separation between the single crystal islands, which is the objective, is completed. When this is carried out by etching, if the controllability of the etching process is poor, an etching defect will occur in which a small portion of the high-melting point metal silicide layer remains, resulting in short-circuiting between the single crystal islands.

On the other hand, if the bottom surface of the separation groove 9 stops at the Sin layer for insulation with the supporting substrate 3, electrically the single crystal islands can be separated from each other, but the Sin layer still spreads over the entire substrate. Existing.

In this case, as mentioned above, the difference in thermal expansion coefficient between the high-melting point metal silicide layer 5 and the SiO film 4 is approximately -0.5 digits, and even with a slight heat treatment such as the subsequent wiring formation process, the high Peeling occurs at the interface between the melting point metal silicide layer 5 and the Si*2 film 4.

However, in one embodiment of the present invention, as shown in FIG. 1, the bottom surface of the separation groove 9 is extended until it reaches the supporting base 3, so that the stress is dispersed for each single crystal island, and as described above. The problems of curvature and peeling of single crystal islands can be solved.

Next, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to FIG. 2, which shows a cross section showing the steps in order.

(]) A
An impurity such as s is diffused to form an n″″ high concentration impurity layer 2. At this time, sb, p, etc. may be used as impurities, but these impurities need to be selected in consideration of the relationship between the heat treatment temperature, heat treatment time, and diffusion coefficient in subsequent steps. Next, the n high concentration impurity layer 2
A high melting point metal silicide layer 5 having a resistivity of about 100 μΩ·m is deposited thereon by sputtering or the like [FIGS. 2(a) and 2(C)].

(2) Next, a silicon dioxide film 4 is formed on a separately prepared single-crystal silicon substrate 3 for a supporting substrate [FIG. 2(b)
].

(3) Then, the substrate shown in FIG. 2(c) and the substrate shown in FIG.
The substrate shown in b) is bonded together at room temperature and pressure so that the surface of the high melting point metal silicide layer 5 and the surface of the silicon dioxide film 4 overlap [FIG. 2(d)].

(4) After that, high-temperature heat treatment that also serves as annealing treatment for the high melting point metal silicide film is performed, and the single crystal silicon substrate is
After polishing from the surface side to a predetermined thickness, an N1 layer 6, which will be necessary for contacting the collector layer in the future, and a diffusion region 7, which will become a base and an emitter, are formed (see Fig. 2).
e)].

(5) Thereafter, separation grooves 9 are formed by dry etching so as to divide the n+ layer 6, and etching is performed until the bottom surface thereof reaches the supporting substrate 3 to obtain a plurality of single crystal islands.

After forming an n'' high concentration impurity layer 10 on the side surface of the separation trench by high-angle ion implantation, a silicon dioxide film 41 is formed by CVD or thermal oxidation, and a low thermal expansion polyimide resin 11 is spun. It is applied by a coating method and baked to form a filling layer.At this time, the low thermal expansion polyimide resin rises, but this raised part is flattened by an etch-back method or the like.After that, a protective film is formed and A semiconductor device can be obtained by performing AQ wiring [FIGS. 2(f) and (g)].

In the above description of the method for manufacturing a semiconductor device of the present invention, the high melting point metal silicide layer 5 is the n0 high concentration impurity layer 2.
However, in the present invention, as shown in FIG. 3, a high melting point metal silicide layer 5 is formed on the silicon dioxide film 4 on the surface of the supporting base 3 [FIG. 3(b), (c)
) L,, Even if it is bonded to the surface of the n1 high concentration impurity layer 2 shown in FIG. 3(a), the second
A structure similar to that shown in Figure (d) can be obtained.

Next, another example of the method for forming the separation groove 9 will be described with reference to FIG.

(1) Prepare a substrate with the single crystal silicon substrate 1 side shown in FIG. 2(d) polished to a predetermined thickness [FIG. 4(a)
)].

(2) Separate the n1 diffusion region 12, which will become the n+ high-concentration impurity layer 10 on the isolation trench and sidewall in the future, to the position where it reaches the high-concentration impurity n'' layer 2 that was previously formed on the bottom surface before forming the active element. Diffusion is formed from the surface of the substrate 1 in an area wider than the groove 9 [FIG. 4(b)].

(3) Then the n required for the collector contact
'' layer 6 and active element diffusion region 7 are formed (see FIG. 4).
C)].

(4) Next, the isolation groove 9 is formed in the wide n+ diffusion region 12 by trench etching, and the inner wall of the groove is oxidized and filled with resin as shown in FIG. 2(d). Figure (d)].

In the manufacturing method described above, the separation groove 9 is formed by dry etching, but any etching method may be used as long as the separation groove can be formed with side walls perpendicular to the substrate surface. . However, depending on the etching method used, it is necessary to consider the crystal orientation of the substrate.

Note that in the above-described embodiment of the present invention, a silicon single crystal substrate is used as the support base 3, but the present invention is not limited to this, and the support base 3 may be a ceramic substrate,
A glass substrate, a sapphire substrate, etc. can be used.

Next, a specific example of the circuit layout of the semiconductor device according to the present invention will be described.

FIG. 5 shows a specific layout example of the circuit of the present invention shown in FIG. 1, where part number 100 is a separation groove;
are four large current capacity elements, 102 is a high withstand voltage element circuit, 1
03 indicates a drive circuit portion, and 104 indicates a logic circuit portion. Further, 105 is a dummy island, and 106 is a separation groove which is arranged and formed wider than the separation groove 100.

In FIG. 5, the logic circuit portion 104 has an operating voltage of several volts at most, so in order to prevent electrical noise from the high-voltage element circuit 102 and heat generation due to the large current capacity element arranged in close proximity, the logic circuit portion 104 has a width of They are separated by a wide separation groove 106. Furthermore, if the specifications of the large current capacity element 101 are, for example, 50V and IA, the large current capacity element 101 will handle as much as 50W of power, and its heat generation will affect not only the nearby logic circuit section 104 but also the drive circuit section. 10
3. The characteristics of each active element of the high voltage element circuit 102 will also deteriorate. Therefore, in the embodiment of the present invention, not only the wide isolation trench 106 but also a dummy island 105 is provided between the island where the large current capacity element 101 is located and the other island to isolate them.

In this dummy island 105, for example, a pattern for PQC, a resolution check pattern for photolithography, an alignment pattern, etc. can be provided. Since this dummy island 105 is formed of a single crystal, it has a greater heat dissipation effect than the separation groove and is suitable for separation.

FIG. 6 shows another layout example of the specific circuit of the present invention shown in FIG. This is an example of an arrangement where the heat dissipation effect is enhanced by placing the heat dissipation effect on the outer periphery of the device.

Note that in both FIGS. 5 and 6, the entire bottom surface of the device is covered with a high melting point metal silicide layer, but when considering only the formation of a large current capacity element, which is one of the purposes of the present invention, The high melting point metal silicide layer may be provided only on the bottom surface of the large current capacity element.

Further, in the above-described embodiments of the present invention, a silicon compound of molybdenum is used as the high-melting point metal silicide, but the present invention also describes the use of a silicon compound of a high-melting point metal such as titanium, tungsten, tantalum, etc. is also possible.

[Effects of the Invention] As explained above, according to the present invention, a low resistance high melting point metal silicide layer is provided on the bottom surface of each semiconductor single crystal island,
Furthermore, an n3 high concentration impurity layer is provided in contact with the high melting point metal silicide layer, and a similar n4 high concentration impurity layer is provided on the side wall connected to the n+ high concentration impurity layer on the bottom surface, so that the channel It also has the effect of a stopper.

Therefore, the structure of the semiconductor device according to the present invention is suitable for use in forming a high voltage and large current element.

Furthermore, according to the present invention, it is possible to bond the active element substrate and the support substrate by directly bonding the high melting point metal silicide surface and the silicon dioxide surface, which is different from the case of the prior art. It does not require complex and expensive processes such as polycrystalline silicon deposition.

Furthermore, according to the present invention, the separation between the single crystal islands is performed near the final step of the entire process, so that the large curvature of the entire substrate due to the deposition of supporting polycrystalline silicon as in the case of the prior art is avoided. Problems such as misalignment of active device patterns and deterioration of reliability caused by this can be avoided.

Similarly, according to the present invention, the filler in the separation groove is not polycrystalline silicon as in the case of the prior art, but a resin whose thermal expansion coefficient matches that of the adjacent parts, so the manufacturing method can be simplified. It is easy to use and does not cause the substrate to curve even during post-process heat treatment such as AQ wiring.

Therefore, according to the present invention, a highly accurate and low cost semiconductor device can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing the structure of a semiconductor device according to an embodiment of the present invention, FIGS. 2 to 4 are sectional views of each step explaining the manufacturing process, and FIGS. FIG. 1 is a plan view of a semiconductor device according to an embodiment. l...Semiconductor single crystal substrate, 2.1o...
・n+ high concentration impurity layer, 3...Support substrate, 4.
...S i O. Film, 5... High melting point metal silicide layer, 6...
...n+ layer, 9...separation groove, 11...
・Polyimide resin.

Claims (1)

[Claims] 1. In a semiconductor device comprising a semiconductor substrate having a silicon compound layer of a high-melting point metal on the bottom surface and a support substrate supporting the semiconductor substrate, a silicon substrate having a silicon oxide layer on the surface as the support substrate. A semiconductor device characterized in that the surface of the silicon compound layer of the refractory metal on the bottom surface of the semiconductor substrate and the surface of the silicon oxide layer on the surface of the support substrate are directly overlapped and bonded together. 2. In a dielectrically isolated semiconductor device, a plurality of semiconductor single crystal islands forming active elements are provided on the silicon oxide film on a support base having a silicon oxide film on the surface, and the semiconductor single crystal A high concentration impurity layer is provided on the side and bottom surfaces of the island, a silicon compound layer of a high melting point metal is provided between the surface of the high concentration impurity layer on the bottom surface and the silicon oxide film on the support base, and the plurality of Semiconductor single crystal islands are insulated and separated from each other by an isolation trench, a silicon oxide film is provided on the surface of the high concentration impurity layer on the side wall of the isolation trench, and inside the isolation trench,
A semiconductor device, characterized in that the semiconductor device is filled with a resin material having a coefficient of thermal expansion approximately equal to that of the semiconductor single crystal island, the support base, and the silicon compound of the high melting point metal. 3. The semiconductor device according to claim 2, wherein the separation groove has a depth extending to a part of the support base. 4. The semiconductor device according to claim 2 or 3, wherein the separation trench is formed to have sidewalls perpendicular to the substrate surface. 5. In a method for manufacturing a dielectrically isolated semiconductor device,
A method for manufacturing a semiconductor device, characterized by comprising the following steps. (1) A step of forming a high concentration impurity layer on a semiconductor single crystal substrate for active element formation, and forming a high melting point metal silicon compound layer thereon. (2) A step of forming a separation insulating film on the surface of a substrate that will become a supporting base. (3) A step of laminating and pasting the high melting point metal silicon compound layer surface of the substrate obtained in step (1) above and the isolation insulating film surface of the substrate obtained in step (2) above. (4) The side of the substrate obtained in step (3) above where the semiconductor single crystal is exposed, which is opposite to the silicon compound layer side of the refractory metal on the side of the semiconductor single crystal substrate for active element formation, is heated to a predetermined thickness. The process of polishing. (5) A step of forming a predetermined active element on the polished surface side of the substrate obtained in step (4). (6) A step of forming a separation groove from a predetermined portion of the active element forming surface obtained in step (5) to a depth that reaches the support base, and separating the semiconductor single crystal islands into a plurality of semiconductor single crystal islands. (7) A step of forming an impurity of the same type as the high concentration impurity formed in step (1) on the side wall of the separation trench. (8) After the step (7), filling the inside of the separation groove with resin.