JP5636827B2 - 半導体装置 - Google Patents
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- JP5636827B2 JP5636827B2 JP2010194627A JP2010194627A JP5636827B2 JP 5636827 B2 JP5636827 B2 JP 5636827B2 JP 2010194627 A JP2010194627 A JP 2010194627A JP 2010194627 A JP2010194627 A JP 2010194627A JP 5636827 B2 JP5636827 B2 JP 5636827B2
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- 239000004065 semiconductor Substances 0.000 title claims description 39
- 238000002955 isolation Methods 0.000 claims description 73
- 230000015556 catabolic process Effects 0.000 claims description 45
- 230000005684 electric field Effects 0.000 claims description 45
- 239000000758 substrate Substances 0.000 claims description 19
- 239000012535 impurity Substances 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 239000010410 layer Substances 0.000 description 78
- 239000011229 interlayer Substances 0.000 description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 13
- 238000000034 method Methods 0.000 description 9
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 8
- 238000000926 separation method Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 239000002344 surface layer Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 108091006146 Channels Proteins 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Description
また、請求項1に記載の発明では、トレンチ分離部(11)は、配線引出部(9)を中心として同心状に配置された多重トレンチ構造とされていることを特徴としている。
このように、複数本のトレンチ分離部(11)によって素子領域(8)と配線引出部(9)との間を分離することにより、基板横方向における耐圧をより高めることが可能となる。
さらに、請求項1に記載の発明では、活性層(2)のうち多重トレンチ構造を構成するトレンチ分離部(11)の間に配置された部分には第2導電型領域(50)が備えられており、第1配線と第2導電型領域(50)との間および第2配線と第2導電型領域(50)との間が抵抗(52)を介して接続されていることを特徴としている。
このような構造とすれば、第2配線(22)と第1配線(19)との間に発生する電位差を各第2導電型領域(50)に分配することができる。これにより、基板横方向での電界分布をより均等化することが可能となり、より耐圧を高めることが可能となる。
本発明の第1実施形態について説明する。図1は、本実施形態にかかる高耐圧MOSFETを有する半導体装置が形成されたチップのレベルシフト素子の断面図であり、図2は、図1に示す半導体装置の上面レイアウトを示した模式図である。図1は、図2のA−A’断面に相当している。以下、これらの図を参照して、本実施形態の半導体装置について説明する。
本発明の第2実施形態について説明する。本実施形態は、第1実施形態に対して素子領域8内のシリコン部(具体的にはn-型ドリフト層7)での電界負担を緩和させる構造を採用したものであり、その他に関しては第1実施形態と同様であるため、第1実施形態と異なる部分についてのみ説明する。
本発明の第3実施形態について説明する。本実施形態は、第1実施形態に対して素子領域8と配線引出部9との間の絶縁構造(具体的にはトレンチ分離部11)での電界負担を緩和させる構造を採用したものであり、その他に関しては第1実施形態と同様であるため、第1実施形態と異なる部分についてのみ説明する。
本発明の第4実施形態について説明する。本実施形態は、第1実施形態に対してトレンチ分離部11を変更したものであり、その他に関しては第1実施形態と同様であるため、第1実施形態と異なる部分についてのみ説明する。
本発明の第5実施形態について説明する。本実施形態は、第4実施形態のようにトレンチ分離部11を多重トレンチ構造としつつ、電界分布の均等化を図ったものであり、その他に関しては第4実施形態と同様であるため、第4実施形態と異なる部分についてのみ説明する。
上記各実施形態では、配線引出部9の周囲をトレンチ分離部11が囲むような構造としたが、素子領域8と配線引出部9とを囲むトレンチ分離部10内において、素子領域8と配線引出部9との間にトレンチ分離部11が配置される構造であれば良い。例えば、素子領域8がトレンチ分離部11にて囲まれるような構造であっても構わない。ただし、高耐圧MOSFET1の近辺への配線引出部9の高電圧の影響が少なくできるように、トレンチ分離部11にて高電圧となる配線引出部9側を囲んだ構造にするのが好ましい。
2 活性層
4 埋込絶縁膜
5 SOI基板
6 n+型埋込領域
7 n-型ドリフト層
8 素子領域
9 配線引出部
11 トレンチ分離部
18 層間絶縁膜
19 ソース配線
22 ドレイン配線
30 p+型電界緩和層
40 n+型電界緩和層
50 p型領域
51 配線部
52 抵抗
Claims (4)
- シリコンからなる活性層(2)と支持基板(3)とが埋込絶縁膜(4)を介して接合されたSOI基板(5)を用いて形成され、前記活性層(2)に対して高耐圧トランジスタ(1)が形成された半導体装置であって、
前記SOI基板(5)における前記活性層(2)のうち前記埋込絶縁膜(4)との界面には第1導電型の埋込領域(6)が備えられ、
前記高耐圧トランジスタ(1)は、前記活性層(2)に含まれた第1導電型層(7)を有し、該第1導電型層(7)に互いにトレンチ分離部(11)にて分離された素子領域(8)と配線引出部(9)とを備えた構成とされ、
前記素子領域(8)は、前記第1導電型層(7)の表面側に第1配線(19)を備えていると共に、前記活性層(2)に備えられた前記埋込領域(6)との間において、前記第1導電型層(7)の表裏面を貫通するように電流を流す縦型のトランジスタにて構成され、
前記配線引出部(9)は、前記第1導電型層(7)の表面側に形成された第2配線(22)を有し、前記トレンチ分離部(11)が前記第1導電型層(7)と同じもしくはそれより深くかつ前記埋込絶縁膜(4)から離間して形成されることで、前記埋込領域(6)を通じて前記素子領域(8)と電気的に接続されており、前記第2配線(22)と前記第1導電型層(7)および前記埋込領域(6)を前記素子領域(8)に流す電流の引出し配線としており、
前記トレンチ分離部(11)は、前記配線引出部(9)を中心として同心状に配置された多重トレンチ構造とされ、
さらに、前記活性層(2)のうち前記多重トレンチ構造を構成する前記トレンチ分離部(11)の間に配置された部分には第2導電型領域(50)が備えられており、
前記第1配線と前記第2導電型領域(50)との間および前記第2配線と前記第2導電型領域(50)との間が抵抗(52)を介して接続されていることを特徴とする半導体装置。 - 前記トレンチ分離部(11)により前記配線引出部(9)が囲まれていることを特徴とする請求項1に記載の半導体装置。
- 前記素子領域(8)における前記第1導電型層(7)のうち前記配線引出部(9)側において、前記トレンチ分離部(11)に沿って前記第1導電型層(7)の表面から形成された第2導電型電界緩和層(30)が備えられていることを特徴とする請求項1または2に記載の半導体装置。
- 前記素子領域(8)における前記第1導電型層(7)のうち前記配線引出部(9)側において、当該第1導電型層(7)よりも高不純物濃度とされ、前記トレンチ分離部(11)に沿って前記第1導電型層(7)の表面から形成された第1導電型電界緩和層(40)が備えられていることを特徴とする請求項1または2に記載の半導体装置。
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CN114639737B (zh) * | 2022-05-17 | 2022-08-30 | 广州粤芯半导体技术有限公司 | Ldmos器件及其制作方法 |
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JPH04123456A (ja) * | 1990-09-14 | 1992-04-23 | Hitachi Ltd | 半導体装置及びその製造方法 |
JP3008480B2 (ja) * | 1990-11-05 | 2000-02-14 | 日産自動車株式会社 | 半導体装置 |
JP2004363302A (ja) * | 2003-06-04 | 2004-12-24 | Toshiba Corp | Mosfet |
JP4974474B2 (ja) * | 2004-06-22 | 2012-07-11 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
JP4863665B2 (ja) * | 2005-07-15 | 2012-01-25 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
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US8097921B2 (en) * | 2007-11-09 | 2012-01-17 | Denso Corporation | Semiconductor device with high-breakdown-voltage transistor |
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