JP6707439B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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Description
以下に、第1実施形態に係る半導体装置の構成について説明する。図1に示すように、第1実施形態に係る半導体装置は、例えばドライバ回路DRCと、プリドライバ回路PDCと、アナログ回路ALCと、電源回路PWCと、ロジック回路LGCと、入出力回路IOCとを有している。第1実施形態に係る半導体装置は、例えばバイポーラトランジスタと、CMOS(Complementary Metal Oxide Semiconductor)トランジスタと、LDMOSトランジスタとが混載されている半導体装置である。
図6に示すように、第1実施形態に係る半導体装置の製造方法は、フロントエンド工程S1と、バックエンド工程S2とを有している。
上記のとおり、逆導電型領域RCRとドリフト領域DRIとの導電型は逆となっているため、逆導電型領域RCRとドリフト領域DRIとのpn接合により、空乏層が形成される。この空乏層により、ゲート絶縁膜GOの直下に位置する半導体基板SUB中での電界が緩和される。そのため、第1導電型がp型(第2導電型がn型)である場合、発生したホットキャリアがゲート絶縁膜GOに向かって加速されにくくなる。
以下に、第2実施形態に係る半導体装置の構成について説明する。なお、以下においては、第1実施形態に係る半導体装置と異なる点について主に説明し、重複する説明は繰り返さない。
Claims (9)
- 第1面を有する半導体基板と、
前記第1面側に配置され、かつ第1の深さを有する絶縁体により構成される絶縁分離構造と、
ゲート電極とを備え、
前記半導体基板は、前記第1面に接して配置されるソース領域と、前記第1面に接して配置されるドレイン領域と、前記第1面に接して配置され、かつ第2の深さを有する逆導電型領域と、前記ソース領域を取り囲むように前記第1面に接して配置されるボディ領域と、前記ドレイン領域及び前記逆導電型領域を取り囲み、かつ前記ソース領域との間で前記ボディ領域とを挟み込むように前記第1面に接して配置されるドリフト領域とを有し、
前記ソース領域、前記ドリフト領域及び前記ドレイン領域は、第1導電型であり、
前記ボディ領域及び前記逆導電型領域は、前記第1導電型の反対の導電型である第2導電型であり、
前記絶縁分離構造は、前記ドレイン領域と前記逆導電型領域との間に配置され、
前記ゲート電極は、前記ソース領域と前記ドリフト領域とにより挟み込まれた前記ボディ領域の部分と絶縁されながら対向し、
前記第1の深さは、前記第2の深さより深く、
前記逆導電型領域は、前記ソース領域と前記ドレイン領域との間に配置されており、かつ前記ソース領域に電気的に接続されている、半導体装置。 - 前記第2の深さは、前記第1の深さの0.3倍以上0.7倍以下である、請求項1に記載の半導体装置。
- 前記逆導電型領域における不純物濃度は、前記ドリフト領域における不純物濃度の10倍以上である、請求項1に記載の半導体装置。
- 第1面と、前記第1面の反対面である第2面とを有する半導体基板と、
前記第1面側に配置され、絶縁体により構成される絶縁分離構造と、
ゲート電極とを備え、
前記半導体基板は、前記第1面に接して配置されるソース領域と、前記第1面に接して配置されるドレイン領域と、前記第1面に接して配置される逆導電型領域と、前記ソース領域を取り囲むように前記第1面に接して配置されるボディ領域と、前記ドレイン領域及び前記逆導電型領域を取り囲み、かつ前記ソース領域との間で前記ボディ領域とを挟み込むように前記第1面に接して配置されるドリフト領域とを有し、
前記ソース領域、前記ドリフト領域及び前記ドレイン領域は第1導電型であり、
前記ボディ領域及び前記逆導電型領域は、前記第1導電型の反対の導電型である第2導電型であり、
前記半導体基板は、前記ドレイン領域と前記逆導電型領域との間に配置され、かつ前記第1面から前記第2面に向かって延びる溝を有し、
前記ゲート電極は、前記ソース領域と前記ドリフト領域とにより挟み込まれた前記ボディ領域の部分と絶縁されながら対向し、
前記絶縁分離構造は、前記溝と、前記溝に充填された前記絶縁体により構成され、
前記逆導電型領域は、前記ソース領域と前記ドレイン領域との間に配置されており、かつ前記ソース領域に電気的に接続されている、半導体装置。 - 前記溝の側壁と前記第1面とのなす角度であるテーパ角は、75°以上90°以下である、請求項4に記載の半導体装置。
- 前記絶縁分離構造は第1の深さを有し、
前記逆導電型領域は第2の深さを有し、
前記第1の深さは、前記第2の深さより深い、請求項4に記載の半導体装置。 - 前記第2の深さは、前記第1の深さの0.3倍以上0.7倍以下である、請求項6に記載の半導体装置。
- 前記逆導電型領域における不純物濃度は、前記ドリフト領域における不純物濃度の10倍以上である、請求項4に記載の半導体装置。
- 第1面と前記第1面の反対面である第2面とを有する半導体基板中において、前記第1面に接してドリフト領域及びボディ領域を形成する工程と、
前記第1面から前記第2面に向かって延びる溝を前記ドリフト領域内に形成するとともに、前記溝中に絶縁体を充填することにより絶縁分離構造を形成する工程と、
ゲート電極を形成する工程と、
前記第1面に接して前記ドリフト領域内に逆導電型領域を形成する工程と、
前記第1面に接して前記ドリフト領域内にドレイン領域を形成するとともに、前記第1面に接して前記ボディ領域内にソース領域を形成する工程とを備え、
前記溝は、前記逆導電型領域と前記ドレイン領域との間に位置しており、
前記ゲート電極は、前記ソース領域と前記ドリフト領域とにより挟み込まれた前記ボディ領域の部分と絶縁しながら対向し、かつ前記絶縁分離構造の前記ソース領域側の端と離間しており、
前記ソース領域、前記ドリフト領域及び前記ドレイン領域は第1導電型であり、
前記ボディ領域及び前記逆導電型領域は、前記第1導電型の反対の導電型である第2導電型であり、
前記逆導電型領域は、前記絶縁分離構造及び前記ゲート電極をマスクとしたイオン注入により形成され、
前記逆導電型領域は、前記ソース領域と前記ドレイン領域との間に配置されており、かつ前記ソース領域に電気的に接続されている、半導体装置の製造方法。
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