US10868210B2 - Solar cell and method of manufacturing the same - Google Patents

Solar cell and method of manufacturing the same Download PDF

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US10868210B2
US10868210B2 US15/385,316 US201615385316A US10868210B2 US 10868210 B2 US10868210 B2 US 10868210B2 US 201615385316 A US201615385316 A US 201615385316A US 10868210 B2 US10868210 B2 US 10868210B2
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conductive
layer
conductive area
polycrystalline
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US20170179325A1 (en
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Indo Chung
Mihee Heo
Juhong YANG
Eunjoo Lee
Jeongbeom Nam
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Jingao Solar Co Ltd
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LG Electronics Inc
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    • H01L31/02—Details
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    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/036—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes
    • H01L31/0392—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including thin films deposited on metallic or insulating substrates ; characterised by specific substrate materials or substrate features or by the presence of intermediate layers, e.g. barrier layers, on the substrate
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    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
    • H01L31/1872—Recrystallisation
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    • H01L31/02—Details
    • H01L31/0216—Coatings
    • H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
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    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
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    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/022441—Electrode arrangements specially adapted for back-contact solar cells
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    • H01L31/0236—Special surface textures
    • H01L31/02363—Special surface textures of the semiconductor body itself, e.g. textured active layers
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    • H01L31/02—Details
    • H01L31/0236—Special surface textures
    • H01L31/02366—Special surface textures of the substrate or of a layer on the substrate, e.g. textured ITO/glass substrate or superstrate, textured polymer layer on glass substrate
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    • H01L31/036—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes
    • H01L31/0368—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including polycrystalline semiconductors
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    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • H01L31/0682—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells back-junction, i.e. rearside emitter, solar cells, e.g. interdigitated base-emitter regions back-junction cells
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    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/546—Polycrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
    • Y02P70/521—

Definitions

  • the present invention relates to a back-surface electrode type solar cell in which all electrodes are provided on the back surface, and a method of manufacturing the same.
  • solar cells are popular next generation cells to convert sunlight into electrical energy.
  • Solar cells may be manufactured by forming various layers and electrodes based on some design.
  • the efficiency of solar cells may be determined by the design of the various layers and electrodes.
  • the problem of low efficiency and low productivity needs to be overcome, and thus, there is a demand for a solar cell and a method of manufacturing the same, which may maximize the efficiency and productivity of the solar cell.
  • a solar cell includes a semiconductor substrate, a protective-film layer formed on a surface of the semiconductor substrate, a polycrystalline semiconductor layer formed over the protective-film layer, a first conductive area formed by selectively doping the semiconductor layer with a first conductive dopant, a second conductive area doped with a second conductive dopant and located between neighboring portions of the first conductive area, a barrier area located between the first conductive area and the second conductive area and doped with no dopant, a first electrode connected to the first conductive area, and a second electrode connected to the second conductive area.
  • Each of the first conductive area and the second conductive area includes a second crystalline area having a crystalline structure different from that of the barrier area, and the second crystalline areas of the first conductive area and the second conductive area include a second polycrystalline area and a fourth crystalline area having different depths.
  • FIG. 1 is a cross-sectional view illustrating a solar cell according to an embodiment of the present invention
  • FIG. 2 is a plan view illustrating the back surface of the solar cell illustrated in FIG. 1 ;
  • FIG. 3 is a flowchart illustrating a method of manufacturing a solar cell according to an embodiment of the present invention
  • FIGS. 4A to 4M are views diagrammatically illustrating respective operations of FIG. 3 ;
  • FIGS. 5 to 12 are views related a method of scanning a doping layer using a laser
  • FIG. 13 is a view illustrating the crystalline structure of a second polycrystalline area
  • FIG. 14 is a TEM photograph illustrating re-crystallization occurring in a semiconductor layer
  • FIG. 15 is a view illustrating change in the thickness of the semiconductor layer when a residual doping layer is removed via wet etching
  • FIG. 16 is a view illustrating change in the thickness of the semiconductor layer when a residual doping layer is removed via dry etching
  • FIGS. 17 and 18 are views illustrating a laser scanning method for forming openings
  • FIG. 19 is a view illustrating the crystalline structure of a fourth polycrystalline area
  • FIG. 20 is a view illustrating the crystalline structure of a third crystalline area
  • FIG. 21 is a cross-sectional view illustrating a solar cell according to an embodiment of the present invention.
  • FIG. 22 is a partial rear plan view of the solar cell illustrated in FIG. 21 ;
  • FIGS. 23A to 23L are cross-sectional views illustrating a method of manufacturing a solar cell according to an embodiment of the present invention.
  • FIG. 24 is a view illustrating the principle of forming a contact hole in an insulation film by a laser
  • FIG. 25 is a cross-sectional view illustrating a solar cell according to another embodiment of the present invention.
  • FIG. 26 is a cross-sectional view of a solar cell according to another embodiment of the present invention.
  • FIG. 27 is a partially enlarged sectional view illustrating a solar cell according to another embodiment of the present invention.
  • FIG. 28 is a partial rear plan view illustrating a solar cell according to another embodiment of the present invention.
  • FIG. 29 is a microphotograph illustrating the back surface of a solar cell according to a manufacturing example
  • FIG. 30 is a photograph illustrating the cross section of a solar cell in the portion in which a contact hole is formed (i.e. a first portion) and in the portion in which no contact hole is formed (i.e. a second portion);
  • FIG. 31 is a graph illustrating the result of analysis of a semiconductor layer via a Raman analysis method in the portion in which the contact hole is formed (i.e. the first portion) and in the portion in which no contact hole is formed (i.e. the second portion);
  • FIG. 32 is a cross-sectional view illustrating an example of a solar cell according to an embodiment of the present invention.
  • FIG. 33 is a plan view illustrating the back surface of the solar cell illustrated in FIG. 32 ;
  • FIG. 34 is a flowchart illustrating a method of manufacturing a solar cell according to an embodiment of the present invention.
  • FIGS. 35A to 35O are views diagrammatically illustrating respective operations of FIG. 34 ;
  • FIG. 36 is a perspective view illustrating a solar cell panel according to an embodiment of the present invention.
  • FIG. 37 is a cross-sectional view taken along line II-II of FIG. 36 .
  • FIG. 1 is a cross-sectional view illustrating an example of the solar cell according to some embodiments of the present invention
  • FIG. 2 is a partial rear plan view of the solar cell illustrated in FIG. 1 .
  • the solar cell 100 includes a semiconductor substrate 10 , a protective-film layer 20 , which is formed on the surface of the semiconductor substrate 10 , a first conductive area 32 and a second conductive area 34 , which are located over the protective-film layer 20 , are formed of a polycrystalline semiconductor, and form a pn junction with the semiconductor substrate 10 , and a first electrode 42 and a second electrode 44 , which are respectively in contact with the first conductive area 32 and the second conductive area 34 .
  • the first conductive area 32 includes a second polycrystalline area 321 , which has a crystalline structure different from that of the remaining area of the first conductive area 32
  • the second conductive area 34 includes a fourth polycrystalline area 341 , which has substantially the same crystalline structure as the second polycrystalline area 321
  • each of the second polycrystalline area 321 and the fourth polycrystalline area 341 further includes a third crystalline area 321 a or 341 a , which is in contact with the first electrode 42 or the second electrode 44 .
  • the solar cell 100 may further include a front-surface field area 130 , an insulation film 24 , and an anti-reflection film 26 , which are provided on the front surface of the semiconductor substrate 10 .
  • the semiconductor substrate 10 is formed of a crystalline semiconductor that is doped with a first conductive dopant at a low concentration.
  • the semiconductor substrate 10 is formed of a monocrystalline or polycrystalline semiconductor.
  • a monocrystalline semiconductor has high crystallinity and thus few defects, and the electrical properties thereof are superior to those of a polycrystalline semiconductor.
  • a first conductive type is any one of a p-type and an n-type.
  • the first conductive area 32 which is of a p-type and forms a pn junction for forming carriers via photoelectric conversion, may be widely formed in order to increase a photoelectric conversion area.
  • the first conductive area 32 having a wide area may effectively collect holes, which move relatively slowly, thereby contributing to an increase in photoelectric conversion efficiency.
  • the semiconductor substrate 10 includes the front-surface field area 130 located on the front surface (i.e. light incident surface) of the semiconductor substrate 10 .
  • the front-surface field area 130 is of the same conductive type as the semiconductor substrate 10 and has a higher doping concentration than the semiconductor substrate 10 .
  • the front-surface field area 130 is a doped area formed by doping the semiconductor substrate 10 with the first conductive dopant at a higher doping concentration than that of the semiconductor substrate 10 , and the doping concentration of the front-surface field area 130 is lower than the doping concentration of the second conductive area 34 , which is of the same conductive type as the front-surface field area 130 .
  • the doping concentration of the front-surface field area 130 may be lower than the doping concentration of the second conductive area 34 .
  • the doping concentration of the front-surface field area 130 may range from 1 ⁇ 10 17 /cm 3 to 1 ⁇ 10 20 /cm 3
  • the doping concentration of the second conductive area 34 may range from 1 ⁇ 10 20 /cm 3 to 1 ⁇ 10 22 /cm 3 .
  • a dopant included in the second conductive area 34 is of the first conductive type, which is the same as that of the first conductive dopant included in the front-surface field area 130 .
  • the first conductive dopant included in the second conductive area 34 and the first conductive dopant included in the front-surface field area 130 are the same material.
  • the front surface of the semiconductor substrate 10 is provided with a textured structure in the form of, for example, pyramids, which increases the penetration of light into the semiconductor substrate 10 .
  • the form of the textured structure varies based on the crystalline structure of the semiconductor substrate 10 .
  • a monocrystalline structure has a consistent crystalline direction, and thus has even convex-concave portions, whereas a polycrystalline structure has an inconsistent crystalline direction, and thus has uneven convex-concave portions.
  • the back surface of the semiconductor substrate 10 may be formed via, for example, mirror surface grinding, and thus may be a relatively smooth flat surface, which has smaller surface roughness than the front surface.
  • the properties of the back surface of the semiconductor substrate 10 may have a great effect on the properties of the solar cell 100 . Therefore, the back surface of the semiconductor substrate 10 may have no convex-concave portions formed via texturing, in order to achieve an improved passivation property.
  • the protective-film layer 20 is formed on the surface of the semiconductor substrate 10 .
  • the protective-film layer 20 may be formed to be brought into contact with the surface of the semiconductor substrate 10 , and thus may exhibit a simplified structure and improved tunneling effects.
  • the protective-film layer 20 may serve as a barrier for electrons and holes so as to prevent minority carriers from passing therethrough and to allow only majority carriers, which accumulate at a portion adjacent to the protective-film layer 20 and thus have a given amount of energy or more, to pass therethrough. At this time, the majority carriers, which have the given amount of energy or more, may easily pass through the protective-film layer 20 owing to tunneling effects.
  • the protective-film layer 20 may serve as a diffusion barrier for preventing the dopants of the conductive areas 32 and 34 from diffusing into the semiconductor substrate 10 .
  • the protective-film layer 20 may be formed of any of various materials to enable the tunneling of the majority carriers.
  • the protective-film layer 20 may be formed of an oxide, a nitride, a semiconductor, or a conductive polymer.
  • the protective-film layer 20 may be formed of a silicon oxide, a silicon nitride, a silicon oxide nitride, intrinsic amorphous silicon, or intrinsic polycrystalline silicon.
  • the protective-film layer 20 may be formed of a silicon oxide.
  • a silicon oxide has an excellent passivation property and ensures easy tunneling of carriers.
  • the thickness of the protective-film layer 20 may be 5 nm or less, and more specifically, may range from 0.5 nm to 2 nm. When the thickness of the protective-film layer 20 exceeds 5 nm, smooth tunneling does not occur, and consequently, the solar cell 100 may not operate. When the thickness of the protective-film layer 20 is below 0.5 nm, it may be difficult to form the protective-film layer 20 having a desired quality. In order to further improve tunneling effects, the thickness of the protective-film layer 20 may range from 0.5 nm to 2 nm.
  • a polycrystalline semiconductor layer 30 which has a crystalline structure different from that of the semiconductor substrate 10 , is formed over the protective-film layer 20 .
  • the semiconductor layer 30 includes the first conductive area 32 and the second conductive area 34 in the same layer.
  • the first conductive area 32 is doped with the second conductive dopant at a high concentration
  • the second conductive area 34 is doped with the first conductive dopant, which is of the same conductive type as that of the dopant included in the semiconductor substrate 10 , at a high concentration.
  • the first conductive dopant when the first conductive dopant is of a p-type, it may be a group-III element, such as boron (B), aluminum (Al), gallium (Ga), or indium (In).
  • the first conductive dopant when the first conductive dopant is of an n-type, it may be a group-V element, such as phosphorus (P), arsenic (As), bismuth (Bi), or antimony (Sb).
  • the second conductive dopant and the first conductive dopant are of opposite conductive types.
  • the first conductive area 32 may be a p-type conductive area and the second conductive area may be an n-type conductive area.
  • the first conductive area 32 may be an n-type conductive area and the second conductive area may be a p-type conductive area.
  • the first conductive area 32 configures an emitter area, which forms a pn junction with the semiconductor substrate 10 with the protective-film layer 20 interposed therebetween so as to produce carriers via photoelectric conversion.
  • the second conductive area 34 configures a back-surface field area, which forms a back-surface field so as to prevent the loss of carriers due to recombination on the surface of the semiconductor substrate 10 .
  • a barrier area 33 may be located between the first conductive area 32 and the second conductive area 34 so that the first conductive area 32 and the second conductive area 34 are spaced apart from each other.
  • shunts may occur, undesirably causing deterioration in the performance of the solar cell 100 . Therefore, unnecessary or undesired shunts may be prevented when the barrier area 33 is located between the first conductive area 32 and the second conductive area 34 .
  • the barrier area 33 may be formed of any of various materials, which may substantially insulate the first conductive area 32 and the second conductive area 34 from each other.
  • the barrier area 33 may be formed of an undoped insulation material, and more specifically, an intrinsic semiconductor that is not doped with a foreign substance (i.e. a dopant).
  • the semiconductor substrate 10 when the semiconductor substrate 10 is of an n-type, it forms a pn junction with the first conductive area 32 , and the first conductive area 32 forms an emitter. In this instance, the area of the first conductive area 32 may be greater than the area of the second conductive area 34 .
  • the wide first conductive area 32 may serve to collect holes. Because holes have longer lifetimes than electrons, the first conductive area 32 may effectively collect holes.
  • the first conductive area 32 and the second conductive area 34 may have different thicknesses. Because the first conductive area 32 and the second conductive area 34 are formed using different methods in different operations as will be described below, the first conductive area 32 and the second conductive area 34 may have different heights.
  • the first conductive area 32 may include the second polycrystalline area 321 .
  • the second polycrystalline area 321 has a crystalline structure different from that of the remaining area of the first conductive area 32 .
  • a semiconductor layer 302 is melted and re-crystallized, thereby forming the second polycrystalline area 321 .
  • the first conductive area 32 may include a first polycrystalline area and the second polycrystalline area 321 .
  • the first polycrystalline area has a first grain size and is formed between the protective-film layer 20 and the second polycrystalline area 321 so as to be brought into contact with the protective-film layer 20 .
  • the second polycrystalline area 321 is formed on the first polycrystalline area and has a second grain size greater than the first grain size.
  • the first polycrystalline area may be an area of the first conductive area 32 in which no re-crystallization occurs, and the first grain size may be the same as the grain size of the semiconductor layer 302 .
  • the grains in the second polycrystalline area 321 are larger than the grains in the semiconductor layer 302 , and have a denser arrangement.
  • the ratio of the cross-sectional area of the second polycrystalline area 321 to the cross-sectional area of the first conductive area 32 may be 0.5:1 or more, and the ratio of the depth of the second polycrystalline area 321 to the thickness of the semiconductor layer 302 may be greater than 0.5:1, but less than 1:1.
  • the second conductive area 34 may include the fourth polycrystalline area 341 .
  • the fourth polycrystalline area 341 has a crystalline structure different from that of the remaining area of the second conductive area 34 .
  • the semiconductor layer 302 is melted and re-crystallized, thereby forming the fourth polycrystalline area 341 .
  • the second conductive area 34 may include a third polycrystalline area and the fourth polycrystalline area 341 .
  • the third polycrystalline area has the first grain size and is formed between the protective-film layer 20 and the fourth polycrystalline area 341 so as to be brought into contact with the protective-film layer 20 .
  • the fourth polycrystalline area 341 is formed on the third polycrystalline area and has the second grain size greater than the first grain size.
  • the third polycrystalline area may be an area of the second conductive area 34 in which no re-crystallization occurs, and the first grain size may be the same as the grain size of the semiconductor layer 302 .
  • the first polycrystalline area and the third polycrystalline area which have the same first grain size, may respectively or collectively be referred to as a first crystalline area
  • the second polycrystalline area 321 and the fourth polycrystalline area 341 which have the same second grain size, may respectively or collectively be referred to as a second crystalline area 321 or 341
  • a fifth polycrystalline area 321 a and a sixth polycrystalline area 341 a which have the same third grain size as will be described below, may respectively or collectively be referred to as the third crystalline area 321 a or 341 a.
  • the grains in the fourth polycrystalline area 341 are substantially the same as the grains in the second polycrystalline area 321 .
  • the ratio of the cross-sectional area of the fourth polycrystalline area 341 to the cross-sectional area of the second conductive area 34 may be greater than the ratio of the cross-sectional area of the second polycrystalline area 321 to that of the first conductive area 32 .
  • the second crystalline areas 321 and 341 may respectively include the third crystalline areas 321 a and 341 a .
  • the crystalline structure of the third crystalline areas 321 a and 341 a may differ from the crystalline structure of the second crystalline areas 321 and 341 .
  • the third crystalline areas 321 a and 341 a are formed in the process of bringing the first electrode 42 and the second electrode 44 into contact with the first conductive area 32 and the second conductive area 34 .
  • the third crystalline areas 321 a and 341 a may be formed when the interfaces of the second crystalline areas 321 and 341 , which are in contact with the first electrode 42 and the second electrode 44 , are re-crystallized.
  • the third crystalline areas 321 a and 341 a have the third grain size, which is smaller than the first grain size and the second grain size. This will be described below in detail.
  • the insulation film 40 is formed over the semiconductor layer 30 .
  • the insulation film 40 has a first opening 40 a for connection between the first conductive area 32 and the first electrode 42 , and a second opening 40 b for connection between the second conductive area 34 and the second electrode 44 .
  • the insulation film 40 functions to passivate the semiconductor layer 30 .
  • the insulation film 40 may be formed of a single film or multiple films in the form of a combination of two or more films selected from the group consisting of a silicon nitride film, a silicon nitride film containing hydrogen, a silicon oxide film, a silicon oxide nitride film, a silicon carbide film, and Al 2 O 3 , MgF 2 , ZnS, TiO 2 , and CeO 2 films.
  • the electrodes 42 and 44 disposed on the back surface of the semiconductor substrate 10 , include the first electrode 42 , which is in contact with the first conductive area 32 , and the second electrode 44 , which is in contact with the second conductive area 34 .
  • the first electrode 42 is brought into contact with the first conductive area 32 through the first opening 40 a
  • the second electrode 44 is brought into contact with the second conductive area 34 through the second opening 40 b
  • the first and second electrodes 42 and 44 may be formed of any of various metal materials, and may have a multilayered structure including two or more layers.
  • the first and second electrodes 42 and 44 may have any of various plan shapes in order to collect and outwardly transfer carriers by being connected respectively to the first conductive area 32 and the second conductive area 34 while not being electrically connected to each other.
  • each of the first and second electrodes 42 and 44 may have a protrusion configured to protrude into the first opening 40 a or the second opening 40 b.
  • the front insulation film 24 and the anti-reflection film 26 are selectively disposed over the front-surface field area 130 on the front surface of the semiconductor substrate 10 . That is, in some embodiments, only the front insulation film 24 may be formed over the semiconductor substrate 10 , only the anti-reflection film 26 may be formed over the semiconductor substrate 10 , or the front insulation film 24 and the anti-reflection film 26 may be sequentially disposed over the semiconductor substrate 10 .
  • the front insulation film 24 and the anti-reflection film 26 may substantially be formed on the entire front surface of the semiconductor substrate 10 .
  • the front insulation film 24 is formed so as to be brought into contact with the surface of the semiconductor substrate 10 for the passivation of defects, which exist in the surface or the bulk of the semiconductor substrate 10 .
  • the front insulation film 24 may increase the open-circuit voltage of the solar cell 150 by removing recombination sites of the minority carriers.
  • the anti-reflection film 26 reduces the reflectance of light introduced into the front surface of the semiconductor substrate 10 .
  • the anti-reflection film 26 may increase the quantity of light, which reaches a pn junction formed at the interface of the semiconductor substrate 10 and the first conductive area 32 .
  • the anti-reflection film 26 may increase the short-circuit current Isc of the solar cell 100 .
  • the front insulation film 24 and the anti-reflection film 26 may increase the open-circuit voltage and the short-circuit current of the solar cell 100 , thereby improving the efficiency of the solar cell 100 .
  • Each of the front insulation film 24 and the anti-reflection film 26 may include a single film or multiple films in the form of a combination of two or more films selected from the group consisting of a silicon nitride film, a silicon nitride film containing hydrogen, a silicon oxide film, a silicon oxide nitride film, an aluminum oxide film, a silicon carbide film, and MgF 2 , ZnS, TiO 2 , and CeO 2 films.
  • the efficiency of the solar cell 100 may be improved.
  • the first and second conductive areas 32 and 34 are formed over the semiconductor substrate 10 with the protective-film layer 20 interposed therebetween, and thus are formed separately from the semiconductor substrate 10 . As such, loss due to recombination may be less than that when a doped area formed by doping an area of the semiconductor substrate 10 with a dopant is used as a conductive area.
  • a plurality of first conductive areas 32 and a plurality of second conductive areas 34 are formed to extend a long length in a given direction, and are arranged side by side.
  • the first conductive areas 32 and the second conductive areas 34 are alternately arranged.
  • the barrier area 33 may be located between the first conductive area 32 and the second conductive area 34 so that the first conductive area 32 and the second conductive area 34 are spaced apart from each other by the barrier area 33 .
  • the area of the first conductive area 32 may be greater than the area of the second conductive area 34 , as illustrated in FIG. 2 .
  • the areas of the first conductive area 32 and the second conductive area 34 may be adjusted by providing the first conductive area 32 and the second conductive area 34 with different widths. In this instance, the width W 1 of the first conductive area 32 is greater than the width W 2 of the second conductive area 34 .
  • first electrode 42 is formed in a stripe shape over the first conductive area 32
  • second electrode 44 is formed in a stripe shape over the second conductive area 34 .
  • FIG. 3 is a flowchart illustrating the method of manufacturing the solar cell according to an embodiment of the present invention.
  • the method of manufacturing the solar cell according to the embodiment includes, in temporal sequence, a protective-film layer forming operation S 101 , an intrinsic semiconductor layer forming operation S 102 , a doping layer forming operation S 103 , a first conductive area forming operation S 104 , a doping layer removal operation S 105 , a texturing operation S 106 , a mask layer patterning operation S 107 , a second conductive area/front-surface field area forming operation S 108 , an insulation film forming operation S 109 , and an electrode forming operation S 110 .
  • FIGS. 4A to 4M are views diagrammatically illustrating the respective operations of FIG. 3 .
  • the second crystalline area and the third crystalline area are illustrated only in the drawings of the corresponding description, and are omitted in the other drawings.
  • protective-film layers 201 and 202 are formed respectively on both surfaces, i.e. the front surface and the back surface, of the semiconductor substrate 10 .
  • the protective-film layers include a front protective-film layer 201 disposed on the front surface of the semiconductor substrate 10 , and a back protective-film layer 202 disposed on the back surface of the semiconductor substrate 10 .
  • FIG. 4A diagrammatically illustrates the protective-film layer forming operation S 101 .
  • the front surface of the semiconductor substrate 10 is illustrated as facing downward.
  • the semiconductor substrate 10 is formed of a silicon crystal growth semiconductor having a monocrystalline or polycrystalline structure, and contains any one of the first conductive dopant and the second conductive dopant, which are of opposite conductive types.
  • the first conductive dopant is an n-type dopant, for example, a group-V element, such as phosphorus (P), arsenic (As), bismuth (Bi), or antimony (Sb)
  • the second conductive dopant is a p-type dopant, for example, a group-III element, such as boron (B), aluminum (Al), gallium (Ga), or indium (In).
  • the semiconductor substrate 10 has a monocrystalline structure in which grains are grown only in a given direction, and contains an n-type dopant. As such, in the semiconductor substrate 10 , holes, which have longer lifetimes than electrons, form majority carriers to facilitate photoelectric conversion at a pn junction surface.
  • the protective-film layers 201 and 202 are configured as oxide layers including a thermal oxide and a silicon oxide, and have a thickness of 5 nm or less, more specifically, a thickness within a range from 0.5 nm to 2 nm.
  • the protective-film layers 201 and 202 reduce recombination sites corresponding to a pn junction surface, and therefore function to enable effective passivation.
  • the thickness of the protective-film layers 201 and 202 exceeds 5 nm, the probability of tunneling of carriers is reduced, causing a reduction in the efficiency of the solar cell 100 .
  • the thickness of the protective-film layers 201 and 202 is below 0.5 nm, the protective-film layers 201 and 202 may not perform a passivation function, causing a reduction in the efficiency of the solar cell 100 .
  • the protective-film layers 201 and 202 may be formed via a Chemical Vapor Deposition (CVD) method, and source gas may include only oxygen gas, or may include oxygen gas and silane gas (SiH 4 ).
  • CVD Chemical Vapor Deposition
  • the protective-film layers 201 and 202 are formed of a thermal oxide SiOx, which is made via a chemical reaction between oxygen ions decomposed from the source gas and the surface of the semiconductor substrate 10 .
  • the protective-film layers 201 and 202 are formed of an oxide (e.g. a silicon oxide (SiOx)), which is made via a chemical reaction between oxygen ions decomposed from the source gas and silicon ions decomposed from the silane gas and the surface of the semiconductor substrate 10 .
  • oxide e.g. a silicon oxide (SiOx)
  • the source gas may further include nitrogen gas and chlorine gas, in addition to oxygen gas and silane gas.
  • chlorine gas enables adjustment in the purity of the protective-film layers 201 and 202
  • nitrogen gas enables adjustment in the film growth rate and uniformity of the protective-film layers 201 and 202 .
  • the amount of chlorine gas may be less than the amount of oxygen gas.
  • the volume ratio of oxygen gas to chlorine gas may range from 1:0.05 to 1:0.1.
  • the ratio When the ratio is below 1:0.05, the increase in purity attributable to chlorine gas may be insufficient. When the ratio exceeds 1:0.1, a greater amount of chlorine gas than a required amount may be included, which may deteriorate the purity of the protective-film layers 201 and 202 and may increase the growth rate of the protective-film layers 201 and 202 , resulting in an increase in the thickness of the protective-film layers 201 and 202 .
  • the amount of nitrogen gas is adjusted in consideration of the size of a chamber in which the protective-film layers 201 and 202 are formed, and the total amount of oxygen gas, chlorine gas and nitrogen gas is adjusted to achieve a required pressure in consideration of processing conditions.
  • the protective-film layers 201 and 202 are formed at a high temperature through a thermal oxidation process, rapid growth of an oxide may make it difficult for the protective-film layers 201 and 202 to be formed to a desired thickness.
  • the protective-film layers 201 and 202 are formed at a temperature lower than room temperature.
  • the growth rate of the protective-film layers 201 and 202 may be controlled so that the protective-film layers 201 and 202 are formed to a small thickness.
  • the protective-film layers 201 and 202 may be formed at a temperature of 600° C. or more and at a pressure of 2 Torr or less.
  • pressure is the actual pressure inside the chamber.
  • the protective-film layers 201 and 202 When the protective-film layers 201 and 202 are formed at a temperature of 600° C. or more, the protective-film layers 201 and 202 may have an increased density and a reduced interface trap density Dit, which may improve a passivation property of the protective-film layers 201 and 202 .
  • the protective-film layers 201 and 202 may be formed at a temperature similar to that of the semiconductor layer 30 , which will be formed after the formation of the protective-film layers 201 and 202 .
  • the protective-film layers 201 and 202 and semiconductor layers 301 and 302 may be formed in successive processes.
  • the protective-film layers 201 and 202 may maintain a low growth rate due to the low pressure, and thus may be easily formed to a desired thickness, even if the protective-film layers 201 and 202 are formed at a high temperature through a thermal oxidation process.
  • the protective-film layers 201 and 202 may be formed at a temperature within a range from 600° C. to 800° C. and at a pressure within a range from 0.01 Torr to 2 Torr.
  • the protective-film layers 201 and 202 are formed at a temperature above 800° C., it is difficult to control the growth rate of an oxide even when the pressure is reduced, and change in the thickness of the oxide may increase.
  • the protective-film layers 201 and 202 may be formed at a temperature within a range from 600° C. to 700° C.
  • the protective-film layers 201 and 202 are formed at a pressure below 0.1 Torr, cost and the like may increase, and load may be applied to an apparatus for manufacturing the protective-film layers 201 and 202 .
  • the pressure may range from 0.5 Torr to 2 Torr.
  • the thickness of the protective-film layers 201 and 202 may range from 0.5 nm to 2 nm. In order to uniformly form the protective-film layers 201 and 202 to this thickness, the process of forming the protective-film layers 201 and 202 may be performed for a time within a range from 10 minutes to 20 minutes.
  • a film has been formed to a thickness above 2 nm in order to prevent tunneling.
  • an oxide layer is formed, between pn junction surfaces, to a thickness at which tunneling occurs.
  • a thin protective-film layer by adjusting the temperature and the pressure when the protective-film layer is formed via a deposition method has not been known. Therefore, such a protective-film layer has been formed via a method that has generally been used in, for example, the semiconductor field, such as, for example, wet oxidation, or thermal oxidation in an atmospheric furnace. As such, it has been impossible to uniformly form a thin protective-film layer so as to achieve efficient tunneling.
  • the protective-film layers 201 and 202 are formed through a thermal oxidation process that is performed at a high temperature, and the rate of thermal oxidation is adjusted at a pressure lower than atmospheric pressure, unlike in the related art.
  • the protective-film layers 201 and 202 may be uniformly formed to a small thickness at which efficient tunneling may be achieved.
  • the protective-film layers 201 and 202 may be formed via a Low Pressure Chemical Vapor Deposition (LPCVD) method.
  • LPCVD Low Pressure Chemical Vapor Deposition
  • protective films are formed respectively on both surfaces, i.e. the front surface and the back surface, of the semiconductor substrate 10 .
  • the first protective-film layer 201 disposed on the front surface of the semiconductor substrate 10 and the second protective-film layer 202 disposed on the back surface of the semiconductor substrate 10 are formed in operation S 101 .
  • semiconductor layers are formed over the protective-film layers 201 and 202 .
  • the semiconductor layers may also be formed via an LPCVD method, two layers may be successively formed using the same deposition facility, which enables an in-situ process.
  • the manufacturing process may be greatly simplified, which may greatly reduce, for example, manufacturing costs and manufacturing time.
  • the difference in temperature between the two processes may be adjusted to 100° C. or less.
  • temperatures, the adjustment of which is relatively difficult, are maintained without great variation as described above, the in-situ process of successively forming the protective-film layers 201 and 202 and the semiconductor layers 301 and 302 may be facilitated.
  • the intrinsic semiconductor layers 301 and 302 which are of a crystalline type and are not doped with a dopant, are formed respectively over the first protective-film layer 201 and the second protective-film layer 202 .
  • FIG. 4B diagrammatically illustrates the intrinsic semiconductor layer forming operation S 102 .
  • the intrinsic semiconductor layers include a first intrinsic semiconductor layer 301 disposed over the first protective-film layer 201 , and a second intrinsic semiconductor layer 302 disposed over the second protective-film layer 202 .
  • the thickness of each of the semiconductor layers may range from 300 nm to 400 nm. When the thickness is below 300 nm, a foreign substance may be doped to the second protective-film layer 202 in the subsequent first conductive area forming operation S 104 . When the thickness is above 400 nm, a foreign substance may be doped on only a portion of the second intrinsic semiconductor layer 302 in a thickness direction, rather than being doped on the entire second intrinsic semiconductor layer 302 .
  • the intrinsic semiconductor layers 301 and 302 are formed via an LPCVD method, in order to enable an in-situ process in connection with the previous operation S 101 .
  • operation S 101 and operation S 102 are performed via the same LPCVD method, the processes of the two operations may be performed using the same equipment.
  • contamination of the protective-film layer by a foreign substance, or an increase in the thickness of the protective-film layer by additional oxidation, which is caused when the semiconductor substrate, on which the protective-film layer has been formed, must be removed from the equipment may be prevented, unlike the related art.
  • source gas includes only gas containing a semiconductor material, for example, silane gas (SiH 4 ), because the semiconductor layers 301 and 302 are intrinsic.
  • the source gas may also contain nitrogen dioxide (N 2 O) gas and/or oxygen (O 2 ) gas so as to adjust, for example, the size and crystallinity of crystal grains.
  • each of the semiconductor layers 301 and 302 is configured as a crystalline semiconductor layer in which a polycrystalline portion in an amount of 80% to 95% and an amorphous portion in an amount of 5% to 20% are mixed with each other.
  • the deposition temperature in this process is equal to or less than the temperature at which the protective-film layers 201 and 202 are formed.
  • the deposition temperature of the semiconductor layers 301 and 302 is lower than the temperature at which the protective-film layers 201 and 202 are formed, the properties of the semiconductor layers 301 and 302 , which directly participate in photo-electric conversion, may be consistent.
  • the semiconductor layers 301 and 302 have a crystalline structure different from that of the semiconductor substrate 10 and are not doped with a foreign substance, the semiconductor layers 301 and 302 have a lower reaction rate than when doped.
  • the deposition temperature of the semiconductor layers 301 and 302 may range from 600° C. to 700° C. As such, the difference between the deposition temperature of the semiconductor layers 301 and 302 and the temperature at which the protective-film layers 201 and 202 are formed may be reduced.
  • the time taken to adjust the temperatures of the two processes and the time taken to stabilize the temperatures may be reduced, which may simplify processing.
  • the deposition pressure in operation S 102 ranges from 0.01 Torr to 0.5 Torr.
  • the deposition pressure is below 0.01 Torr, the implementation of the process may be limited and the processing time of the semiconductor layers 301 and 302 may excessively increase.
  • the deposition pressure is above 0.5 Torr, the uniformity of the semiconductor layers 301 and 302 is reduced.
  • the semiconductor layers 301 and 302 are processed at a low deposition pressure, in order to improve the properties of the semiconductor layers 301 and 302 as described above. More specifically, the semiconductor layers 301 and 302 are formed as the source gas including silane gas is thermally decomposed so that a semiconductor material is deposited over the protective-film layers 201 and 202 . Although the deposition temperature and/or the deposition pressure may be increased in order to increase the deposition rate, this may increase the difference in crystallinity inside the semiconductor layers 301 and 302 . Meanwhile, the mobility of carriers greatly depends on the grain size of the semiconductor layer, and the increased difference in crystallinity means that the semiconductor layers 301 and 302 have inconsistent properties. In operation S 102 , because the deposition pressure ranges from 0.01 Torr to 0.5 Torr, the difference in crystallinity may be effectively reduced.
  • FIG. 4C diagrammatically illustrates the doping layer forming operation S 103 .
  • the doping layer 314 is disposed only over the second semiconductor layer 302 , and is not present over the first semiconductor layer 301 .
  • the dopant contained in the doping layer 314 may be the second conductive dopant, which is of an opposite conductive type of that of the dopant in the semiconductor substrate 10 .
  • the dopant in the doping layer 314 is a p-type dopant.
  • a group-III element such as boron (B), aluminum (Al), gallium (Ga), or indium (In) is used as the dopant in the doping layer 314 .
  • the dopant in the doping layer 314 is an n-type dopant.
  • a group-V element such as phosphorus (P), arsenic (As), bismuth (Bi), or antimony (Sb), is used as the dopant in the doping layer 314 .
  • the dopant included in the doping layer 314 is introduced into the second semiconductor layer 302 in the subsequent operation S 104 , causing the second semiconductor layer 302 to form a pn junction with the semiconductor substrate 10 with the second protective-film layer 202 interposed therebetween.
  • the concentration of the dopant included in the doping layer 314 ranges from 1 ⁇ 10 20 /cm 3 to 1 ⁇ 10 22 /cm 3 , and is greater than the concentration of a dopant in a first conductive area, which will be described in the subsequent step.
  • the doping layer 314 having the above concentration of dopant is configured as a semiconductor layer formed of amorphous silicon, and has a thickness within a range from 30 nm to 50 nm.
  • the doping layer 314 When the thickness is below 30 nm, while the doping layer 314 is irradiated with a laser, the doping layer 314 may fail to effectively absorb the laser, which causes damage to the second protective-film layer 202 , which is thin. On the other hand, when the thickness is above 50 nm, the doping layer 314 may excessively absorb the laser, and thus the dopant may not be effectively introduced into the second semiconductor layer 302 .
  • amorphous silicon has a high coefficient of absorption of light, as is well known, and thus is capable of reducing the strength of light by absorbing light penetrating the layer.
  • the dopant included in the doping layer 314 is selectively introduced into the second semiconductor layer 302 by the laser. At this time, because the doping layer 314 configured as an amorphous semiconductor layer is irradiated with the laser, damage to the second protective-film layer 202 , which is present beneath the second semiconductor layer 302 and is thin, may be prevented.
  • the doping layer 314 may be formed via a deposition method that enables cross-sectional deposition, such as Plasma Enhanced Chemical Vapor Deposition (PECVD), because the doping layer 314 is an amorphous semiconductor layer containing the dopant and is formed only on the back surface of the semiconductor substrate 10 .
  • PECVD Plasma Enhanced Chemical Vapor Deposition
  • a mixture of silane gas, B 2 H 6 gas containing the dopant, or BCI3 is used as source gas, the processing temperature is maintained within a range from 200° C. to 300° C., and the processing pressure is maintained within a range from 1 Torr to 4 Torr.
  • the doping layer 314 may be an oxide film containing the dopant, which is selectively formed of boron silicate glass (BSG) or phosphor silicate glass (PSG).
  • BSG boron silicate glass
  • PSG phosphor silicate glass
  • the oxide film may also be formed over the second semiconductor layer 302 via a PECVD method, a mixture of oxygen gas, silane gas, B 2 H 6 gas containing the dopant, or BCI3 gas may be used as source gas, the processing temperature is maintained within a range from 200° C. to 300° C., and the processing pressure is maintained within a range from 1 Torr to 4 Torr.
  • a laser scanning method may also be adjusted based on the properties of the film by reducing the energy of a laser compared to the instance where the amorphous semiconductor layer is used as the doping layer, or by adjusting the pulse width of the laser.
  • FIG. 4D diagrammatically illustrates the first conductive area forming operation S 104 .
  • the first conductive area 32 is formed by selectively irradiating the doping layer 314 with a laser. As illustrated in FIG. 4D , the entire doping layer 314 is not irradiated with the laser, but only a portion of the doping layer 314 , which has a first width S 1 corresponding to the first conductive area 32 , is selectively irradiated with the laser so that the remaining portion of the doping layer 314 , which has a second width S 2 , is not irradiated with the laser. In the doping layer 314 irradiated with the laser, the dopant included in the doping layer 314 thermally diffuses into the second semiconductor layer 302 , whereby the first conductive area 32 is formed. Then, the doping layer 314 irradiated with the laser is removed.
  • the first conductive area 32 is formed using the laser as described above, for example, a process of masking the doping layer 314 in order to selectively introduce the dopant included in the doping layer 314 into the second semiconductor layer 302 may be omitted, which may simplify the manufacturing process and may reduce manufacturing costs.
  • the semiconductor substrate 10 forms a pn junction with the first conductive area 32 with the second protective-film layer 202 interposed therebetween.
  • the concentration of the dopant in the first conductive area 32 ranges from 1 ⁇ 10 20 /cm 3 to 1 ⁇ 10 22 /cm 3 , and is substantially the same as the concentration of the dopant in the doping layer 314 .
  • FIG. 5 illustrates the first conductive areas 32 formed on the semiconductor substrate 10 .
  • the first conductive areas 32 have a line width Wa within a range from 500 ⁇ m to 700 ⁇ m.
  • the first conductive areas 32 extend a long length along the y-axis of FIG. 5 , and the respective neighboring first conductive areas 32 are spaced apart from each other by a constant distance Wb. As such, the first conductive areas 32 generally form a striped arrangement.
  • the first conductive areas 32 having the form of stripes, as illustrated in FIG. 5 may be formed one by one by directly irradiating the doping layer 314 with a laser in a laser progress direction, i.e. along the y-axis of FIG. 5 , which is the longitudinal direction of the first conductive areas 32 .
  • the first conductive areas 32 may be formed at the same time by irradiating the entire doping layer 314 with a laser.
  • the laser may use a pulse-type laser illustrated in FIG. 6 , and may have an energy of 0.5 J/cm 2 to 2.5 J/cm 2 , a frequency of 10 KHz to 100 KHz, a pulse width of 80 ns to 100 ns (nanoseconds), and a wavelength of 350 nm to 600 nm.
  • FIG. 6 illustrates the oscillation of a pulse-type laser with respect to a time axis.
  • the pulse-type laser is discontinuously emitted with respect to the time axis, and the pulse width for each laser shot ranges from 80 ns to 100 ns.
  • the distribution of energy for each laser shot has the shape of a top hat so that it forms steep slopes at the beginning and the end of the shot and is constant throughout the remaining portion.
  • FIG. 7 illustrates the coefficient of absorption depending on the wavelength of a laser.
  • the x-axis of the graph represents the wavelength of a laser
  • the y-axis represents the coefficient of absorption of a laser. It can be seen that a laser is absorbed by amorphous silicon and a great amount of laser is absorbed near wavelengths from 350 nm to 600 nm, which are used in this step.
  • the power of the laser may be calculated by multiplying the value of energy for each unit of time by the pulse width of the laser.
  • the power of the laser may be adjusted by adjusting its pulse width.
  • the doping layer 314 formed of amorphous silicon is irradiated with a laser having an adjusted pulse width, in order to uniformly thermally diffuse the dopant included in the doping layer 314 into the semiconductor layer 302 and to prevent the protective-film layer, which is thin, from being damaged by the laser.
  • an area scanned by a single laser oscillation (hereinafter referred to as a shot) may be defined as a spot.
  • the spot of the pulse-type laser has a square shape.
  • FIG. 8 illustrates the distribution of energy in the spot with respect to the horizontal axis and the vertical axis.
  • the distribution of energy of a laser has the shape of a top hat with respect to each of the horizontal axis and the vertical axis.
  • the top hat is laterally symmetrical and forms steep slopes at opposite ends thereof, thereby generally showing a trapezoidal distribution, as illustrated.
  • FIG. 9 is a view illustrating a method for scanning the first conductive area using the spot that has the distribution of energy described above.
  • FIG. 9 although only a portion of the first conductive area 32 formed into a stripe shape is illustrated and, for convenience of description, only first to third spots SP 1 to SP 3 are exemplified, a greater number of spots may be used in practice in order to form the first conductive area 32 having a stripe shape.
  • the first conductive area 32 may be longitudinally scanned using a laser, which has a greater spot size than the first conductive area 32 , so that spots partially overlap each other.
  • the first spot SP 1 to the third spot SP 3 have a substantially square shape, which has a first width Tb corresponding to a horizontal width and a second width Ta corresponding to a vertical width.
  • the first to third spots SP 1 to SP 3 are named using ordinal numbers based on the temporal sequence of laser oscillations.
  • the first spot SP 1 is made by a laser oscillation that precedes the second and third spots SP 2 and SP 3 , and then the second spot SP 2 and the third spot SP 3 are made in this sequence by laser oscillations.
  • the first spot SP 1 to the third spot SP 3 have a substantially square shape and have a length Ta along the vertical axis and a length Tb along the horizontal axis.
  • laser scanning is performed in the same direction as the longitudinal direction of the first conductive area 32 (along the y-axis of FIG. 9 ), and the first spot SP 1 to the third spot SP 3 are formed along the longitudinal direction of the second conductive area 32 so as to correspond to the scan direction.
  • the first spot SP 1 and the second spot SP 2 partially overlap each other to form an overlapping area Mo
  • the second spot SP 2 and the third spot SP 3 partially overlap each other to form another overlapping area Mo.
  • the width of the overlapping area Mo may range from 5 ⁇ m to 15 ⁇ m in consideration of the distribution of energy having steep slopes at opposite ends thereof.
  • the ratio of the horizontal width of the overlapping area Mo to the horizontal width Tb ranges from 1/182 to 1/110.
  • FIG. 10 illustrates the distribution of energy in the first spot SP 1 to the third spot SP 3 with respect to the horizontal axis.
  • the sloping portion of the first spot SP 1 and the sloping portion of the second spot SP 2 overlap each other, and the sloping portion of the second spot SP 2 and the sloping portion of the third spot SP 3 overlap each other.
  • the energy of a laser corresponds to the integral value of the two overlapped spots, which may be the same as the energy of the remaining area. Accordingly, these spots may generally have constant energy.
  • each spot does not overlap the first conductive area 32 on opposite portions thereof in the width direction by lengths La and Lb.
  • the distribution of energy of the spot also has the shape of a top hat in the vertical direction
  • the vertical width Ta of the spot SP matches the width Wa of the first conductive area 32 with a ratio of 1:1
  • variation in energy occurs due to the sloping portions at opposite edges of the spot.
  • the concentration of the dopant may vary depending on variation in energy. Therefore, it is necessary to correct such variation in energy.
  • the vertical width Ta of the first to third spots SP 1 to SP 3 is greater than 1.1 times, but is less than 1.3 times the first width Wa of the first conductive area 32 , in consideration of the distribution of energy. Because the width Wa of the first conductive area 32 ranges from 500 ⁇ m to 700 ⁇ m, the vertical width Ta of the spot SP ranges from 550 ⁇ m to 910 ⁇ m.
  • FIG. 11 illustrates a dopant concentration profile depending on a thickness when the semiconductor layer 302 is doped with a dopant via the method described above.
  • the thickness is described as increasing closer to the second protective-film layer.
  • the solid line represents the instance where laser scanning is performed via the above-described method (Experimental Example), and the dotted line represents the instance where the first conductive area is formed via thermal diffusion as in the related art (Comparative Example).
  • Boron (B) was used as the dopant, and the dopant was introduced so as to increase the thickness.
  • the graph may be divided into a section A and a section B depending on variation in concentration profile.
  • both Experimental Example and Comparative Example have a shape in which the doping concentration of the dopant descends to the lowest point and then ascends. That is, both Experimental Example and Comparative Example have the same concentration profile during the section A.
  • both Experimental Example and Comparative Example have a shape in which, as the thickness increases, the doping concentration of the dopant gradually descends after reaching the highest point.
  • the highest point of Experimental Example is higher than the highest point of Comparative Example, and the gradient of descent of Experimental Example is more gentle than the gradient of descent of Comparative Example.
  • the dopant is doped at a higher concentration in Experimental Example than in Comparative Example, and is more uniformly doped in Experimental Example than in Comparative Example.
  • FIG. 12 illustrates the instance where the distribution of energy in the spot has substantially the shape of a complete rectangle, unlike the above description.
  • a spot SP′ has the shape of a square, of which the vertical width Ta has a first length and the horizontal width Tb has a second length, in the same manner as the above description.
  • the distribution of energy of a laser has the shape of a complete square having the same length along the vertical axis and the horizontal axis, and thus the value of energy in the spot is constant regardless of a distance.
  • the vertical width Ta of the spot SP′ is the same as the width Wa of the first conductive area 32 , and neighboring spots SP′ are close to each other, but do not overlap each other in the horizontal direction.
  • FIG. 13 is a view illustrating the crystalline structure of the first conductive area 32 after operation S 104 ends
  • FIG. 14 is a TEM photograph illustrating re-crystallization occurring in the semiconductor layer.
  • FIG. 14 (a) illustrates the cross section of a crystalline semiconductor layer and a doping layer formed of amorphous silicon on the crystalline semiconductor layer before laser irradiation, and (b) illustrates the cross section of the semiconductor layer that has undergone re-crystallization.
  • the black layer beneath the semiconductor layer is the semiconductor substrate.
  • the first conductive area 32 includes the second polycrystalline area 321 , which has a crystalline structure different from the crystalline structure of the semiconductor layer 302 .
  • the second polycrystalline area 321 is formed as the semiconductor layer 302 is melted and re-crystallized by laser ablation when the doping layer 314 is irradiated with the laser.
  • the second polycrystalline area 321 has a crystalline structure different from the crystalline structure of the semiconductor layer 302 .
  • the grains in the second polycrystalline area 321 have better crystallinity than the crystalline semiconductor layer 302 .
  • Crystallinity is a concept including the size of grains and defects, and may be said to be good when the size of grains increases and the number of defects decreases.
  • the semiconductor layer 302 When the semiconductor layer 302 is irradiated with a laser, ablation occurs. In this process, because defects included in the grains are removed and the density of grains increases as the size of grains increases during re-crystallization, the crystallinity of the second polycrystalline area 321 becomes better than that of the semiconductor layer 302 .
  • the first conductive area 32 includes the second polycrystalline area 321 as described above, resistance against the movement of carriers through the first conductive area 32 is reduced, which may increase the efficiency of collection of carriers, and consequently the efficiency of the solar cell 100 .
  • the second polycrystalline area 321 is formed in the depth direction from the surface of the semiconductor layer 302 toward the protective-film layer 20 .
  • the laser introduced into the doping layer 314 is not so strong that it melts the entire first conductive area 32 because some of the laser is absorbed by the semiconductor layer 302 and the pulse width of the laser has been adjusted.
  • the depth DT 1 of the second polycrystalline area 321 is smaller than the thickness of the semiconductor layer 302 .
  • the depth DT 1 may be greater than half, but less than the thickness of the semiconductor layer 302 .
  • the power of the laser is insufficient for thermally diffusing the dopant in the first conductive area 32
  • the depth DT 1 of the second polycrystalline area 321 is equal to the thickness of the semiconductor layer 302
  • the power of the laser is excessively large, causing damage to the second protective-film layer 202 .
  • the cross-sectional area of the second polycrystalline area 321 is half or more of the cross-sectional area of the first conductive area 32 .
  • the second polycrystalline area 321 has a substantially U-shaped cross-section, and the depth DT 1 thereof is greater than half the thickness of the semiconductor layer 302 .
  • the cross-sectional area of the second polycrystalline area 321 may be half or more of the cross-sectional area of the first conductive area 32 .
  • the width DR 1 of the second polycrystalline area 321 corresponds to the width of a laser irradiation area, i.e. the first conductive area 32
  • the width DR 1 is substantially the same as the width of the first conductive area 32 within a range from 500 ⁇ m to 700 ⁇ m.
  • a residual doping layer 314 a over the second semiconductor layer 302 is removed.
  • the residual doping layer 314 a may have a shape in which openings are formed in local portions of the doping layer 314 .
  • a portion of the first protective-film layer 201 and the first semiconductor layer 301 thereon, which are sequentially formed on the front surface of the semiconductor substrate 10 may be selectively removed.
  • dry etching such as Reactive Ion Etching (RIE)
  • “Dipping” is an etching method of immersing the entire semiconductor substrate 10 in a tub in which an etchant is stored. When removing the residual doping layer 314 a by dipping the same in the etchant, a portion of the semiconductor layer 301 formed on the front surface of the semiconductor substrate 10 may be removed at the same time, and the semiconductor layer 302 may also be etched by over-etching, attributable to the reactivity of the etchant.
  • FIG. 4E diagrammatically illustrates wet etching in which the residual doping layer 314 a is removed by dipping.
  • the thickness of the residual doping layer 314 a ranges from 30 nm to 50 nm, whereas the thickness of the first semiconductor layer 301 formed on the front surface of the semiconductor substrate 10 ranges from 300 nm to 400 nm. Therefore, even if the etching rates of the residual doping layer 314 a and the first semiconductor layer 301 differ from each other, the first semiconductor layer 301 is not completely removed, and thus a portion of the first semiconductor layer 301 remains while the residual doping layer 314 a is completely removed.
  • the semiconductor substrate 10 when the semiconductor substrate 10 is dipped into the etchant, the residual doping layer 314 a and the first conductive area 32 therebetween are exposed to the etchant.
  • the first conductive area 32 is also exposed to the etchant while the residual doping layer 314 a is completely removed, the first conductive area 32 , into which the dopant has been introduced, is in a stably coupled state, and thus serves as an etch stopper.
  • the first conductive area 32 has a first thickness t 1
  • an undoped area 33 from which the residual doping layer 314 a has been removed, has a second thickness t 2 , which is smaller than the first thickness t 1 due to over-etching.
  • FIG. 16 illustrates a difference in thickness between the first conductive area 32 and the area 33 , from which the residual doping layer 314 a has been removed, after the residual doping layer 314 a is removed via dry etching.
  • the first conductive area 32 has a third thickness t 3
  • the undoped area 33 has a fourth thickness t 4 , which is greater than the third thickness t 3 .
  • the difference between the third thickness t 3 and the fourth thickness t 4 is substantially the same as the thickness of the residual doping layer 314 a.
  • Dry etching physically removes the film, and thus exhibits substantially the same etching rate regardless of materials. Therefore, because the first conductive area 32 is also etched simultaneously with the dry etching of the residual doping layer 314 a , the difference between the third thickness t 3 and the fourth thickness t 4 is substantially the same as the thickness of the residual doping layer 314 a.
  • the semiconductor substrate 10 is dipped into an etchant so that the first semiconductor layer 301 , formed on the front surface of the semiconductor substrate 10 , and the first protective-film layer 201 thereunder, are completely removed, and simultaneously, the exposed front surface of the semiconductor substrate 10 is also etched, whereby the front surface of the semiconductor substrate 10 is textured.
  • FIG. 4F diagrammatically illustrates this step.
  • the mask layer 315 is formed over the entire surface of the second semiconductor layer 302 so as to protect the second semiconductor layer 302 while the front surface of the semiconductor substrate 10 is textured.
  • the mask layer 315 prevents a dopant from being introduced into the first conductive area 32 when the dopant is introduced into the undoped area 33 in order to form a second conductive area in the subsequent process.
  • the mask layer 315 may be formed of a material that includes no foreign substance, which serves as a dopant. That is, the mask layer 315 may be formed of any of various materials capable of preventing the introduction of the foreign substance.
  • the mask layer 315 is a silicon carbide (SiC) film that effectively blocks the introduction of a dopant, and has a thickness within a range from 100 nm to 200 nm.
  • the silicon carbide film is easily removed by laser ablation, and is easily removed using a dilute hydrofluoric acid (HF) solution because it is changed to an oxide in the subsequent operation S 108 . This will be described below in detail with regard to the corresponding operation S 108 .
  • HF dilute hydrofluoric acid
  • the mask layer 315 is only formed over the second semiconductor layer 302 , and is not formed on the textured surface, i.e. the front surface of the semiconductor substrate 10 .
  • the mask layer 315 may be formed via any of various methods that enable cross-sectional deposition.
  • the mask layer 315 may be formed via a PECVD method that enables cross-sectional deposition.
  • the surface of the semiconductor substrate 10 may be effectively textured.
  • KOH+ is shown, unlike FIG. 4E .
  • openings 315 a are formed in the mask layer 315 so as to expose an area of the semiconductor layer 302 (i.e. the undoped area 33 ) in which the first conductive area 32 has not been formed.
  • FIG. 4G diagrammatically illustrates the mask layer patterning step.
  • the openings 315 a are formed by selectively irradiating the mask layer 315 with a laser so that a portion of the mask layer 315 is subjected to laser ablation.
  • the laser is a pulse-type laser, of which the pulse width is adjusted, and has an energy of 0.5 J/cm 2 to 2.5 J/cm 2 , a frequency of 10 KHz to 100 KHz, a pulse width of 160 ns to 200 ns (nanoseconds), and a wavelength of 350 nm to 600 nm.
  • the pulse-type laser meeting these conditions is the same as the laser used in the above-described first conductive area forming operation S 104 , but has a great difference only in terms of the pulse width.
  • the laser facility used in the above first conductive area forming operation S 104 may also be used in this step, which may reduce manufacturing costs and may simplify the process.
  • FIGS. 17 and 18 illustrate a laser scanning method in operation S 107 .
  • the laser scanning method may be substantially the same as that used in the above operation S 104 , the only difference being that the pulse width of the laser is reduced.
  • the opening 315 a is elongated in the longitudinal direction of the undoped area 33 (along the y-axis of FIG. 17 ) so as to expose the undoped area 33 in the longitudinal direction thereof.
  • the opening 315 a is formed just above the undoped area 33 so as to expose the undoped area 33 in the longitudinal direction thereof.
  • the respective neighboring openings 315 a are spaced apart from each other by a constant distance so as to generally form a striped arrangement.
  • FIG. 18 illustrates a laser scanning method of forming the openings.
  • FIG. 18 only three spots are illustrated for convenience of description, and the distribution of energy in the spot has a top hat shape in the same manner as FIG. 7 .
  • a spot SA has a substantially square shape having a first length Na along the horizontal axis and a second length Nb along the vertical axis.
  • the first length Na is greater than the width S 1 of the opening 315 a and is less than the width S 2 of the undoped area 33 in consideration of the distribution of energy.
  • the first conductive area 32 may be exposed through the opening 315 a .
  • shunts between the first conductive area 32 and the second conductive area 34 may occur.
  • the first to third spots SA 1 to SA 3 partially overlap the neighboring spots to form overlapping areas Mr in consideration of the distribution of energy.
  • the width of the overlapping area Mr ranges from 5 ⁇ m to 15 ⁇ m in consideration of the distribution of energy.
  • the distribution of the energy of the laser has been described above as having a top hat shape.
  • the first length Nb is substantially the same as the width S 1 of the opening 315 a.
  • the opening 315 a may be accurately formed at a desired position, and the number of processes may be reduced.
  • the width S 1 of the opening 315 a is less than the width S 2 of the undoped area 33 .
  • the width S 1 of the opening 315 a is less than the width S 2 of the undoped area 33 , a portion of the undoped area 33 , i.e. opposite edges of the undoped area 33 are not exposed, but are covered with the mask layer 315 . Therefore, when the dopant is introduced into the undoped area 33 in the subsequent step, no doping occurs in the covered portion for forming the barrier area 33 , which is formed of an intrinsic semiconductor layer.
  • the barrier area 33 is located between the first conductive area 32 and the second conductive area 34 and prevents shunts between the first conductive area 32 and the second conductive area 34 , which are of different conductive types.
  • FIG. 19 is a cross-sectional view illustrating the crystalline structure of the second conductive area after the mask layer patterning operation S 107 ends.
  • the second conductive area 34 includes the fourth polycrystalline area 341 , which has a crystalline structure different from that of the remaining area of the second conductive area 34 .
  • the grains in the fourth polycrystalline area 341 have better crystallinity than the unchanged crystalline structure of the barrier area 33 , and thus have few defects and are larger and more dense.
  • the semiconductor layer 302 When the semiconductor layer 302 is irradiated with a laser, ablation occurs. In this process, because defects included in the grains are removed and the grains are increased in volume and density during re-crystallization, the crystallinity of the fourth polycrystalline area 341 becomes better than that of the semiconductor layer 302 .
  • the laser used when the second polycrystalline area 321 is formed and the laser used when the fourth polycrystalline area 341 is formed differ from each other only in terms of the pulse width thereof, and have substantially the same energy. Therefore, because the crystallinity of the fourth polycrystalline area 341 is substantially the same as that of the second polycrystalline area 321 , the crystalline structure of the fourth polycrystalline area 341 is substantially the same as the crystalline structure of the second polycrystalline area 321 .
  • a laser is selectively absorbed by amorphous silicon depending on the wavelength thereof as illustrated in FIG. 7 , no laser within a wavelength range of 350 nm or more is absorbed by a silicon carbide.
  • the mask layer 315 formed of a silicon carbide is irradiated with a laser
  • the laser directly penetrates the mask layer 315 , melting the semiconductor layer 302 .
  • the fourth polycrystalline area 341 is formed in the depth direction from the surface of the semiconductor layer 302 to the protective-film layer 202 .
  • the depth DT 2 of the fourth polycrystalline area 341 is greater than the depth DT 1 of the second polycrystalline area 321 .
  • the ratio of the cross-sectional area of the fourth polycrystalline area 341 to the cross-sectional area of the second conductive area 34 is 0.5:1 or more, and is greater than the ratio of the cross-sectional area of the second polycrystalline area 321 to the cross-sectional area of the first conductive area 32 .
  • the fourth polycrystalline area 341 which has better crystallinity than the semiconductor layer 302 , is widely formed in the second conductive area 34 , carriers may effectively move in the second conductive area 34 , which may further increase the efficiency with which the solar cell 100 generates power.
  • the width DR 2 of the fourth polycrystalline area 341 corresponds to the width of the area irradiated with a laser, i.e. the opening 315 a , and is substantially within a range from 205 ⁇ m to 350 ⁇ m, which is the same as the width of the second conductive area 34 .
  • the width DR 2 of the fourth polycrystalline area 341 is less than the width DR 1 of the second polycrystalline area 321 .
  • the width DR 2 of the fourth polycrystalline area 341 may be half the width of the second polycrystalline area 321 .
  • a dopant is introduced into the front surface of the semiconductor substrate 10 to form the front-surface field area 130 and is also introduced into the undoped area 33 on the back surface, which is exposed through the opening 315 a , to form the second conductive area 34 .
  • FIG. 4H diagrammatically illustrates this step.
  • the dopant is the first conductive dopant, which is the same as that used in the semiconductor substrate 10 .
  • the first conductive dopant is an n-type dopant including a group-V element, such as phosphorus (P), arsenic (As), bismuth (Bi), or antimony (Sb).
  • the first conductive dopant is a p-type dopant including a group-III element, such as boron (B), aluminum (Al), gallium (Ga), or indium (In).
  • the second conductive area 34 and the front-surface field area 130 may be formed at the same time by thermally diffusing the first conductive dopant in a gas atmosphere including the first conductive dopant.
  • a gas atmosphere including the first conductive dopant Any of various gases including the first conductive dopant may be used as the gas atmosphere.
  • the first conductive dopant is an n-type, phosphoryl chloride (POCl 3 ) is used.
  • the first conductive dopant thermally diffuses from the back surface of the semiconductor substrate 10 to the undoped area 33 through the opening 315 a whereby the second conductive area 34 is formed, and the first conductive area 32 is protected by the mask layer 315 .
  • the undoped area 33 between the first conductive area 32 and the second conductive area 34 is masked by the mask layer 315 while the dopant is introduced, no dopant is introduced into the undoped area 33 , whereby the barrier area 33 is formed as an intrinsic semiconductor layer.
  • the doping concentration of the second conductive area 34 is the same as that of the first conductive area 32 .
  • the first conductive dopant which is of the same conductive type as the dopant introduced into the semiconductor substrate 10 , is introduced into the front surface of the semiconductor substrate 10 , whereby the front-surface field area 130 is formed.
  • the doping concentration of the front-surface field area 130 ranges from 1 ⁇ 10 17 /cm 3 to 1 ⁇ 10 20 /cm 3 , which is lower than that of the second conductive area 34 .
  • the semiconductor substrate 10 on which the front-surface field area 130 has been formed, is a monocrystalline semiconductor layer
  • the second semiconductor layer 302 on which the second conductive area 34 has been formed, is a crystalline semiconductor layer.
  • the semiconductor substrate 10 and the second semiconductor layer 302 have different doping concentrations.
  • the second conductive area 34 and the front-surface field area 130 may be formed separately.
  • the front surface of the semiconductor substrate 10 may be protected by a protective film.
  • the protective film may be removed, and a second conductive dopant may be introduced only into the front surface of the semiconductor substrate 110 so as to sequentially form the front-surface field area 130 .
  • cross-sectional doping may be easily performed, and for example, the doping depth and the doping profile of the front-surface field area 130 may be easily controlled.
  • a front-surface field area 130 having desired properties may be formed.
  • the mask layer formed of a silicon carbide (SiC) or the amorphous silicon dopant layer used in operation S 108 may be wet-etched by an etchant (e.g. KOH).
  • an etchant e.g. KOH.
  • the n-type (e.g. phosphor) conductive area having higher reactivity is etched at the highest rate
  • the p-type (e.g. boron) conductive area, having lower reactivity is etched at the lowest rate
  • the barrier area may have a thickness between those of the n-type and p-type conductive areas.
  • FIGS. 4I and 4J diagrammatically illustrate this step.
  • the front insulation film 24 and the anti-reflection film 26 are sequentially formed over the front-surface field area 130 on the front surface of the semiconductor substrate 10 , and the insulation film 40 formed of an insulation material is formed over the second semiconductor layer 302 on the back surface of the semiconductor substrate 10 .
  • the insulation material may be a thin film formed of a silicon oxide (SiOx), a silicon nitride (SiNx), a silicon oxide nitride (SiNxOy), or a silicon carbide (SiC).
  • SiOx silicon oxide
  • SiNx silicon nitride
  • SiNxOy silicon oxide nitride
  • SiC silicon carbide
  • the insulation films may be formed via any of various methods, such as, for example, vacuum deposition, chemical vapor deposition, spin coating, screen printing, or spray coating.
  • the insulation films may be formed via a PECVD method that enables cross-sectional deposition.
  • the insulation film 24 and the anti-reflection film 26 may be formed using different source gases within the same chamber via an in-situ process.
  • a PECVD method may be used to form the insulation film 40 on only the back surface.
  • the process of forming the front insulation film 24 and the anti-reflection film 26 and the process of forming the insulation film 40 may be an in-situ process.
  • the insulation films have been described as being first formed on the front surface of the semiconductor substrate 10 , and then being formed to cover the back surface of the semiconductor substrate 10 .
  • the exposure of the first conductive area 32 and the second conductive area 34 to heat is minimized, deterioration in properties or damage may be prevented to the maximum extent.
  • FIGS. 4K to 4M diagrammatically illustrate the electrode forming operation S 110 .
  • a first opening 40 a formed in the insulation film 40 exposes a portion of the first conductive area 32 and a second opening 40 b formed in the insulation film 40 exposes a portion of the second conductive area 34 .
  • the widths of the first and second openings 40 a and 40 b formed in the insulation film 40 may be less than the width of the opening 315 a formed in the mask layer 315 .
  • Each of the first opening 40 a and the second opening 40 b may take the form of a slit, which is elongated in the longitudinal direction of the first conductive area 32 or the second conductive area 34 . In this instance, the first opening 40 a and the second opening 40 b are alternately arranged to form a striped arrangement.
  • the first opening 40 a and the second opening 40 b are formed via laser ablation.
  • a laser used in operation S 110 may have a frequency of 400 KHz and a power of 0.5 watts to 2 watts so as to be suitable for the openings 40 a and 40 b having a width within a range from 15 ⁇ m to 30 ⁇ m, and also may have a pico-second (ps) pulse width in consideration of the fact that the width of the openings 40 a and 40 b ranges from 10 ⁇ m to 20 ⁇ m, in order to facilitate laser ablation.
  • ps pico-second
  • FIG. 20 is a cross-sectional view illustrating the crystalline structure of the semiconductor layer when the openings 40 a and 40 b are formed using a laser.
  • the openings 40 a and 40 b which expose the first conductive area 32 and the second conductive area 34 , are formed via laser ablation, and the second crystalline areas 321 and 341 thereunder are melted and re-crystallized, whereby the fifth polycrystalline area 321 a is formed in the second polycrystalline area 321 and the sixth polycrystalline area 341 a is formed in the fourth polycrystalline area 341 .
  • the crystalline structure of the third crystalline areas 321 a and 341 a has lower crystallinity than the crystalline structure of the second crystalline areas 321 and 341 .
  • the third crystalline areas 321 a and 341 a are formed using a pico-second (ps) scale laser, having an extremely short laser irradiation time, a re-crystallization time is reduced compared to the second crystalline areas 321 and 341 , which are formed using a nano-second (ns) scale laser, and thus the third crystalline areas 321 a and 341 a have reduced crystallinity.
  • the grains in the third crystalline areas 321 a and 341 a are smaller than the grains in the second crystalline areas 321 and 341 .
  • the third crystalline areas 321 a and 341 a are formed in the depth direction from the surface of the semiconductor layer 302 to the protective-film layer 202 .
  • the depth of the third crystalline areas 321 a and 341 a is tens of nanometers, which is much smaller than that of the second crystalline areas 321 and 341 , and the width of the third crystalline areas 321 a and 341 a is substantially the same as the width of the openings 40 a and 40 b.
  • the electrodes 42 and 44 are respectively connected to the first conductive area 32 and the second conductive area 34 through the openings 40 a and 40 b , the electrodes 42 and 44 are substantially in contact with the third crystalline areas 321 a and 341 a .
  • the third crystalline areas 321 a and 341 a may have convex-concave portions on the surface thereof, and the surfaces of the first electrode 42 and the second electrode 44 , which are in contact with the third crystalline areas 321 a and 341 a , may have a multilayered structure including two or more layers, and may include convex-concave portions corresponding to the convex-concave portions on the surfaces of the third crystalline areas 321 a and 341 a.
  • the first conductive area 32 and the second conductive area 34 are formed using a laser, and the first conductive area 32 and the second conductive area 34 having a crystalline structure are re-crystallized to achieve improved crystallinity, which improves the efficiency of the solar cell 100 .
  • the openings 40 a and 40 b may be formed via any of various methods, such as, for example, dry etching or wet etching.
  • An electrode layer 400 is formed over the entire insulation film 40 so that the first opening 40 a and the second opening 40 b are filled with the electrode layer 400 . Because the electrode layer 400 needs to be brought into contact with the first conductive area 32 through the first opening 40 a , and also needs to be brought into contact with the second conductive area 34 through the second opening 40 b , the electrode layer 400 is formed of a conductive material.
  • the electrode layer 400 may be formed using paste including aluminum (Al), or may be formed using a multilayered metal via a sputtering method.
  • the electrode layer 400 may be formed via, for example, plating, deposition, or sputtering. In an example form, paste including aluminum may be applied to the insulation film 40 .
  • the electrode layer 400 is patterned so as to be brought into contact with the first conductive area 32 and the second conductive area 34 .
  • the patterning may be performed via various known methods.
  • the first and second electrodes 42 and 44 are formed using a laser firing contact technique. In this instance, because the first and second electrodes 42 and 44 are formed when the first and second electrodes 42 and 44 are formed, and thus no process of forming the first and second openings 40 a and 40 b is required.
  • FIG. 21 is a cross-sectional view illustrating a solar cell according to an embodiment of the present invention
  • FIG. 22 is a partial rear plan view of the solar cell illustrated in FIG. 21 .
  • the solar cell according to the present embodiment is substantially similar to the solar cell described above with reference to FIG. 1 . Thus, a repeated description thereof may be omitted.
  • the solar cell 100 includes the semiconductor substrate 10 , the first conductive area 32 formed over the semiconductor substrate 10 and configured as a semiconductor layer of a first conductive type, the second conductive area 34 of a second conductive type, which is opposite to the first conductive type, the insulation film 40 disposed over the first conductive area 32 and having a first contact hole 461 , the first electrode 42 electrically connected to the first conductive area 32 through the first contact hole 461 , and the second electrode 44 electrically connected to the second conductive area 34 .
  • the first conductive area 32 includes a first portion 321 including the portion in which the first contact hole 461 is formed, and a second portion 322 located in the area excluding the first portion 321 .
  • the first portion 321 has larger surface roughness than the second portion 322 , and the crystallinity of the first portion 321 may differ from the crystallinity of the second portion 322 .
  • the solar cell 100 may further include, for example, the front insulation film 24 and the anti-reflection film 26 , which are disposed over the front surface of the semiconductor substrate 10 . This will be described below in more detail.
  • the semiconductor substrate 10 may include a base area 110 , which includes a first or second conductive dopant at a relatively low doping concentration, and thus is of a first or second conductive type.
  • the semiconductor substrate 10 may include the front-surface field area (or field area) 130 disposed on one surface (e.g. the front surface) of the semiconductor substrate 10 .
  • the front-surface field area 130 may be of the same conductive type as that of the base area 110 and may have a higher doping concentration than the base area 110 .
  • the protective-film layer 20 may be formed over the other surface (e.g. the back surface) of the semiconductor substrate 10 .
  • the protective-film layer 20 may be formed to be brought into contact with the back surface of the semiconductor substrate 10 , and thus may exhibit a simplified structure and improved tunneling effects.
  • the present invention is not limited thereto.
  • the semiconductor layer 30 including the conductive areas 32 and 34 may be disposed over the protective-film layer 20 .
  • the semiconductor layer 30 may be formed to be brought into contact with the protective-film layer 20 , and thus may exhibit a simplified structure and improved tunneling effects.
  • the present invention is not limited thereto.
  • the semiconductor layer 30 may include the first conductive area 32 , which includes a first conductive dopant and thus is of a first conductive type, and the second conductive area 34 , which includes a second conductive dopant and thus is of a second conductive type.
  • the first conductive area 32 and the second conductive area 34 may be located in the same plane over the protective-film layer 20 .
  • a barrier area 36 may be located between the first conductive area 32 and the second conductive area 34 in the same plane as the conductive areas 32 and 34 .
  • the first conductive area 32 may be formed of a semiconductor (e.g. silicon) including the first conductive dopant, the conductive type of which is opposite to that of the base area 110 .
  • the second conductive area 34 may include the same second conductive dopant as that of the base area 110 , but may have a higher doping concentration than the base area 110 .
  • the first and second conductive areas 32 and 34 are formed over the semiconductor substrate 10 (more accurately, over the protective-film layer 20 ) separately from the semiconductor substrate 10 , and are respectively configured as a semiconductor layer doped with the first or second conductive dopant.
  • the first and second conductive areas 32 and 34 may be configured as a semiconductor layer, which has a crystalline structure different from that of the semiconductor substrate 10 , in order to be easily formed on the semiconductor substrate 10 .
  • the first and second conductive areas 32 and 34 may be formed by doping, for example, an amorphous semiconductor layer, a microcrystalline semiconductor layer, or a polycrystalline semiconductor layer (e.g. amorphous silicon, microcrystalline silicon, or polycrystalline silicon), which may be easily manufactured via any of various methods, such as, for example, deposition, with the first or second conductive dopant.
  • the first and second conductive areas 32 and 34 may have thermal stability and excellent electrical properties.
  • the first or second conductive dopant may be introduced into the semiconductor layer while the semiconductor layer is formed, or after the semiconductor layer is formed, via any of various doping methods, such as thermal diffusion or ion implantation.
  • the barrier area 36 may be formed of, for example, an undoped insulation material (e.g. an oxide or a nitride). Alternatively, the barrier area 36 may be formed of an intrinsic semiconductor. At this time, the first conductive area 32 , the second conductive area 34 , and the barrier area 36 may be configured as the same semiconductor layer (e.g. an amorphous silicon, microcrystalline silicon, or polycrystalline silicon layer), which is continuously formed such that the side surfaces thereof come into contact with one another.
  • the barrier area 36 may be formed of an i-type (intrinsic) semiconductor material, which substantially includes no dopant.
  • an area of the semiconductor layer is doped with the first conductive dopant so as to form the first conductive area 32
  • another area of the semiconductor layer is doped with the second conductive dopant so as to form the second conductive area 34
  • the remaining area in which the first conductive area 32 and the second conductive area 34 are not formed may configure the barrier area 36 .
  • the method of manufacturing the first conductive area 32 , the second conductive area 34 , and the barrier area 36 may be simplified.
  • the barrier area 36 may be formed via any of various methods, so as to have any of various thicknesses and any of various shapes.
  • the barrier area 36 may take the form of a trench that is an empty space.
  • FIGS. 21 and 22 illustrate that the barrier area 36 causes the first conductive area 32 and the second conductive area 34 to be wholly spaced apart from each other.
  • the barrier area 36 may be formed to cause the first conductive area 32 and the second conductive area 34 to be spaced apart from each other only along a portion of the boundary therebetween.
  • no barrier area 36 may be formed so that the boundaries of the first conductive area 32 and the second conductive area 34 come into contact with each other.
  • the first conductive area 32 and/or the second conductive area 34 may include the first portion 321 and the second portion 322 , which differ from each other in surface roughness and crystallinity. This is because the surface roughness and the crystallinity vary when a contact hole 46 is formed in the insulation film 40 through a laser etching or ablation process. This will be described below in more detail.
  • the insulation film 40 may be formed over the first and second conductive areas 32 and 34 and the barrier area 36 on the back surface of the semiconductor substrate 10 .
  • the insulation film 40 may be formed to be brought into contact with the first and second conductive areas 32 and 34 and the barrier area 36 , and thus may have a simplified structure.
  • the present invention is not limited thereto.
  • the insulation film 40 includes the contact hole 46 for electrical connection between the conductive areas 32 and 34 and the electrodes 42 and 44 .
  • the contact hole 46 includes the first contact hole 461 for connection between the first conductive area 32 and the first electrode 42 , and a second contact hole 462 for connection between the second conductive area 34 and the second electrode 44 .
  • the insulation film 40 serves to prevent the first conductive area 32 and the second conductive area 34 from being connected to the wrong electrodes (i.e. the second electrode 44 in the instance of the first conductive area 32 and the first electrode 42 in the instance of the second conductive area 34 ).
  • the insulation film 40 may exert passivation effects of the first and second conductive areas 32 and 34 and/or the barrier area 36 .
  • the front insulation film 24 and/or the anti-reflection film 26 may be disposed over the front surface of the semiconductor substrate 10 (more accurately, over the front-surface field area 130 formed on the front surface of the semiconductor substrate 10 ).
  • the present invention is not limited thereto, and an insulation film having a different stacking structure may be formed over the front-surface field area 130 .
  • the front insulation film 24 and the anti-reflection film 26 may substantially be formed throughout the front surface of the semiconductor substrate 10 .
  • the insulation film 40 may be formed throughout the back surface of the semiconductor layer 30 excluding the contact hole 46 .
  • “formed throughout” includes not only physically complete formation, but also formation with inevitably excluded parts.
  • the first conductive area 32 and the second conductive area 34 extend a long length to form stripes and are alternately arranged in the direction crossing the longitudinal direction thereof.
  • the barrier area 36 may be located, as a spacer, between the first conductive area 32 and the second conductive area 34 .
  • a plurality of first conductive areas 32 which are spaced apart from one another, may be interconnected at one edge thereof, and a plurality of second conductive areas 34 , which are spaced apart from one another, may be interconnected at the other edge thereof.
  • the present invention is not limited thereto.
  • the first conductive area 32 may be wider than the second conductive area 34 .
  • the areas of the first conductive area 32 and the second conductive area 34 may be adjusted by providing the first and second conductive areas 32 and 34 with different widths. That is, the width W 1 of the first conductive area 32 may be greater than the width W 2 of the second conductive area 34 .
  • first electrode 42 may be formed in a stripe shape so as to correspond to the first conductive area 32
  • second electrode 44 may be formed in a stripe shape so as to correspond to the second conductive area 34 .
  • the present embodiment illustrates the instance where the first and second contact holes 461 and 462 are formed so as to connect only portions of the first and second electrodes 42 and 44 to the first conductive area 32 and the second conductive area 34 respectively. More specifically, a plurality of first contact holes 461 may be spaced apart from one another by a constant distance in the direction in which the first conductive area 32 extends, and a plurality of second contact holes 462 may be spaced apart from one another by a constant distance in the direction in which the second conductive area 34 extends. As such, the number or the total area of the first and second contact holes 461 and 462 may be reduced, which may minimize the time and cost of the process of forming the first and second contact holes 461 and 462 .
  • the first contact holes 461 may be formed so as to partially overlap each other, and the second contact holes 462 may be formed so as to partially overlap each other.
  • at least one of the first and second contact holes 461 and 462 may be elongated along the first and second conductive areas 32 and 34 so as to correspond to the entire first and second electrodes 42 and 44 .
  • the width W 3 of the electrodes 42 and 44 may be greater than the width W 4 of the contact hole 46 .
  • the first and second electrodes 42 and 44 may have a reduced resistance attributable to the sufficient width thereof, and alignment between the first and second conductive areas 32 and 34 and the first and second electrodes 42 and 44 may be improved.
  • the first conductive areas 32 which are spaced apart from one another, may be interconnected at one edge thereof, and the second conductive areas 34 , which are spaced apart from one another, may be interconnected at the other edge thereof.
  • the present invention is not limited thereto.
  • the contact hole 46 may be formed by irradiating a local portion of the insulation film 40 with a laser so that the insulation film 40 is evaporated in the corresponding portion.
  • the method of forming the contact hole 46 will be described later in more detail with reference to FIG. 23K .
  • the conductive areas 32 and 34 which are close to the insulation film 40 , undergo variation in properties.
  • the first conductive area 32 includes the first portion 321 , which includes the portion in which the first contact hole 461 is formed, and the second portion 322 , which constitutes the remaining area excluding the first portion 321 and has surface roughness and crystallinity different from those of the first portion 321 .
  • the first portion 321 may have the same or similar size as the first contact hole 461 (e.g. with an error of 10% or less) and may overlap the first contact hole 461 .
  • the second portion 322 may be the remaining portion excluding the first portion 321 .
  • the first portion 321 has larger surface roughness than the second portion 322 .
  • the first contact hole 461 is formed using a laser, heat is transferred to the first conductive area 32 .
  • the portion of the first conductive area 32 that is melted and re-crystallized by the heat constitutes the first portion 321 .
  • the first portion 321 has greater surface curvature, and consequently larger surface roughness than the second portion 322 .
  • the first portion 321 has crystallinity different from that of the second portion 322 because it is also affected by the laser when the first contact hole 461 is formed, and thus is re-crystallized under conditions different from those for the second portion 322 . More specifically, the crystallinity of the second portion 322 may be lower than the crystallinity of the first portion 321 .
  • the first portion 321 may include a polycrystalline semiconductor, and the degree of crystallization of the first portion 321 may be lower than that of the second portion 322 . As such, the mobility of carriers may be maintained at a high value throughout the entire first conductive area 32 .
  • the present invention is not limited thereto.
  • the second portion 322 may include a polycrystalline semiconductor, and the first portion 321 may include a microcrystalline semiconductor or an amorphous semiconductor.
  • the first portion 321 may include an amorphous semiconductor.
  • the crystallinity of the first portion 321 may be similar to the crystallinity of the second portion 322 .
  • the insulation film 40 includes, for example, a nitride. Therefore, in order to form the first contact hole 461 , it is necessary to use a laser that is capable of etching or removing a layer including a nitride.
  • the laser for removing the layer including the nitride has a relatively small pulse width. With a laser having such a pulse width, however, a sufficient amount of energy required for crystallization may not be supplied to the first conductive area 32 .
  • the second portion 322 which is not affected by the formation of the first contact hole 461 , remains at a relatively high degree of crystallization, i.e.
  • the first portion 321 has a lower degree of crystallization, i.e. lower crystallinity than the second portion 322 .
  • the degree of crystallization of the first portion 321 may range from 50% to 70%, and the degree of crystallization of the second portion 322 may range from 85% to 98%.
  • the degree of crystallization of the second portion 322 is limited to the range within which the first conductive area 32 may exhibit excellent thermal stability and excellent electrical properties.
  • the degree of crystallization of the second portion 322 is below 85%, the first conductive area 32 may have difficulty in exhibiting excellent properties due to low mobility.
  • the degree of crystallization of the first portion 321 is limited to the range within which the first contact hole 461 is stably formed in the insulation film 40 without considerably deteriorating various properties, such as, for example, the mobility of carriers, of the first portion 321 .
  • various properties such as, for example, the mobility of carriers, of the first portion 321 .
  • the degree of crystallization of the first portion 321 is below 50%, the thermal stability and electrical properties of the corresponding portion may be deteriorated.
  • the pulse width of the laser used to form the first contact hole 461 needs to be increased. In this instance, for example, the nitride may not be easily removed, which may make it difficult to stably form the first contact hole 461 .
  • the degree of crystallization of the first portion 321 may be greater than the degree of crystallization of the second portion 322 by 5% or more (e.g. 10% or more). This difference ensures that the first portion 321 and the second portion 322 exert sufficient effects.
  • the present invention is not limited thereto.
  • the crystal grains in the first portion 321 may be smaller than the crystal grains in the second portion 322 . This is considered to be because the heat provided to the first portion 321 by a laser is not sufficient to realize crystallization, and thus crystal grains are not grown to a large size and are irregularly arranged.
  • the ratio of the size of crystal grains (e.g. the average size of crystal grains) in the first portion 321 to the size of crystal grains (e.g. the average size of crystal grains) in the second portion 322 may range from 10% to 50%.
  • the size of crystal grains in the first portion 321 may range from 10 nm to 1 ⁇ m.
  • the crystallinity of the first portion 321 may not be sufficient.
  • the pulse width of the laser used to form the first contact hole 461 is increased, which may make it difficult to stably form the first contact hole 461 .
  • the degree of crystallization of the first and second portions 321 and 322 may be measured or analyzed by various methods.
  • the degree of crystallization of the first and second portions 321 and 322 may indicate the percentage of a crystalline structure in the semiconductor layer 30 (e.g. a silicon semiconductor layer), and may be measured or analyzed using, for example, X-ray diffraction (XRD), electron backscatter diffraction (EBSD), or a RAMAN analyzer.
  • XRD X-ray diffraction
  • EBSD electron backscatter diffraction
  • RAMAN analyzer a RAMAN analyzer
  • the first portion 321 may have various properties different from those of the second portion 322 .
  • Microscopic shapes of the first portion 321 and the second portion 322 are schematically illustrated in the enlarged circle of FIG. 22 .
  • a saw damage mark SD 2 of the second portion 322 is seen to be deeper than a saw damage mark SD 1 of the first portion 321 .
  • the semiconductor substrate 10 is formed by cutting a semiconductor ingot, and at this time, the saw damage marks SD 1 and SD 2 remain on the semiconductor substrate 10 . Because the properties of a semiconductor device greatly depend on the properties of the semiconductor substrate, a very high-quality semiconductor substrate having no saw damage marks is used in the semiconductor device.
  • the semiconductor substrate 10 having the saw damage marks SD 1 and SD 2 may reduce costs.
  • the semiconductor substrate 10 of the solar cell 100 includes the saw damage marks SD 1 and SD 2 , because the portion of the first conductive area 32 that is melted and re-crystallized by a laser undergoes variation in crystallinity, the saw damage marks SD 1 and SD 2 are seen at different degrees.
  • the saw damage mark SD 2 may be clearly and deeply seen in the second portion 322 , which has relatively high or excellent crystallinity, and the saw damage mark SD 1 may be seen to be blurry or may not be clearly visible in the first portion 321 , which has low crystallinity.
  • the portion of the solar cell 100 including the first portion 321 may be seen to be brighter than the portion including the second portion 322 . This is because the insulation film 40 is removed from the first portion 321 .
  • a first area A 1 which corresponds to a portion of the second portion 322 close to the first portion 321 or a portion of the insulation film 40 , may be seen to be brighter than a second area A 2 , which corresponds to the remaining portion of the second portion 322 or the insulation film 40 .
  • the first area A 1 may have a predetermined width and may be seen to be brighter than the second area A 2 . This is considered to be because the insulation film 40 close to the first contact hole 461 undergoes variation in thickness or properties when the first contact hole 461 is formed, whereby the corresponding portion is seen to be brighter than the remaining portion.
  • the second conductive area 34 includes a first portion 341 including the portion in which the second contact hole 462 is formed, and a second portion 342 located in the area excluding the first portion 341 .
  • the description of the first contact hole 461 , the first portion 321 and the second portion 322 of the first conductive area 32 may be applied to the second contact hole 462 , the first portion 341 and the second portion 342 of the second conductive area 34 , and thus a detailed description of the second contact hole 462 , the first portion 341 and the second portion 342 of the second conductive area 34 is omitted.
  • the first portions 321 and 341 of the first and second conductive areas 32 and 34 may have the same or similar properties (e.g.
  • the second portions 322 and 342 of the first and second conductive areas 32 and 34 may have the same or similar properties. This is because the first and second conductive areas 32 and 34 or the second portions 322 and 342 are included in the semiconductor layer 30 , which is formed through a single process, to thereby be irradiated with the same or similar laser, and the first portions 321 and 341 are also irradiated with the same or similar laser so as to form the first and second contact holes 461 and 462 .
  • the electrodes 42 and 44 which are connected to (e.g. in contact with) the first portions 321 and 341 through the contact hole 46 , also have large surface roughness.
  • the surfaces of the electrodes 42 and 44 may reflect light, which penetrates the semiconductor substrate 10 and is directed to the back surface, to enable the reuse of light.
  • such large surface roughness may maximize the contact area between the first portions 321 and 341 and the electrodes 42 and 44 , thereby improving bonding properties.
  • the surface roughness of the barrier area 36 may be smaller than the surface roughness of the first portions 321 and 341 and may be larger than the surface roughness of the second portions 322 and 342 .
  • the crystallinity of the barrier area 36 may be higher than the crystallinity of the first portions 321 and 341 and lower than the crystallinity of the second portions 322 and 342 .
  • the degree of crystallization of the barrier area 36 may be higher than the degree of crystallization of the first portions 321 and 341 and lower than the degree of crystallization of the second portions 322 and 342 .
  • the crystal grains in the barrier area 36 may be larger than the crystal grains in the first portions 321 and 341 and smaller than the crystal grains in the second portions 322 and 342 .
  • heat generated by a laser may be supplied to the entire first and second conductive areas 32 and 34 when a doping process (see FIG. 23F ) is performed on the first and second conductive areas 32 and 34 , or when a mask layer for doping (see reference numeral 340 in FIG. 23G ) is patterned.
  • the mask layer 340 includes a material that may be easily patterned by a laser (e.g. a carbide, such as a silicon carbide).
  • the laser used to perform the doping process or to pattern the mask layer 340 has a larger pulse width than the laser used to form the contact hole 46 in the insulation film 40 .
  • the degree of crystallization of the first and second conductive areas 32 and 34 may be higher than the degree of crystallization of the barrier area 36 , and the crystal grains in the first and second conductive areas 32 and 34 may be larger than the crystal grains in the barrier area 36 .
  • the surface roughness of the first and second conductive areas 32 and 34 is smaller than that of the barrier area 36 .
  • the portion in which the contact hole 46 is formed forms the first portions 321 and 341 , which have a lower degree of crystallization, i.e. lower crystallinity than the barrier area 36 .
  • the first portions 321 and 341 have smaller surface roughness than the barrier area 36 .
  • the first and second conductive areas 32 and 34 and the barrier area 36 include a polycrystalline semiconductor.
  • the second portion 322 may include a polycrystalline semiconductor
  • the first portion 321 and the barrier area 36 may include a microcrystalline semiconductor or an amorphous semiconductor.
  • the barrier area 36 may have crystallinity superior to that of the first portions 321 and 341 .
  • the second portion 322 includes a microcrystalline semiconductor
  • the first portion 321 and the barrier area 36 may include an amorphous semiconductor.
  • the first and second portions 321 and 322 and the barrier area 36 include an amorphous semiconductor
  • the first and second portions 321 and 322 and the barrier area 36 may have similar crystallinities.
  • the second portions 322 and 342 of the first and second conductive areas 32 and 34 may have crystallinity superior to that of the barrier area 36 .
  • the first portions 321 and 341 of the first and second conductive areas 32 and 34 which are connected to the electrodes 42 and 44 , may have large surface roughness, which may improve the reflectance and bonding of the electrodes 42 and 44 .
  • first portions 321 and 341 corresponding to the contact hole 46 may have larger surface roughness than the second portions 322 and 342 , whereby the reflectance of the electrodes 42 and 44 may be improved and the bonding of the electrodes 42 and 44 may be improved.
  • the second portions 322 and 342 in which no contact hole 46 is formed may have a high degree of crystallization, i.e. high crystallinity, thus having high mobility and excellent electrical properties. Thus, the efficiency of the solar cell 100 may be improved.
  • FIGS. 21 and 22 illustrate the instance where no textured structure is disposed on the back surface of the semiconductor substrate 10 on which the first and second conductive areas 32 and 34 have been formed.
  • the present invention is not limited thereto, and a textured structure may be disposed on the back surface of the semiconductor substrate 10 .
  • the first portions 321 and 341 may have uneven surfaces
  • the second portions 322 and 342 may have larger surface roughness than the first portions 321 and 341 , but may have relatively regular convex-concave portions depending on a particular crystalline surface.
  • FIGS. 23A to 23L are cross-sectional views illustrating the method of manufacturing the solar cell according to an embodiment of the present invention.
  • the semiconductor substrate 10 which includes the base area 110 including a second conductive dopant, is prepared.
  • the protective-film layer 20 is formed on the surface of the semiconductor substrate 10 .
  • the protective-film layer 20 may be formed on the entire back surface of the semiconductor substrate 10 .
  • the protective-film layer 20 may be formed via, for example, thermal growth, deposition (e.g. Plasma Enhanced Chemical Vapor Deposition (PECVD) or Atomic Layer Deposition (ALD)), or chemical oxidation.
  • PECVD Plasma Enhanced Chemical Vapor Deposition
  • ALD Atomic Layer Deposition
  • the present invention is not limited thereto, and the first protective-film layer 20 may be formed via any of various methods.
  • the first conductive area 32 , the second conductive area 34 , and the front-surface field area 130 are formed on the protective-film layer 20 .
  • a textured structure may be formed on the front surface of the semiconductor substrate 10 . This will be described below in detail.
  • the semiconductor layer 30 is formed over the protective-film layer 20 .
  • the semiconductor layer 30 may be formed of a microcrystalline, amorphous, or polycrystalline semiconductor.
  • the semiconductor layer 30 may be formed via, for example, thermal growth or deposition (e.g. Low Pressure Chemical Vapor Deposition (LPCVD)).
  • LPCVD Low Pressure Chemical Vapor Deposition
  • the present invention is not limited thereto, and the semiconductor layer 30 may be formed via any of various methods.
  • the semiconductor layer 30 may be formed using a polycrystalline semiconductor having high crystallinity.
  • the degree of crystallization of the semiconductor layer 30 may range from 80% to 98% (e.g. within a range from 85% to 98%).
  • the front surface of the semiconductor substrate 10 may be subjected to texturing, so as to have convex-concave portions.
  • the texturing performed on the surface of the semiconductor substrate 10 may be wet texturing or dry texturing. Wet texturing may be performed by dipping the semiconductor substrate 10 into a texturing solution, and advantageously has a short processing time. Dry texturing is the process of grinding the surface of the semiconductor substrate 10 using, for example, a diamond grill or a laser, and may disadvantageously entail a long processing time and the potential for damage to the semiconductor substrate 10 , although it may form even convex-concave portions.
  • the semiconductor substrate 10 may be textured via, for example, Reactive Ion Etching (RIE). As such, in the present invention, the semiconductor substrate 10 may be textured via any of various methods.
  • RIE Reactive Ion Etching
  • the present embodiment illustrates the instance where the front surface of the semiconductor substrate 10 is textured after the semiconductor layer 30 is formed.
  • the present invention is not limited thereto.
  • the surface of the semiconductor substrate 10 may be textured before the semiconductor layer 30 is formed, or in another process.
  • the first conductive area 32 , the second conductive area 34 , and the barrier area 36 are formed in the semiconductor layer 30 .
  • an area of the semiconductor layer 30 corresponding to the first conductive area 32 may be doped with a first conductive dopant via any of various methods such as, for example, ion implantation, thermal diffusion, or laser doping
  • an area of the semiconductor layer 30 corresponding to the second conductive area 34 may be doped with the second conductive dopant via any of various methods such as, for example, ion implantation, thermal diffusion, or laser doping.
  • the area located between the first conductive area 32 and the second conductive area 34 configures the barrier area 36 .
  • the front surface of the semiconductor substrate 10 is doped with the second conductive dopant so as to form the front-surface field area 130 .
  • the front-surface field area 130 may be formed via any of various methods such as, for example, ion implantation, thermal diffusion, or laser doping. Various other methods may be used.
  • the front-surface field area 130 may be formed by doping the front surface of the semiconductor substrate 10 with the second conductive dopant when the semiconductor layer 30 is doped with the second conductive dopant in order to form the second conductive area 34 .
  • one of the first and second conductive areas 32 and 34 may be formed by forming a dopant layer 320 , which includes the first or second conductive dopant, over the semiconductor layer 30 , and selectively introducing the first or second conductive dopant of the dopant layer 320 into the semiconductor substrate 10 via laser doping using a laser 302 or 304 . Then, the other one of the first and second conductive areas 32 and 34 may be formed via ion implantation or thermal diffusion of the first or second conductive dopant using the mask layer 340 , which includes an opening 340 a .
  • the front-surface field area 130 may be formed when the second conductive area 34 is formed, which may simplify processing.
  • the dopant layer 320 including the first conductive dopant is formed over the semiconductor layer 30 , and a portion of the dopant layer 320 corresponding to the first conductive area 32 is selectively irradiated with the laser 302 to perform a laser doping process.
  • the first conductive dopant included in the dopant layer 320 diffuses into the semiconductor layer 30 so as to form the first conductive area 32 .
  • the dopant layer 320 may be formed of any of various materials including the first conductive dopant.
  • the dopant layer 320 may be formed of a semiconductor (e.g. silicon) including the first conductive dopant.
  • the dopant layer 320 may include a sufficient amount of first conductive dopant.
  • the dopant layer 320 having an amorphous structure may have a high coefficient of absorption of light, and may thus reduce the strength of light passing therethrough, thereby minimizing the effect of the laser 302 on the semiconductor layer 30 or the protective-film layer 20 .
  • the dopant layer 320 may be formed by changing, for example, reaction gas or temperature in the process of forming the semiconductor layer 30 .
  • the semiconductor layer 30 and the dopant layer 320 may be formed through successive processes, i.e. an in-situ process.
  • the dopant layer 320 may be formed of, for example, boron, silicate glass, or phosphor silicate glass, or may be formed of any of various other materials.
  • the thickness of the dopant layer 320 may range from 30 nm to 50 nm.
  • the laser 302 may have an excessive effect on the semiconductor layer 30 or the protective-film layer 20 , causing deterioration in properties.
  • the thickness of the dopant layer 320 is above 50 nm, it may be difficult to effectively diffuse the dopant into the semiconductor layer 30 .
  • the present invention is not limited as to the thickness of the dopant layer 320 .
  • the laser 302 may be a laser capable of sufficiently diffusing the first conductive dopant in the portion of the semiconductor layer 30 corresponding to the first conductive area 32 .
  • an ultraviolet laser may be used as the laser 302 . This is because ultraviolet laser radiation may be absorbed by a nanometer-scale film.
  • the semiconductor layer 30 or the protective-film layer 20 may be damaged when a green laser is used as a laser for doping.
  • a pulse-type laser i.e. a laser having a nanometer-scale pulse width (i.e. within a range from 1 nm to 999 nm) may be used.
  • a laser having such a nanometer-scale pulse width may supply a sufficient amount of heat to the dopant layer 320 and the semiconductor layer 30 , and therefore re-crystallization may occur in the portion of the semiconductor layer 30 that is irradiated with the laser.
  • a sufficient amount of heat is supplied, sufficient crystallization is realized in the corresponding portion of the semiconductor layer 30 (i.e. in the first conductive area 32 ). Therefore, the first conductive area 32 has a higher degree of re-crystallization and includes larger crystal grains than the portion of the semiconductor layer 30 in which the first conductive area 32 is not formed.
  • the pulse width of the laser 302 may range from 80 ns to 100 ns. This pulse width is limited to the range within which the dopant may be effectively diffused and within which the properties of the first conductive area 32 may be improved via re-crystallization. However, the present invention is not limited thereto.
  • the dopant layer 320 is removed.
  • the method of removing the dopant layer 320 may be any of known methods.
  • the dopant layer 320 may be removed via wet etching using, for example, an alkaline solution, or dry etching, such as reactive ion etching.
  • the mask layer 340 is formed over the semiconductor layer 30 including the first conductive area 32 , and as illustrated in FIG. 23H , the opening 340 a corresponding to the second conductive area 34 is formed in the mask layer 340 .
  • the opening 340 a may be formed via laser ablation using the laser 304 .
  • the mask layer 340 may be formed of any of various materials, which may prevent diffusion of the second conductive dopant.
  • the mask layer 340 may be a silicon carbide film including a silicon carbide (SiC).
  • SiC silicon carbide
  • the mask layer 340 may effectively prevent diffusion of the dopant, may be easily patterned by the laser 304 , and may be easily removed after processing.
  • the laser 304 for forming the opening 340 a in the mask layer 340 may be a laser that is similar to the laser 302 used in the laser doping process for forming the first conductive area 32 . That is, the laser 304 may be an ultraviolet laser. In addition, the laser 304 may be a pulse-type laser, which has a nanometer-scale pulse width (i.e. within a range from 1 nm to 999 nm). However, the pulse width of the laser 304 used to form the opening 340 a may be slightly greater than the pulse width of the laser 302 used to form the first conductive area 32 . This serves to transfer a higher temperature of heat to the mask layer 340 so as to melt and evaporate a portion of the mask layer 340 .
  • the pulse width of the laser 304 may range from 160 ns to 200 ns. This pulse width is limited to the range within which the laser may form the opening 340 a in the mask layer 340 and may improve the properties of the second conductive area 34 .
  • the present invention is not limited thereto.
  • the laser 304 which has a nanometer-scale pulse width as described above, may supply a sufficient amount of heat to the semiconductor layer 30 , whereby re-crystallization may occur in the portion of the semiconductor layer 30 irradiated with the laser. Because the corresponding portion of the semiconductor layer 30 (i.e. the second conductive area 34 ) is crystallized when such a sufficient amount of heat is supplied, the second conductive area 34 has a higher degree of re-crystallization and includes larger crystal grains than the portion of the semiconductor layer 30 in which the first and second conductive areas 32 and 34 are not formed (i.e. the barrier area 36 ).
  • the second conductive area 34 is formed by diffusing the second conductive dopant through the opening 340 a , and the mask layer 340 is removed. Any of various methods, such as thermal diffusion or ion implantation, may be used to diffuse the second conductive dopant.
  • the front-surface field area 130 may also be formed on the front surface of the semiconductor substrate 10 simultaneously with the formation of the second conductive area 34 .
  • the first conductive area 32 is crystallized in the laser doping process
  • the second conductive area 34 is crystallized in the patterning process of forming the opening 340 a .
  • the first and second conductive areas 34 may have a higher degree of crystallization and may include larger crystal grains than the barrier area 36 , which is not irradiated with a laser.
  • the front insulation film 24 and the anti-reflection film 26 are sequentially formed on the front surface of the semiconductor substrate 10 , and the insulation film 40 is formed on the back surface of the semiconductor substrate 10 .
  • the front insulation film 24 , the anti-reflection film 26 , or the insulation film 40 may be formed via any of various methods, such as, for example, chemical vapor deposition, vacuum deposition, spin coating, screen printing, or spray coating.
  • the front insulation film 24 , the anti-reflection film 26 , or the insulation film 40 may be formed via chemical vapor deposition.
  • the contact hole 46 is formed in the insulation film 40 .
  • the contact hole 46 may be formed via laser ablation by irradiating the corresponding portion of the insulation film 40 with a laser 306 .
  • the laser 306 may be any laser capable of forming the contact hole 46 in the insulation film 40 .
  • the laser 306 may be an ultraviolet laser. This is because ultraviolet laser radiation may be absorbed by a nanometer-scale film.
  • the laser 306 may be a pulse-type laser, i.e. a laser having a picometer-scale pulse width (i.e. within a range from 1 pm to 999 pm) or having an output of 0.5 W to 2 W. This is because it may be difficult to form the contact hole 46 in the insulation film 40 formed of a nitride when the laser 306 has a nanometer-scale pulse width.
  • the laser 306 having such a picometer-scale pulse width may form the contact hole 46 by supplying heat at a high strength for a short time.
  • the laser 306 may have a pulse width of 1 pm or 100 pm. This pulse width is limited to the range within which the laser may stably form the contact hole 46 in the insulation film 40 formed of a predetermined material. However, the present invention is not limited thereto.
  • the contact hole 46 is formed based on the principle illustrated in FIG. 24 .
  • the insulation film 40 is irradiated with the laser 306 as illustrated in (a) of FIG. 24
  • the corresponding portion of the insulation film 40 absorbs heat as illustrated in (b) of FIG. 24
  • the insulation film 40 is melted and evaporated as illustrated in (c) of FIG. 24 , whereby the contact hole 46 is formed as illustrated in (d) of FIG. 24 .
  • the laser 306 has a picometer-scale pulse width, a relatively small amount of heat is supplied to the portion of the semiconductor layer 30 corresponding to the contact hole 46 .
  • the first portions 321 and 341 of the semiconductor layer 30 are changed to thus have properties different from those of the second portions 322 and 342 . More specifically, when the first portions 321 and 341 are melted and crystallized, some portions of the first portions 321 and 341 may not be re-crystallized because a sufficient amount of heat is not supplied thereto.
  • the first portions 321 and 341 corresponding to the contact hole 46 have a lower degree of crystallization and include larger crystal grains than the second portions 322 and 342 , which maintain the original properties of the first and second conductive areas 32 and 34 .
  • the first portions 321 and 341 corresponding to the contact hole 46 have a lower degree of crystallization, i.e. lower crystallinity, and include smaller crystal grains than the barrier area 36 , which is not irradiated with a laser during laser doping or patterning. This is because the heat supplied by the laser 306 is not sufficient for crystallization.
  • the semiconductor layer 30 is melted and re-crystallized such that some portions thereof are crystallized but some portions thereof are not crystallized, the first portions 321 and 341 have larger surface roughness than the second portions 322 and 342 and the barrier area 36 .
  • the saw damage marks see reference numerals SD 1 and SD 2 of FIG.
  • the semiconductor substrate 10 may be different due to variation in the crystallinity of the first portions 321 and 341 , and some of the properties of the insulation film 40 may vary in the first area A 1 , which corresponds to a portion of the insulation film 40 or the second portions 322 and 342 , which are close to the first portions 321 and 341 , whereby the first area A 1 may be seen to be brighter than the second area A 2 , which corresponds to the remaining portion of the insulation film 40 or the second portions 322 and 342 .
  • the contact hole 46 is filled with the first and second electrodes 42 and 44 .
  • a plurality of electrode layers are formed in sequence throughout the conductive areas 32 and 34 and the insulation film 40 via, for example, sputtering or plating, and are then patterned to form the first and second electrodes 42 and 44 .
  • the patterning may be performed using, for example, an etchant or etching paste, or performed via dry etching.
  • the electrodes 42 and 44 may be formed over the conductive areas 32 and 34 to have a desired pattern so that the contact hole 46 is filled with the electrodes 42 and 44 .
  • the solar cell 100 having excellent efficiency may be manufactured via simplified processing, which may improve the productivity of the solar cell 100 .
  • forming the contact hole 46 using the laser 306 enables easy and rapid formation of the contact hole 46 .
  • forming the contact hole 46 using the laser 306 may greatly increase, for example, a degree of freedom of design.
  • FIG. 25 is a cross-sectional view illustrating a solar cell according to another embodiment of the present invention.
  • an intermediate insulation film 41 may be disposed between the semiconductor layer 30 and the insulation film 40 .
  • the intermediate insulation film 41 disposed between the semiconductor layer 30 and the insulation film 40 may prevent a laser (see reference numeral 306 in FIG. 23K ) having an excessive effect on the semiconductor layer 30 (i.e. the first and second conductive areas 32 and 34 ) when the contact hole 46 is formed using the laser 306 .
  • the intermediate insulation film 41 may be disposed over the entire semiconductor layer 30 to improve a passivation property of the semiconductor layer 30 .
  • the electrodes 42 and 44 may be electrically connected to the conductive areas 32 and 33 with the intermediate insulation film 41 interposed therebetween.
  • the intermediate insulation film 41 may be formed of an oxide film (e.g. a silicon oxide film), which may improve a passivation property without deteriorating electrical properties between the electrodes 42 and 44 and the conductive areas 32 and 34 .
  • the thickness of the intermediate insulation film 41 may be equal to or less than the thickness of the protective-film layer 20 so as to reduce low contact resistance between the electrodes 42 and 44 and the conductive areas 32 and 34 .
  • the present invention is not limited thereto, and for example, the material and thickness of the intermediate insulation film 41 may be altered in various ways.
  • FIG. 26 is a cross-sectional view of a solar cell according to another embodiment of the present invention.
  • the first conductive area 32 and the second conductive area 34 may be formed on different surfaces of the semiconductor substrate 10 .
  • FIG. 26 illustrates the instance where the second conductive area 34 is doped with a dopant, which is different from a dopant in the base area 110 of the semiconductor substrate 10 , at a higher doping concentration than the base area 110 .
  • the present invention is not limited thereto, and the second conductive area 34 may be a semiconductor layer including an amorphous, microcrystalline or polycrystalline semiconductor, which is formed separately from the semiconductor substrate 10 .
  • another protective-film layer may be disposed, or may not be disposed between the second conductive area 34 and the semiconductor substrate 10 .
  • FIG. 26 illustrates the instance where the protective-film layer 20 , the first conductive area 32 and the first electrode 42 are disposed on the back surface of the semiconductor substrate 10
  • the protective-film layer 20 , the first conductive area 32 and the second electrode 44 may be disposed on the front surface of the semiconductor substrate 10
  • the second conductive area 34 may be disposed on the front surface of the semiconductor substrate 10 in the same manner as the first conductive area 32 , or may be disposed on the back surface of the semiconductor substrate 10 , unlike the first conductive area 32 .
  • Various other alterations are possible.
  • FIG. 27 is a partially enlarged sectional view illustrating a solar cell according to another embodiment of the present invention.
  • the first portion 321 is formed in the thickness direction of the first conductive area 32 to extend between the first conductive area 32 and the protective-film layer 20 .
  • the first portion 321 is formed in a portion of the first conductive area 32 in the thickness direction of the first conductive area 32 .
  • the first portion 321 may be located close to the first electrode 42 .
  • Such a structure may be formed when the laser 306 has no effect on the first conductive area 32 in the thickness direction.
  • the first portion 321 is formed near the surface of the electrodes 42 and 44 , which determines the reflectance and contact resistance of the electrodes 42 and 44
  • the first conductive area 32 which have excellent electrical properties and mobility, may remain below the first portion 321 .
  • FIG. 27 illustrates the second portion 322 as being located below the first portion 321
  • the present invention is not limited thereto.
  • a third portion which has a higher degree of crystallization, i.e. higher crystallinity than the first portion 321 , but has a lower degree of crystallization, i.e. lower crystallinity than the second portion 322 , may be located below the first portion 321 .
  • the second conductive area 34 may be similarly formed such that the first portion 341 is formed only in a portion of the second conductive area 34 in the thickness direction.
  • FIG. 28 is a partial rear plan view illustrating a solar cell according to another embodiment of the present invention.
  • no insulation film (see reference numeral 40 in FIG. 21 ) is illustrated, and only the first and second conductive area 32 and 34 , the barrier area 36 and the first and second electrodes 42 and 44 are illustrated.
  • the insulation film 40 is disposed between the first and second electrodes 42 and 44 and the first and second conductive areas 32 and 34 and the barrier area 36 .
  • the first contact hole see reference numeral 461 in FIG.
  • connection between the first electrode 42 and the first conductive area 32 may be formed in the portion of the insulation film 40 at which the first electrode 42 and the first conductive area 32 overlap each other, and the second contact hole (see reference numeral 462 in FIG. 21 ) for connection between the second electrode 44 and the second conductive area 34 may be formed in the portion of the insulation film 40 at which the second electrode 44 and the second conductive area 34 overlap each other.
  • a plurality of second conductive areas 34 may have an island shape and may be space apart from one another, and the first conductive area 32 may be formed throughout the remaining portion excluding the second conductive areas 34 and the barrier areas 36 surrounding the respective second conductive areas 34 .
  • the first conductive area 32 which functions as an emitter area, may have the maximum area, which may improve photoelectric conversion efficiency.
  • the present invention is not limited thereto, and of course, the second conductive areas 34 may have any of various other shapes so long as they can have the minimum area possible.
  • FIG. 28 illustrates the second conductive areas 34 as having a circular shape
  • the present invention is not limited thereto.
  • the second conductive areas 34 may have an elliptical shape or a polygonal shape such as, for example, a triangular shape, a rectangular shape, or a hexagonal shape.
  • a protective-film layer formed of a silicon oxide film was formed on one surface of an n-type monocrystalline semiconductor substrate.
  • a semiconductor layer including polycrystalline silicon was formed over the protective-film layer via low-pressure chemical vapor deposition.
  • a first conductive area and a second conductive area were formed in the semiconductor layer respectively by doping an area of the semiconductor layer with a p-type dopant via laser doping and by doping another area of the semiconductor layer with an n-type dopant via thermal diffusion using a mask layer.
  • a back passivation film formed of a silicon nitride film and a silicon carbide film was formed, and contact holes were formed in the back passivation film using a laser having a pulse width of 20 pm.
  • a first electrode and a second electrode were formed so as to be electrically connected to the first conductive area and the second conductive area through the contact holes.
  • FIG. 29 A microphotograph of the back surface of a solar cell according to the manufacturing example is illustrated in FIG. 29 , and photographs of the cross section of the solar cell in the portion in which the contact hole is formed (i.e. a first portion) and in the portion in which no contact hole is formed (i.e. a second portion) are illustrated respectively in (a) and (b) of FIG. 30 .
  • the result of analysis of the semiconductor layer via a Raman analysis method in the portion in which the contact hole is formed (i.e. the first portion) and in the portion in which no contact hole is formed (i.e. the second portion) is illustrated in FIG. 31 , and the degree of crystallization thereof is illustrated in Table 1.
  • the result was measured in the portion of the semiconductor layer close to the electrode, in the middle portion of the semiconductor layer, and in the portion of the semiconductor layer close to the protective-film layer.
  • the saw damage mark SD 2 of the portion in which no contact hole is formed is deeper than the saw damage mark SD 1 of the portion in which the contact hole is formed (i.e. the first portion).
  • the area corresponding to the periphery of the brightest portion, in which the contact hole is formed i.e. the first area A 1
  • the semiconductor layer in the portion in which the contact hole is formed has large surface roughness
  • the semiconductor layer in the portion in which no contact hole is formed i.e. the second portion has small surface roughness.
  • the portion in which the contact hole is formed i.e. the first portion
  • the portion in which no contact hole is formed i.e. the second portion
  • the degree of crystallization increases with increasing distance from the electrode. This is presumed to be because the effect of the laser is reduced with increasing distance from the electrode.
  • FIG. 32 is a cross-sectional view illustrating an example of the solar cell according to some embodiments of the present invention
  • FIG. 33 is a partial rear plan view illustrating the solar cell illustrated in FIG. 32 .
  • the solar cell according to the present embodiment may be substantially the same as the above-described solar cell. Thus, a repeated description may be omitted.
  • the solar cell 100 includes the semiconductor substrate 10 , a protective-film layer 202 formed on the surface of the semiconductor substrate 10 , the first conductive area 32 formed over the protective-film layer 202 and configured as a semiconductor layer of a first conductive type, the second conductive area 34 of a second conductive type, which is opposite to the first conductive type, and the first electrode 42 and the second electrode 44 configured to be brought into contact with the first conductive area 32 and the second conductive area 34 respectively.
  • the first conductive area 32 includes a contact-hole area, which is exposed through a first contact hole 40 a .
  • the surface of the contact-hole area has first contact-hole surface roughness R 1 .
  • the second conductive area 34 includes a contact-hole area, which is exposed through a second contact hole 40 b .
  • the surface of the contact-hole area has second contact-hole surface roughness R 2 .
  • the first and second electrodes 42 and 44 respectively have first electrode surface roughness, which corresponds to the first contact-hole surface roughness R 1 , and second electrode surface roughness, which corresponds to the second contact-hole surface roughness R 2 . This will be described later in detail.
  • the semiconductor substrate 10 may be doped with a first or second conductive dopant at a relatively low doping concentration, and thus may be of a first or second conductive type.
  • the semiconductor substrate 10 may include the front-surface field area (or the field area) 130 disposed on one surface (e.g. the front surface) of the semiconductor substrate 10 .
  • the front-surface field area 130 may be of the same conductive type as the semiconductor substrate 10 , and may have a higher doping concentration than the semiconductor substrate 10 .
  • the present embodiment illustrates the instance where the front-surface field area 130 is a doped area formed by doping the semiconductor substrate 10 with a second conductive dopant at a relatively high doping concentration.
  • the front-surface field area 130 may include a second conductive crystalline (monocrystalline or polycrystalline) semiconductor so as to constitute a portion of the semiconductor substrate 10 .
  • the front-surface field area 130 may be formed by doping a separate semiconductor layer (e.g. an amorphous semiconductor layer, a microcrystalline semiconductor layer, or a polycrystalline semiconductor layer), rather than the semiconductor substrate 10 , with the second conductive dopant.
  • the front-surface field area 130 may be configured as a field area, which functions similar to a layer (e.g. the front insulation film 24 and/or the anti-reflection film 26 ), which is formed close to the semiconductor substrate 10 and is doped with a fixed charge.
  • the front insulation film 24 may be formed of an oxide (e.g.
  • the semiconductor substrate 10 may include no separate doping area, which may minimize defects of the semiconductor substrate 10 .
  • the front-surface field area 130 having various configurations may be formed using various other methods.
  • the protective-film layer 202 may be formed on the other surface (e.g. the back surface) of the semiconductor substrate 10 .
  • the protective-film layer 202 may be formed on the entire back surface of the semiconductor substrate 10 .
  • the protective-film layer 202 may be easily formed without patterning.
  • the thickness of the protective-film layer 202 may be less than the thickness of the insulation film 40 .
  • the thickness of the protective-film layer 202 may be 5 nm or less (more specifically, 2 nm or less, for example, within a range from 0.5 nm to 2 nm).
  • the thickness of the protective-film layer 202 exceeds 5 nm, smooth tunneling does not occur, and consequently, the solar cell 100 may not operate.
  • the thickness of the protective-film layer 202 is below 0.5 nm, it may be difficult to form the protective-film layer 202 having a desired quality.
  • the thickness of the protective-film layer 202 may be 2 nm or less (more specifically, within a range from 0.5 nm to 2 nm). At this time, in order to further improve tunneling effects, the thickness of the protective-film layer 202 may range from 0.5 nm to 1.5 nm. However, the present invention is not limited thereto, and the thickness of the protective-film layer 202 may have any of various values.
  • the semiconductor layer 302 including the conductive areas 32 and 34 may be disposed over the protective-film layer 202 .
  • the semiconductor layer 302 may be formed to be brought into contact with the protective-film layer 202 , and thus may exhibit a simplified structure and improved tunneling effects.
  • the present invention is not limited thereto.
  • the semiconductor layer 302 may include the first conductive area 32 , which includes a first conductive dopant and thus is of a first conductive type, and the second conductive area 34 , which includes a second conductive dopant and thus is of a second conductive type.
  • the first conductive area 32 and the second conductive area 34 may be located in the same plane over the protective-film layer 202 . That is, there may be no layer interposed between the first and second conductive areas 32 and 34 and the protective-film layer 202 . Alternatively, when another layer is interposed between the first and second conductive areas 32 and 34 and the protective-film layer 202 , the interposed layer may have the same stacking structure.
  • the barrier area 33 may be located between the first conductive area 32 and the second conductive area 34 in the same plane as the conductive areas 32 and 34 .
  • the first conductive area 32 configures an emitter area, which forms a pn junction with the semiconductor substrate 10 with the protective-film layer 202 interposed therebetween so as to produce carriers via photoelectric conversion.
  • the second conductive area 34 configures a back-surface field area, which forms a back-surface field so as to prevent the loss of carriers due to recombination on the surface of the semiconductor substrate 10 .
  • the barrier area 33 may be located between the first conductive area 32 and the second conductive area 34 so that the first conductive area 32 and the second conductive area 34 are spaced apart from each other.
  • shunts may occur, undesirably causing deterioration in the performance of the solar cell 100 . Therefore, unnecessary or undesired shunts may be prevented when the barrier area 33 is located between the first conductive area 32 and the second conductive area 34 .
  • the barrier area 33 may be formed of any of various materials, which may substantially insulate the first conductive area 32 and the second conductive area 34 from each other.
  • the barrier area 33 may be formed of an undoped insulation material, and more specifically, an intrinsic semiconductor including no dopant.
  • a groove may be formed between the first conductive area 32 and the second conductive area 34 so as to physically isolate the first conductive area 32 and the second conductive area 34 from each other.
  • the semiconductor substrate 10 when the semiconductor substrate 10 is of an n-type, it forms a pn junction with the first conductive area 32 , and the first conductive area 32 forms an emitter. In this instance, the area of the first conductive area 32 may be greater than the area of the second conductive area 34 .
  • the wide first conductive area 32 may serve to collect holes. Because holes have longer lifetimes than electrons, the first conductive area 32 may effectively collect holes.
  • the back insulation film 40 is formed over the semiconductor layer 302 .
  • the back insulation film 40 includes the first contact hole 40 a for connection between the first conductive area 32 and the first electrode 42 , and the second contact hole 40 b for connection between the second conductive area 34 and the second electrode 44 , and functions to passivate the semiconductor layer 302 .
  • the first and second conductive areas 32 and 34 are exposed respectively through the contact holes 40 a and 40 b of the insulation film 40 , and the exposed first and second conductive areas 32 and 34 have a particular surface shape.
  • the contact holes are typically shaped as a plurality of circular, elliptical or polygonal openings, spaced apart from one another, or as stripe-shaped openings.
  • the first conductive area 32 and the second conductive area 34 may have a predetermined shape depending on the shape of the contact holes 40 a and 40 b , and in particular, may have predetermined surface roughnesses, which may be referred to as the first and second contact-hole surface roughnesses R 1 and R 2 .
  • the back insulation film 40 may be formed of a single film or multiple films in the form of a combination of two or more films selected from the group consisting of a silicon nitride film, a silicon nitride film containing hydrogen, a silicon oxide film, a silicon oxide nitride film, a silicon carbide film, and Al 2 O 3 , MgF 2 , ZnS, TiO 2 , and CeO 2 films.
  • the electrodes 42 and 44 disposed on the back surface of the semiconductor substrate 10 , include the first electrode 42 , which is in contact with the first conductive area 32 , and the second electrode 44 , which is in contact with the second conductive area 34 .
  • the first electrode 42 may penetrate the contact hole 40 a in the back insulation film 40 to thereby be brought into contact with the first conductive area 32 having the first contact-hole surface roughness R 1 , whereby the surface of the first electrode 42 may have first electrode surface roughness Ra 1 .
  • the first electrode surface roughness Ra 1 may be acquired when the first contact-hole surface roughness R 1 is transferred to the surface of the first electrode 42 .
  • the second electrode 44 may penetrate the contact hole 40 b in the back insulation film 40 to thereby be brought into contact with the second conductive area 34 having the second contact-hole surface roughness R 2 , whereby the surface of the second electrode 44 may have second electrode surface roughness Ra 2 .
  • the second electrode surface roughness Ra 2 may be acquired when the second contact-hole surface roughness R 2 is transferred to the surface of the second electrode 44 .
  • the first and second electrodes 42 and 44 may include any of various metal materials.
  • the first and second electrodes 42 and 44 may have any of various plan shapes in order to collect and outwardly transfer carriers by being connected respectively to the first conductive area 32 and the second conductive area 34 while not being electrically connected to each other.
  • the contact holes 40 a and 40 b may be formed by irradiating local portions of the insulation film 40 with a laser so that the corresponding portions of the insulation film 40 are removed via evaporation. Through this process, the first and second contact-hole surface roughnesses R 1 and R 2 may be acquired.
  • the contact holes 40 a and 40 b are formed using a laser, heat is transferred to the first and second conductive areas 32 and 34 , causing corresponding portions of the first and second conductive areas 32 and 34 to be melted and re-crystallized.
  • the re-crystallized portions exhibit sharper curvature than the remaining portion, and thus have increased surface roughnesses, i.e. the first and second contact-hole surface roughnesses R 1 and R 2 .
  • the electrodes 42 and 44 connected to (e.g. in contact with) the first and second conductive areas 32 and 34 through the contact holes 40 a and 40 b have increased surface roughnesses. That is, the first and second electrodes 42 and 44 may have the first and second electrode surface roughnesses Ra 1 and Ra 2 , which are acquired when the first and second contact-hole surface roughnesses R 1 and R 2 are transferred to the first and second electrodes 42 and 44 .
  • the surfaces of the electrodes 42 and 44 may reflect light, which penetrates the semiconductor substrate 10 and is directed to the back surface, to enable the reuse of light.
  • such large surface roughness may maximize the contact area between the portions of the first and second conductive areas 32 and 34 corresponding to the first and second contact holes 40 a and 40 b and the electrodes 42 and 44 , thereby improving bonding properties.
  • the contact holes may be formed by removing the back insulation film 40 using etching paste, rather than laser irradiation.
  • groove-shaped marks of the profile of the contact holes may be imprinted in the contact-hole areas of the first conductive area 32 and the second conductive area 34 .
  • the thickness of the first and second electrodes 42 and 44 may be 1 ⁇ m or less. More specifically, the height of the first and second electrodes 42 and 44 from the interface with the conductive areas 32 and 34 to the other surface may be 1 ⁇ m or less.
  • the first and second electrodes 42 and 44 may be a multilayered film formed via deposition.
  • the first and second electrodes 42 and 44 may have a four layered structure including a first titanium layer, an aluminum layer, a second titanium layer, and a nickel-vanadium alloy layer.
  • the first titanium layer has a thickness of 50 nm or less
  • the aluminum layer has a thickness of 550 nm or less
  • the second titanium layer has a thickness of 150 nm or less
  • the nickel-vanadium alloy layer has a thickness of 250 nm or less.
  • the present invention is not limited thereto, and various other metals may be used.
  • the portions of the first and second conductive areas 32 and 34 which are connected to the electrodes 42 and 44 through the first and second contact holes 40 a and 40 b , may have the first and second contact-hole surface roughnesses R 1 and R 2 , which are relatively high, thus improving the reflectance and bonding of the electrodes 42 and 44 .
  • the present invention is not limited thereto.
  • the first and second conductive areas 32 and 34 are formed over the semiconductor substrate 10 with the protective-film layer 202 interposed therebetween, and thus are formed separately from the semiconductor substrate 10 . As such, loss due to recombination may be less than that when a doped area formed by doping an area of the semiconductor substrate 10 with a dopant is used as a conductive area.
  • the portion corresponding to the contact holes 40 a and 40 b have larger surface roughness than the remaining portion, whereby the reflectance of the electrodes 42 and 44 may be improved and the bonding of the electrodes 42 and 44 may be improved.
  • the portion in which no contact holes 40 a and 40 b are formed may have a high degree of crystallization, i.e. high crystallinity, thus achieving high mobility and excellent electrical properties. Thus, the efficiency of the solar cell 100 may be improved.
  • the above description illustrates the instance where the first conductive area 32 and the second conductive area 34 are disposed together over the same protective-film layer 202 and are covered together with the insulation film 40 .
  • the present invention is not limited thereto.
  • FIGS. 32 and 33 illustrate the instance where no textured structure is disposed on the back surface of the semiconductor substrate 10 on which the first and second conductive areas 32 and 34 have been formed.
  • the present invention is not limited thereto, and a textured structure may be provided on the back surface of the semiconductor substrate 10 .
  • the front insulation film 24 and the anti-reflection film 26 are selectively disposed over the front-surface field area 130 on the front surface of the semiconductor substrate 10 . That is, in some embodiments, only the front insulation film 24 may be formed over the semiconductor substrate 10 , only the anti-reflection film 26 may be formed over the semiconductor substrate 10 , or the front insulation film 24 and the anti-reflection film 26 may be sequentially disposed over the semiconductor substrate 10 .
  • the front insulation film 24 and the anti-reflection film 26 may substantially be formed on the entire front surface of the semiconductor substrate 10 .
  • the front insulation film 24 is formed so as to be brought into contact with the surface of the semiconductor substrate 10 for the passivation of defects, which exist in the surface or the bulk of the semiconductor substrate 10 .
  • the front insulation film 24 may increase the open-circuit voltage of the solar cell 150 by removing recombination sites of minority carriers.
  • the anti-reflection film 26 reduces the reflectance of light introduced into the front surface of the semiconductor substrate 10 .
  • the anti-reflection film 26 may increase the quantity of light, which reaches a pn junction formed at the interface of the semiconductor substrate 10 and the first conductive area 32 .
  • the anti-reflection film 26 may increase the short-circuit current Isc of the solar cell 100 .
  • the front insulation film 24 and the anti-reflection film 26 may increase the open-circuit voltage and the short-circuit current of the solar cell 100 , thereby improving the efficiency of the solar cell 100 .
  • Each of the front insulation film 24 and the anti-reflection film 26 may include a single film or multiple films in the form of a combination of two or more films selected from the group consisting of a silicon nitride film, a silicon nitride film containing hydrogen, a silicon oxide film, a silicon oxide nitride film, an aluminum oxide film, a silicon carbide film, and MgF 2 , ZnS, TiO 2 , and CeO 2 films.
  • the efficiency of the solar cell 100 may be improved.
  • the first and second conductive areas 32 and 34 are formed over the semiconductor substrate 10 with the protective-film layer 202 interposed therebetween, and thus are formed separately from the semiconductor substrate 10 . As such, loss due to recombination may be less than that when a doped area formed by doping an area of the semiconductor substrate 10 with a dopant is used as a conductive area.
  • a plurality of first conductive areas 32 and a plurality of second conductive areas 34 are formed to extend a long length in a given direction, and are arranged side by side.
  • the first conductive areas 32 and the second conductive areas 34 are alternately arranged.
  • the barrier area 33 may be located between the first conductive area 32 and the second conductive area 34 so that the first conductive area 32 and the second conductive area 34 are spaced apart from each other by the barrier area 33 .
  • the area of the first conductive area 32 may be greater than the area of the second conductive area 34 , as illustrated in FIG. 33 .
  • the areas of the first conductive area 32 and the second conductive area 34 may be adjusted by providing the first conductive area 32 and the second conductive area 34 with different widths. In this instance, the width W 1 of the first conductive area 32 is greater than the width W 2 of the second conductive area 34 .
  • the first electrode 42 is formed in a stripe shape over the first conductive area 32
  • the second electrode 44 is formed in a stripe shape over the second conductive area 34 .
  • the first and second electrodes 42 and 44 are partially brought into contact with the first conductive area 32 and the second conductive area 34 in the contact-hole areas. Images having the profile of the contact holes are imprinted on the surfaces of the first and second electrodes 42 and 44 , as illustrated in FIG. 35N .
  • the profile of the contact holes, imprinted on the surfaces of the first and second electrodes 42 and 44 depends on the shape of openings formed in the insulation film 40 and the surface properties of the contact-hole areas of the first conductive area 32 and the second conductive area 34 , which are formed upon the formation of the openings.
  • the profile of the contact holes imprinted on the first and second electrodes 42 and 44 is seen as convex-concave portions, which correspond to the surface roughness of the first conductive area 32 and the second conductive area 34 generated when the contact holes are formed.
  • the convex-concave portions remain on the surface of a cell electrode, and thus remain in a final cell structure, thereby having an effect on cell properties and module properties.
  • FIG. 34 is a flowchart illustrating the manufacturing method according to some embodiments of the present invention.
  • the method of manufacturing the solar cell according to the present embodiment includes a protective-film layer forming operation S 101 , a semiconductor layer forming operation S 102 , a first conductive area forming operation S 103 , a second conductive area forming operation S 104 , an insulation film forming operation S 105 , a contact hole forming operation S 106 , and an electrode forming operation S 107 .
  • FIGS. 35A to 35O are views diagrammatically illustrating the respective operations of FIG. 34 .
  • FIG. 35J is a plan view of FIG. 35I
  • FIG. 35M is a plan view of FIG. 35L .
  • FIG. 35A diagrammatically illustrates the protective-film layer forming operation S 101 .
  • the front surface of the semiconductor substrate 10 is illustrated as facing downward.
  • the semiconductor substrate 10 is formed of a silicon crystal growth semiconductor having a monocrystalline or polycrystalline structure, and contains any one of the first conductive dopant and the second conductive dopant, which are of opposite conductive types.
  • the first conductive dopant is an n-type dopant, for example, a group-V element, such as phosphorus (P), arsenic (As), bismuth (Bi), or antimony (Sb)
  • the second conductive dopant is a p-type dopant, for example, a group-III element, such as boron (B), aluminum (Al), gallium (Ga), or indium (In).
  • the semiconductor substrate 10 has a monocrystalline structure in which grains are grown only in a given direction, and contains an n-type dopant. As such, in the semiconductor substrate 10 , holes, which have longer lifetimes than electrons, form majority carriers to facilitate photoelectric conversion at a pn junction surface.
  • the protective-film layer 202 is configured as an oxide layer including a thermal oxide and a silicon oxide, and has a thickness of 5 nm or less, more specifically, a thickness within a range from 0.5 nm to 3 nm.
  • the protective-film layer 202 reduces recombination sites corresponding to a pn junction surface, and therefore functions to enable effective passivation.
  • the protective-film layer 202 may be formed via a method that has generally been used in, for example, the semiconductor field, such as, for example, wet oxidation, thermal oxidation in an atmospheric furnace, PECVD or LPCVD.
  • the semiconductor layer 302 is formed over the protective-film layer 202 .
  • the semiconductor layer 302 may also be formed via an LPCVD method.
  • the protective-film layer 202 and the semiconductor layer 302 are formed via CVD, the two layers may be successively formed using the same deposition facility, which enables an in-situ process.
  • the manufacturing process may be greatly simplified, which may greatly reduce, for example, manufacturing costs and manufacturing time.
  • both the protective-film layer 202 and the semiconductor layer 302 are formed via an LPCVD method, the difference in temperature between the two processes may be adjusted to 100° C. or less.
  • temperatures, the adjustment of which is relatively difficult, are maintained without great variation as described above, the in-situ process of successively forming the protective-film layer 202 and the semiconductor layer 302 may be facilitated.
  • FIG. 35B diagrammatically illustrates the semiconductor layer forming operation S 102 .
  • the thickness of the semiconductor layer 302 ranges from 300 nm to 400 nm. When the thickness is below 300 nm, a foreign substance may be doped to the protective-film layer 202 in the subsequent first conductive area forming operation S 104 . When the thickness is above 400 nm, a foreign substance may be doped on only a portion of the semiconductor layer 302 in a thickness direction, rather than being doped on the entire semiconductor layer 302 .
  • the intrinsic semiconductor layer 302 may be formed via an LPCVD method, in order to enable an in-situ process in connection with the previous operation S 101 .
  • operation S 101 and operation S 102 are performed via the same LPCVD method, the processes of the two operations may be performed using the same equipment.
  • contamination of the protective-film layer 202 by a foreign substance, or an increase in the thickness of the protective-film layer 202 by additional oxidation, which is caused when the semiconductor substrate, on which the protective-film layer 202 has been formed, must be removed from the equipment, may be prevented, unlike the related art.
  • source gas includes only gas containing a semiconductor material, for example, silane gas (SiH 4 ), because the semiconductor layer 302 is intrinsic.
  • the source gas may also contain nitrogen dioxide (N 2 O) gas and/or oxygen (O 2 ) gas so as to adjust, for example, the size and crystallinity of crystal grains.
  • the semiconductor layer 302 is configured as a polycrystalline semiconductor layer, without limitation thereon.
  • the semiconductor layer 302 may be configured as an amorphous semiconductor layer, or may be configured as a layer including a crystalline structure and amorphous structure.
  • FIG. 35C diagrammatically illustrates a doping layer forming step.
  • the dopant contained in the doping layer 314 may be of a conductive type, which is opposite to the conductive type of the dopant in the semiconductor substrate 10 .
  • the dopant in the doping layer 314 is a p-type dopant.
  • a group-III element such as boron (B), aluminum (Al), gallium (Ga), or indium (In)
  • the dopant in the doping layer 314 is an n-type dopant.
  • a group-V element such as phosphorus (P), arsenic (As), bismuth (Bi), or antimony (Sb), is used as the dopant in the doping layer 314 .
  • the dopant included in the doping layer 314 is introduced into the semiconductor layer 302 in the subsequent operation S 104 , causing the semiconductor layer 302 to form a pn junction with the semiconductor substrate 10 with the protective-film layer 202 interposed therebetween.
  • the concentration of the dopant included in the doping layer 314 ranges from 1 ⁇ 10 20 /cm 3 to 1 ⁇ 10 22 /cm 3 , and is greater than the concentration of a dopant in a first conductive area, which will be described in the subsequent step.
  • the doping layer 314 having the above concentration of dopant is configured as a semiconductor layer formed of amorphous silicon, and has a thickness within a range from 30 nm to 50 nm.
  • the doping layer 314 When the thickness is below 30 nm, while the doping layer 314 is irradiated with a laser, the doping layer 314 may fail to effectively absorb the laser, which causes damage to the protective-film layer 202 , which is thin. On the other hand, when the thickness is above 50 nm, the doping layer 314 may excessively absorb the laser, and thus the dopant may not be effectively introduced into the semiconductor layer 302 .
  • amorphous silicon has a high coefficient of absorption of light, as is well known, and thus is capable of reducing the strength of light by absorbing light penetrating the layer.
  • the dopant included in the doping layer 314 is selectively introduced into the semiconductor layer 302 by the laser. At this time, because the doping layer 314 configured as an amorphous semiconductor layer is irradiated with the laser, damage to the protective-film layer 202 , which is present beneath the semiconductor layer 302 and is thin, may be prevented.
  • the doping layer 314 may be formed via a deposition method that enables cross-sectional deposition, such as Plasma Enhanced Chemical Vapor Deposition (PECVD), because the doping layer 314 is an amorphous semiconductor layer containing the dopant and is formed only on the back surface of the semiconductor substrate 10 .
  • PECVD Plasma Enhanced Chemical Vapor Deposition
  • a mixture of silane gas, B 2 H 6 gas containing the dopant, or BCI 3 is used as source gas, the processing temperature is maintained within a range from 200° C. to 300° C., and the processing pressure is maintained within a range from 1 Torr to 4 Torr.
  • the doping layer 314 may be an oxide film containing the dopant, which is selectively formed of boron silicate glass (BSG) or phosphor silicate glass (PSG).
  • BSG boron silicate glass
  • PSG phosphor silicate glass
  • the semiconductor layer 302 including a first conductive dopant or a second conductive dopant may be formed using a dopant gas so that, instead of using the dopant layer, the dopant gas is introduced into the semiconductor layer via thermal diffusion or ion implantation.
  • FIG. 35D diagrammatically illustrates the first conductive area forming operation S 103 .
  • the first conductive area 32 is formed by directly irradiating the doping layer 314 with a laser. As illustrated in FIG. 35D , the entire doping layer 314 is not irradiated with the laser, but only a portion of the doping layer 314 , which has a first width S 1 corresponding to the first conductive area 32 , is selectively irradiated with the laser so that the remaining portion of the doping layer 314 , which has a second width S 2 , is not irradiated with the laser. In the doping layer 314 irradiated with the laser, the dopant included in the doping layer 314 thermally diffuses into the semiconductor layer 302 , whereby the first conductive area 32 is formed. Then, the doping layer 314 irradiated with the laser is removed.
  • the first conductive area 32 is formed using the laser as described above, for example, a process of masking the doping layer 314 in order to selectively introduce the dopant included in the doping layer 314 into the semiconductor layer 302 may be omitted, which may simplify the manufacturing process and may reduce manufacturing costs.
  • the semiconductor substrate 10 forms a pn junction with the first conductive area 32 with the protective-film layer 202 interposed therebetween.
  • the concentration of the dopant in the first conductive area 32 ranges from 1 ⁇ 10 20 /cm 3 to 1 ⁇ 10 22 /cm 3 , and is substantially the same as the concentration of the dopant in the doping layer 314 .
  • the crystalline structure of the semiconductor layer 302 may vary based on the properties of the laser. That is, when the intrinsic semiconductor layer 302 is an amorphous semiconductor layer, the amorphous semiconductor layer may be crystallized via laser irradiation, thereby being changed into a crystalline semiconductor layer. In addition, when the intrinsic semiconductor layer 302 is a polycrystalline semiconductor layer, the degree of crystallization of an area formed via laser irradiation may be higher than the degree of crystallization of an area formed via deposition. In this area, the size of grains may be increased.
  • the residual doping layer 314 a over the semiconductor layer 302 is removed.
  • dry etching such as Reactive Ion Etching (RIE)
  • “Dipping” is an etching method of immersing the entire semiconductor substrate 10 in a tub in which an etchant is stored. When removing the residual doping layer 314 a by dipping the same in the etchant, a portion of the front surface of the semiconductor substrate 10 may be removed at the same time.
  • FIG. 35E diagrammatically illustrates wet etching in which the residual doping layer 314 a is removed by dipping.
  • FIG. 35F diagrammatically illustrates this step.
  • the mask layer 315 is formed over the entire surface of the semiconductor layer 302 so as to protect the semiconductor layer 302 while the front surface of the semiconductor substrate 10 is textured.
  • the mask layer 315 prevents a dopant from being introduced into the first conductive area 32 when the dopant is introduced into the undoped area 33 in order to form a second conductive area in the subsequent process.
  • the mask layer 315 may be formed of a material that includes no foreign substance, which serves as a dopant. That is, the mask layer 315 may be formed of any of various materials capable of preventing the introduction of the foreign substance.
  • the mask layer 315 is a silicon carbide (SiC) film that effectively blocks the introduction of a dopant, and has a thickness within a range from 100 nm to 200 nm.
  • the silicon carbide film is easily removed by laser ablation, and is easily removed using a dilute hydrofluoric acid (HF) solution because it is changed to an oxide in the subsequent step. This will be described below in detail with regard to the corresponding step.
  • HF dilute hydrofluoric acid
  • the mask layer 315 is only formed over the semiconductor layer 302 , and is not formed on the textured front surface of the semiconductor substrate 10 .
  • the mask layer 315 may be formed via any of various methods that enable cross-sectional deposition.
  • the mask layer 315 may be formed via a PECVD method that enables cross-sectional deposition.
  • the surface of the semiconductor substrate 10 may be effectively textured.
  • KOH+ is shown, unlike FIG. 35E .
  • an exposing area 315 a is formed in the mask layer 315 so as to expose a portion of the undoped area 33 .
  • the exposing area corresponds to the second conductive area 34 , and the mask layer 315 prevents the dopant from entering the first conductive area 32 and the barrier area 33 in the subsequent doping process of forming the second conductive area 34 .
  • FIG. 35G diagrammatically illustrates a mask layer patterning step.
  • the exposing area 315 a is formed by selectively irradiating the mask layer 315 with a laser so that a portion of the mask layer 315 is subjected to laser ablation.
  • the laser is a pulse-type laser, of which the pulse width is adjusted, and has an energy of 0.5 J/cm 2 to 2.5 J/cm 2 , a frequency of 10 KHz to 100 KHz, a pulse width of 160 ns to 200 ns (nanoseconds), and a wavelength of 350 nm to 600 nm.
  • the pulse-type laser meeting these conditions is the same as the laser used in the above-described first conductive area forming operation S 104 , but has a great difference only in terms of the pulse width.
  • the laser facility used in the above first conductive area forming operation S 104 may also be used in this step, which may reduce manufacturing costs and may simplify the process.
  • a laser of which the pulse width is wider than that of the laser, which is used in the above-described operation S 103 , may be used.
  • the exposing area 315 a may be more accurately formed at a desired position, and the number of processes may be reduced.
  • the barrier area 33 is located between the first conductive area 32 and the second conductive area 34 , thereby preventing shunts between the first conductive area 32 and the second conductive area 34 , which are of different conductive types.
  • the second conductive area 34 is formed by introducing a dopant into the undoped area 33 of the semiconductor layer, which is exposed through the exposing area 315 a in the masking layer 315 , on the back surface of the semiconductor substrate 10 .
  • the front-surface field area 130 may be formed on the front surface simultaneously with the formation of the second conductive area 34 .
  • FIG. 35H diagrammatically illustrates this step.
  • the dopant is the first conductive dopant, which is the same as that used in the semiconductor substrate 10 .
  • the first conductive dopant is an n-type dopant including a group-V element, such as phosphorus (P), arsenic (As), bismuth (Bi), or antimony (Sb).
  • the first conductive dopant is a p-type dopant including a group-III element, such as boron (B), aluminum (Al), gallium (Ga), or indium (In).
  • the second conductive area 34 and the front-surface field area 130 may be formed at the same time by thermally diffusing the first conductive dopant in a gas atmosphere including the first conductive dopant.
  • a gas atmosphere including the first conductive dopant Any of various gases including the first conductive dopant may be used as the gas atmosphere.
  • the first conductive dopant is an n-type, phosphoryl chloride (POCl 3 ) is used.
  • the first conductive dopant thermally diffuses from the back surface of the semiconductor substrate 10 to the undoped area 33 through the exposing area 315 a , whereby the second conductive area 34 is formed, and the first conductive area 32 is protected by the mask layer 315 .
  • the undoped area 33 between the first conductive area 32 and the second conductive area 34 is masked by the mask layer 315 while the dopant is introduced, no dopant is introduced into the undoped area 33 , whereby the barrier area 33 is formed as an intrinsic semiconductor layer.
  • the doping concentration of the second conductive area 34 is the same as that of the first conductive area 32 .
  • the first conductive dopant which is of the same conductive type as the dopant introduced into the semiconductor substrate 10 , is introduced into the front surface of the semiconductor substrate 10 , whereby the front-surface field area 130 is formed.
  • the doping concentration of the front-surface field area 130 ranges from 1 ⁇ 10 17 /cm 3 to 1 ⁇ 10 20 /cm 3 , which is lower than that of the second conductive area 34 .
  • the semiconductor substrate 10 on which the front-surface field area 130 has been formed, is a monocrystalline semiconductor layer, and the semiconductor layer 302 , on which the second conductive area 34 has been formed, is a crystalline semiconductor layer.
  • the semiconductor substrate 10 and the semiconductor layer 302 have different doping concentrations.
  • the second conductive area 34 and the front-surface field area 130 may be formed separately.
  • the front surface of the semiconductor substrate 10 may be protected by a protective film.
  • the protective film may be removed, and a second conductive dopant may be introduced only into the front surface of the semiconductor substrate 110 so as to sequentially form the front-surface field area 130 .
  • cross-sectional doping may be easily performed, and for example, the doping depth and the doping profile of the front-surface field area 130 may be easily controlled.
  • a front-surface field area 130 having desired properties may be formed.
  • FIGS. 35I to 35K diagrammatically illustrate this step.
  • the front insulation film 24 and the anti-reflection film 26 are sequentially formed over the front-surface field area 130 on the front surface of the semiconductor substrate 10 , and the back insulation film 40 formed of an insulation material is formed over the semiconductor layer 302 on the back surface of the semiconductor substrate 10 .
  • the insulation material may be a thin film formed of a silicon oxide (SiOx), a silicon nitride (SiNx), a silicon oxide nitride (SiNxOy), or a silicon carbide (SiC).
  • SiOx silicon oxide
  • SiNx silicon nitride
  • SiNxOy silicon oxide nitride
  • SiC silicon carbide
  • the insulation films may be formed via any of various methods, such as, for example, vacuum deposition, chemical vapor deposition, spin coating, screen printing, or spray coating.
  • the insulation films may be formed via a PECVD method that enables cross-sectional deposition.
  • the insulation film 24 and the anti-reflection film 26 may be formed using different source gases within the same chamber via an in-situ process.
  • a PECVD method may be used to form the insulation film 40 on only the back surface.
  • the process of forming the front insulation film 24 and the anti-reflection film 26 and the process of forming the insulation film 40 may be an in-situ process.
  • the insulation films have been described as being first formed on the front surface of the semiconductor substrate 10 , and then being formed to cover the back surface of the semiconductor substrate 10 .
  • the exposure of the first conductive area 32 and the second conductive area 34 to heat is minimized, deterioration in properties or damage may be prevented to the maximum extent.
  • FIGS. 35L and 35M diagrammatically illustrate the contact hole forming operation S 106 .
  • the first contact hole 40 a formed in the back insulation film 40 exposes a portion of the first conductive area 32 and the second contact hole 40 b exposes a portion of the second conductive area 34 .
  • Each of the first contact hole 40 a and the second contact hole 40 b may take the form of a slit, which is elongated in the longitudinal direction of the first conductive area 32 or the second conductive area 34 , or may form an arrangement of a plurality of circles, ovals or polygons, which are spaced apart from one another.
  • a stripped arrangement of the first contact hole 40 a and the second contact hole 40 b is formed on the first conductive area 32 and the second conductive area 34 , which are alternately arranged.
  • the exposed areas of the first and second conductive areas 32 and 34 in which the first and second contact holes 40 a and 40 b are formed, have first and second contact-hole surface roughnesses R 1 and R 2 respectively.
  • the first contact hole 40 a and the second contact hole 40 b are formed via laser ablation.
  • a laser used in operation S 106 may have a frequency of 400 KHz and a power of 0.5 watts to 2 watts so as to be suitable for the openings 40 a and 40 b having a width within a range from 15 ⁇ m to 30 ⁇ m, and also may have a pico-second (ps) pulse width in consideration of the fact that the width of the openings 40 a and 40 b ranges from 10 ⁇ m to 20 ⁇ m, in order to facilitate laser ablation.
  • ps pico-second
  • the surfaces of the first and second conductive areas 32 and 34 provided with the contact holes 40 a and 40 b have marks, which distinguish the corresponding areas from the remaining area, formed thereon by the laser used in the contact hole forming step. That is, the surfaces of the first and second conductive areas 32 and 34 provided with the contact holes 40 a and 40 b undergoes variation in the crystalline structure thereof depending on the strength of the laser because the crystal grains in the surface of the semiconductor layer 302 are melted and re-crystallized, thereby having first and second contact-hole surface roughnesses R 1 and R 2 , which include changed surface roughnesses.
  • the contact holes 40 a and 40 b may be formed via any of various methods, such as wet etching or dry etching.
  • the areas of the semiconductor layer 302 in which the contact holes 40 a and 40 b are formed are changed in shape, thereby being formed with marks that distinguish the corresponding areas from the remaining area.
  • grooves may be formed in the substrate in the corresponding areas, or the corresponding areas may have the first and second contact-hole surface roughnesses R 1 and R 2 , which are the same as those acquired via laser irradiation.
  • the marks of the contact holes are not formed through an insulation film removal process using a photoresist, and as illustrated in the enlarged circles of FIG. 35L , convex-concave portions having a predetermined size are formed on the contact-hole areas of the first conductive area 32 and the second conductive area 34 .
  • the convex-concave portions typically have a height or width of 500 nm or less.
  • FIGS. 35N to 35O diagrammatically illustrate the electrode forming operation S 107 .
  • the electrode layer 400 is formed throughout the first conductive area 32 , the second conductive area 34 , and the back insulation film 40 through the first contact hole 40 a and the second contact hole 40 b . Because the electrode layer 400 needs to be brought into contact with the first conductive area 32 through the first contact hole 40 a , and also needs to be brought into contact with the second conductive area 34 through the second contact hole 40 b , the electrode layer 400 is formed of a conductive material.
  • the electrode layer 400 may be formed using a multilayered metal via a sputtering method.
  • the thickness of the electrode layer 400 may be 1 ⁇ m or less.
  • the thickness of the electrode layer 400 is above 850 nm, the transfer of the first and second contact-hole surface roughnesses R 1 and R 2 to the surfaces of the first and second electrodes 41 and 42 may be difficult. Because screen printing using paste or electroplating has conventionally been used in the process of filling the contact holes with an electrode having a thickness of tens of micrometers, the profile of the contact hole does not remain on the surface of the electrode.
  • the electrode layer 400 may have a multilayered structure.
  • the electrode layer 400 may have a four layered structure including a first titanium layer, an aluminum layer, a second titanium layer, and a nickel-vanadium alloy layer.
  • the first titanium layer has a thickness of 50 nm or less
  • the aluminum layer has a thickness of 550 nm or less
  • the second titanium layer has a thickness of 150 nm or less
  • the nickel-vanadium alloy layer has a thickness of 250 nm or less.
  • the present invention is not limited thereto, and various other metals may be used.
  • the electrode layer 400 is formed via deposition, such as, for example, an electron beam method or a spluttering method.
  • deposition such as, for example, an electron beam method or a spluttering method.
  • the profile of the contact hole is imprinted on the electrode surface.
  • the first and second electrodes 42 and 44 formed in the contact holes 40 a and 40 b for electrode contact are formed to have a small thickness via sputtering, the surface roughness of the surfaces of the first and second conductive areas 32 and 34 provided with the contact holes 40 a and 40 b is transferred to the first and second electrodes 42 and 44 , whereby the first and second electrodes 42 and 44 are provided with first and second convex-concave interfaces R 1 and R 2 .
  • the reflectiveness of the first and second electrodes 32 and 34 may be increased. Because the surface roughness is visible from the cell electrode side, an electrode patterning process may be performed at an accurate position using the profile of the contact hole imprinted on the electrode without requiring a separate alignment key in the subsequent patterning process.
  • the electrode layer 400 may be formed via evaporation, which is capable of realizing excellent operation coverage.
  • evaporation the surface roughnesses of the first and second conductive areas 32 and 34 exposed through the contact holes 40 a and 40 b may be more effectively transferred to the first and second electrodes 42 and 44 .
  • the electrode layer 400 is patterned so as to be brought into contact with each of the first conductive area 32 and the second conductive area 34 while separating the first conductive area 32 and the second conductive area 34 from each other.
  • Various known patterning methods may be used.
  • the profile of the contact hole imprinted on the electrode surface may be used for alignment during the separation process.
  • the solar cell panel according to the present embodiment may include the solar cell 100 according to the above-described embodiments. Thus, a repeated description may be omitted.
  • FIG. 36 is a perspective view illustrating a solar cell panel according to an embodiment of the present invention
  • FIG. 37 is a cross-sectional view taken along line II-II of FIG. 36 .
  • the solar cell panel 200 includes a plurality of solar cells 101 and 102 , and interconnectors 242 for electrically interconnecting the solar cells 101 and 102 .
  • the solar cell panel 200 includes a sealing member 230 for surrounding and sealing the solar cells 101 and 102 and the interconnectors 242 for interconnecting the solar cells 101 and 102 , a front substrate 210 disposed on the front surface of the solar cells 101 and 102 above the sealing member 230 , and a back substrate 220 disposed on the back surface of the solar cells 101 and 102 above the sealing member 230 . This will be described below in more detail.
  • the solar cells 101 and 102 may be substantially the same as the solar cell 100 according to the above-described embodiments. Thus, a repeated description is omitted.
  • the solar cells 101 and 102 may be electrically interconnected in series and/or in parallel by the interconnectors 242 .
  • the interconnectors 242 may electrically interconnect two neighboring solar cells 101 and 102 among the solar cells 101 and 102 .
  • each interconnector 242 may include a core layer 142 a , which is formed of a metal, and a solder layer, which is coated over the surface of the core layer at a small thickness and includes a solder material so as to enable soldering with the first and second electrodes 42 and 44 of FIG. 1 .
  • the core layer may include Ni, Cu, Ag or Al as a main material
  • the solder layer may be formed of an alloy including at least one of tin, lead, silver, bismuth, and indium.
  • the solar cell includes the first and second electrodes 42 and 44 , each of which has the surface roughness described above in the embodiment of FIG. 32 . That is, each of the first and second electrodes 42 and 44 may include a first convex-concave portion at the interface thereof with the first or second conductive area 32 or 34 , and the first convex-concave portion may be the same as the surface roughness. In addition, each of the first and second electrodes 42 and 44 may have a second convex-concave portion on the outermost surface thereof on the opposite side of the interface, the second convex-concave portion corresponding to the first convex-concave portion.
  • the interconnectors 242 are disposed on the first and second electrodes 42 and 44 each having the surface roughness.
  • the surface area of the first and second electrodes 42 and 44 is increased owing to the surface roughness, which may increase bonding between the interconnectors 242 and the first and second electrodes 42 and 44 .
  • the interconnectors 242 may be bonded to the electrodes of the solar cells 101 and 102 using a conductive adhesive, which is provided on the outermost surface of each of the electrodes 42 and 44 , on which the second convex-concave portion is formed.
  • bonding between the interconnectors 242 and the first and second electrodes 42 and 44 may be increased by the surface roughnesses of the first and second electrodes 42 and 44 .
  • the interconnectors 242 may include a first conductive interconnector connected to the first electrode of the first solar cell 101 , a second conductive interconnector connected to the second electrode of the second solar cell 102 , and a third conductive interconnector for interconnecting the first conductive interconnector and the second conductive interconnector.
  • the first conductive interconnector is electrically connected to the first electrode of the first solar cell 101 via a conductive adhesive layer and is insulated from the second electrode via an insulation layer.
  • the second conductive interconnector is electrically connected to the second electrode of the second solar cell 102 via a conductive adhesive layer and is insulated from the first electrode via an insulation layer.
  • the first interconnector, the second interconnector, and the third interconnector may be integrated with each other, or may be successively connected to one another.
  • the solar cells 101 and 102 may have different arrangements.
  • the insulation layer or the conductive adhesive layer is formed between the conductive interconnector and the electrode. At this time, when the electrode surface is provided with a convex-concave portion, the insulation layer or the conductive adhesive layer may come into contact with the convex-concave portion of the electrode, which may increase bonding force, and consequently the properties of the module.
  • the interconnectors may be bonded respectively to the first electrode and the second electrode formed on the back surface of the solar cells 101 and 102 .
  • the interconnectors need to be connected to all cell electrode. In this instance, bonding force may be increased, and the efficiency of the solar cell may be improved.
  • Bus ribbons 145 are interconnected by the interconnectors 242 so as to interconnect alternate ends of the interconnectors 242 , which interconnect the solar cells 101 and 102 in a column (in other words, a solar cell string).
  • the bus ribbons 145 may be located on the ends of the solar cell strings so as to cross the solar cell string.
  • the bus ribbons 145 may interconnect the solar cell strings adjacent to each other, or may connect the solar cell string(s) to a junction box, which prevents the backflow of current.
  • the material, shape, connection structure, and the like of the bus ribbons 145 may be altered in various ways, and the present invention is not limited as to them.
  • the sealing member 230 may include a first sealing member 231 disposed on the front surface of the solar cells 101 and 102 , and a second sealing member 232 disposed on the back surface of the solar cells 101 and 102 .
  • the first sealing member 231 and the second sealing member 232 prevent the introduction of moisture and oxygen, which may have a negative effect on the solar cells 101 and 102 , and realize a chemical bond between respective elements of the solar cell panel 200 .
  • the solar cell panel 200 may be integrated through a lamination process that applies heat and/or pressure in the state in which the front substrate 210 , the first sealing member 231 , the solar cells 101 and 102 , the second sealing material 232 , and the back substrate 220 are sequentially stacked one above another.
  • the first and second sealing members 231 and 232 may be formed of ethylene vinyl acetate (EVA) copolymer resin, polyvinyl butyral, silicone resin, ester-based resin, or olefin-based resin.
  • EVA ethylene vinyl acetate
  • the present invention is not limited thereto.
  • the first and second sealing members 231 and 232 may be formed using any of various materials via any of various methods, rather than lamination.
  • the first and second sealing members 231 and 232 may have light transmittance, thus allowing light introduced through the front substrate 210 or light reflected by the front substrate 210 to reach the solar cells 101 and 102 .
  • the front substrate 210 is disposed on the first sealing member 231 and configures the front surface of the solar cell panel 200 .
  • the front substrate 210 may be formed of a light-transmitting material capable of transmitting light and may have a strength required to protect the solar cells 101 and 102 from external shocks, etc.
  • the front substrate 210 may be configured as a glass substrate.
  • the front substrate 210 may be configured as a tempered glass substrate in order to increase the strength thereof.
  • the front substrate 210 may additionally include various materials capable of improving various properties.
  • the front substrate 210 may be a sheet or a film formed of, for example, a resin. That is, the present invention is not limited as to the material of the front substrate 210 , and the front substrate 210 may be formed of any of various materials.
  • the back substrate 220 may be disposed on the second sealing material 232 and may serve as a layer that is disposed on the back surface of the solar cells 101 and 102 so as to protect the solar cells 101 and 102 .
  • the back substrate 220 may have waterproofing, insulation, and ultraviolet blocking functions.
  • the back substrate 220 may have a strength required to protect the solar cells 101 and 102 from external shocks, etc., and may transmit or reflect light depending on the structure of the solar cell panel 200 .
  • the back substrate 220 in the structure of introducing light through the back substrate 220 , the back substrate 220 may be formed of a light-transmitting material.
  • the back substrate 220 In the structure of reflecting light from the back substrate 220 , the back substrate 220 may be formed of a light-reflecting material, or a material that does not transmit light.
  • the back substrate 220 may be configured as a glass substrate, or may be configured as a film or sheet.
  • the back substrate 220 may be of a Tedlar/PET/Tedlar (TPT) type, or may be formed of a polyvinylidene fluoride (PVDF) resin formed on at least one surface of polyethylene terephthalate (PET).
  • PVDF polyvinylidene fluoride
  • PET polyethylene terephthalate
  • Polyvinylidene is a polymer having the structure of (CH 2 CF 2 )n, which is a double fluorine molecular structure, and thus has excellent mechanical, weather-proofing, and ultraviolet-resistant properties.
  • the present invention is not limited as to the material of the back substrate 220 .
  • a semiconductor layer which forms an emitter and a back-surface field (BSF) is re-crystallized when it is irradiated with a laser.
  • each of the emitter and the BSF may include a second crystalline area having improved crystallinity, which may increase the efficiency of a solar cell.

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CN117712199A (zh) 2022-09-08 2024-03-15 浙江晶科能源有限公司 太阳能电池及光伏组件

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