TWI787470B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TWI787470B
TWI787470B TW108106302A TW108106302A TWI787470B TW I787470 B TWI787470 B TW I787470B TW 108106302 A TW108106302 A TW 108106302A TW 108106302 A TW108106302 A TW 108106302A TW I787470 B TWI787470 B TW I787470B
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well region
doping type
drain
substrate
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TW202004857A (zh
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王猛
杜益成
喻慧
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大陸商矽力杰半導體技術（杭州）有限公司
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Abstract

本申請公開了一種半導體裝置及其製造方法，該製造方法包括：在第一摻雜類型的基板中形成具有與第一摻雜類型相反的第二摻雜類型的第一阱區，第一阱區圍繞基板的第一區域；在第一區域中形成具有第二摻雜類型的源極區與汲極區；以及在基板中形成具有第二摻雜類型的埋層，埋層位於第一區域的下方，與第一阱區相連；其中，埋層與第一阱區共同包圍第一區域。該半導體裝置及其製造方法的有益效果是，可以省去製作接面深度較大的阱區的步驟，實現了LDMOS製程與CMOS等其他製程結合的目的，還可以同時提升裝置的擊穿電壓BV和導通電阻Rdson的性能。

Description

半導體裝置及其製造方法
本發明係有關半導體裝置製造領域，尤其是一種半導體裝置及其製造方法。
功率開關可以是半導體裝置，包括金屬-氧化物半導體場效電晶體(Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET)和絕緣閘極雙極電晶體(Insulated Gate Bipolar Transistor, IGBT)等。橫向擴散金屬氧化物半導體(Laterally Diffused Metal Oxide Semiconductor, LDMOS)被廣泛地用在開關型調節器中。 圖1示出了現有技術中的LDMOS結構示意圖。 如圖1所示，摻雜類型為N型的阱區102製作在基板101中，體區109與漂移區110均位於阱區102中，源極區115形成在體區109中，汲極區116形成在漂移區110中。由於漂移區110的存在，汲極116可以承受高電壓。因此，LDMOS電晶體具有大驅動電流、低導通電阻和高擊穿電壓的優點，廣泛地用於開關型調節器。 然而，現有技術中的阱區102通常需要較大的接面深度，因此，阱區102需要單獨完成製作，不能與CMOS等其他製程結合。 此外，由於為了降低LDMOS的導通電阻Rdson，漂移區110的摻雜濃度不能過低，而為了增加LDMOS的擊穿電壓BV，漂移區110的摻雜濃度又不能過高，這使得現有的LDMOS裝置的擊穿電壓BV和導通電阻Rdson的性能不能均得到最大的提升。
有鑑於此，本公開提供了一種半導體裝置及其製造方法，可以省去製作接面深度較大的阱區的步驟，實現了LDMOS製程與CMOS等其他製程結合的目的，還可以同時提升裝置的擊穿電壓BV和導通電阻Rdson的性能。 根據本公開的一方面，提供了一種半導體裝置的製造方法，包括：在第一摻雜類型的基板中形成具有與第一摻雜類型相反的第二摻雜類型的第一阱區，所述第一阱區圍繞所述基板的第一區域；在所述第一區域中形成具有第二摻雜類型的源極區與汲極區；以及在所述基板中形成具有第二摻雜類型的埋層，所述埋層位於所述第一區域的下方，與所述第一阱區相連；其中，所述埋層與所述第一阱區共同包圍所述第一區域。 較佳地，在形成所述汲極區的步驟之前，還包括在所述第一區域中形成具有第二摻雜類型的漂移區，其中，所述汲極區位於所述漂移區中。 較佳地，在形成所述源極區的步驟之前，還包括在所述第一區域中形成具有第一摻雜類型的體區，其中，所述源極區位於所述漂移區中。 較佳地，在形成所述漂移區的步驟之前，還包括在所述第一區域中形成具有第一摻雜類型的第一深阱區，其中，所述漂移區和所述體區位於所述第一深阱區中。 較佳地，其中，所述第一深阱區的摻雜濃度峰值位於所述漂移區的下方。 較佳地，在形成所述汲極區的步驟之前，還包括在所述基板上形成閘極結構，其中，至少部分所述第一深阱區位於所述源極區與所述汲極區之間的所述閘極結構的下方。 較佳地，形成所述閘極結構的步驟包括：在所述第一區域上形成高壓汲極氧化層；在所述基板上形成閘極氧化層，所述高壓汲極氧化層與所述閘極氧化層相連；以及在所述高壓汲極氧化層與所述閘極氧化層上形成閘極導體，所述閘極導體位於所述源極區與所述汲極區之間。 較佳地，形成所述閘極結構的步驟還包括在所述閘極導體兩端的側壁上形成側牆。 較佳地，在形成所述體區的步驟之後，還包括在所述體區中形成具有第一摻雜類型的體區摻雜區，所述體區摻雜區與所述源極區相連。 較佳地，所述第一摻雜類型為選自N型和P型之一，所述第二摻雜類型為N型和P型的另一種。 較佳地，還包括在所述基板上形成NMOS結構、PMOS結構以及PAMOS結構中的一種或者組合。 較佳地，所述NMOS結構、所述PMOS結構以及所述PAMOS結構中的至少一個具有形成於所述基板中的第二摻雜類型的第二阱區，所述第一阱區和所述第二阱區同步形成。 根據本公開的另一方面，提供了一種半導體裝置，包括：基板，其為第一摻雜類型；第一阱區，位於所述基板中，並圍繞所述基板的第一區域，所述第一阱區為與第一摻雜類型相反的第二摻雜類型；源極區與汲極區，均位於所述第一區域中，所述源極區與所述汲極區為第二摻雜類型；以及埋層，位於所述基板中，並位於所述第一區域的下方，與所述第一阱區相連，所述埋層為第二摻雜類型；其中，所述埋層與所述第一阱區共同包圍所述第一區域。 較佳地，還包括漂移區，位於所述第一區域中，所述漂移區為第二摻雜類型，其中，所述汲極區位於所述漂移區中。 較佳地，還包括體區，位於所述第一區域中，所述體區為第一摻雜類型，其中，所述源極區位於所述漂移區中。 較佳地，還包括第一深阱區，位於所述第一區域中，所述第一深阱區為第一摻雜類型，其中，所述漂移區和所述體區位於所述第一深阱區中。 較佳地，所述第一深阱區的摻雜濃度峰值位於所述漂移區的下方。 較佳地，還包括閘極結構，位於所述基板上，其中，至少部分所述第一深阱區位於所述源極區與所述汲極區之間的所述閘極結構的下方。 較佳地，所述閘極結構包括：高壓汲極氧化層，位於所述第一區域上；閘極氧化層，位於在所述基板上，與所述高壓汲極氧化層相連；以及閘極導體，位於所述高壓汲極氧化層與所述閘極氧化層上，所述閘極導體位於所述源極區與所述汲極區之間。 較佳地，所述閘極結構還包括側牆，位於所述閘極導體兩端的側壁上。 較佳地，還包括體區摻雜區，位於所述體區中與所述源極區相連，所述體區摻雜區為第一摻雜類型。 較佳地，所述第一阱區和所述埋層構成具有第一摻雜類型的腔體，所述腔體嵌在所述基板中。 較佳地，所述第一摻雜類型為選自N型和P型之一，所述第二摻雜類型為N型和P型的另一種。 較佳地，還包括位於所述基板上的NMOS結構、PMOS結構以及PAMOS結構中的一種或者組合。 根據本公開實施例的半導體裝置的結構及其製造方法，透過在將源汲極區製作在基板的第一區域中，並在基板中形成共同包圍第一區域的第一阱區與埋層，本公開的第一阱區與埋層取代了現有技術中接面深度較大的阱區，從而達到了第一阱區與CMOS等其他裝置的阱區共同形成的目的，實現了製程上的結合。 根據本公開實施例的半導體裝置的結構及其製造方法，透過在基板中形成摻雜類型與漂移區不同的第一深阱區，調整第一深阱區的摻雜濃度分佈，將第一深阱區的摻雜濃度峰值集中分佈在漂移區下方，折衷優化了半導體裝置的低壓側結構的擊穿電壓BV與導通電阻Rdson。 根據本公開實施例的半導體裝置的結構及其製造方法，透過調節漂移區的摻雜濃度，進一步折衷優化了擊穿電壓BV與導通電阻Rdson。 根據本公開實施例的半導體裝置的結構及其製造方法，僅透過在基板的第一區域下方形成與第一阱區相連的埋層，構成了包圍第一區域的腔體，從而形成了半導體裝置的高壓側結構，此外，利用第一阱區將埋層與基板上表面連通，將半導體裝置的高壓側結構於低壓側結構隔開，在不影響半導體裝置的導通電阻Rdson與擊穿電壓BV的前提下，保證了高壓側結構的正常工作。
為使本公開實施例的目的、技術方案和優點更加清楚，下面將結合本公開實施例的圖式，對本公開實施例的技術方案進行清楚、完整的描述。顯然所描述的實施例是本公開的一部分實施例，而不是全部的實施例。基於所描述的本公開的實施例，本領域普通技術人員在無需創造性勞動的前提下所獲得的所有其他實施例，都屬於本公開保護的範圍。 圖2A示出了本公開第一實施例的半導體裝置的結構示意圖。 如圖2A所示，本公開第一實施例的半導體裝置包括：高壓側結構與低壓側結構，高壓側結構與低壓側結構共用基板100與閘極氧化層420，其中，高壓側結構包括：基板100、第一阱區210、第一深阱區221、埋層230、第一體區311、第一漂移區312、第一高壓汲極氧化層411、閘極氧化層420、第一閘極導體431、第一側牆441、第一體區摻雜區511、第一源極區512、第一汲極區513以及第一輕摻雜汲極區(未示出)。低壓側結構包括：基板100、第二深阱區222、第二體區321、第二漂移區322、閘極氧化層420、第二高壓汲極氧化層412、第二閘極導體432、第二側牆442、第二體區摻雜區521、第二源極區522、第二汲極區523以及第二輕摻雜汲極區(未示出)。其中，基板100、第一深阱區221、第二深阱區222、第一體區311、第二體區321、第一體區摻雜區511以及第二體區摻雜區521為第一摻雜類型，第一阱區210、埋層230、第一漂移區312、第二漂移區322、第一源極區512、第一汲極區513、第二源極區522以及第二汲極區523為第二摻雜類型，第一摻雜類型與第二摻雜類型相反。第一摻雜類型為選自N型和P型之一，第二摻雜類型為N型和P型的另一種。 在本實施例中，基板100的摻雜類型為P型摻雜。 第一阱區210位於基板100中，並圍繞位基板100中的第一區域10，第一阱區210的一端與埋層230相連，另一端延伸至基板100表面。阱區210的摻雜類型為N型摻雜，摻雜物包括磷。 埋層230位於基板100中，並位於第一區域10下方且不與第一深阱區221接觸。埋層230的摻雜類型為N型摻雜，摻雜物包括磷。其中，埋層230與第一阱區210共同包圍第一區域10，形成一個N型摻雜的腔體結構，嵌入在基板100中。 第一深阱區221與第二深阱區222位於基板100中，其中，第一深阱區221位於第一區域10中。第一深阱區221與第二深阱區222的摻雜類型為P型摻雜，摻雜物包括硼。 第一體區311與第一漂移區312位於第一深阱區221中，且至少部分第一深阱區221位於第一體區311與第一漂移區312之間，第二體區321與第二漂移區322位於第二深阱區222中，且至少部分第二深阱區222位於第二體區321與第二漂移區322之間。第一體區311與第二體區321的摻雜類型為P型摻雜，摻雜物包括硼。第一漂移區312與第二漂移區322的摻雜類型為N型摻雜，摻雜物包括磷。 第一體區摻雜區511與第一源極區512相連並位於第一體區311中，第一汲極區513並位第一漂移區312中，第二體區摻雜區521與第二源極區522相連並位於第二體區321中，第二汲極區523並位第二漂移區322中，第一輕摻雜汲極區與第二輕摻雜汲極區分別位於第一汲極區513與第二汲極區523處。第一體區摻雜區511與第二體區摻雜區521的摻雜類型為P型摻雜，第一源極區512、第一汲極區513第二源極區522、第二汲極區523第一輕摻雜汲極區以及第二輕摻雜汲極區的摻雜類型為N型摻雜。其中，第一輕摻雜汲極區與第二輕摻雜汲極區的摻雜濃度小於第一汲極區513與第二汲極區523的摻雜濃度。 閘極氧化層420位於基板100上，第一高壓汲極氧化層411位於第一漂移區312上與閘極氧化層420相連，第一閘極導體431位於高壓汲極氧化層411與閘極氧化層420上，第一閘極導體431的一端延伸至第一源極區512與第一體區摻雜區511相連一側的相對一側的上方，另一端延伸至第一漂移區312上方，第一側牆441位於第一閘極導體431兩端的側壁上。其中，至少部分第一深阱區221位於第一源極區512與第一汲極區513之間的閘極結構的下方，進一步地，至少部分第一深阱區221位於第一體區311與第一漂移區312之間的閘極氧化層420下方。第二高壓汲極氧化層412位於第二漂移區322上與閘極氧化層420相連，第二閘極導體432位於高壓汲極氧化層412與閘極氧化層420上，第二閘極導體432的一端延伸至第二源極區522與第二體區摻雜區521相連一側的相對一側的上方，另一端延伸至第二漂移區322上方，第二側牆442位於第二閘極導體432兩端的側壁上。其中，至少部分第一深阱區221位於第一源極區512與第一汲極區513之間的閘極結構的下方，進一步地，至少部分第一深阱區221位於第一體區311與第一漂移區312之間的閘極氧化層420下方。第一閘極導體431與第二閘極導體432的材料包括多晶矽。 在本實施例的半導體裝置中，高壓側結構與低壓側結構的不同之處在於，高壓側結構比低壓側結構多一層埋層230，即高壓側結構的第一阱區210與埋層230共同包圍第一區域10，就可以構成高壓側結構，引入N型摻雜的埋層230可以在不影響裝置的擊穿電壓BV與導通電阻Rdson的前提下，保證高壓側結構的正常工作。此外，埋層230的引入可以基於之前的BCD製程架構並用很小的額外成本來進一步優化裝置的擊穿電壓BV與導通電阻Rdson。具體地，透過在半導體裝置中增加P型的第一深阱區221與第二深阱區222，可以使第一深阱區221與第二深阱區222的濃度峰值分佈集中在第一漂移區312與第二漂移區322下方，從而可以對低壓側結構的擊穿電壓BV與導通電阻Rdson進行折衷優化。進一步地，透過調節第一深阱區221與第二深阱區222的濃度分佈，可以在第一漂移區312於第二漂移區322下方提供充足的P型摻雜濃度，從而提升半導體裝置的擊穿電壓BV，進一步地，還可以提升第一漂移區312於第二漂移區322的摻雜濃度，對半導體裝置的擊穿電壓BV與導通電阻Rdson再一次進行折衷優化。 圖2B示出了本公開第一實施例的半導體裝置的製造方法流程示意圖，圖3A至圖3I示出了圖2B中各步驟的半導體裝置的結構示意圖。下面將結合圖2B至圖3I對本公開第一實施例的半導體裝置的製造方法進行具體說明。 在步驟S01中，在基板中形成N阱區/P阱區。具體地，如圖3A所示，透過離子注入的方式在基板100中形成第一阱區210。第一阱區210圍繞基板100的第一區域10，第一阱區210還用於接出在後續步驟中形成的埋層。其中，基板100的摻雜類型為P型摻雜。第一阱區210的摻雜類型為N型摻雜，摻雜物包括磷。在一些其他實施例中，第一阱區210的摻雜類型為P型摻雜。 在步驟S02中，在基板中形成深P阱區。具體地，如圖3B所示，透過離子注入的方式在基板100中形成第一深阱區221與第二深阱區222，其中，第一深阱區221位於第一區域10中，透過調節第一深阱區221與第二深阱區222的摻雜濃度來提升本實施例半導體裝置的擊穿電壓BV。其中，第一深阱區221與第二深阱區222的摻雜類型為P型摻雜，摻雜物包括硼。 在步驟S03中，在基板上形成場氧化層。具體地，利用矽局部氧化隔離(Local Oxidation of Silicon，LOCOS)技術在基板上形成場氧化層。 在步驟S04中，在深P阱區中形成漂移區。具體地，如圖3C所示，透過離子注入的方式分別在第一深阱區221與第二深阱區222中形成第一漂移區321與第二漂移區322，透過調節第一漂移區321與第二漂移區322的摻雜濃度來實現本實施例半導體裝置擊穿電壓BV與導通電阻Rdson的折衷優化。其中，第一漂移區321與第二漂移區322的摻雜類型為N型摻雜，摻雜物包括磷。 在步驟S05中，在基板上產生高壓汲極氧化層。具體地，如圖3D所示，用遮罩板限定第一高壓汲極區域與第二高壓汲極區域，並透過LOCOS技術在高壓汲極區域形成第一高壓汲極氧化層411與第二高壓汲極氧化層412。 在步驟S06中，在基板中形成埋層。具體地，如圖3E所示，透過離子注入的方式在基板100中的第一區域10形成埋層230，埋層230位於第一深阱區221下方且不與第一深阱區221接觸。第一阱區210環繞第一深阱區221，第一阱區210的一端與埋層230相連，另一端延伸至基板100表面。埋層230的摻雜類型為N型摻雜，摻雜物包括磷。 在步驟S07中，在基板上形成閘極氧化層。具體地，如圖3F所示，在基板100上形成閘極氧化層420，閘極氧化層420分別與第一高壓汲極氧化層411與第二高壓汲極氧化層412相連。 在步驟S08中，在閘極氧化層與高壓汲極氧化層上形成多晶矽閘極。具體地，如圖3G所示，在閘極氧化層420以及與之相連的第一高壓汲極氧化層411上形成第一閘極導體431，在閘極氧化層420以及與之相連的第二高壓汲極氧化層412上形成第二閘極導體432，其中，第一閘極導體431與第二閘極導體432的材料包括多晶矽閘極。 在步驟S09中，在深P阱區中形成體區。具體地，如圖3H所示，透過離子注入的方式分別在第一深阱區221中形成第一體區311、在第二深阱區222中形成第二體區321，使得至少部分第一深阱區221位於第一體區311與第一漂移區312之間，至少部分第二深阱區222位於第二體區321與第二漂移區322之間，在第一體區311與第二體區321的摻雜濃度決定了本實施例半導體裝置的閾值。其中，第一體區311與第二體區321的摻雜類型為P型摻雜，摻雜物包括硼。 在步驟S010中，在體區中形成輕摻雜汲極區。具體的，如圖3H所示，利用第一高壓汲極氧化層411與第一閘極導體431作為硬遮罩並透過離子注入的方式在本實施例半導體裝置的汲極區處形成輕摻雜汲極區。其中，輕摻雜汲極區的的摻雜類型為N型摻雜。 在步驟S011中，在多晶矽閘極側壁形成側牆。具體的，如圖3I所示，在第一閘極導體431的側壁形成第一側牆441，在第二閘極導體432的側壁形成第二側牆442。 在步驟S012中，分別在體區與漂移區中形成源極區與汲極區。具體的，如圖3I所示，利用第一高壓汲極氧化層411、第一閘極導體431以及第一側牆441作為硬遮罩並透過離子注入的方式分別在第一體區311形成相連的第一體區摻雜區511與第一源極區512，並在第一漂移區312處形成在處形成第一汲極區513。利用第二高壓汲極氧化層412、第二閘極導體432以及第二側牆442作為硬遮罩並透過離子注入的方式分別在第二體區321形成相連的第二體區摻雜區521與二第源極區522，並在第二漂移區322處形成在處形成第二汲極區523。 圖4示出了本公開第二實施例的半導體裝置的結構示意圖。 本公開第二實施例的半導體裝置包括：N型LDMOS、NMOS、PMOS以及PAMOS。在本實施例中，基板100的摻雜類型為P型摻雜。 NLDMOS部分結構與第一實施例基本相同，此處不再贅述，不同之處在於，在第一阱區210中形成隔離區501。 NMOS包括：基板100、第一N阱區223(第二阱區)、第一P阱區330、閘極氧化層420、第三閘極導體433、第三體區摻雜區531、第三源極區532以及第三汲極區533。 第一N阱區223位於基板100中，第一P阱區330位於第一N阱區223中，第三體區摻雜區531、第三源極區532以及第三汲極區533位於第一P阱區330中，閘極氧化層420位於基板100上，第三閘極導體433位於第三源極區532與第三汲極區533之間的閘極氧化層420上。 PMOS包括：基板100、第二N阱區224(第二阱區)、閘極氧化層420、第四閘極導體434、第四體區摻雜區541、第四源極區542以及第四汲極區543。 第二N阱區224位於基板100中，第四體區摻雜區541、第四源極區542以及第四汲極區543位於第二N阱區224中，閘極氧化層420位於基板100上，第四閘極導體434位於第四源極區542與第四汲極區543之間的閘極氧化層420上。 PAMOS包括：基板100、第三N阱區225(第二阱區)、第二P阱區350、第三高壓汲極氧化層415、閘極氧化層420、第五閘極導體435、第五體區摻雜區551、第五源極區552以及第五汲極區553。 第三N阱區225位於基板100中，第二P阱區350位於第三N阱區225中，第五體區摻雜區551與第五源極區552位於第三N阱區225中，第五汲極區553第二P阱區350中。閘極氧化層420位於基板100上，第三高壓汲極氧化層415位於第二P阱區350上並與閘極氧化層420相連，第五閘極導體435位於第三高壓汲極氧化層415與閘極氧化層420上，第三高壓汲極氧化層415的一端延伸至第五源極區552上方，另一端延伸至第二P阱區350上方，其中，至少部分第三N阱區225位於第五源極區552與第五汲極區553之間的閘極結構的下方。 在本實施例中，第一阱區210的接面深度與第一N阱區223、第二N阱區224以及第三N阱區225的接面深度大致相同，因此可以在一道工序中共同形成。 圖5A至圖5H示出了圖4中本公開第二實施例的半導體裝置在製造時各步驟的結構示意圖。 如圖5A所示，透過離子注入的方式在基板100中形成第一阱區210、第一N阱區223、第二N阱區224以及第三N阱區225，透過離子注入的方式在第一N阱區223中形成第一P阱區330、在第三N阱區225中形成第二P阱區350。第一阱區210圍繞基板100的第一區域10，第一阱區210還用於接出在後續步驟中形成的埋層。其中，基板100的摻雜類型為P型摻雜。第一阱區210的摻雜類型為N型摻雜，摻雜物包括磷。在一些其他實施例中，第一阱區210的摻雜類型為P型摻雜。 如圖5B所示，透過離子注入的方式在基板100中形成第一深阱區221與第二深阱區222，其中，第一深阱區221位於第一區域10中，透過調節第一深阱區221與第二深阱區222的摻雜濃度來提升本實施例半導體裝置的擊穿電壓BV。其中，第一深阱區221與第二深阱區222的摻雜類型為P型摻雜，摻雜物包括硼。之後，在基板100上形成場氧化層(未示出)。具體地，利用LOCOS技術在基板100上形成場氧化層。 如圖5C所示，透過離子注入的方式分別在第一深阱區221與第二深阱區222中形成第一漂移區321與第二漂移區322，透過調節第一漂移區321與第二漂移區322的摻雜濃度來實現本實施例半導體裝置擊穿電壓BV與導通電阻Rdson的折衷優化。其中，第一漂移區321與第二漂移區322的摻雜類型為N型摻雜，摻雜物包括磷。 如圖5D所示，用遮罩板限定第一高壓汲極區域、第二高壓汲極區域以及第三高壓汲極區域，並透過LOCOS技術在高壓汲極區域形成第一高壓汲極氧化層411、第二高壓汲極氧化層412以及第三高壓汲極氧化層415。 如圖5E所示，透過離子注入的方式在基板100中形成埋層230，埋層230位於第一深阱區221下方且不與第一深阱區221接觸。第一阱區210環繞第一深阱區221，第一阱區210的一端與埋層230相連，另一端延伸至基板100表面。埋層230的摻雜類型為N型摻雜，摻雜物包括磷。 如圖5F所示，在基板100上形成閘極氧化層420，閘極氧化層420分別與第一高壓汲極氧化層411、第二高壓汲極氧化層412以及第三高壓汲極氧化層415相連。 如圖5G所示，在閘極氧化層420以及與之相連的第一高壓汲極氧化層411上形成第一閘極導體431，在閘極氧化層420以及與之相連的第二高壓汲極氧化層412上形成第二閘極導體432，在第一P阱區330上方的閘極氧化層420上第三閘極導體433，在第二N阱區224上方的閘極氧化層420上第四閘極導體434，在閘極氧化層420以及與之相連的第三高壓汲極氧化層451上形成第五閘極導體435，其中，第一閘極導體431、第二閘極導體432、第三閘極導體433、第四閘極導體434以及第五閘極導體435的材料包括多晶矽閘極。 如圖5H所示，透過離子注入的方式分別在第一深阱區221中形成第一體區311、在第二深阱區222中形成第二體區321，使得至少部分第一深阱區221位於第一體區311與第一漂移區312之間，至少部分第二深阱區222位於第二體區321與第二漂移區322之間，在第一體區311與第二體區321的摻雜濃度決定了本實施例半導體裝置的閾值。其中，第一體區311與第二體區321的摻雜類型為P型摻雜，摻雜物包括硼。 如圖5H所示，利用第一高壓汲極氧化層411與第一閘極導體431作為硬遮罩並透過離子注入的方式在本實施例半導體裝置的汲極區處形成輕摻雜汲極區。其中，輕摻雜汲極區的的摻雜類型為N型摻雜。 如圖5I所示，在第一閘極導體431的側壁形成第一側牆441，在第二閘極導體432的側壁形成第二側牆442。 如圖5I所示，利用第一高壓汲極氧化層411、第一閘極導體431以及第一側牆441作為硬遮罩並透過離子注入的方式分別在第一體區311形成相連的第一體區摻雜區511與第一源極區512，並在第一漂移區312處形成在處形成第一汲極區513，還在第一阱區210中形成隔離區501。利用第二高壓汲極氧化層412、第二閘極導體432以及第二側牆442作為硬遮罩並透過離子注入的方式分別在第二體區321形成相連的第二體區摻雜區521與二第源極區522，並在第二漂移區322處形成在處形成第二汲極區523。利用第三閘極導體532為硬遮罩在第一P阱區330中形成第三體區摻雜區531、第三源極區532以及第三汲極區533。利用第四閘極導體542為硬遮罩在第二N阱區224中形成第四體區摻雜區541、第四源極區542以及第四汲極區543。 利用第五高壓汲極氧化層415、第五閘極導體451作為硬遮罩並透過離子注入的方式分別在第三N阱區225中形成第五體區摻雜區551與第五源極區552，並在第二P阱區中形成在處形成第五汲極區513。 根據本公開第一與第二實施例的半導體裝置的結構及其製造方法，透過在將源汲極區製作在基板的第一區域中，並在基板中形成共同包圍第一區域的第一阱區與埋層，本公開的第一阱區與埋層取代了現有技術中接面深度較大的阱區，從而達到了第一阱區與CMOS等其他裝置的阱區共同形成的目的，實現了製程上的結合。 根據本公開第一與第二實施例的半導體裝置的結構及其製造方法，透過在基板中形成摻雜類型與漂移區不同的第一深阱區，調整第一深阱區的摻雜濃度分佈，將第一深阱區的摻雜濃度峰值集中分佈在漂移區下方，折衷優化了半導體裝置的低壓側結構的擊穿電壓BV與導通電阻Rdson。 根據本公開第一與第二實施例的半導體裝置的結構及其製造方法，透過調節漂移區的摻雜濃度，進一步折衷優化了擊穿電壓BV與導通電阻Rdson。 根據本公開第一與第二實施例的半導體裝置的結構及其製造方法，僅透過在基板的第一區域下方形成與第一阱區相連的埋層，構成了包圍第一區域的腔體，從而形成了半導體裝置的高壓側結構，即高壓側結構僅比低壓側結構多出一層埋層，此外，利用第一阱區將埋層與基板上表面連通，將半導體裝置的高壓側結構於低壓側結構隔開，在不影響半導體裝置的導通電阻Rdson與擊穿電壓BV的前提下，保證了高壓側結構的正常工作。 以上所述僅為本公開的較佳實施例，並不用於限制本公開，對於本領域技術人員而言，本公開可以有各種改動和變化。凡在本公開的精神和原理之內所作的任何修改、等同替換、改進等，均應包含在本公開的保護範圍之內。
10‧‧‧第一區域 100‧‧‧基板 101‧‧‧基板 102‧‧‧阱區 109‧‧‧體區 110‧‧‧漂移區 115‧‧‧源極區 116‧‧‧汲極區 210‧‧‧第一阱區 221‧‧‧第一深阱區 222‧‧‧第二深阱區 223‧‧‧第一N阱區 224‧‧‧第二N阱區 225‧‧‧第三N阱區 230‧‧‧埋層 311‧‧‧第一體區 312‧‧‧第一漂移區 321‧‧‧第二體區 322‧‧‧第二漂移區 330‧‧‧第一P阱區 350‧‧‧第二P阱區 411‧‧‧第一高壓汲極氧化層 412‧‧‧第二高壓汲極氧化層 415‧‧‧第三高壓汲極氧化層 420‧‧‧閘極氧化層 431‧‧‧第一閘極導體 432‧‧‧第二閘極導體 433‧‧‧第三閘極導體 434‧‧‧第四閘極導體 435‧‧‧第五閘極導體 441‧‧‧第一側牆 442‧‧‧第二側牆 501‧‧‧隔離區 511‧‧‧第一體區摻雜區 512‧‧‧第一源極區 513‧‧‧第一汲極區 521‧‧‧第二體區摻雜區 522‧‧‧第二源極區 523‧‧‧第二汲極區 531‧‧‧第三體區摻雜區 532‧‧‧第三源極區 533‧‧‧第三汲極區 541‧‧‧第四體區摻雜區 542‧‧‧第四源極區 543‧‧‧第四汲極區 551‧‧‧第五體區摻雜區 552‧‧‧第五源極區 553‧‧‧第五汲極區 S01‧‧‧步驟 S02‧‧‧步驟 S03‧‧‧步驟 S04‧‧‧步驟 S05‧‧‧步驟 S06‧‧‧步驟 S07‧‧‧步驟 S08‧‧‧步驟 S09‧‧‧步驟 S010‧‧‧步驟 S011‧‧‧步驟 S012‧‧‧步驟
為了更清楚地說明本公開實施例的技術方案，下面將對實施例的圖式作簡單介紹，顯而易見地，下面的描述中的圖式僅涉及本公開的一些實施例，而非對本公開的限制。 圖1示出了現有技術中的LDMOS結構示意圖。 圖2A示出了本公開第一實施例的半導體裝置的結構示意圖。 圖2B示出了本公開第一實施例的半導體裝置的製造方法流程示意圖。 圖3A至圖3I示出了圖2B中各步驟的半導體裝置的結構示意圖。 圖4示出了本公開第二實施例的半導體裝置的結構示意圖。 圖5A至圖5I示出了圖4中本公開第二實施例的半導體裝置在製造時各步驟的結構示意圖。
10‧‧‧第一區域
100‧‧‧基板
210‧‧‧第一阱區
221‧‧‧第一深阱區
222‧‧‧第二深阱區
230‧‧‧埋層
311‧‧‧第一體區
312‧‧‧第一漂移區
321‧‧‧第二體區
322‧‧‧第二漂移區
411‧‧‧第一高壓汲極氧化層
412‧‧‧第二高壓汲極氧化層
420‧‧‧閘極氧化層
431‧‧‧第一閘極導體
432‧‧‧第二閘極導體
441‧‧‧第一側牆
442‧‧‧第二側牆
511‧‧‧第一體區摻雜區
512‧‧‧第一源極區
513‧‧‧第一汲極區
521‧‧‧第二體區摻雜區
522‧‧‧第二源極區
523‧‧‧第二汲極區

Claims (24)

  1. 一種半導體裝置的製造方法，包括：在第一摻雜類型的基板中形成具有與第一摻雜類型相反的第二摻雜類型的第一阱區，所述第一阱區圍繞所述基板的第一區域；在所述第一區域中形成具有第一摻雜類型的第一深阱區；在所述第一區域中形成具有第二摻雜類型的源極區與汲極區；以及在所述基板中形成具有第二摻雜類型的埋層，所述埋層位於所述第一區域的下方，與所述第一阱區相連；其中，所述埋層與所述第一阱區共同包圍所述第一區域，以及其中，所述埋層不與所述第一深阱區接觸。
  2. 根據請求項1所述的製造方法，在形成所述汲極區的步驟之前，還包括在所述第一區域中形成具有第二摻雜類型的漂移區，其中，所述汲極區位於所述漂移區中。
  3. 根據請求項2所述的製造方法，在形成所述源極區的步驟之前，還包括在所述第一區域中形成具有第一摻雜類型的體區， 其中，所述源極區位於所述體區中。
  4. 根據請求項3所述的製造方法，在形成所述漂移區的步驟之前，還包括在所述第一區域中形成具有第一摻雜類型的所述第一深阱區，其中，所述漂移區和所述體區位於所述第一深阱區中。
  5. 根據請求項4所述的製造方法，其中，所述第一深阱區的摻雜濃度峰值位於所述漂移區的下方。
  6. 根據請求項4所述的製造方法，在形成所述汲極區的步驟之前，還包括在所述基板上形成閘極結構，其中，至少部分所述第一深阱區位於所述源極區與所述汲極區之間的所述閘極結構的下方。
  7. 根據請求項6所述的製造方法，其中，形成所述閘極結構的步驟包括：在所述第一區域上形成高壓汲極氧化層；在所述基板上形成閘極氧化層，所述高壓汲極氧化層與所述閘極氧化層相連；以及在所述高壓汲極氧化層與所述閘極氧化層上形成閘極導體，所述閘極導體位於所述源極區與所述汲極區之間。
  8. 根據請求項7所述的製造方法，其中，形成所述閘極結構的步驟還包括在所述閘極導體兩端的側壁上形成側牆。
  9. 根據請求項6所述的製造方法，在形成所述體區的步驟之後，還包括在所述體區中形成具有第一摻雜類型的體區摻雜區，所述體區摻雜區與所述源極區相連。
  10. 根據請求項1至9中任一項所述的製造方法，其中，所述第一摻雜類型為選自N型和P型之一，所述第二摻雜類型為N型和P型的另一種。
  11. 根據請求項10所述的製造方法，還包括在所述基板上形成NMOS結構、PMOS結構以及PAMOS結構中的一種或者組合。
  12. 根據請求項11所述的製造方法，其中，所述NMOS結構、所述PMOS結構以及所述PAMOS結構中的至少一個具有形成於所述基板中的第二摻雜類型的第二阱區，所述第一阱區和所述第二阱區同步形成。
  13. 一種半導體裝置，包括：基板，其為第一摻雜類型；第一阱區，位於所述基板中，並圍繞所述基板的第一 區域，所述第一阱區為與第一摻雜類型相反的第二摻雜類型；第一深阱區，位於所述第一區域中，所述第一深阱區為第一摻雜類型；源極區與汲極區，均位於所述第一區域中，所述源極區與所述汲極區為第二摻雜類型；以及埋層，位於所述基板中，並位於所述第一區域的下方，與所述第一阱區相連，所述埋層為第二摻雜類型；其中，所述埋層與所述第一阱區共同包圍所述第一區域，以及其中，所述埋層不與所述第一深阱區接觸。
  14. 根據請求項13所述的半導體裝置，還包括漂移區，位於所述第一區域中，所述漂移區為第二摻雜類型，其中，所述汲極區位於所述漂移區中。
  15. 根據請求項14所述的半導體裝置，還包括體區，位於所述第一區域中，所述體區為第一摻雜類型，其中，所述源極區位於所述體區中。
  16. 根據請求項15所述的半導體裝置，其中，所述漂移區和所述體區位於所述第一深阱區中。
  17. 根據請求項16所述的半導體裝置，其中，所述第一深 阱區的摻雜濃度峰值位於所述漂移區的下方。
  18. 根據請求項15所述的半導體裝置，還包括閘極結構，位於所述基板上，其中，至少部分所述第一深阱區位於所述源極區與所述汲極區之間的所述閘極結構的下方。
  19. 根據請求項18所述的半導體裝置，其中，所述閘極結構包括：高壓汲極氧化層，位於所述第一區域上；閘極氧化層，位於在所述基板上，與所述高壓汲極氧化層相連；以及閘極導體，位於所述高壓汲極氧化層與所述閘極氧化層上，所述閘極導體位於所述源極區與所述汲極區之間。
  20. 根據請求項19所述的半導體裝置，其中，所述閘極結構還包括側牆，位於所述閘極導體兩端的側壁上。
  21. 根據請求項18所述的半導體裝置，還包括體區摻雜區，位於所述體區中與所述源極區相連，所述體區摻雜區為第一摻雜類型。
  22. 根據請求項13所述的半導體裝置，其中，所述第一阱區和所述埋層構成具有第二摻雜類型的腔體，所述腔體嵌 在所述基板中。
  23. 根據請求項13至22中任一項所述的半導體裝置，其中，所述第一摻雜類型為選自N型和P型之一，所述第二摻雜類型為N型和P型的另一種。
  24. 根據請求項23所述的半導體裝置，還包括位於所述基板上的NMOS結構、PMOS結構以及PAMOS結構中的一種或者組合。
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