CN102054774B - Vdmos晶体管兼容ldmos晶体管及其制作方法 - Google Patents

Vdmos晶体管兼容ldmos晶体管及其制作方法 Download PDF

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CN102054774B
CN102054774B CN2009102091875A CN200910209187A CN102054774B CN 102054774 B CN102054774 B CN 102054774B CN 2009102091875 A CN2009102091875 A CN 2009102091875A CN 200910209187 A CN200910209187 A CN 200910209187A CN 102054774 B CN102054774 B CN 102054774B
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transistor
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ldmos transistor
vdmos
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CN102054774A (zh
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桂林春
王乐
赵志勇
何丽丽
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CSMC Technologies Fab2 Co Ltd
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CSMC Technologies Corp
Wuxi CSMC Semiconductor Co Ltd
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Priority to EP10826075.3A priority patent/EP2437288A4/en
Priority to US13/384,002 priority patent/US8530961B2/en
Priority to JP2012524103A priority patent/JP5356598B2/ja
Priority to PCT/CN2010/078121 priority patent/WO2011050712A1/zh
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Abstract

一种VDMOS晶体管兼容LDMOS晶体管的制作方法，包括：提供具有LDMOS晶体管区和VDMOS晶体管区的衬底；在衬底内形成N埋层区域；在N埋层区域上形成外延层；在LDMOS晶体管区VDMOS晶体管区形成隔离区；在LDMOS晶体管区形成漂移区；在LDMOS晶体管区和VDMOS晶体管区形成栅极；在LDMOS晶体管区VDMOS晶体管区形成PBODY区；在LDMOS晶体管区形成N型GRADE区；在VDMOS晶体管区形成NSINK区，所述NSINK区与N埋层区域连通；在LDMOS晶体管区VDMOS晶体管区形成源极和漏极；在LDMOS晶体管区形成P+区，P+区与源极相接。本发明实现了高压和大电流的性能需求。

Description

VDMOS晶体管兼容LDMOS晶体管及其制作方法
技术领域
本发明涉及半导体器件的制造领域，尤其涉及一种VDMOS晶体管兼容LDMOS晶体管及其制作方法。
背景技术
随着半导体工艺技术的不断发展。BIPOLAR(双极)、CMOS(互补金属氧化物半导体场效应管)和DMOS(双扩散金属氧化物半导体场效应管)原本三个独立的分支不断的相互融合，逐步发展出了BIPOLAR与CMOS一起集成的BICMOS和三者共同集成的BCD工艺。采用Bipolar/CMOS/DMOS整合的BCD工艺，将通常有的3种不同的工艺类型结合起来：bipolar针对模拟控制；CMOS针对数字控制；DMOS针对处理在芯片或系统上管理中出现高电压大电流，实现系统的软启动和功率输出。由于BCD工艺综合了以上三种器件各自的优点，这使基于BCD的产品可以集成复杂的控制功能，使它已成为功率集成电路的主流工艺技术。对于BCD工艺可以针对不同的电路选择不同的器件来达到相应子电路的最优化，实现整个电路的低功耗、高集成度、高速度、高驱动能力、大电流的要求。
目前BCD工艺中出现的高压MOS晶体管都是以LDMOS(横向双扩散金属氧化物半导体)为主。现有BCD工艺中形成LDMOS晶体管的步骤如图1所示，提供衬底，所述衬底的材料可以是硅或硅锗等；向衬底内注入硼离子，形成N埋层区域101；采用外延法在N埋层区域101上形成N外延层；在N外延层上形成第一光刻胶层(未示出)，经过光刻工艺后，定义出N阱图形；以第一光刻胶层为掩膜，沿N阱图形向N外延层注入磷离子，形成N阱102；去除第一光刻胶后，在N外延层上形成第二光刻胶层(未示出)，经过光刻工艺后，定义出P阱图形；以第二光刻胶层为掩膜，沿P阱图形向N外延层注入硼离子，形成P阱103。
如图2所示，去除第二光刻胶层后，采用场氧化法在N阱102与P阱103交界处形成硅局部氧化隔离(LOCOS)区104；在N外延层上形成第三光刻胶层(未示出)，经过光刻工艺后，在P阱103区定义出漂移区图形；以第三光刻胶层为掩膜，沿漂移区图形向N外延层内注入磷离子，并进行退火工艺，形成漂移区106a；接着继续以第三光刻胶层为掩膜，采用湿氧热氧化法氧化漂移区106a的外延层，形成LOCOS场板106b。接着去除第三光刻胶层。
如图3所示，在N外延层上依次形成多晶硅层和第四光刻胶层(未示出)，经过曝光显影工艺后，在第四光刻胶层上定义出栅极图形；以第四光刻胶层为掩膜，沿栅极图形刻蚀多晶硅层，在P阱103区的部分N外延层和漂移区上形成栅极108。去除第四光刻胶层。
参考图4，在N外延层、硅局部氧化隔离(LOCOS)区104和栅极108上形成第五光刻胶层(未示出)，经过曝光显影工艺后，在P阱103区的栅极108和硅局部氧化隔离(LOCOS)区104之间的第五光刻胶层上定义出PBODY区(P型衬底浓度过渡区)图形；以第五光刻胶层为掩膜，沿PBODY区图形向N外延层内注入磷离子，形成PBODY区109，所述PBODY区109的作用为通过它与源/漏极横向扩散长度差形成有效沟道控制LDMOS的阈值电压。去除第五光刻胶层后，在N外延层、硅局部氧化隔离(LOCOS)区104和栅极108上形成第六光刻胶层(未示出)，经过曝光显影工艺后，在漂移区106之间的第六光刻胶层上定义出开口图形；以第六光刻胶层为掩膜，沿开口图形向N外延层内注入磷离子，并经过退火工艺后，使磷离子扩散均匀且深度加大，形成N型GRADE(浓度梯度)区110，所述GRADE区110的作用为在源/漏极外面形成低浓度的N型离子，降低PN结的掺杂浓度，提高结的击穿电压。去除第六光刻胶层。
如图5所示，在N外延层、硅局部氧化隔离(LOCOS)区104和栅极108上形成第七光刻胶层(未示出)，经过曝光显影工艺后，形成源/漏极图形；以第七光刻胶层为掩膜，沿源/漏极图形向N外延层内的PBODY区109和N型GRADE区110中注入磷离子，在PBODY区109内形成源极S，在N型GRADE区110内形成漏极D。继续参考图5，去除第七光刻胶层后，在N外延层、硅局部氧化隔离(LOCOS)区104和栅极108上形成第八光刻胶层(未示出)，经过光刻工艺后，定义出P+区图形；以第八光刻胶层为掩膜，沿P+区图形向N外延层内的PBODY区109注入硼离子，形成P+区112，所述P+区112与源极S相接，其作用为防止衬底电极与源极短接，减小衬偏效应。接着，去除第八光刻胶层。
但是，由于现有的BCD工艺平台中的高压MOS都是以LDMOS为主，而无法做到LDMOS与VDMOS(垂直双扩散金属氧化物半导体)同时兼容在同一个工艺平台上，既满足LDMOS的高耐压，又满足VDMOS的高电流驱动能力。
发明内容
本发明解决的问题是提供一种VDMOS晶体管兼容LDMOS晶体管的制作方法，防止BCD工艺无法兼容VDMOS晶体管和LDMOS晶体管。
为解决上述问题，本发明提供一种VDMOS晶体管兼容LDMOS晶体管的制作方法，包括：提供衬底，所述衬底具有LDMOS晶体管区和VDMOS晶体管区；向衬底注入离子，形成N埋层区域；在N埋层区域上形成外延层后，向外延层注入离子，在LDMOS晶体管区形成N阱和P阱，在VDMOS晶体管区形成高压N阱；在LDMOS晶体管区的N阱和P阱交界处及LDMOS晶体管区和VDMOS晶体管区交界处形成隔离区；在LDMOS晶体管区的P阱区域形成漂移区；在LDMOS晶体管区的P阱区域的部分外延层和部分漂移区上，以及在VDMOS晶体管区形成栅极；在LDMOS晶体管区的栅极和隔离区之间的外延层内，以及在VDMOS晶体管区的栅极之间的外延层内形成PBODY区；在LDMOS晶体管区的漂移区之间的外延层内形成N型GRADE区；在VDMOS晶体管区的隔离区与邻近栅极之间的外延层内形成NSINK区，所述NSINK区与N埋层区域连通；在LDMOS晶体管区的PBODY区内形成源极，在N型GRADE区内形成漏极，以及在VDMOS晶体管区的PBODY区内形成源极，在NSINK区内形成漏极；在LDMOS晶体管区的PBODY区形成P+区，所述P+区与源极相接。
可选的，所述形成NSINK区注入的离子为磷离子。所述注入离子的剂量为1×1015/cm2，能量为300KeV～400KeV。
可选的，所述形成N埋层区域注入的离子为锑离子，注入离子的剂量为1×1015/cm2，能量为40KeV。
可选的，所述形成漂移区还包括：向P阱局部区域注入磷离子，形成漂移区；在漂移区进行氧化工艺形成LOCOS场板。
可选的，所述注入磷离子的剂量为1×1012/cm2，能量为40KeV～50KeV。所述氧化漂移区的方法为湿氧热氧化法。
可选的，所述形成PBODY区注入的离子为硼离子，注入离子的剂量为2×1013/cm2，能量为40KeV。
可选的，所述形成N型GRADE区注入的离子为磷离子，注入离子的剂量为1×1013/cm2，能量为80KeV～100KeV。
可选的，所述形成源极/漏极注入的离子为砷离子，注入离子的剂量为4×1015/cm2，能量为80KeV。
可选的，所述形成P+区注入的离子为二氟化硼离子，注入离子的剂量为2×1015/cm2，能量为60KeV～80KeV。
本发明还提供一种VDMOS晶体管兼容LDMOS晶体管，包括：衬底，所述衬底具有LDMOS晶体管区和VDMOS晶体管区；位于衬底内的N埋层区域；位于N埋层区域上的外延层；在LDMOS晶体管区的N外延层内形成有N阱和与N阱相接的P阱；在VDMOS晶体管区形成有高压N阱；位于在LDMOS晶体管区的N阱和P阱交界处及LDMOS晶体管区和VDMOS晶体管区交界处的隔离区；位于LDMOS晶体管区的P阱区域的漂移区；位于LDMOS晶体管区的P阱区域的部分外延层和部分漂移区上，以及在VDMOS晶体管区的外延层上的栅极；位于LDMOS晶体管区栅极和隔离区之间的外延层内，以及位于VDMOS晶体管区的栅极之间的外延层内的PBODY区；位于LDMOS晶体管区漂移区之间的外延层内的N型GRADE区；位于LDMOS晶体管区和VDMOS晶体管区的PBODY区内的源极；位于LDMOS晶体管区的PBODY区内的P+区，所述P+区与源极相接；位于VDMOS晶体管区隔离区与邻近栅极之间的外延层内的NSINK区，所述NSINK区与N埋层区域连通；位于LDMOS晶体管区的N型GRADE区内和NSINK区内的漏极。
与现有技术相比，本发明具有以下优点：在VDMOS晶体管区的隔离区与邻近栅极之间的外延层内形成NSINK区，所述NSINK区与N埋层区域连通。使漏极之间连通，从而实现BCD工艺平台上LDMOS晶体管与VDMOS晶体管的兼容技术，进而实现了高压和大电流的性能需求。
附图说明
图1至图5是现有BCD工艺中形成LDMOS晶体管的示意图；
图6至图11是采用本发明的方法制作VDMOS晶体管兼容LDMOS晶体管的示意图。
具体实施方式
本发明制作VDMOS晶体管兼容LDMOS晶体管具体实施方式如下：提供衬底，所述衬底具有LDMOS晶体管区和VDMOS晶体管区；向衬底注入离子，形成N埋层区域；在N埋层区域上形成外延层后，向外延层注入离子，在LDMOS晶体管区形成N阱和P阱，在VDMOS晶体管区形成高压N阱；在LDMOS晶体管区的N阱和P阱交界处及LDMOS晶体管区和VDMOS晶体管区交界处形成隔离区；在LDMOS晶体管区的P阱区域形成漂移区；在LDMOS晶体管区的P阱区域的部分外延层和部分漂移区上，以及在VDMOS晶体管区形成栅极；在LDMOS晶体管区的栅极和隔离区之间的外延层内，以及在VDMOS晶体管区的栅极之间的外延层内形成PBODY区；在LDMOS晶体管区的漂移区之间的外延层内形成N型GRADE区；在VDMOS晶体管区的隔离区与邻近栅极之间的外延层内形成NSINK区，所述NSINK区与N埋层区域连通；在LDMOS晶体管区的PBODY区内形成源极，在N型GRADE区内形成漏极，以及在VDMOS晶体管区的PBODY区内形成源极，在NSINK区内形成漏极；在LDMOS晶体管区的PBODY区形成P+区，所述P+区与源极相接。
基于上述实施方式形成的VDMOS晶体管兼容LDMOS晶体管，包括：衬底，所述衬底具有LDMOS晶体管区和VDMOS晶体管区；位于衬底内的N埋层区域；位于N埋层区域上的外延层；在LDMOS晶体管区的N外延层内形成有N阱和与N阱相接的P阱；在VDMOS晶体管区形成有高压N阱；位于在LDMOS晶体管区的N阱和P阱交界处及LDMOS晶体管区和VDMOS晶体管区交界处的隔离区；位于LDMOS晶体管区的P阱区域的漂移区；位于LDMOS晶体管区的P阱区域的部分外延层和部分漂移区上，以及在VDMOS晶体管区的外延层上的栅极；位于LDMOS晶体管区栅极和隔离区之间的外延层内，以及位于VDMOS晶体管区的栅极之间的外延层内的PBODY区；位于LDMOS晶体管区漂移区之间的外延层内的N型GRADE区；位于LDMOS晶体管区和VDMOS晶体管区的PBODY区内的源极；位于LDMOS晶体管区的PBODY区内的P+区，所述P+区与源极相接；位于VDMOS晶体管区隔离区与邻近栅极之间的外延层内的NSINK区，所述NSINK区与N埋层区域连通；位于LDMOS晶体管区的N型GRADE区内和NSINK区内的漏极。
本发明在VDMOS晶体管区的隔离区与邻近栅极之间的外延层内形成NSINK区，所述NSINK区与N埋层区域连通。使漏极之间连通，从而实现BCD工艺平台上LDMOS晶体管与VDMOS晶体管的兼容技术，进而实现了高压和大电流的性能需求。
下面结合附图对本发明的具体实施方式做详细的说明。
图6至图11是采用本发明的方法制作VDMOS晶体管兼容LDMOS晶体管的示意图。如图6所示，提供衬底，所述衬底的材料可以是硅或硅锗等，且所述衬底具有LDMOS晶体管区I和VDMOS晶体管区II。向衬底内注入N型离子，形成N埋层区域201，所述注入的N型离子为锑离子，注入离子的剂量为1×1015/cm2，能量为大约40KeV。接着，采用外延生长法在N埋层区域201上形成N外延层202，所述N外延层的厚度为大约4μm。
如图7所示，先在N外延层上形成第一光刻胶层(未示出)，经过光刻工艺后，在LDMOS晶体管区I定义出N阱图形；以第一光刻胶层为掩膜，沿N阱图形向N外延层注入N型离子，形成N阱202a，所述N型离子可以是磷离子，注入的剂量为6×1012/cm2～8×1012/cm2，能量为大约150KeV。用灰化法或湿法刻蚀法去除第一光刻胶后，在N外延层上形成第二光刻胶层(未示出)，经过光刻工艺后，在LDMOS晶体管区I定义出P阱图形；以第二光刻胶层为掩膜，沿P阱图形向N外延层注入P型离子，形成P阱202b，所述P型离子可以是硼离子，注入的剂量为8×1012/cm2～1×1013/cm2，能量为50KeV～60KeV。用灰化法或湿法刻蚀法去除第二光刻胶后，在N外延层上形成第三光刻胶层(未示出)，经过光刻工艺后，在VDMOS晶体管区II定义出高压N阱图形；以第三光刻胶层为掩膜，沿高压N阱图形向N外延层注入N型离子，形成高压N阱202c，所述N型离子可以是磷离子，注入的剂量为1×1012/cm2～2×1012/cm2，能量为150KeV。
再参考图7，用灰化法或湿法刻蚀法去除第三光刻胶层后，采用场氧化法在LDMOS晶体管区I的N阱202a与P阱202b交界处的N外延层内，以及LDMOS晶体管区I和VDMOS晶体管区II的交界处的N外延层内形成硅局部氧化隔离(LOCOS)区204。具体形成工艺为：用热氧化法在N外延层上形成垫氧化层；用化学气相沉积法在垫氧化层上形成腐蚀阻挡层，所述腐蚀阻挡层的材料为氮化硅；用旋涂法在腐蚀阻挡层上形成第四光刻胶层(未示出)，经过曝光显影工艺，定义隔离区图形；以第四光刻胶层为掩膜，用干法刻蚀法刻蚀腐蚀阻挡层和垫氧化层，形成开口；去除第四光刻胶层后，用热氧化法氧化开口处的N外延层，使氧气与硅结合，形成材料为二氧化硅的硅局部氧化隔离(LOCOS)区204。
继续参考图7，在N外延层上形成第五光刻胶层(未示出)，经过光刻工艺后，在LDMOS晶体管区I的P阱202b区定义出漂移区图形；以第五光刻胶层为掩膜进行腐蚀阻挡层腐蚀形成漂移区开口图形，沿漂移区图形向N外延层内注入磷离子，去第五光刻胶层后并进行退火工艺，形成漂移区206a；接着继续以腐蚀阻挡层为掩膜，采用湿氧热氧化法漂移区206a的N外延层，形成LOCOS场板206b。接着用热磷酸去除腐蚀阻挡层，用氢氟酸去除垫氧化层。
如图8所示，用化学气相沉积法在N外延层上形成厚度为约3000埃的多晶硅层；用旋涂法在多晶硅层上形成第六光刻胶层(未示出)，经过曝光显影工艺后，在第六光刻胶层上定义出栅极图形；以第六光刻胶层为掩膜，沿栅极图形刻蚀多晶硅层，在LDMOS晶体管区I的P阱103区的部分N外延层和漂移区上形成栅极208a，在VDMOS晶体管区II的N外延层上形成栅极208b。接着，灰化法或湿法刻蚀法去除第六光刻胶层。
参考图9，在N外延层、硅局部氧化隔离(LOCOS)区204和栅极208a、208b上形成第七光刻胶层(未示出)，经过曝光显影工艺后，定义出PBODY区图形；以第七光刻胶层为掩膜，沿PBODY区图形向N外延层内注入N型离子，在LDMOS晶体管区I的栅极208a和硅局部氧化隔离(LOCOS)区204之间形成PBODY区209a，在VDMOS晶体管区II的栅极208b之间形成PBODY区209b，所述PBODY区209a、209b的作用为通过它与源/漏极横向扩散长度差形成有效沟道控制LDMOS的阈值电压，其中所述P型离子为硼离子，注入的剂量约为2×1013/cm2，能量为40KeV。接着，灰化法或湿法刻蚀法去除第七光刻胶层。
继续参考图9，在N外延层、硅局部氧化隔离(LOCOS)区204和栅极208a、208b上形成第八光刻胶层(未示出)，经过光刻工艺后，在漂移区106之间的第八光刻胶层上定义出开口图形；以第八光刻胶层为掩膜，沿开口图形向N外延层内注入N型离子，并经过退火工艺后，使N型离子扩散均匀且深度加大，形成N型GRADE区210，所述N型GRADE区210的作用为在源/漏极外面形成低浓度的N型离子，降低PN结的掺杂浓度，提高结的击穿电压。去除第八光刻胶层。
本实施例中，所述形成N型GRADE区210所注入的N型离子为磷离子，注入的剂量为1×1013/cm2，能量为80KeV～100KeV。
如图10所示，在N外延层、硅局部氧化隔离(LOCOS)区204和栅极208a、208b上旋涂第九光刻胶层(未示出)，经过曝光显影工艺后，在VDMOS晶体管区II定义出NSINK区图形；以第九光刻胶层为掩膜，沿NSINK区图形向VDMOS晶体管区II的硅局部氧化隔离(LOCOS)区204与邻近栅极208b之间的外延层内注入N型离子，形成NSINK区212，所述NSINK区212与N埋层区域201连通。其中，NSINK区212区的作用为将漏极电极由衬底引出，尽可能提高掺杂浓度，减小串联电阻。去除第九光刻胶层。
本实施例中，所述形成NSINK区212所注入的N型离子为磷离子，注入的剂量为1×1015/cm2，能量为300KeV～400KeV。
如图11所示，在N外延层、硅局部氧化隔离(LOCOS)区204和栅极208a、208b上旋涂第十光刻胶层(未示出)，经过光刻工艺后，定义出源极和漏极图形；以第十光刻胶层为掩膜，沿源极和漏极图形向LDMOS晶体管区I的N外延层内的PBODY区209a和N型GRADE区210中注入N型离子，在PBODY区209a内形成源极S，在N型GRADE区210内形成漏极D；向VDMOS晶体管区II的N外延层内的PBODY区209b和NSINK区212中注入N型离子，在PBODY区209b内形成源极S，在NSINK区212内形成漏极D。
本实施例中，形成源极S和漏极D所注入的N型离子为砷离子，注入的剂量为4×1015/cm2，能量为80KeV。
继续参考图11，去除第十光刻胶层后，在N外延层、硅局部氧化隔离(LOCOS)区204和栅极208a、208b上形成第十一光刻胶层(未示出)，经过光刻工艺后，在LDMOS晶体管区I定义出P+区图形；以第十一光刻胶层为掩膜，沿P+区图形向LDMOS晶体管区I的N外延层内的PBODY区209a注入P型离子，形成P+区214，所述P+区214与LDMOS晶体管区I的源极S相接，其作用为防止LDMOS的衬底电极与源极短接，减小衬偏效应。接着，去除第十一光刻胶层。
本实施例中，形成P+区214所注入的P型离子为二氟化硼离子，注入离子的剂量为2×1015/cm2，能量为60KeV～80KeV。
基于上述实施例形成的VDMOS晶体管兼容LDMOS晶体管，包括：衬底，所述衬底具有LDMOS晶体管区I和VDMOS晶体管区II；N埋层区域201，通过向衬底注入P型离子形成；外延层，位于N埋层区域上；N阱202a和与N阱202a相接的P阱202b，位于LDMOS晶体管区I的N外延层内；高压N阱，位于VDMOS晶体管区II的N处延层内；硅局部氧化隔离(LOCOS)区204，位于LDMOS晶体管区I的N阱202a和P阱202b交界处及LDMOS晶体管区I和VDMOS晶体管区II交界处；漂移区206，位于LDMOS晶体管区I的P阱202b区域；栅极208a，位于LDMOS晶体管区I的P阱区域的部分外延层和部分漂移区206上；栅极208b，位于VDMOS晶体管区II的外延层上；PBODY区209a，位于LDMOS晶体管区I栅极208a和硅局部氧化隔离(LOCOS)区204之间的外延层内；PBODY区209b，位于VDMOS晶体管区II的栅极208b之间的外延层内；N型GRADE区210，位于LDMOS晶体管区I漂移区206之间的外延层内；NSINK区212，位于VDMOS晶体管区II的硅局部氧化隔离(LOCOS)区204与邻近栅极208b之间的外延层内，所述NSINK区212与N埋层区域201连通；源极S，分别位于LDMOS晶体管区I和VDMOS晶体管区II的PBODY区209a、209b内；漏极D，位于LDMOS晶体管区I的N型GRADE区210内和NSINK区212内；P+区214，位于LDMOS晶体管区I的PBODY区209a内，所述P+区214与PBODY区209a内的源极S相接。
虽然本发明已以较佳实施例披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (12)

1.一种VDMOS晶体管兼容LDMOS晶体管的制作方法，其特征在于，包括：
提供衬底，所述衬底具有LDMOS晶体管区和VDMOS晶体管区；
向衬底注入离子，形成N埋层区域；
在N埋层区域上形成外延层后，向外延层注入离子，在LDMOS晶体管区形成N阱和P阱，在VDMOS晶体管区形成高压N阱；
在LDMOS晶体管区的N阱和P阱交界处及LDMOS晶体管区和VDMOS晶体管区交界处形成隔离区；
在LDMOS晶体管区的Ｐ阱区域形成漂移区；
在LDMOS晶体管区的Ｐ阱区域的部分外延层和部分漂移区上，以及在VDMOS晶体管区形成栅极；
在LDMOS晶体管区的栅极和隔离区之间的外延层内，以及在VDMOS晶体管区的栅极之间的外延层内形成PBODY区；
在LDMOS晶体管区的漂移区之间的外延层内注入N型离子，并经过退火工艺后，使N型离子扩散均匀且深度加大，形成Ｎ型GRADE区；
在VDMOS晶体管区的隔离区与邻近栅极之间的外延层内注入N型离子，形成NSINK区，所述NSINK区与Ｎ埋层区域连通；
在LDMOS晶体管区的PBODY区内形成源极，在N型GRADE区内形成漏极，以及在VDMOS晶体管区的PBODY区内形成源极，在NSINK区内形成漏极；
在LDMOS晶体管区的PBODY区形成P+区，所述P+区与源极相接。
2.根据权利要求1所述VDMOS晶体管兼容LDMOS晶体管的制作方法，其特征在于，所述形成NSINK区注入的离子为磷离子。
3.根据权利要求2所述VDMOS晶体管兼容LDMOS晶体管的制作方法，其特征在于，所述注入磷离子的剂量为1×1015/cm2，能量为300KeV～400KeV。
4.根据权利要求1所述VDMOS晶体管兼容LDMOS晶体管的制作方法，其特征在于，所述形成N埋层区域注入的离子为锑离子，注入离子的剂量为1×1015/cm2，能量为40KeV。
5.根据权利要求1所述VDMOS晶体管兼容LDMOS晶体管的制作方法，其特征在于，所述形成漂移区还包括：
向Ｐ阱局部区域注入磷离子，形成漂移区；
在漂移区进行氧化工艺形成LOCOS场板。
6.根据权利要求5所述VDMOS晶体管兼容LDMOS晶体管的制作方法，其特征在于，所述注入磷离子的剂量为1×1012/cm2，能量为40KeV～50KeV。
7.根据权利要求5所述VDMOS晶体管兼容LDMOS晶体管的制作方法，其特征在于，所述氧化漂移区的方法为湿氧热氧化法。
8.根据权利要求1所述VDMOS晶体管兼容LDMOS晶体管的制作方法，其特征在于，所述形成PBODY区注入的离子为硼离子，注入离子的剂量为2×1013/cm2，能量为40KeV。
9.根据权利要求1所述VDMOS晶体管兼容LDMOS晶体管的制作方法，其特征在于，所述形成Ｎ型GRADE区注入的离子为磷离子，注入离子的剂量为1×1013/cm2，能量为80KeV～100KeV。
10.根据权利要求1所述VDMOS晶体管兼容LDMOS晶体管的制作方法，其特征在于，所述形成源极/漏极注入的离子为砷离子，注入离子的剂量为4×1015/cm2，能量为80KeV。
11.根据权利要求1所述VDMOS晶体管兼容LDMOS晶体管的制作方法，其特征在于，所述形成P+区注入的离子为二氟化硼离子，注入离子的剂量为2×1015/cm2，能量为60KeV～80KeV。
12.一种VDMOS晶体管兼容LDMOS晶体管的半导体器件，包括：衬底，所述衬底具有LDMOS晶体管区和VDMOS晶体管区；位于衬底内的N埋层区域；位于N埋层区域上的外延层；在LDMOS晶体管区的N外延层内形成有N阱和与N阱相接的P阱；在VDMOS晶体管区形成有高压N阱；位于在LDMOS晶体管区的N阱和P阱交界处及LDMOS晶体管区和VDMOS晶体管区交界处的隔离区；位于LDMOS晶体管区的Ｐ阱区域的漂移区；位于LDMOS晶体管区的Ｐ阱区域的部分外延层和部分漂移区上，以及在VDMOS晶体管区的外延层上的栅极；位于LDMOS晶体管区栅极和隔离区之间的外延层内，以及位于VDMOS晶体管区的栅极之间的外延层内的PBODY区；向LDMOS晶体管区漂移区之间的外延层内注入N型离子，并经过退火工艺后，使N型离子扩散均匀且深度加大形成的Ｎ型GRADE区；位于LDMOS晶体管区和VDMOS晶体管区的PBODY区内的源极；位于LDMOS晶体管区的PBODY区内的P+区，所述P+区与源极相接，其特征在于，还包括：向VDMOS晶体管区隔离区与邻近栅极之间的外延层内注入N型离子形成的NSINK区，所述NSINK区与Ｎ埋层区域连通；位于LDMOS晶体管区的N型GRADE区内和NSINK区内的漏极。
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