WO2011050712A1 - Vdmos晶体管兼容ldmos晶体管及其制作方法 - Google Patents

Vdmos晶体管兼容ldmos晶体管及其制作方法 Download PDF

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Publication number
WO2011050712A1
WO2011050712A1 PCT/CN2010/078121 CN2010078121W WO2011050712A1 WO 2011050712 A1 WO2011050712 A1 WO 2011050712A1 CN 2010078121 W CN2010078121 W CN 2010078121W WO 2011050712 A1 WO2011050712 A1 WO 2011050712A1
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region
transistor
vdmos
ldmos transistor
epitaxial layer
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PCT/CN2010/078121
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English (en)
French (fr)
Inventor
桂林春
王乐
赵志勇
何丽丽
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无锡华润上华半导体有限公司
无锡华润上华科技有限公司
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Priority to JP2012524103A priority Critical patent/JP5356598B2/ja
Priority to US13/384,002 priority patent/US8530961B2/en
Priority to EP10826075.3A priority patent/EP2437288A4/en
Publication of WO2011050712A1 publication Critical patent/WO2011050712A1/zh

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    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823487—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
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    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology
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    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
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    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7809—Vertical DMOS transistors, i.e. VDMOS transistors having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Definitions

  • VDMOS transistor compatible LDMOS transistor and manufacturing method thereof The present application claims priority to Chinese patent application filed on October 28, 2009, the Chinese Patent Office, Application No. 200910209187.5, entitled "VDMOS transistor compatible LDMOS transistor and its manufacturing method" The entire contents of which are incorporated herein by reference.
  • TECHNICAL FIELD The present invention relates to the field of manufacturing semiconductor devices, and in particular, to a VDMOS transistor compatible LDMOS transistor and a method of fabricating the same. BACKGROUND OF THE INVENTION With the continuous development of semiconductor process technology.
  • Bipolar/CMOS/DMOS integrated BCD process combines three different process types: bipolar for analog control; CMOS for digital control; DMOS for high voltage and high current in processing on chip or system management, Realize the soft start and power output of the system.
  • the BCD process combines the advantages of each of the above three devices, this enables BCD-based products to integrate complex control functions, making it the main circuit optimization of the power integrated circuit, achieving low power consumption and high integration of the entire circuit. Degree, high speed, high drive capacity, high current requirements.
  • the high voltage MOS transistors appearing in the BCD process are mainly LDMOS (transverse double diffused metal oxide semiconductor). The step of forming an LDMOS transistor in the existing BCD process is as shown in FIG.
  • the material of the substrate may be silicon or silicon germanium, etc.; implanting boron ions into the substrate to form an N buried region 101;
  • An epitaxial method forms an N epitaxial layer on the N buried region 101;
  • a first photoresist layer (not shown) is formed on the N epitaxial layer, and after the photolithography process, an N well pattern is defined;
  • the layer is a mask, and phosphorus ions are implanted into the N epitaxial layer along the N-well pattern to form an N-well 102.
  • a second photoresist layer (not shown) is formed on the N epitaxial layer, and the light is passed through.
  • boron ions are implanted into the N epitaxial layer along the P well pattern to form a P well 103.
  • a local oxidation isolation (LOCOS) region 104 is formed at the junction of the N well 102 and the P well 103 by field oxidation; and a third photolithography is formed on the N epitaxial layer.
  • LOC local oxidation isolation
  • a glue layer (not shown), after the photolithography process, defining a drift region pattern in the P well 103 region; using the third photoresist layer as a mask, implanting phosphorus ions into the N epitaxial layer along the drift region pattern, and An annealing process is performed to form the drift region 106a.
  • the epitaxial layer of the drift region 106a is oxidized by wet oxygen thermal oxidation using the third photoresist layer as a mask to form the LOCOS field plate 106b.
  • the third photoresist layer is then removed. As shown in FIG.
  • a polysilicon layer and a fourth photoresist layer are sequentially formed on the N epitaxial layer, and after the exposure and development process, a gate pattern is defined on the fourth photoresist layer;
  • the four photoresist layers are masks, the polysilicon layer is etched along the gate pattern, and the gate 108 is formed on a portion of the N epitaxial layer and the drift region of the P well 103 region.
  • the fourth photoresist layer is removed. Referring to FIG.
  • a fifth photoresist layer (not shown) is formed on the N epitaxial layer, the local oxide isolation (LOCOS) region 104 and the gate 108, and after the exposure and development process, the gate of the P well 103 region
  • a PBODY region P-type substrate concentration transition region
  • the pattern implants phosphorus ions into the N epitaxial layer to form a PBODY region 109 which functions to form a threshold voltage of the effective channel control LDMOS by its difference from the source/drain lateral diffusion length.
  • a sixth photoresist layer (not shown) is formed on the N epitaxial layer, the silicon local oxidation isolation (LOCOS) region 104 and the gate electrode 108, after the exposure and development process, in the drift region.
  • LOC silicon local oxidation isolation
  • An opening pattern is defined on the sixth photoresist layer between 106; the sixth photoresist layer is used as a mask, and phosphorus ions are implanted into the N epitaxial layer along the opening pattern, and after the annealing process, the phosphorus ions are uniformly diffused And the depth is increased to form an N-type GRADE (concentration gradient) region 110, the role of the GRADE region 110 is to form a low concentration of N-type ions outside the source/drain, reduce the doping concentration of the PN junction, and improve the junction blow Wear voltage.
  • the sixth photoresist layer is removed. As shown in FIG.
  • a seventh photoresist layer (not shown) is formed on the N epitaxial layer, the silicon partial oxidation isolation (LOCOS) region 104, and the gate electrode 108, and after the exposure and development process, source/drain patterns are formed.
  • LOCOS silicon partial oxidation isolation
  • source/drain patterns are formed.
  • phosphorus ions are implanted into the PBODY region 109 and the N-type GRADE region 110 in the N epitaxial layer along the source/drain pattern, and a source S is formed in the PBODY region 109, at N Type GRADE area A drain D is formed in 110.
  • an eighth photoresist layer (not shown) is formed on the N epitaxial layer, the silicon local oxidation isolation (LOCOS) region 104, and the gate electrode 108, and is subjected to a photolithography process.
  • a P+ region pattern is defined; using the eighth photoresist layer as a mask, boron ions are implanted into the PBODY region 109 in the N epitaxial layer along the P+ region pattern to form a P+ region 112, and the P+ region 112 and the source S are formed. Connected, the role is to prevent the substrate electrode from short-circuiting with the source, reducing the shimming effect.
  • the eighth photoresist layer is removed.
  • the problem to be solved by the present invention is to provide a method for fabricating a VDMOS transistor compatible LDMOS transistor, which prevents the BCD process from being compatible with VDMOS transistors and LDMOS transistors.
  • the present invention provides a method for fabricating a VDMOS transistor compatible LDMOS transistor, comprising: providing a substrate having an LDMOS transistor region and a VDMOS transistor region; implanting ions into the substrate to form an N buried region; After forming an epitaxial layer on the N buried region, implanting ions into the epitaxial layer, forming an N well and a P well in the LDMOS transistor region, and forming a high voltage N well in the VDMOS transistor region; at the junction of the N well and the P well in the LDMOS transistor region and An isolation region is formed at a boundary between the LDMOS transistor region and the VDMOS transistor region; a drift region is formed in a P well region of the LDMOS transistor region; a partial epitaxial layer and a partial drift region of the P well region of the LDMOS transistor region, and a gate is formed in the VDMOS transistor region a PBODY region is formed in the epitaxial layer between the gate and the isolation region of the L
  • the ions implanted in the NSENNK region are phosphorus ions.
  • the dose of the implanted ions It is lx l0 15 /cm 2 and the energy is 300KeV ⁇ 400KeV.
  • the ions implanted in the N buried region are erbium ions, and the implanted ions have a dose of l l0 15 /cm 2 and an energy of 40 KeV.
  • the forming the drift region further includes: implanting phosphorus ions into a local region of the P well to form a drift region; performing an oxidation process in the drift region to form a LOCOS field plate.
  • the dose of the implanted phosphorus ions is lx l0 12 /cm 2 and the energy is 40KeV ⁇ 50KeV.
  • the method of oxidizing the drift region is a wet oxygen thermal oxidation method.
  • the ions implanted in the PBODY region are boron ions, and the implanted ions have a dose of 2 ⁇ 10 13 /cm 2 and an energy of 40 KeV.
  • the ions implanted in the N-type GRADE region are phosphorus ions, and the implanted ions have a dose of l ⁇ 10 13 /cm 2 and an energy of 80 KeV to 100 KeV.
  • the source/drain implanted ions are arsenic ions, and the implanted ions have a dose of 4 ⁇ 10 15 /cm 2 and an energy of 80 KeV.
  • the ions implanted in the P+ region are boron difluoride ions, and the implanted ions have a dose of 2 ⁇ 10 15 /cm 2 and an energy of 60 KeV to 80 KeV.
  • the present invention also provides a VDMOS transistor compatible LDMOS transistor, comprising: a substrate having an LDMOS transistor region and a VDMOS transistor region; an N buried region located within the substrate; an epitaxial layer located on the N buried region; An N-well and a P-well connected to the N-well are formed in the N-epitaxial layer of the LDMOS transistor region; a high-voltage N-well is formed in the VDMOS transistor region; the N-well and P-well junctions in the LDMOS transistor region and the LDMOS transistor region are located An isolation region at the junction with the VDMOS transistor region; a drift region in the P-well region of the LDMOS transistor region; a portion of the epitaxial layer and a portion of the drift region of the P-well region of the LDMOS transistor region, and an epitaxial layer on the VDMOS transistor region a gate; an epitaxial layer between the gate and the isolation region of the LDMOS transistor region; and a PBODY region in the epitaxial layer
  • the present invention has the advantage that an NSENNK region is formed in an epitaxial layer between an isolation region of a VDMOS transistor region and an adjacent gate, and the NSENK region is in communication with the N buried region.
  • the drains are connected to each other, thereby realizing the compatibility technology of the LDMOS transistor and the VDMOS transistor on the BCD process platform, thereby realizing the performance requirements of high voltage and high current.
  • FIGS. 1 to 5 are schematic views showing formation of an LDMOS transistor in a conventional BCD process; and FIGS. 6 to 11 are schematic views showing fabrication of a VDMOS transistor compatible LDMOS transistor by the method of the present invention.
  • the present invention is a VDMOS transistor compatible LDMOS transistor.
  • the embodiment is as follows: providing a substrate having an LDMOS transistor region and a VDMOS transistor region; implanting ions into the substrate to form an N buried region; After the epitaxial layer is formed, ions are implanted into the epitaxial layer, N-well and P-well are formed in the LDMOS transistor region, and a high-voltage N-well is formed in the VDMOS transistor region; N-well and P-well junctions in the LDMOS transistor region and the LDMOS transistor region and VDMOS Forming an isolation region at a junction of a transistor region; forming a drift region in a P-well region of the LDMOS transistor region; forming a gate on a portion of the epitaxial layer and a portion of the drift region of the P-well region of the LDMOS transistor region, and forming a gate in the VDMOS transistor region; Forming a PBODY region in an epit
  • VDMOS transistor formed based on the above embodiment is compatible with LDMOS transistor, including: lining a substrate having an LDMOS transistor region and a VDMOS transistor region; an N buried region located in the substrate; an epitaxial layer on the N buried region; an N well and an N well formed in the N epitaxial layer of the LDMOS transistor region a P-well connected to the N-well; a high-voltage N-well formed in the VDMOS transistor region; an isolation region located at the junction of the N-well and the P-well at the LDMOS transistor region and at the junction of the LDMOS transistor region and the VDMOS transistor region; located in the LDMOS transistor region a drift region of the P-well region; a portion of the epitaxial layer and a portion of the drift region of the P-well region of the LDMOS transistor region, and a gate on the epitaxial layer of the VDMOS transistor region; between the gate of the LDMOS transistor region and the isolation region In the epi
  • the present invention forms an NSENNK region in an epitaxial layer between an isolation region of a VDMOS transistor region and an adjacent gate, the NSENK region being in communication with the N buried region.
  • the drains are connected to each other, thereby realizing the compatibility technology of the LDMOS transistor and the VDMOS transistor on the BCD process platform, thereby realizing the performance requirements of high voltage and high current.
  • 6 to 11 are schematic views showing fabrication of a VDMOS transistor compatible LDMOS transistor by the method of the present invention. As shown in FIG.
  • a substrate which may be made of silicon or silicon germanium or the like, and has a LDMOS transistor region I and a VDMOS transistor region II.
  • N-type ions are implanted into the substrate to form an N-buried region 201.
  • the implanted N-type ions are erbium ions, and the implanted ions have a dose of lx10 15 /cm 2 and an energy of about 40 KeV.
  • an N epitaxial layer 202 is formed on the N buried region 201 by epitaxial growth, and the thickness of the N epitaxial layer is about 4 ⁇ m.
  • a first photoresist layer (not shown) is formed on the germanium epitaxial layer.
  • a germanium well pattern is defined in the LDMOS transistor region I; a mask, implanting N-type ions into the N epitaxial layer along the N-well pattern to form an N-well 202a, which may be a phosphorus ion implanted at a dose of 6 ⁇ 10 12 /cm 2 to 8 ⁇ 10 12 /cm 2 , energy It is about 150KeV.
  • a second photoresist layer (not shown) is formed on the N epitaxial layer, and after the photolithography process, a P-well pattern is defined in the LDMOS transistor region I;
  • the layer is a mask, and P-type ions are implanted into the N epitaxial layer along the P-well pattern to form a P-well 202b.
  • the P-type ions may be boron ions, and the implanted dose is 8 ⁇ 10 12 /cm 2 ⁇ lxl 13 /cm 2 , energy It is 50KeV ⁇ 60KeV.
  • a third photoresist layer (not shown) is formed on the N epitaxial layer, and after the photolithography process, a high voltage is defined in the VDMOS transistor region II. N-well pattern; using the third photoresist layer as a mask, implanting N-type ions into the N epitaxial layer along the high-voltage N-well pattern to form a high-voltage N-well 202c, which may be a phosphorus ion, and the implanted dose is Ixl0 12 /cm 2 ⁇ 2xl0 12 /cm 2 , the energy is 150KeV.
  • field oxide is used in the N epitaxial layer at the junction of the N well 202a and the P well 202b of the LDMOS transistor region I, and A local oxide isolation (LOCOS) region 204 is formed in the N epitaxial layer at the junction of the LDMOS transistor region I and the VDMOS transistor region II.
  • LOC local oxide isolation
  • the specific forming process is: forming a pad oxide layer on the N epitaxial layer by thermal oxidation; forming a corrosion barrier layer on the pad oxide layer by chemical vapor deposition, the material of the etching barrier layer is silicon nitride; Forming a fourth photoresist layer (not shown) on the etch barrier layer, defining an isolation region pattern through an exposure development process; etching the etch barrier layer by dry etching using the fourth photoresist layer as a mask Forming an opening with the pad oxide layer; after removing the fourth photoresist layer, the N epitaxial layer at the opening is oxidized by thermal oxidation to combine oxygen with silicon to form a local oxide isolation (LOCOS) region of silicon dioxide. 204.
  • LOC local oxide isolation
  • a fifth photoresist layer (not shown) is formed on the N epitaxial layer, and after the photolithography process, a drift region pattern is defined in the P well 202b region of the LDMOS transistor region I;
  • the adhesive layer is etched by the etching barrier layer to form a drift region opening pattern, and phosphorus ions are implanted into the N epitaxial layer along the drift region pattern, and after the fifth photoresist layer is removed, an annealing process is performed to form a drift region 206a;
  • the etching barrier layer is a mask, and the N epitaxial layer of the drift region 206a is wet oxidized to form the LOCOS field plate 206b.
  • the corrosion barrier layer is then removed with hot phosphoric acid and the pad oxide layer is removed with hydrofluoric acid.
  • a polysilicon layer having a thickness of about 3000 angstroms is formed on the N epitaxial layer by chemical vapor deposition; a sixth photoresist layer (not shown) is formed on the polysilicon layer by spin coating, and exposed and developed.
  • a gate pattern is defined on the sixth photoresist layer; the sixth photoresist layer is used as a mask, and the polysilicon layer is etched along the gate pattern, in the portion N of the P well 103 region of the LDMOS transistor region I.
  • Epitaxial layer and drift region A gate 208a is formed, and a gate 208b is formed on the N epitaxial layer of the VDMOS transistor region II.
  • the sixth photoresist layer is removed by ashing or wet etching. Referring to FIG.
  • a seventh photoresist layer (not shown) is formed on the N epitaxial layer, the silicon partial oxidation isolation (LOCOS) region 204, and the gate electrodes 208a, 208b, and after the exposure development process, a PBODY region pattern is defined;
  • N-type ions are implanted into the N epitaxial layer along the PBODY region pattern, and a PBODY region 209a is formed between the gate 208a of the LDMOS transistor region I and the local oxidation isolation (LOCOS) region 204 of the silicon.
  • the PBODY regions 209a, 209b functioning to form a threshold voltage of the effective channel control LDMOS by the difference in lateral diffusion length from the source/drain.
  • the P-type ion is a boron ion
  • the implanted dose is about 2 x 10 13 /cm 2 and the energy is 40 KeV.
  • the seventh photoresist layer is removed by ashing or wet etching.
  • an eighth photoresist layer (not shown) is formed over the N epitaxial layer, the silicon partial oxidation isolation (LOCOS) region 204, and the gate electrodes 208a, 208b, after the photolithography process, in the drift region 106.
  • LOC silicon partial oxidation isolation
  • An opening pattern is defined on the eighth photoresist layer; the N-type ion is implanted into the N epitaxial layer along the opening pattern by using the eighth photoresist layer as a mask, and the N-type ions are uniformly diffused after the annealing process And the depth is increased to form an N-type GRADE region 210, the N-type GRADE region 210 functions to form a low concentration of N-type ions outside the source/drain, reduce the doping concentration of the PN junction, and increase the breakdown voltage of the junction. .
  • the eighth photoresist layer is removed.
  • the N-type ions implanted in the N-type GRADE region 210 are phosphorus ions, and the implanted dose is l xl 13 /cm 2 and the energy is 80 KeV - 100 KeV.
  • a ninth photoresist layer (not shown) is spin-coated on the N epitaxial layer, the silicon partial oxidation isolation (LOCOS) region 204, and the gate electrodes 208a, 208b, after exposure and development processes, in the VDMOS transistor.
  • LOC silicon partial oxidation isolation
  • the region II defines the NSENNK region pattern; the ninth photoresist layer is used as a mask, and the NSENK region pattern is implanted into the epitaxial layer between the local oxidation isolation (LOCOS) region 204 of the VDMOS transistor region II and the adjacent gate 208b.
  • the N-type ions form an NSENNK region 212 that is in communication with the N-buried region 201.
  • the role of the 212 region of the NSINK region is to draw the drain electrode from the substrate, thereby increasing the doping concentration as much as possible and reducing the series resistance.
  • the ninth photoresist layer is removed.
  • the N-type ions implanted in the NSNNK region 212 are phosphorus ions implanted at a dose of lxl0 15 /cm 2 and an energy of 300 KeV to 400 KeV.
  • a tenth photoresist layer (not shown) is spin-coated on the N epitaxial layer, the silicon partial oxidation isolation (LOCOS) region 204, and the gate electrodes 208a, 208b. After the photolithography process, the source is defined.
  • Pole and drain patterns using a tenth photoresist layer as a mask, injecting N-type ions into the PBODY region 209a and the N-type GRADE region 210 in the N epitaxial layer of the LDMOS transistor region I along the source and drain patterns, A source S is formed in the PBODY region 209a, and a drain D is formed in the N-type GRADE region 210; N-type ions are implanted into the PBODY region 209b and the NSENNK region 212 in the N epitaxial layer of the VDMOS transistor region II, in the PBODY region 209b A source S is formed therein, and a drain 0 is formed in the NSENNK region 212.
  • the N-type ions implanted in the source S and the drain D are arsenic ions, and the implanted dose is 4 ⁇ 10 15 /cm 2 and the energy is 80 KeV.
  • an eleventh photoresist layer (not shown) is formed on the N epitaxial layer, the silicon partial oxidation isolation (LOCOS) region 204, and the gate electrodes 208a, 208b.
  • a P+ region pattern is defined in the LDMOS transistor region I; and a P-type ion is implanted into the PBODY region 209a in the N epitaxial layer of the LDMOS transistor region I along the P+ region pattern using the eleventh photoresist layer as a mask.
  • the P+ region 214 is connected to the source S of the LDMOS transistor region I, and functions to prevent the substrate electrode of the LDMOS from being short-circuited with the source, thereby reducing the shimming effect.
  • the eleventh photoresist layer is removed.
  • the P-type ions implanted in the P+ region 214 are boron difluoride ions, and the implanted ions have a dose of 2 ⁇ 10 15 /cm 2 and an energy of 60 KeV to 80 KeV.
  • the VDMOS transistor compatible LDMOS transistor formed based on the above embodiment includes: a substrate having an LDMOS transistor region I and a VDMOS transistor region II; a N buried region 201 formed by implanting P-type ions into the substrate; an epitaxial layer , located in the N buried region; N well 202a and P well 202b connected to N well 202a, located in the N epitaxial layer of LDMOS transistor region I; high voltage N well, located in the N extension of VDMOS transistor region II; A local oxide isolation (LOCOS) region 204 is located at the junction of N-well 202a and P-well 202b of LDMOS transistor region I and at the junction of LDMOS transistor region I and VDMOS transistor region II; drift region 206, P-well in LDMOS transistor region I a 202b region; a gate 208a on a partial epitaxial layer and a partial drift region 206 of the P well region of the LDMOS transistor region I; a gate 208b on the epit

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Description

VDMOS晶体管兼容 LDMOS晶体管及其制作方法 本申请要求于 2009 年 10 月 28 日提交中国专利局、 申请号为 200910209187.5、 发明名称为 "VDMOS晶体管兼容 LDMOS晶体管及其制作 方法"的中国专利申请的优先权， 其全部内容通过引用结合在本申请中。 技术领域 本发明涉及半导体器件的制造领域， 尤其涉及一种 VDMOS晶体管兼容 LDMOS晶体管及其制作方法。 背景技术 随着半导体工艺技术的不断发展。 BIPOLAR (双极）、 CMOS (互补金属 氧化物半导体场效应管）和 DMOS (双扩散金属氧化物半导体场效应管）原本 三个独立的分支不断的相互融合，逐步发展出了 BIPOLAR与 CMOS—起集成的 BICMOS和三者共同集成的 BCD工艺。 采用 Bipolar/CMOS/DMOS整合的 BCD 工艺， 将通常有的 3种不同的工艺类型结合起来： bipolar针对模拟控制； CMOS 针对数字控制； DMOS针对处理在芯片或系统上管理中出现高电压大电流， 实 现系统的软启动和功率输出。 由于 BCD工艺综合了以上三种器件各自的优点， 这使基于 BCD的产品可以集成复杂的控制功能，使它己成为功率集成电路的主 电路的最优化， 实现整个电路的低功耗、 高集成度、 高速度、 高驱动能力、 大 电流的要求。 目前 BCD工艺中出现的高压 MOS晶体管都是以 LDMOS (横向双扩散金属 氧化物半导体） 为主。 现有 BCD工艺中形成 LDMOS晶体管的步骤如图 1所示， 提供衬底， 所述衬底的材料可以是硅或硅锗等； 向衬底内注入硼离子， 形成 N 埋层区域 101 ; 采用外延法在 N埋层区域 101上形成 N外延层； 在 N外延层上形 成第一光刻胶层（未示出） ， 经过光刻工艺后， 定义出 N阱图形； 以第一光刻 胶层为掩膜， 沿 N阱图形向 N外延层注入磷离子， 形成 N阱 102; 去除第一光刻 胶后， 在 N外延层上形成第二光刻胶层（未示出） ， 经过光刻工艺后， 定义出 P阱图形； 以第二光刻胶层为掩膜， 沿 P阱图形向 N外延层注入硼离子， 形成 P 阱 103。 如图 2所示， 去除第二光刻胶层后， 采用场氧化法在 N阱 102与 P阱 103交界 处形成硅局部氧化隔离（LOCOS )区 104;在 N外延层上形成第三光刻胶层（未 示出）， 经过光刻工艺后， 在 P阱 103区定义出漂移区图形； 以第三光刻胶层为 掩膜， 沿漂移区图形向 N外延层内注入磷离子， 并进行退火工艺， 形成漂移区 106a; 接着继续以第三光刻胶层为掩膜， 采用湿氧热氧化法氧化漂移区 106a 的外延层， 形成 LOCOS场板 106b。 接着去除第三光刻胶层。 如图 3所示， 在 N外延层上依次形成多晶硅层和第四光刻胶层（未示出） ， 经过曝光显影工艺后，在第四光刻胶层上定义出栅极图形； 以第四光刻胶层为 掩膜， 沿栅极图形刻蚀多晶硅层， 在 P阱 103区的部分 N外延层和漂移区上形成 栅极 108。 去除第四光刻胶层。 参考图 4, 在 N外延层、 硅局部氧化隔离 （LOCOS ) 区 104和栅极 108上形 成第五光刻胶层（未示出） ， 经过曝光显影工艺后， 在 P阱 103区的栅极 108和 硅局部氧化隔离 （LOCOS ) 区 104之间的第五光刻胶层上定义出 PBODY区 （P 型衬底浓度过渡区）图形； 以第五光刻胶层为掩膜， 沿 PBODY区图形向 N外延 层内注入磷离子， 形成 PBODY区 109, 所述 PBODY区 109的作用为通过它与源 /漏极横向扩散长度差形成有效沟道控制 LDMOS的阈值电压。 去除第五光刻胶 层后， 在 N外延层、 硅局部氧化隔离 （LOCOS )区 104和栅极 108上形成第六光 刻胶层（未示出） ， 经过曝光显影工艺后， 在漂移区 106之间的第六光刻胶层 上定义出开口图形； 以第六光刻胶层为掩膜， 沿开口图形向 N外延层内注入磷 离子， 并经过退火工艺后， 使磷离子扩散均匀且深度加大， 形成 N型 GRADE (浓度梯度） 区 110, 所述 GRADE区 110的作用为在源 /漏极外面形成低浓度的 N型离子， 降低 PN结的掺杂浓度， 提高结的击穿电压。 去除第六光刻胶层。 如图 5所示， 在 N外延层、 硅局部氧化隔离 （LOCOS ) 区 104和栅极 108上 形成第七光刻胶层（未示出） ， 经过曝光显影工艺后， 形成源 /漏极图形； 以 第七光刻胶层为掩膜， 沿源 /漏极图形向 N外延层内的 PBODY区 109和 N型 GRADE区 110中注入磷离子， 在 PBODY区 109内形成源极 S, 在 N型 GRADE区 110内形成漏极 D。 继续参考图 5, 去除第七光刻胶层后， 在 N外延层、 硅局部 氧化隔离 （LOCOS ) 区 104和栅极 108上形成第八光刻胶层（未示出） ， 经过 光刻工艺后， 定义出 P+区图形； 以第八光刻胶层为掩膜， 沿 P+区图形向 N外延 层内的 PBODY区 109注入硼离子， 形成 P+区 112, 所述 P+区 112与源极 S相接， 其作用为防止衬底电极与源极短接，减小衬偏效应。接着，去除第八光刻胶层。 但是， 由于现有的 BCD工艺平台中的高压 MOS都是以 LDMOS为主， 而无法做到 LDMOS与 VDMOS (垂直双扩散金属氧化物半导体）同时兼容在 同一个工艺平台上，既满足 LDMOS的高耐压，又满足 VDMOS的高电流驱动 能力。 发明内容 本发明解决的问题是提供一种 VDMOS晶体管兼容 LDMOS晶体管的制作 方法， 防止 BCD工艺无法兼容 VDMOS晶体管和 LDMOS晶体管。 为解决上述问题，本发明提供一种 VDMOS晶体管兼容 LDMOS晶体管的 制作方法， 包括： 提供衬底， 所述衬底具有 LDMOS晶体管区和 VDMOS晶体 管区； 向衬底注入离子， 形成 N埋层区域； 在 N埋层区域上形成外延层后， 向外延层注入离子， 在 LDMOS晶体管区形成 N阱和 P阱， 在 VDMOS晶体 管区形成高压 N阱； 在 LDMOS晶体管区的 N阱和 P阱交界处及 LDMOS晶 体管区和 VDMOS晶体管区交界处形成隔离区；在 LDMOS晶体管区的 P阱区 域形成漂移区； 在 LDMOS 晶体管区的 P阱区域的部分外延层和部分漂移区 上， 以及在 VDMOS晶体管区形成栅极；在 LDMOS晶体管区的栅极和隔离区 之间的外延层内， 以及在 VDMOS 晶体管区的栅极之间的外延层内形成 PBODY区； 在 LDMOS晶体管区的漂移区之间的外延层内形成 N型 GRADE 区；在 VDMOS晶体管区的隔离区与邻近栅极之间的外延层内形成 NSINK区， 所述 NSINK区与 N埋层区域连通； 在 LDMOS晶体管区的 PBODY区内形成 源极， 在 N型 GRADE区内形成漏极， 以及在 VDMOS晶体管区的 PBODY 区内形成源极， 在 NSINK区内形成漏极； 在 LDMOS晶体管区的 PBODY区 形成 P+区， 所述 P+区与源极相接。 可选的， 所述形成 NSINK区注入的离子为磷离子。 所述注入离子的剂量 为 l x l015/cm2, 能量为 300KeV~400KeV。 可选的， 所述形成 N埋层区域注入的离子为锑离子， 注入离子的剂量为 l l015/cm2, 能量为 40KeV。 可选的， 所述形成漂移区还包括： 向 P阱局部区域注入磷离子， 形成漂移 区； 在漂移区进行氧化工艺形成 LOCOS场板。 可选的， 所述注入磷离子的剂量为 l x l012/cm2, 能量为 40KeV~50KeV。 所述氧化漂移区的方法为湿氧热氧化法。 可选的， 所述形成 PBODY 区注入的离子为硼离子， 注入离子的剂量为 2x l013/cm2, 能量为 40KeV。 可选的， 所述形成 N型 GRADE区注入的离子为磷离子， 注入离子的剂量 为 l x l013/cm2, 能量为 80KeV~100KeV。 可选的， 所述形成源极 /漏极注入的离子为砷离子， 注入离子的剂量为 4x l015/cm2, 能量为 80KeV。 可选的， 所述形成 P+区注入的离子为二氟化硼离子， 注入离子的剂量为 2x l015/cm2, 能量为 60KeV~80KeV。 本发明还提供一种 VDMOS晶体管兼容 LDMOS晶体管， 包括： 衬底， 所 述衬底具有 LDMOS晶体管区和 VDMOS晶体管区； 位于衬底内的 N埋层区 域； 位于 N埋层区域上的外延层； 在 LDMOS晶体管区的 N外延层内形成有 N阱和与 N阱相接的 P阱； 在 VDMOS晶体管区形成有高压 N阱； 位于在 LDMOS晶体管区的 N阱和 P阱交界处及 LDMOS晶体管区和 VDMOS晶体 管区交界处的隔离区； 位于 LDMOS 晶体管区的 P阱区域的漂移区； 位于 LDMOS晶体管区的 P阱区域的部分外延层和部分漂移区上， 以及在 VDMOS 晶体管区的外延层上的栅极；位于 LDMOS晶体管区栅极和隔离区之间的外延 层内， 以及位于 VDMOS晶体管区的栅极之间的外延层内的 PBODY区； 位于 LDMOS晶体管区漂移区之间的外延层内的 N型 GRADE区； 位于 LDMOS晶 体管区和 VDMOS晶体管区的 PBODY区内的源极；位于 LDMOS晶体管区的 PBODY区内的 P+区， 所述 P+区与源极相接； 位于 VDMOS晶体管区隔离区 与邻近栅极之间的外延层内的 NSINK区， 所述 NSINK区与 N埋层区域连通； 位于 LDMOS晶体管区的 N型 GRADE区内和 NSINK区内的漏极。 与现有技术相比，本发明具有以下优点：在 VDMOS晶体管区的隔离区与 邻近栅极之间的外延层内形成 NSINK区， 所述 NSINK区与 N埋层区域连通。 使漏极之间连通， 从而实现 BCD工艺平台上 LDMOS晶体管与 VDMOS晶体 管的兼容技术， 进而实现了高压和大电流的性能需求。 附图说明 图 1至图 5是现有 BCD工艺中形成 LDMOS晶体管的示意图； 图 6至图 11是采用本发明的方法制作 VDMOS晶体管兼容 LDMOS晶体 管的示意图。
具体实施方式 本发明制作 VDMOS晶体管兼容 LDMOS晶体管具体实施方式如下：提供 衬底，所述衬底具有 LDMOS晶体管区和 VDMOS晶体管区；向衬底注入离子， 形成 N埋层区域； 在 N埋层区域上形成外延层后， 向外延层注入离子， 在 LDMOS晶体管区形成 N阱和 P阱， 在 VDMOS晶体管区形成高压 N阱； 在 LDMOS晶体管区的 N阱和 P阱交界处及 LDMOS晶体管区和 VDMOS晶体 管区交界处形成隔离区； 在 LDMOS 晶体管区的 P阱区域形成漂移区； 在 LDMOS晶体管区的 P阱区域的部分外延层和部分漂移区上， 以及在 VDMOS 晶体管区形成栅极； 在 LDMOS晶体管区的栅极和隔离区之间的外延层内， 以 及在 VDMOS晶体管区的栅极之间的外延层内形成 PBODY区；在 LDMOS晶 体管区的漂移区之间的外延层内形成 N型 GRADE区；在 VDMOS晶体管区的 隔离区与邻近栅极之间的外延层内形成 NSINK区，所述 NSINK区与 N埋层区 域连通；在 LDMOS晶体管区的 PBODY区内形成源极，在 N型 GRADE区内 形成漏极， 以及在 VDMOS晶体管区的 PBODY区内形成源极， 在 NSINK区 内形成漏极； 在 LDMOS晶体管区的 PBODY区形成 P+区， 所述 P+区与源极 相接。 基于上述实施方式形成的 VDMOS晶体管兼容 LDMOS晶体管， 包括：衬 底， 所述衬底具有 LDMOS晶体管区和 VDMOS晶体管区； 位于衬底内的 N 埋层区域； 位于 N埋层区域上的外延层； 在 LDMOS晶体管区的 N外延层内 形成有 N阱和与 N阱相接的 P阱； 在 VDMOS晶体管区形成有高压 N阱； 位 于在 LDMOS晶体管区的 N阱和 P阱交界处及 LDMOS晶体管区和 VDMOS 晶体管区交界处的隔离区； 位于 LDMOS晶体管区的 P阱区域的漂移区； 位于 LDMOS晶体管区的 P阱区域的部分外延层和部分漂移区上， 以及在 VDMOS 晶体管区的外延层上的栅极；位于 LDMOS晶体管区栅极和隔离区之间的外延 层内， 以及位于 VDMOS晶体管区的栅极之间的外延层内的 PBODY区； 位于 LDMOS晶体管区漂移区之间的外延层内的 N型 GRADE区； 位于 LDMOS晶 体管区和 VDMOS晶体管区的 PBODY区内的源极；位于 LDMOS晶体管区的 PBODY区内的 P+区， 所述 P+区与源极相接； 位于 VDMOS晶体管区隔离区 与邻近栅极之间的外延层内的 NSINK区， 所述 NSINK区与 N埋层区域连通； 位于 LDMOS晶体管区的 N型 GRADE区内和 NSINK区内的漏极。 本发明在 VDMOS 晶体管区的隔离区与邻近栅极之间的外延层内形成 NSINK 区， 所述 NSINK 区与 N埋层区域连通。 使漏极之间连通， 从而实现 BCD工艺平台上 LDMOS晶体管与 VDMOS晶体管的兼容技术， 进而实现了 高压和大电流的性能需求。 下面结合附图对本发明的具体实施方式做详细的说明。 图 6至图 1 1是采用本发明的方法制作 VDMOS晶体管兼容 LDMOS晶体管的 示意图。 如图 6所示， 提供衬底， 所述衬底的材料可以是硅或硅锗等， 且所述 衬底具有 LDMOS晶体管区 I和 VDMOS晶体管区 II。 向衬底内注入 N型离子， 形 成 N埋层区域 201 , 所述注入的 N型离子为锑离子， 注入离子的剂量为 l x l015/cm2, 能量为大约 40KeV。 接着， 采用外延生长法在 N埋层区域 201上形 成 N外延层 202 , 所述 N外延层的厚度为大约 4μηι。 如图 7所示， 先在 Ν外延层上形成第一光刻胶层（未示出） ， 经过光刻工 艺后， 在 LDMOS晶体管区 I定义出 Ν阱图形； 以第一光刻胶层为掩膜， 沿 N阱 图形向 N外延层注入 N型离子， 形成 N阱 202a, 所述 N型离子可以是磷离子， 注 入的剂量为 6x l012/cm2~8x l012/cm2, 能量为大约 150KeV。用灰^ ^法或湿法刻蚀 法去除第一光刻胶后， 在 N外延层上形成第二光刻胶层（未示出） ， 经过光刻 工艺后， 在 LDMOS晶体管区 I定义出 P阱图形； 以第二光刻胶层为掩膜， 沿 P 阱图形向 N外延层注入 P型离子， 形成 P阱 202b, 所述 P型离子可以是硼离子， 注入的剂量为 8xl012/cm2~lxl013/cm2, 能量为 50KeV~60KeV。 用灰化法或湿法 刻蚀法去除第二光刻胶后， 在 N外延层上形成第三光刻胶层（未示出） ， 经过 光刻工艺后，在 VDMOS晶体管区 II定义出高压 N阱图形； 以第三光刻胶层为掩 膜， 沿高压 N阱图形向 N外延层注入 N型离子， 形成高压 N阱 202c, 所述 N型离 子可以是磷离子， 注入的剂量为 Ixl012/cm2~2xl012/cm2, 能量为 150KeV。 再参考图 7, 用灰化法或湿法刻蚀法去除第三光刻胶层后， 采用场氧化法 在 LDMOS晶体管区 I的 N阱 202a与 P阱 202b交界处的 N外延层内， 以及 LDMOS 晶体管区 I和 VDMOS晶体管区 II的交界处的 N外延层内形成硅局部氧化隔离 ( LOCOS )区 204。 具体形成工艺为： 用热氧化法在 N外延层上形成垫氧化层； 用化学气相沉积法在垫氧化层上形成腐蚀阻挡层，所述腐蚀阻挡层的材料为氮 化硅； 用旋涂法在腐蚀阻挡层上形成第四光刻胶层（未示出）， 经过曝光显影 工艺， 定义隔离区图形； 以第四光刻胶层为掩膜， 用干法刻蚀法刻蚀腐蚀阻挡 层和垫氧化层， 形成开口； 去除第四光刻胶层后， 用热氧化法氧化开口处的 N 外延层， 使氧气与硅结合， 形成材料为二氧化硅的硅局部氧化隔离 （LOCOS ) 区 204。 继续参考图 7, 在 N外延层上形成第五光刻胶层（未示出） ， 经过光刻工 艺后， 在 LDMOS晶体管区 I的 P阱 202b区定义出漂移区图形； 以第五光刻胶层 为掩膜进行腐蚀阻挡层腐蚀形成漂移区开口图形， 沿漂移区图形向 N外延层内 注入磷离子， 去第五光刻胶层后并进行退火工艺， 形成漂移区 206a; 接着继续 以腐蚀阻挡层为掩膜， 采用湿氧热氧化法漂移区 206a的 N外延层， 形成 LOCOS 场板 206b。 接着用热磷酸去除腐蚀阻挡层， 用氢氟酸去除垫氧化层。 如图 8所示， 用化学气相沉积法在 N外延层上形成厚度为约 3000埃的多晶 硅层； 用旋涂法在多晶硅层上形成第六光刻胶层（未示出）， 经过曝光显影工 艺后， 在第六光刻胶层上定义出栅极图形； 以第六光刻胶层为掩膜， 沿栅极图 形刻蚀多晶硅层， 在 LDMOS晶体管区 I的 P阱 103区的部分 N外延层和漂移区上 形成栅极 208a, 在 VDMOS晶体管区 II的 N外延层上形成栅极 208b。 接着， 灰化 法或湿法刻蚀法去除第六光刻胶层。 参考图 9,在 N外延层、硅局部氧化隔离（LOCOS )区 204和栅极 208a、 208b 上形成第七光刻胶层（未示出） ， 经过曝光显影工艺后， 定义出 PBODY区图 形； 以第七光刻胶层为掩膜， 沿 PBODY区图形向 N外延层内注入 N型离子， 在 LDMOS晶体管区 I的栅极 208a和硅局部氧化隔离 （ LOCOS ) 区 204之间形成 PBODY区 209a,在 VDMOS晶体管区 II的栅极 208b之间形成 PBODY区 209b, 所 述 PBODY区 209a、 209b的作用为通过它与源 /漏极横向扩散长度差形成有效沟 道控制 LDMOS的阈值电压， 其中所述 P型离子为硼离子， 注入的剂量约为 2xl013/cm2, 能量为 40KeV。 接着， 灰化法或湿法刻蚀法去除第七光刻胶层。 继续参考图 9,在 N外延层、硅局部氧化隔离（LOCOS )区 204和栅极 208a、 208b上形成第八光刻胶层（未示出） ， 经过光刻工艺后， 在漂移区 106之间的 第八光刻胶层上定义出开口图形； 以第八光刻胶层为掩膜， 沿开口图形向 N外 延层内注入 N型离子， 并经过退火工艺后， 使 N型离子扩散均匀且深度加大， 形成 N型 GRADE区 210 , 所述 N型 GRADE区 210的作用为在源 /漏极外面形成低 浓度的 N型离子， 降低 PN结的掺杂浓度， 提高结的击穿电压。 去除第八光刻胶 层。 本实施例中， 所述形成 N型 GRADE区 210所注入的 N型离子为磷离子， 注 入的剂量为 l xl013/cm2, 能量为 80KeV~100KeV。 如图 10所示， 在 N外延层、 硅局部氧化隔离 （LOCOS ) 区 204和栅极 208a、 208b上旋涂第九光刻胶层（未示出） ， 经过曝光显影工艺后， 在 VDMOS晶体 管区 II定义出 NSINK区图形； 以第九光刻胶层为掩膜， 沿 NSINK区图形向 VDMOS晶体管区 II的硅局部氧化隔离（LOCOS )区 204与邻近栅极 208b之间的 外延层内注入 N型离子，形成 NSINK区 212,所述 NSINK区 212与 N埋层区域 201 连通。 其中， NSINK区 212区的作用为将漏极电极由衬底引出， 尽可能提高掺 杂浓度， 减小串联电阻。 去除第九光刻胶层。 本实施例中， 所述形成 NSINK区 212所注入的 N型离子为磷离子， 注入的 剂量为 lxl015/cm2, 能量为 300KeV~400KeV。 如图 11所示， 在 N外延层、 硅局部氧化隔离 （LOCOS ) 区 204和栅极 208a、 208b上旋涂第十光刻胶层（未示出）， 经过光刻工艺后， 定义出源极和漏极图 形； 以第十光刻胶层为掩膜， 沿源极和漏极图形向 LDMOS晶体管区 I的 N外延 层内的 PBODY区 209a和 N型 GRADE区 210中注入 N型离子， 在 PBODY区 209a 内形成源极 S, 在 N型 GRADE区 210内形成漏极 D; 向 VDMOS晶体管区 II的 N外 延层内的 PBODY区 209b和 NSINK区 212中注入 N型离子，在 PBODY区 209b内形 成源极 S, 在 NSINK区 212内形成漏极0。 本实施例中， 形成源极 S和漏极 D所注入的 N型离子为砷离子， 注入的剂量 为 4xl015/cm2, 能量为 80KeV。 继续参考图 11 , 去除第十光刻胶层后， 在 N外延层、 硅局部氧化隔离 ( LOCOS ) 区 204和栅极 208a、 208b上形成第十一光刻胶层（未示出） ， 经过 光刻工艺后，在 LDMOS晶体管区 I定义出 P+区图形；以第十一光刻胶层为掩膜， 沿 P+区图形向 LDMOS晶体管区 I的 N外延层内的 PBODY区 209a注入 P型离子， 形成 P+区 214, 所述 P+区 214与 LDMOS晶体管区 I的源极 S相接， 其作用为防止 LDMOS的衬底电极与源极短接， 减小衬偏效应。 接着， 去除第十一光刻胶层。 本实施例中， 形成 P+区 214所注入的 P型离子为二氟化硼离子， 注入离 子的剂量为 2xl015/cm2, 能量为 60KeV~80KeV。 基于上述实施例形成的 VDMOS晶体管兼容 LDMOS晶体管， 包括： 衬底， 所述衬底具有 LDMOS晶体管区 I和 VDMOS晶体管区 II； N埋层区域 201 , 通过 向衬底注入 P型离子形成； 外延层， 位于 N埋层区域上； N阱 202a和与 N阱 202a 相接的 P阱 202b,位于 LDMOS晶体管区 I的 N外延层内； 高压 N阱，位于 VDMOS 晶体管区 II的 N处延层内； 硅局部氧化隔离 （LOCOS ) 区 204, 位于 LDMOS晶 体管区 I的 N阱 202a和 P阱 202b交界处及 LDMOS晶体管区 I和 VDMOS晶体管区 II交界处； 漂移区 206, 位于 LDMOS晶体管区 I的 P阱 202b区域； 栅极 208a, 位 于 LDMOS晶体管区 I的 P阱区域的部分外延层和部分漂移区 206上；栅极 208b, 位于 VDMOS晶体管区 II的外延层上； PBODY区 209a, 位于 LDMOS晶体管区 I 栅极 208a和硅局部氧化隔离（ LOCOS )区 204之间的外延层内； PBODY区 209b, 位于 VDMOS晶体管区 II的栅极 208b之间的外延层内； N型 GRADE区 210, 位 于 LDMOS晶体管区 I漂移区 206之间的外延层内； NSINK区 212, 位于 VDMOS 晶体管区 II的硅局部氧化隔离 （LOCOS ) 区 204与邻近栅极 208b之间的外延层 内， 所述 NSINK区 212与 N埋层区域 201连通； 源极 S, 分别位于 LDMOS晶体管 区 I和 VDMOS晶体管区 II的 PBODY区 209a、 209b内； 漏极 D, 位于 LDMOS晶 体管区 I的 N型 GRADE区 210内和 NSINK区 212内； P+区 214, 位于 LDMOS晶体 管区 I的 PBODY区 209a内， 所述 P+区 214与 PBODY区 209a内的源极 S相接。 虽然本发明已以较佳实施例披露如上，但本发明并非限定于此。任何本领 域技术人员， 在不脱离本发明的精神和范围内， 均可作各种更动与修改， 因此 本发明的保护范围应当以权利要求所限定的范围为准。

Claims

权 利 要 求
1. 一种 VDMOS晶体管兼容 LDMOS晶体管的制作方法， 其特征在于， 包括： 提供衬底， 所述衬底具有 LDMOS晶体管区和 VDMOS晶体管区； 向衬底注入离子， 形成 N埋层区域； 在 N埋层区域上形成外延层后， 向外延层注入离子， 在 LDMOS晶体管区 形成 N阱和 P阱， 在 VDMOS晶体管区形成高压 N阱； 在 LDMOS晶体管区的 N阱和 P阱交界处及 LDMOS晶体管区和 VDMOS 晶体管区交界处形成隔离区； 在 LDMOS晶体管区的 P阱区域形成漂移区； 在 LDMOS 晶体管区的 P阱区域的部分外延层和部分漂移区上， 以及在 VDMOS晶体管区形成栅极； 在 LDMOS晶体管区的栅极和隔离区之间的外延层内， 以及在 VDMOS晶 体管区的栅极之间的外延层内形成 PBODY区； 在 LDMOS晶体管区的漂移区之间的外延层内形成 N型 GRADE区； 在 VDMOS晶体管区的隔离区与邻近栅极之间的外延层内形成 NSINK区， 所述 NSINK区与 N埋层区域连通； 在 LDMOS晶体管区的 PBODY区内形成源极， 在 N型 GRADE区内形成 漏极， 以及在 VDMOS晶体管区的 PBODY区内形成源极， 在 NSINK区内 形成漏极； 在 LDMOS晶体管区的 PBODY区形成 P+区， 所述 P+区与源极相接。
2. 根据权利要求 1所述 VDMOS晶体管兼容 LDMOS晶体管的制作方法， 其 特征在于， 所述形成 NSINK区注入的离子为磷离子。
3. 根据权利要求 2所述 VDMOS晶体管兼容 LDMOS晶体管的制作方法， 其 特征在于， 所述注入离子的剂量为 lxl015/cm2, 能量为 300KeV~400KeV。
4. 根据权利要求 1所述 VDMOS晶体管兼容 LDMOS晶体管的制作方法， 其 特征在于， 所述形成 N埋层区域注入的离子为锑离子， 注入离子的剂量为 l l015/cm2, 能量为 40KeV。
5. 根据权利要求 1所述 VDMOS晶体管兼容 LDMOS晶体管的制作方法， 其 特征在于， 所述形成漂移区还包括： 向 P阱局部区域注入磷离子， 形成漂移区； 在漂移区进行氧化工艺形成 LOCOS场板。
6. 根据权利要求 5所述 VDMOS晶体管兼容 LDMOS晶体管的制作方法， 其 特征在于， 所述注入磷离子的剂量为 l x l012/cm2, 能量为 40KeV~50KeV。
7. 根据权利要求 5所述 VDMOS晶体管兼容 LDMOS晶体管的制作方法， 其 特征在于， 所述氧化漂移区的方法为湿氧热氧化法。
8. 根据权利要求 1所述 VDMOS晶体管兼容 LDMOS晶体管的制作方法， 其 特征在于， 所述形成 PBODY 区注入的离子为硼离子， 注入离子的剂量为 2x l013/cm2, 能量为 40KeV。
9. 根据权利要求 1所述 VDMOS晶体管兼容 LDMOS晶体管的制作方法， 其 特征在于， 所述形成 N型 GRADE 区注入的离子为磷离子， 注入离子的剂 量为 l x l 013/cm2, 能量为 80KeV~100KeV。
10.根据权利要求 1所述 VDMOS晶体管兼容 LDMOS晶体管的制作方法， 其 特征在于， 所述形成源极 /漏极注入的离子为砷离子， 注入离子的剂量为 4x l015/cm2, 能量为 80KeV。
11.根据权利要求 1所述 VDMOS晶体管兼容 LDMOS晶体管的制作方法， 其 特征在于， 所述形成 P+区注入的离子为二氟化硼离子， 注入离子的剂量为 2x l015/cm2, 能量为 60KeV~80KeV。
12.—种 VDMOS 晶体管兼容 LDMOS 晶体管， 包括： 衬底， 所述衬底具有 LDMOS晶体管区和 VDMOS晶体管区； 位于衬底内的 N埋层区域； 位于 N埋层区域上的外延层； 在 LDMOS晶体管区的 N外延层内形成有 N阱和 与 N阱相接的 P阱；在 VDMOS晶体管区形成有高压 N阱；位于在 LDMOS 晶体管区的 N阱和 P阱交界处及 LDMOS晶体管区和 VDMOS晶体管区交 界处的隔离区；位于 LDMOS晶体管区的 P阱区域的漂移区；位于 LDMOS 晶体管区的 P阱区域的部分外延层和部分漂移区上， 以及在 VDMOS晶体 管区的外延层上的栅极； 位于 LDMOS 晶体管区栅极和隔离区之间的外延 层内， 以及位于 VDMOS晶体管区的栅极之间的外延层内的 PBODY区； 位于 LDMOS 晶体管区漂移区之间的外延层内的 N型 GRADE 区； 位于 LDMOS晶体管区和 VDMOS晶体管区的 PBODY区内的源极；位于 LDMOS 晶体管区的 PBODY区内的 P+区， 所述 P+区与源极相接。 其特征在于， 还 包括： 位于 VDMOS晶体管区隔离区与邻近栅极之间的外延层内的 NSINK 区， 所述 NSINK 区与 N埋层区域连通； 位于 LDMOS 晶体管区的 N型 GRADE区内和 NSINK区内的漏极。
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