CN105931983B - 用于高压器件的低成本的掩膜还原方法及器件 - Google Patents

用于高压器件的低成本的掩膜还原方法及器件 Download PDF

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CN105931983B
CN105931983B CN201610074498.5A CN201610074498A CN105931983B CN 105931983 B CN105931983 B CN 105931983B CN 201610074498 A CN201610074498 A CN 201610074498A CN 105931983 B CN105931983 B CN 105931983B
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conduction type
type
layer
break
barrier layer
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CN105931983A (zh
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秀明土子
雷燮光
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Alpha and Omega Semiconductor Cayman Ltd
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Alpha and Omega Semiconductor Inc
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Abstract

本发明提出了一种半导体器件及其制备方法，该器件包括P‑型半导体衬底、在半导体衬底上方的N‑型阱、在N‑型阱中被一个或多个P‑型隔离结构隔开的P型区、以及在P‑型区下方被隔离结构隔开的N‑型穿通阻挡层。与N‑型阱相比，穿通阻挡层重掺杂。P‑型区在两个隔离结构之间的宽度等于或小于N‑型穿通阻挡层的宽度。半导体器件可以是双极晶体管、CMOS器件或DMOS器件。利用本发明的技术，任意器件组合可以集成在一个单独芯片上。

Description

用于高压器件的低成本的掩膜还原方法及器件
技术领域
本发明主要涉及半导体器件，更确切地说，是关于在同一集成电路上集成高压和低压器件的结构及其制备方法。
背景技术
双极-CMOS-DMOS（BCD）工艺技术在一个单独的芯片上，结合了双极晶体管、互补的金属-氧化物-半导体（CMOS）器件以及双扩散金属-氧化物-半导体（DMOS）器件。双极器件用于模拟电路，CMOS器件用于逻辑电路，DMOS器件用于高压器件。BCD器件具有双极晶体管的高频和高功率驱动性能的优势，CMOS晶体管的低功率消耗和高集成密度的优势，每个DMOS晶体管的漏极和源极之间优良的功率可控性，以及大电流和高击穿电压等优势。因此，BCD技术常用于制备高压功率管理集成电路或模拟片上系统应用，在无线便携电子产品和消费电子产品中有着特殊应用。
通常在BCD技术中，最高的工作电压受到以下限制：（1）PN结垂直结构的穿通击穿，（2）高压阱至p-衬底或接地，和/或（3）其他参数。这种垂直结击穿是外延厚度、掺杂浓度以及结深度的函数。因此，除了高压和低压器件的隔离之外，BCD技术还需要一个N-型阻挡层，在高压阱中拥有一个低压器件，以防止穿通。图1A表示带有传统隔离和穿通阻挡层结构的BCD器件10的示例。器件10具有一个N-型外延层14，在P-型衬底12上。多个P-型区（P-阱）16和18位于N-外延层14中，而没有显示器件的具体结构。制备掩埋的P-型区22需要一个专用掩膜，从N-外延层14的底部向上延伸到P-阱18的底部边缘中，并且合并在一起。掩埋的P-型区22还向下延伸到衬底12中，因此使器件10与要制备其他器件的半导体芯片剩余区域隔离。器件10还包括一个N-型掩埋区20，在P-阱16下方，防止P-阱16和P-型衬底12之间的穿通，从而限制器件10的最大工作电压。N-型掩埋区20在制备过程中需要一个专用掩膜。因此，通过使用一定厚度的N-外延层14，并且控制P-阱16的深度以及N-型外延区20和P-型掩埋区22之间的水平距离，可以优化器件10的性能。
制备工艺将从衬底材料12开始，对区域20和22进行离子注入，以便分别形成在后续过程中。需要一个专用的零掩膜，刻蚀硅的未使用区域，以保留用于对准的标记。然后，在衬底材料12的上方放置一个外延层14，制备多个N-阱和P-阱从外延层的顶面开始向下延伸。通过额外的工艺，形成一种特殊功能，例如双极晶体管或MOSFET。要注意的是，可以使用P-外延层代替N-外延层，但是需要一个额外的足够深的轻掺杂N-阱区，将P-转换成N-。N外延只能通过P-隔离形成N-阱。
还可选择，如图1B所示，通过全部注入，在P-型衬底12a上方形成一个P-型掩埋层22a。另外，P-阱隔离区18a必须足够深，以接触P-型掩埋层22a。利用这种结构，可以使用一个较小的掩膜。虽然图1B所示结构对于工作电压相对很低（例如小于40伏）的器件来说非常好，但是当器件具有较高的工作电压（例如100V或更高）时，通常使用图1A所示的结构。
BCD器件的制备可能需要复杂的工艺技术，以及大量的光掩膜。制备N-型掩埋区20和P-型掩埋层22以及轻掺杂的深N-阱区（图中没有表示出）用于制备N-阱，需要高温长程扩散循环。此外，外延工艺昂贵。因此，传统的BCD工艺流程冗长而且昂贵，从而增加了BCD器件的制备成本。制备BCD器件的不同处理工艺仍然需要降低制备成本，以提高性能。
正是在这样的背景下，提出了本发明的实施例。
发明内容
本发明的目的在于提供一种半导体器件及其制备方法，能够在同一集成电路上集成高压和低压器件。
本发明的一个技术方案是提供一种半导体器件，包括：
一个第一导电类型的半导体衬底；
一个第二导电类型的第一层，在第一导电类型的半导体衬底上方；
一个或多个第一导电类型的隔离结构，在一部分第二导电类型的第一层中，其中配置一个或多个隔离结构，使形成在第二导电类型的第一层中的第一导电类型区域隔离，其中一个或多个隔离结构向深处延伸，穿过第二导电类型的第一层，到达第一导电类型的半导体衬底；以及
一个第二导电类型的穿通阻挡层，在第一导电类型的区域下方，被第一导电类型的一个或多个隔离结构隔开；其中与第二导电类型的第一层相比，第二导电类型的穿通阻挡层重掺杂，其中第一导电类型的区域宽度等于或小于第二导电类型的穿通阻挡层宽度。
其中，该器件可以配置成双极晶体管、互补型金属-氧化物-半导体（CMOS）器件或双扩散金属-氧化物-半导体（DMOS）器件。
其中，该器件可以配置成N-通道横向双扩散金属-氧化物-半导体（NLDMOS）器件、双重降低表面电场NLDMOS器件、P-通道LDMOS（PLDMOS）器件、垂直NPN晶体管、横向PNP晶体管或N-型结栅极场效应晶体管（NJFET）。
其中，第一导电类型为P，第二导电类型为N。
其中，第二导电类型的第一层的掺杂浓度约为1×1015cm-3。
其中，第二导电类型穿通阻挡层的掺杂浓度范围为1×1016cm-3至1×1017cm-3左右。
本发明的另一个技术方案是提供一种半导体器件的制备方法，包括：
a）在第一导电类型的半导体衬底上方，制备一个第二导电类型的不带图案的第一层；
b）制备一个或多个第一导电类型的隔离结构，其中一个或多个隔离结构向深处延伸，穿过第二导电类型的第一层，到达第一端导电类型的半导体衬底；
c）在被一个或多个隔离结构隔开的那部分第一层中，制备一个第一导电类型的区域；并且
d）在被一个或多个隔离结构隔开的第一导电类型的区域下方，制备一个第二导电类型的穿通阻挡层，其中与第二导电类型的第一层相比，第二导电类型的穿通阻挡层重掺杂。
其中，第一导电类型为P，第二导电类型为N。
其中，第二导电类型的第一层的掺杂浓度约为1×1015cm-3。
其中，第二导电类型穿通阻挡层的掺杂浓度范围为1×1016cm-3至1×1017cm-3左右。
其中，通过带有隔离掩膜的离子注入以及驱动扩散工艺，制备多个隔离结构，其中隔离掩膜与有源区掩膜制成的多个有源区图案对准。
其中，驱动扩散工艺驱动第二导电类型的第一层以及第一导电类型的隔离结构中的离子。
其中，利用第一阱掩膜，通过中等能量离子注入，制备第一导电类型的区域，利用第一阱掩膜或不同于第一阱掩膜的第二阱掩膜，通过高能离子注入，制备第二导电类型的穿通阻挡层，其中第一导电类型的区域在两个邻近的隔离结构之间的宽度，等于或小于第二导电类型的穿通阻挡层的宽度。
其中，利用第一阱掩膜制备第一导电类型的区域之后，增大了第一阱掩膜开口的尺寸，然后利用相同的掩膜制备穿通阻挡层。
其中，第二导电类型不带图案的第一层，由全面注入（blanket implantation）制成。
其中，第二导电类型不带图案的第一层以及第二导电类型的穿通阻挡层都是通过沉积形成的外延层，其中第二导电类型的第一层在第二导电类型的穿通阻挡层上方。
所述的方法中，还包括在第二导电类型的穿通阻挡层下方以及半导体衬底上方，制备一个第二导电类型的第二层，其中外延层中的第二导电类型的第二层，其掺杂浓度类似于第二导电类型第一层的掺杂浓度。
其中，第二导电类型穿通阻挡层的厚度小于第二导电类型第一层的厚度。
综上所述，本发明的优点在于，通过多个方面的实施例，说明依据本发明的技术允许将双极、CMOS和DMOS器件集成在一个单独晶圆上。这样有利于制备以下紧凑型器件，包括例如实现逻辑功能的CMOS元件，实现模拟器件的双极元件，以及实现高压器件的DMOS元件。
本发明能够有效省去制备NBL和DNW昂贵的外延和高温长程扩散循环，可以大幅降低成本。尤其是全面磷注入和场氧化物的制备，可以代替这些昂贵的工艺，同时仍然形成所需的N-阱区。基于本发明的技术可以避免使用零掩膜，减少用于制备P-型隔离结构、N-掩埋层穿通阻挡层和P-掩埋层的掩膜和长程高温扩散工艺步骤。
本发明的工艺还可以使用P-型半导体衬底作为起始材料。衬底可以分成多个区域，用于制备不同工作电压额定值的器件。每个区域都被本文所述的隔离结构隔开。
附图说明
阅读以下详细说明，并参照附图之后，本发明的目的及优势将显而易见：
图1A和1B表示传统半导体器件示例的剖面示意图。
图2A-2G表示依据本发明的一个方面，利用低成本的掩膜还原方法制备半导体器件的一系列剖面示意图。
图3表示依据图2A-2G的方向，带有隔离结构和穿通阻挡层器件的剖面示意图。
图4A-4G表示依据本发明的各个方面，配置的各种器件的示例。
图5A-5F表示依据本发明的一个方面，器件制备方法的一系列剖面示意图。
图5F’表示根据图5A-5F所示的一种变化的方法，利用带角度的注入，制备穿通阻挡层的剖面示意图。
图5F-1至5F-4表示根据图5A-5F所示的另一种变化的方法，包括在注入之前，减小光致抗蚀剂的厚度，增大开口，以制备一个穿通阻挡层。
图6表示依据图5A-5F所示，带有隔离结构和穿通阻挡层的器件的剖面示意图。
图7A-7G表示依据本发明的各个方面，制备不同器件的示例。
图8A-8F表示依据本发明的一个方面，器件制备方法的一系列剖面示意图。
图8B-1表示利用图8A-8F所示的一种变化的方法，带有隔离结构器件的剖面示意图。
图9表示依据图8A-8F的示例，带有隔离结构和穿通阻挡层器件的剖面示意图。
图10A-10E表示依据本发明的各个方面，配置各种器件的示例。
具体实施方式
在以下详细说明中，参照附图，表示本发明可以实施的典型实施例。就这一点而言，根据图中所示方向，使用“顶部”、“底部”、“正面”、“背面”、“向前”、“向后”等方向术语。由于本发明实施例的零部件，可以位于各种不同方向上，因此所用的方向术语仅用于解释说明，不用于局限。应明确，无需偏离本发明的范围，就能实现其他实施例，做出结构或逻辑上的变化。因此，以下详细说明不用于局限，本发明的范围应由所附的权利要求书限定。
本发明的实施例提出了一种带有N-型穿通阻挡层的BCD器件，其中N-型穿通阻挡层形成在P-型层下方。N-型穿通阻挡层可以利用全面注入或外延沉积形成。P-型层下方的N-型穿通阻挡层，终止了到P-型衬底的穿通。另外，用于使高压器件和低压器件隔离的隔离结构的制备，可以通过高能和低能硼注入以及/或者低能硼注入之后高温/长程驱动。依据本发明的实施例，可以引入最少的光掩膜和制备工艺，制备这种BCD器件。以下提出了在p-型层下方制备N-型穿通阻挡层的三个实施例。
第一个实施例
图2A-2G表示依据本发明的一个实施例，器件制备方法的一系列剖面示意图。如图2A所示，工艺从P-型半导体衬底202作为初始材料刻蚀。衬底202可以分成多个区域，用于制备不同工作电压额定值的器件。每个区域都由下文所述的隔离结构隔离。为了示例，图中表示形成在两个隔离结构之间的半导体器件。这样做是为了说明常用的制备工艺，并不用于限制本发明的任何实施例。要理解的是，半导体器件可以是双极晶体管、CMOS器件或DMOS器件。还应理解，利用以下说明提出的技术，任意器件组合可以集成在一个单独的芯片上。
在P-型衬底202上首先生长屏蔽氧化物（例如一层二氧化硅SiO2）。屏蔽氧化物的厚度范围为200至300Å（埃）。屏蔽氧化物终止了沟道作用，用作保护P-型衬底表面的一个盖。然后，通过全面磷注入，在P-型衬底202上方形成一个N-型层204，如图2B所示。N-型层204的掺杂浓度约为1×1015cm-3。
在图2C中，可以在N-型层204上方，沉积一个氮化硅（SiN）层206。SiN层206的厚度约为1000Å至2000Å左右。光致抗蚀剂（图中没有表示出）形成在层206上，形成图案，作为有源区掩膜。通过光致抗蚀剂中的开口，刻蚀掉暴露于蚀刻剂的那部分层206，形成SiN图案206，刻蚀在N-型层204的表面终止。然后，形成一个隔离掩膜208，定义隔离区。也就是说，隔离掩膜208为隔离结构覆盖不接受硼注入的区域。如图2D所示，将隔离掩膜208对准到有源区掩膜制成的SiN图案206。因此，可以省去用于对准的零掩膜。通过硼注入，形成一个或多个P-型隔离结构210。
在图2E中，利用热场氧化循环，生长场氧化物212，并且驱动磷和硼，分别形成N-型阱204和P-型隔离结构210。也就是说，利用隔离掩膜208，只通过一次掩膜工艺，就能形成N-型阱204和P-型隔离区210。要注意的是，如果使用浅沟槽隔离物（STI）的话，那么衬里氧化循环可以用于驱动。
制备深N-阱（DNW）掩膜214，定义N掩埋层（NBL）区。通过掩膜214中的开口，进行高能注入，制备一个掩埋N-型穿通阻挡层216，如图2F所示。DNW注入接受低温短程扩散，保护急剧锐化的注入形状。穿通阻挡层216用作重掺杂的N-型掩埋层，掺杂浓度范围为1×1017cm-3至1×1018cm-3左右。此后，利用另一个光掩膜220，利用中等注入能量的P-型注入（例如硼），在较深的N-型穿通阻挡层216上方形成P-型层/区218，如图2G所示。在本例中，P-型区218在两个邻近的隔离结构之间的厚度，小于穿通阻挡层216的厚度。在一些实施例中，P-型层/区218可以是用于LV NMOS本体的P-阱，用于VNPN基极的P-基极，或用于PLDMOS漏极延伸物的P-漂移。由于N-型注入和P-型注入使用两个单独的掩膜，因此P-型层218和N-型穿通阻挡层216的尺寸不同。
依据本发明的各个方面，省去制备NBL和DNW昂贵的外延和高温长程扩散循环，可以大幅降低成本。尤其是全面磷注入和场氧化物的制备，可以代替这些昂贵的工艺，同时仍然形成所需的N-阱区。除了避免必须使用昂贵的外延工艺之外，关于第一个实施例的本方法还可以节省成本，并且避免必须使用零掩膜，减少用于制备P-型隔离结构210、N-掩埋层穿通阻挡层216和P-掩埋层218的掩膜和长程高温扩散工艺步骤。
图3表示依据本发明的上述实施例，带有隔离结构和穿通阻挡层器件的剖面示意图。确切地说，器件可以形成在N-型穿通阻挡层216上方的N-型阱204中，以及两个邻近的P-型隔离结构210之间，其中穿通阻挡层216上方的P-型层218的宽度，小于穿通阻挡层216的宽度。N-型穿通阻挡层216终止P-型层/区218和P-型衬底202之间的穿通或联通。要理解的是，该器件可以是双极晶体管、CMOS或DMOS器件。图4A-4G表示依据本发明的实施例，配置的各种器件的示例。对于本领域的技术人员来说，这些器件众所周知，因此，为了简便，省去了这些器件的功能说明以及制备工艺。
图4A表示器件401的有源区配置成低压CMOS，包括一个NMOS形成在P-阱区（P-型层/区）218中，以及一个PMOS形成在N-阱区410中。P-阱区中NMOS的工作电压范围为1-10伏，并且可以浮动至高于接地端的电势。器件结构的隔离，使这种器件具有较低的噪声。
图4B表示一个可选实施例，其中器件402的要求配置成一个N-通道LDMOS，包括一个N+源极区420位于P-阱区218中，以及一个N+漏极接触吸引区422位于N-阱或N-漂流区424中。
图4C表示双重降低表面电场NLDMOS器件403的一个可选实施例，双重降低表面电场NLDMOS器件403形成在两个P-型隔离结构210之间的N-型阱204中。器件403的有源区包括一个N+源极区430，位于P-阱区218中，以及一个N+漏极接触吸引区432，位于N-阱区434中。双重降低表面电场NLDMOS器件403在横向器件导通状态下（Rds-on），为源极和漏极之间提供低电阻。
图4D表示P-通道LDMOS器件404的一个可选实施例，P-通道LDMOS器件404形成在两个P-型隔离结构210之间的N-型阱204中。除了P+源极区440现位于N-阱区444中，作为本体，P+漏极接触吸引区442现位于P-阱或P漂流区218中，作为漏极之外，P-通道LDMOS 404可以用与图4B所示相同的方式制备。
图4E表示高压垂直NPN晶体管（VNPN）405的一个可选实施例，高压垂直NPN晶体管（VNPN）405形成在两个p-型隔离结构210之间。器件405的有源区包括一个重掺杂N+区450，位于高压P-阱区（HVPW）218中。重掺杂N+区450、P-阱区218以及P-阱218下方的N-型区216和204，配置带有N+区450的垂直NPN，作为发射极，P-阱218作为基极，HVPW 218下方的N-型区作为集电极。位于HVPW 218中的P+区452为基极提供接触传感器，同时位于HVPW 218以外的N-型阱204顶部的N-型区454，为集电极提供接触传感器。
图4F表示一个可选实施例，其中器件406的要求配置成横向PNP（LPNP），包括P区460作为发射极，P环462作为集电极包围着中心P发射极区460，N环464作为基极接触传感器，包围着集电极P环462和发射极P区460。
图4G表示N-型结栅极场效应晶体管（NJFET）407的一个可选实施例，N-型结栅极场效应晶体管（NJFET）407形成在两个p-型隔离结构210之间。器件407的有源区包括一个重掺杂P+区470，位于P-阱区218中，作为栅极。栅极接触N-型区216，构成一个PN结。
第二个实施例
图5A-5F表示依据本发明的一个实施例，器件制备方法的一系列剖面示意图。在图5A中，该工艺使用P-型半导体衬底502作为起始材料。衬底502可以分成多个区域，用于制备不同工作电压额定值的器件。每个区域都被下文所述的隔离结构隔开。为了示例，该图表示形成在两个隔离结构之间的半导体器件。这只是为了表示通用的制备工艺，并不意味着对本发明实施例的局限。要理解的是，该半导体器件可以是双极晶体管、CMOS器件或DMOS器件。还应理解的是，利用下文中所述的技术，任意器件组合都可以集成在一个单独芯片上。
在P-型衬底502上生长厚度为200-300Å的屏蔽氧化物（例如一层二氧化硅SiO2）之后，通过全面磷注入，在P-型衬底502上方制备一个N-型层504，如图5B所示。N-型层204的掺杂浓度约为1×1015cm-3。
在图5C中，一层氮化硅（SiN）506可以沉积在N-型层504上方。SiN层506的厚度约为1000Å至2000Å左右。在层506上形成光致抗蚀剂（图中没有表示出），形成图案，作为有源区掩膜。通过光致抗蚀剂中的开口，刻蚀掉暴露于蚀刻剂的那部分层506，构成SiN图案506，刻蚀在N-型层504的表面上终止。然后，制备一个隔离掩膜508，以定义隔离区。也就是说，隔离掩膜508为隔离结构覆盖了没有接受硼注入的区域。如图5D所示，隔离掩膜508对准到有源区掩膜制成的SiN图案506。从而，可以省去用于对准的零掩膜。然后，通过硼注入，制备P-型隔离层510。
在图5E中，利用热场氧化循环，生长场氧化物512，还驱动磷和硼，分别构成N-型阱504和P-型隔离区510。也就是说，利用隔离掩膜508，可以只用一个掩膜步骤，就制成N-型阱504和P-型隔离区510。要注意的是，如果使用浅沟槽隔离物（STI）的话，衬里氧化循环将作为驱动。
图5F表示利用一个掩膜步骤，可以在较高能量下进行重掺杂N型注入，在较低能量下进行P型注入。也就是说，可以省去深N-阱（DNW）掩膜步骤。确切地说，利用光掩膜514，通过高能N-型注入（例如磷）制备N-型穿通阻挡层516，通过P-型注入（例如硼）在中等注入能量下，在较深的n-型穿通阻挡层516上方，形成一个P-型层/区518。N-型穿通阻挡层516重掺杂，其掺杂浓度范围为1×1016cm-3至1×1018cm-3左右。DNW注入接受低温短程扩散，保存了急剧尖锐的注入形状。在一些实施例中，P-型层/区518对LV NMOS本体来说，可以P-阱，对于VNPN基极来说，可以是P-基极，或者对于PLDMOS漏极延伸物来说，可以是P-漂移。要注意的是，由于N-型和P-型注入物使用一个单独的掩膜，因此N-型穿通阻挡层516和P-型层/区518的厚度相同。在本结构中，P型层518下方的重掺杂N型穿通阻挡层516，终止了P型层518和P-型衬底502之间的穿通。
必须有一个比P型层518更宽的N型穿通阻挡层516，以防止从P型层518的拐角到P-型衬底502的穿通。图5F’表示一种可能的实施例，其中利用带角度的注入，制备比P-型层518更宽的穿通阻挡层516。带角度的注入通常包括指挥与衬底表面呈一定角度的一束离子，同时在垂直于表面的轴周围旋转衬底。通过控制注入的角度和能量，注入穿通阻挡层516的N-型掺杂物可以制得足够深、足够宽，从而避免穿通。
在另一个可能的实施例中，在中等能量的P-型注入和高能N-型注入之间，进行光致抗蚀剂514的部分灰化，如图5F-1至5F-3所示。确切地说，图5E的工艺之后，在图5E的结构上形成光致抗蚀剂514，并形成图案，如图5F-1所示。利用中等能量P-型注入，制备P-型层518。然后，通过光致抗蚀剂514的部分灰化，减小光致抗蚀剂514的厚度，增大掩膜开口的宽度，如图5F-2所示。在图5F-3中，通过高能N-型注入，在P-型层518下方制备N型穿通阻挡层516。如图5F-3所示，较深的N型穿通阻挡层516比形成在上方的P-型层518更宽。在一个可选的进一步改进方案中，通过带角度的注入N-型注入物，使穿通阻挡层516更宽，如图5F-4所示。
图6表示依据本发明的上述实施例，带有隔离结构和穿通阻挡层的器件600的剖面示意图。确切地说，器件可以形成在N-型穿通阻挡层516上方的N-型阱504中，以及两个邻近的P-型隔离结构510之间，其中穿通阻挡层516上方的P-型层518的尺寸近似相等。N-型穿通阻挡层516终止了P-型层/区518和P-型衬底502之间的穿通。要理解的是，该器件可以是双极晶体管、CMOS或DMOS器件。与上述第一个实施例所述的方法类似，第二个实施例的方法还避免了使用零掩膜和外延层。另外，与第二个实施例相关的方法可以节省成本，减少掩膜步骤，避免了制备P-型隔离结构510、N-掩埋层穿通阻挡层516和P-型层518过程中的长程高温扩散工艺。
图7A-7G表示依据本发明的实施例，配置不同器件的示例。对于本领域的技术人员来说，这些器件众所周知，因此可以省去这些器件的功能说明以及制备工艺。
图7A表示一个低压CMOS器件701，形成在两个P-型隔离结构510之间的N-型阱504中。器件701的有源区包括形成在P-阱区（P-型层/区）518中的NMOS，以及形成在N-阱区710中的PMOS。
图7B表示一个可选实施例，其中器件702的有源区配置成N-通道LDMOS，N-通道LDMOS包括一个位于P-阱区518中的N+源极区720，以及一个位于N-阱724中的N+漏极接触传感区722。
图7C表示双重降低表面电场NLDMOS器件703的一个可选实施例，双重降低表面电场NLDMOS器件703形成在两个P-型隔离结构510之间的N-型阱504中。器件703的有源区包括一个N+源极区730，位于P-阱区218中，以及一个N+漏极接触传感区732，位于N-阱区734中。双重降低表面电场NLDMOS器件703在横向器件带有超级结的导通状态下（Rds-on），为源极和漏极之间提供低电阻。
图7D表示P-通道LDMOS器件704的一个可选实施例，P-通道LDMOS器件704形成在两个P-型隔离结构510之间的N-型阱504中。除了P+源极区740现位于N-阱区744中，作为本体，P+漏极接触传感区742现位于P-阱区518中，作为漏极之外，P-通道LDMOS 704可以用与图4B所示相同的方式制备。
图7E表示高压垂直NPN晶体管（VNPN）705的一个可选实施例，高压垂直NPN晶体管（VNPN）705形成在两个p-型隔离结构510之间。器件705的有源区包括一个重掺杂N+区750，位于高压P-阱区（HVPW）518中。重掺杂N+区750、P-阱区518以及P-阱518下方的N-型区516和504，配置带有N+区750的垂直NPN，作为发射极，P-阱518作为基极，HVPW 518下方的N-型区作为集电极。位于HVPW 5中的P+区752为基极提供接触传感器，同时位于HVPW 518以外的N-型阱504顶部的N-型区754，为集电极提供接触传感器。
图7F表示一个可选实施例，其中器件706的要求配置成横向PNP（LPNP），包括P区760作为发射极，P环462作为集电极包围着中心P发射极区760，N环764作为基极接触传感器，包围着集电极P环762和发射极P区760。
图7G表示N-型结栅极场效应晶体管（NJFET）707的一个可选实施例，N-型结栅极场效应晶体管（NJFET）707形成在两个p-型隔离结构510之间。器件707的有源区包括一个重掺杂P+区770，位于P-阱区518中，作为栅极。栅极接触N-型区516，构成一个PN结。
第三个实施例
图8A-8F表示依据本发明的一个实施例，器件制备方法的一系列剖面示意图。在图8A中，该工艺使用P-型半导体衬底802作为起始材料。衬底802可以分成多个区域，用于制备不同工作电压额定值的器件。每个区域都被下文所述的隔离结构隔开。为了示例，该图表示形成在两个隔离结构之间的半导体器件。这只是为了表示通用的制备工艺，并不意味着对本发明实施例的局限。要理解的是，该半导体器件可以是双极晶体管、CMOS器件或DMOS器件。还应理解的是，利用下文中所述的技术，任意器件组合都可以集成在一个单独芯片上。
然后，代替进行全面注入，通过外延沉积在P-型衬底802上制备N-型外延结构。N-型外延结构包括两个或三个N-型外延层。在本例中，N-型外延结构包括两层，如图8B所示，底层804是较重掺杂层，掺杂浓度范围为1×1016cm-3至1×1017cm-3左右，顶层805是次重掺杂层，掺杂浓度约为1×1015cm-3。底层804的厚度约为0.5μm，顶层806的厚度约为1-2μm。在三层结构的示例中，如图8B-1所示，较重掺杂层夹在两个次重掺杂层803和805之间。为了解释说明，图8C-8F仅表示出了带有两层N-外延结构的器件制备的剖面示意图。
在N-型外延结构上生长屏蔽氧化物之后，可以在上方沉积一个氮化硅层（SiN）。SiN层806的厚度约为1000Å至2000Å左右。在层806上制备光致抗蚀剂（图中没有表示出），并形成图案，作为有源区掩膜。通过光致抗蚀剂中的开口，刻蚀掉暴露于蚀刻剂的那部分层806，形成SiN图案806，如图8C所示。
形成一个隔离掩膜808，定义隔离区。也就是说，隔离掩膜808为隔离结构覆盖不接受硼注入的区域。如图8D所示，将隔离掩膜808对准到有源区掩膜制成的SiN图案806。因此，可以省去用于对准的零掩膜。通过硼注入，形成P-型隔离层810。
在图8E中，利用热场氧化循环，生长场氧化物812，并且驱动磷和硼，分别形成N-型阱804和P-型隔离结构810。也就是说，利用隔离掩膜808，只通过一次掩膜工艺，就能形成N-型阱804和P-型隔离区810。要注意的是，如果使用浅沟槽隔离物（STI）的话，那么衬里氧化循环可以用于驱动。
在图8F中，通过光掩膜814，可以利用P-型注入中等能量，在N-型外延层805中制备P-型层818。要注意的是，在本实施例中，不需要N-型注入。P-型层818下方的重掺杂N-型外延层804终止了P-型层和P-型衬底802之间的穿通。因此，可以省去DNW掩膜过程。在本实施例中，优化N-外延结构的厚度和掺杂浓度非常重要。
图9表示依据本发明的上述实施例，带有隔离结构和穿通阻挡层的器件900的剖面示意图。确切地说，器件900具有一个三层N-外延结构。重掺杂N-外延层804夹在次重掺杂层803和805之间。器件形成在N-外延层804上方的N-外延层805中，以及两个邻近的P-型隔离结构810之间。N-外延层804作为穿通阻挡层，终止了P-型层/区818和P-型衬底802之间穿通。要理解的是，该器件可以是双极晶体管、CMOS或DMOS器件。
虽然使用了外延工艺，但是与第三个实施例有关的上述方法仍然可以节省成本，避免使用零掩膜，减少掩膜工艺，避免了制备P-型隔离结构810、N-掩埋层穿通阻挡层816和P-型层818过程中的长程高温扩散工艺。
图10A-10E表示依据本发明的实施例，配置不同器件的示例。对于本领域的技术人员来说，这些器件众所周知，因此可以省去这些器件的功能说明以及制备工艺。
图10A表示一个低压CMOS器件1001，形成在两个P-型隔离结构810之间的N-型层805中。器件1001的有源区包括形成在P-阱区（P-型层/区）818中的NMOS，以及形成在N-阱区1010中的PMOS。
图10B表示一个可选实施例，其中器件1002的有源区配置成N-通道LDMOS，N-通道LDMOS包括一个位于P-阱区818中的N+源极区1020，以及一个位于N-阱1024中的N+漏极接触传感区1022。
图10C表示双重降低表面电场NLDMOS器件1003的一个可选实施例，双重降低表面电场NLDMOS器件1003形成在两个P-型隔离结构810之间的N-外延层805中。器件1003的有源区包括一个N+源极区1030，位于P-阱区818中，以及一个N+漏极接触传感区1032，位于N-阱区1034中。双重降低表面电场NLDMOS器件1003在横向器件导通状态下（Rds-on），通过超级结在源极和漏极之间提供低电阻。
图10D表示P-通道LDMOS器件1004的一个可选实施例，P-通道LDMOS器件1004形成在两个P-型隔离结构810之间的N-外延层805中。除了P+源极区1040现位于N-阱区1044中，作为本体，P+漏极接触吸引区1042现位于P-阱区818中，作为漏极之外，P-通道LDMOS1004可以用与图4B所示相同的方式制备。
图10E表示高压垂直NPN晶体管（VNPN）1005的一个可选实施例，高压垂直NPN晶体管（VNPN）1005形成在两个p-型隔离结构810之间。器件1005的有源区包括一个重掺杂N+区1050，位于高压P-阱区（HVPW）818中。重掺杂N+区1050、P-阱区818以及P-阱818下方的N-外延层805、804和803，配置带有N+区1050的垂直NPN，作为发射极，P-阱818作为基极，HVPW818下方的N-外延层作为集电极。位于HVPW 中的P+区1052为基极提供接触传感器，同时位于HVPW 818以外的N-型层805顶部的N-区1054，为集电极提供接触传感器。另外，依据第三个实施例，器件的有源区可以配置成横向PNP，与图7F所示的有源区类似，或者配置成N-型结栅极场效应晶体管（NJFET），与图7G所示的要求类似。
本发明的各个方面允许将双极、CMOS和DMOS器件集成在一个单独晶圆上。这样有利于制备以下紧凑型器件，包括例如实现逻辑功能的CMOS元件，实现模拟器件的双极元件，以及实现高压器件的DMOS元件。
因此，本发明的范围不应局限于以上说明，而应由所附的权利要求书及其全部等效内容决定。本方法中所述步骤的顺序并不用于局限进行相关步骤的特定顺序的要求。任何可选件（无论首选与否），都可与其他任何可选件（无论首选与否）组合。在以下权利要求中，除非特别声明，否则不定冠词“一个”或“一种”都指本文内容中的一个或多个项目的数量。除非在指定的权利要求中用“意思是”特别指出，否则所附的权利要求书应认为是包括意义及功能的限制。权利要求书中没有用“意思是”特别指出用于特定功能的任意项目，都不应认为是具体所述的“意思”或“步骤”。

Claims (17)

1.一种半导体器件，其特征在于，包括：
一个第一导电类型的半导体衬底；
一个第二导电类型的第一层，在第一导电类型的半导体衬底上方；
一个或多个第一导电类型的隔离结构，在一部分第二导电类型的第一层中，其中配置一个或多个隔离结构，使形成在第二导电类型的第一层中的一个第一导电类型的区域隔离，其中一个或多个隔离结构向深处延伸，穿过第二导电类型的第一层，到达第一导电类型的半导体衬底；其中，第一导电类型的区域通过第一阱掩膜制备，并在制备后使第一阱掩膜的开口尺寸增大，以及
一个第二导电类型的穿通阻挡层，利用开口尺寸增大了的同一个第一阱掩膜制备，在第一导电类型的区域下方，被第一导电类型的一个或多个隔离结构隔开；其中与第二导电类型的第一层相比，第二导电类型的穿通阻挡层重掺杂，其中第一导电类型的区域宽度等于或小于第二导电类型的穿通阻挡层宽度。
2.如权利要求1所述的半导体器件，其特征在于，其中该器件配置成双极晶体管、互补型金属-氧化物-半导体器件或双扩散金属-氧化物-半导体器件。
3.如权利要求1所述的半导体器件，其特征在于，其中该器件配置成N-通道横向双扩散金属-氧化物-半导体器件、双重降低表面电场NLDMOS器件、P-通道LDMOS器件、垂直NPN晶体管、横向PNP晶体管或N-型结栅极场效应晶体管。
4.如权利要求1所述的半导体器件，其特征在于，其中第一导电类型为P，第二导电类型为N。
5.如权利要求1所述的半导体器件，其特征在于，其中第二导电类型的第一层的掺杂浓度为1×1015cm-3。
6.如权利要求1所述的半导体器件，其特征在于，其中第二导电类型的穿通阻挡层的掺杂浓度范围为1×1016cm-3至1×1017cm-3。
7.一种半导体器件的制备方法，其特征在于，包括：
a）在第一导电类型的半导体衬底上方，制备一个第二导电类型的不带图案的第一层；
b）制备一个或多个第一导电类型的隔离结构，其中一个或多个隔离结构向深处延伸，穿过第二导电类型的第一层，到达第一导电类型的半导体衬底；
c）在被一个或多个隔离结构隔开的那部分第一层中，利用第一阱掩膜制备一个第一导电类型的区域；制备第一导电类型的区域之后，增大第一阱掩膜开口的尺寸，并且
d）在被一个或多个隔离结构隔开的第一导电类型的区域下方，利用开口尺寸增大了的同一个所述第一阱掩膜制备一个第二导电类型的穿通阻挡层，其中与第二导电类型的第一层相比，第二导电类型的穿通阻挡层重掺杂。
8.如权利要求7所述的制备方法，其特征在于，其中第一导电类型为P，第二导电类型为N。
9.如权利要求7所述的制备方法，其特征在于，其中第二导电类型的第一层的掺杂浓度为1×1015cm-3。
10.如权利要求7所述的制备方法，其特征在于，其中第二导电类型穿通阻挡层的掺杂浓度范围为1×1016cm-3至1×1017cm-3。
11.如权利要求7所述的制备方法，其特征在于，其中通过带有隔离掩膜的离子注入以及驱动扩散工艺，制备多个隔离结构，其中隔离掩膜与有源区掩膜制成的多个有源区图案对准。
12.如权利要求11所述的制备方法，其特征在于，其中驱动扩散工艺驱动第二导电类型的第一层以及第一导电类型的隔离结构中的离子。
13.如权利要求7所述的制备方法，其特征在于，其中利用第一阱掩膜，通过中等能量离子注入，制备第一导电类型的区域，以及利用第一阱掩膜或不同于第一阱掩膜的第二阱掩膜，通过高能离子注入，制备第二导电类型的穿通阻挡层，其中第一导电类型的区域在两个邻近的隔离结构之间的宽度，等于或小于第二导电类型的穿通阻挡层的宽度。
14.如权利要求7所述的制备方法，其特征在于，其中第二导电类型的不带图案的第一层，由全面注入制成。
15.如权利要求7所述的制备方法，其特征在于，其中第二导电类型的不带图案的第一层以及第二导电类型的穿通阻挡层都是通过沉积形成的外延层，其中第二导电类型的第一层在第二导电类型的穿通阻挡层上方。
16.如权利要求15所述的制备方法，其特征在于，还包括在第二导电类型的穿通阻挡层下方以及半导体衬底上方，制备一个第二导电类型的第二层，其中外延层中的第二导电类型的第二层，其掺杂浓度类似于第二导电类型的第一层的掺杂浓度。
17.如权利要求15所述的制备方法，其特征在于，其中第二导电类型的穿通阻挡层的厚度小于第二导电类型的第一层的厚度。
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