TWI762535B - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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Publication number
TWI762535B
TWI762535B TW106143041A TW106143041A TWI762535B TW I762535 B TWI762535 B TW I762535B TW 106143041 A TW106143041 A TW 106143041A TW 106143041 A TW106143041 A TW 106143041A TW I762535 B TWI762535 B TW I762535B
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Taiwan
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semiconductor chip
semiconductor
semiconductor device
lead
pin
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TW106143041A
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TW201828448A (zh
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中村弘幸
下山浩哉
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日商瑞薩電子股份有限公司
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    • B—PERFORMING OPERATIONS; TRANSPORTING
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    • B62D5/0403—Power-assisted or power-driven steering electrical, e.g. using an electric servo-motor connected to, or forming part of, the steering gear characterised by constructional features, e.g. common housing for motor and gear box
    • B62D5/0406—Power-assisted or power-driven steering electrical, e.g. using an electric servo-motor connected to, or forming part of, the steering gear characterised by constructional features, e.g. common housing for motor and gear box including housing for electronic control unit
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Abstract

本發明之課題在於使半導體裝置之性能提高。 本發明之半導體裝置PKG係以密封部MR密封包含高側開關用之第1場效電晶體之半導體晶片CPH、包含低側開關用之第2場效電晶體之半導體晶片CPL、及包含控制半導體晶片CPH、CPL各者之電路之半導體晶片CPC的半導體裝置。將第1場效電晶體之源極用且電性連接於半導體晶片CPH之焊墊PDHS1之引腳LD2、與第2場效電晶體之汲極用且電性連接於半導體晶片CPL之背面電極之引腳LD3，配置於俯視時之密封部MR的同一邊。

Description

半導體裝置
本發明係關於一種半導體裝置，例如可較佳地使用於密封包含高側開關用之場效電晶體之半導體晶片、包含低側開關用之場效電晶體之半導體晶片、及控制該等之半導體晶片的半導體裝置者。
作為電源電路之一例而廣泛使用之換流器電路具有以下構成：於被供給電源電壓之端子與被供給接地電壓之端子之間，串聯連接有高側開關用之功率MOSFET與低側開關用之功率MOSFET。可藉由以控制電路控制高側開關用之功率MOSFET之閘極電壓與低側開關用之功率MOSFET之閘極電壓，而由換流器電路進行電源電壓之轉換。 於日本專利特開2015-2185號公報(專利文獻1)，記載一種具備用以控制電力之複數個功率晶片、及控制各功率晶片之IC(Integrated Circuit：積體電路)之電力用半導體裝置相關之技術。 於日本專利特開2014-30049號公報(專利文獻2)記載一種使晶片焊墊1c露出於密封體3之正面3a側之QFP(Quad Flat Package：四邊平面封裝)21。 [先前技術文獻] [專利文獻] [專利文獻1]日本專利特開2015-2185號公報 [專利文獻2]日本專利特開2014-30049號公報
[發明所欲解決之問題] 對於密封包含高側開關用之場效電晶體之半導體晶片、包含低側開關用之場效電晶體之半導體晶片、及控制該等之半導體晶片的半導體裝置，期望提高性能。或，期望提高安裝半導體裝置之配線基板之配線設計之自由度。或，期望提高半導體裝置之性能，且提高安裝半導體裝置之配線基板之配線設計之自由度。 其他之課題與新穎之特徵可自本說明書之記敍及添附圖式明瞭。 [解決問題之技術手段] 根據一實施形態，半導體裝置係以密封體密封包含高側開關用之第1場效電晶體之第1半導體晶片、包含低側開關用之第2場效電晶體之第2半導體晶片、及包含控制上述第1及第2半導體晶片各者之電路之第3半導體晶片的半導體裝置。半導體裝置進而具備：電性連接於上述第1半導體晶片之上述第1場效電晶體之汲極用之第1汲極電極的第1引腳，及電性連接於上述第1半導體晶片之上述第1場效電晶體之源極用之第1源極電極的第2引腳。半導體裝置進而具備：電性連接於上述第2半導體晶片之上述第2場效電晶體之汲極用之第2汲極電極的第3引腳，及電性連接於上述第2半導體晶片之上述第2場效電晶體之源極用之第2源極電極的第4引腳。於俯視時，上述密封體具有沿著第1方向延伸之第1邊、與沿著上述第1方向延伸，且位於與上述第1邊為相反側之第2邊，上述第1引腳與上述第4引腳與上述密封體之上述第1邊交叉，上述第2引腳與上述第3引腳與上述密封體之上述第2邊交叉。於俯視時，於上述第1邊與上述第2邊之間，且上述第1半導體晶片與上述第2半導體晶片之間，配置有上述第3半導體晶片。電流自上述第1引腳經由上述第1半導體晶片之上述第1場效電晶體向上述第2引腳流通，電流自上述第3引腳經由上述第2半導體晶片之上述第2場效電晶體向上述第4引腳流通。 [發明之效果] 根據一實施形態，可提高半導體裝置之性能。 再者，可提高安裝半導體裝置之配線基板之配線設計之自由度。 或者，可提高半導體裝置之性能，並且提高安裝半導體裝置之配線基板之配線設計之自由度。
於以下之實施形態中為了方便起見，於必要時分割成複數個部分或實施形態進行說明，但除了特別明示之情形以外，該等並非互無關係者，而存在一者為另一者之一部分或全部之變化例、細節、補充說明等之關係。又，於以下之實施形態中，於提及要素之數量等(包含個數、數值、量、範圍等)之情形時，除了特別明示之情形及原理上明確限定於特定數量之情形等外，並非限定於該特定之數者，可為特定之數以上或以下。再者，於以下之實施形態中，其構成要素(亦包含要素步驟等)除了特別明示之情形及原理上明確認為必須之情形等以外，當然並非為必須者。同樣地，於以下之實施形態中，於提及構成要素等之形狀、位置關係等時，除了特別明示之情形及原理上明確認為與其相左之情形等以外，則包含實質上與該形狀等近似或類似者等。對於上述數值及範圍亦同。 以下，基於圖式詳細地說明實施形態。另，於用以說明實施形態之所有圖式中，對具有同一功能之構件附註同一符號，省略其反覆說明。又，於以下之實施形態中，除了特別必要時以外，原則上不反覆進行同一或同樣部分之說明。 又，於實施形態中所用之圖式中，即使為剖視圖，為了易於觀察圖式，亦有省略陰影線之情形。又，即使為俯視圖，為了易於觀察圖式，亦有附註陰影線之情形。 又，於本申請案中，將場效電晶體記為MOSFET(Metal Oxide Semiconductor Field Effect Transistor：金屬氧化物半導體場效電晶體)或略記為MOS，但作為閘極絕緣膜並非將非氧化膜除外者。即，於本申請案中，於提及MOSFET時，不僅為對閘極絕緣膜使用氧化膜(氧化矽膜)之MISFET(Metal Insulator Semiconductor Field Effect Transistor：MIS型場效電晶體)，亦包含將氧化膜(氧化矽膜)以外之絕緣膜用於閘極絕緣膜之MISFET。 ＜關於探討之背景＞ 近年來，展望汽車之自動運行之實用化之功能安全，而近行將先前之3相BLDC(無刷DC)馬達設為6相或12相之BLDC馬達之設計開發。BLDC馬達由於非自整流型，故普遍認為其控制較為複雜。因此，於6相BLDC馬達中保有2組先前之3相(U相、V相、W相)，於12相BLDC馬達中保有4組先前之3相(U相、V相、W相)，則即使某1組發生異常，異常亦不會立即顯著化。 本發明者探討藉由SiP(System in Package：系統級封裝)進行控制，該SiP包含：包含高側開關用之功率MOSFET之半導體晶片(相當於後述之半導體晶片CHP)、包含低側開關用之功率MOSFET之半導體晶片(相當於後述之半導體晶片CPL)、及控制該等之半導體晶片(相當於後述之半導體晶片CPC)。藉由該SiP形成換流器電路，將自該換流器電路供給之交流電力供給至BLDC馬達之各相線圈。因此，作為控制6相BLDC馬達或12相BLDC馬達之控制板(對應於後述之控制板PB)，本發明者探討於配線基板(對應於後述之配線基板PB1)上搭載6個或12個上述SiP者。另，後述之半導體裝置PKG相當於該SiP者。 圖1係模式性顯示形成於控制12相BLDC馬達之控制板之電路(馬達驅動系統)的電路圖。於圖1中，各換流器電路INV各自由上述SiP形成。 圖1所示之馬達MOT係12相BLDC馬達，具有12個線圈CL，各線圈CL分別連接於換流器電路INV。即，由於對馬達MOT所具有之12個線圈各者設置換流器電路INV，故圖1之電路總計具有12個換流器電路INV。由於需要與換流器電路INV之數量相當之上述SiP，故於圖1之電路中，需要12個上述SiP。各換流器電路INV(更特定而言係換流器電路INV之後述之控制電路CLC)連接於控制電路CT，由該控制電路CT予以控制。自各換流器電路INV向連接於該換流器電路INV之各線圈CL供給交流電力，藉此驅動馬達MOT。 圖2係顯示汽車之齒條與小齒輪型之轉向機構之說明圖。本發明者探討於圖2之轉向機構中，利用轉向軸SF之周圍空間而配置實現圖1之電路之控制板(電子裝置、模組)PB。即，探討轉向軸SF貫通控制板PB。 於圖2所示之轉向機構中，於連結於方向盤(轉向盤)HN之轉向軸SF之前端有齒條與小齒輪機構RP。當轉動方向盤HN時，伴隨與此，轉向軸SF亦旋轉，由齒條與小齒輪機構RP將該旋轉運動轉換為水平運動，經由橫拉桿TR及大王銷KP而傳遞至輪胎TY。藉此，可藉由方向盤HN之操作(旋轉)改變輪胎TY之朝向而進行操舵。 當轉動方向盤HN時，由於轉向軸SF亦旋轉，故於轉向軸SF貫通控制板PB之情形時，控制板PB亦與轉向軸SF一起旋轉。圖3係顯示控制板PB與轉向軸SF一起旋轉之狀態之說明圖(俯視圖)。另，圖3之(a)係顯示控制板PB之平面形狀為矩形(長方形)之情形，圖3之(b)係顯示控制板PB之平面形狀為圓形之情形。 控制板PB旋轉所需之空間於將控制板PB之平面形狀設為圓形時最不佔空間。例如，如圖3之(a)般控制板PB之平面形狀為矩形之情形時，由於以該矩形之對角線長度為直徑之圓形區域為控制板PB旋轉所需之空間，故與控制板PB之尺寸相比，控制板PB旋轉所需之空間變大。相對於此，如圖3之(b)般控制板PB之平面形狀為圓形之情形時，控制板PB旋轉所需之空間與控制板PB之尺寸大致相同。因此，可藉由將控制板PB之平面形狀設為圓形，而有效地抑制配置控制板PB所需且使該控制板PB旋轉所需之空間。 因此，作為控制12相BLDC馬達之控制板PB，本發明者針對平面形狀為圓形狀且搭載12個SiP之控制板PB進行探討。 然而，於此種控制板PB中，由於需要引繞12個SiP所需之配線，故配線之限制變大，從而導致配線設計之自由度降低。因此，對於搭載於此種控制板PB之SiP，亦期望應用如易於進行控制板PB(配線基板)側之配線設計之設計。 ＜關於電路構成＞ 圖4係顯示使用本實施形態之半導體裝置(半導體封裝、電子裝置)PKG之換流器電路INV之電路圖。另，於圖4中，由附註符號CPH之虛線包圍之部分形成於半導體晶片CPH內，由附註符號CPL之虛線包圍之部分形成於半導體晶片CPL內，由附註符號CPC之虛線包圍之部分形成於半導體晶片CPC內，由附註符號PKG之一點鏈線包圍之部分形成於半導體裝置PKG內。 圖4所示之用於換流器電路INV之半導體裝置PKG具有：2個功率MOSFET1、2，用以檢測流通於功率MOSFET1流通之電流之感測MOSFET3、用以檢測流通於功率MOSFET2之電流之感測MOSFET4、及控制電路CLC。控制電路CLC形成於半導體晶片(控制用半導體晶片)CPC內，功率MOSFET1及感測MOSFET3形成於半導體晶片(高側用半導體晶片、功率晶片)CPH內，功率MOSFET2及感測MOSFET4形成於半導體晶片(低側用半導體晶片、功率晶片)CPL內。且，將該等3個半導體晶片CPC、CPH、CPL作為1個相同之封裝予以密封，而形成半導體裝置PKG。另，圖4之換流器電路INV對應於將上述圖1所示之換流器電路INV詳細顯示者。 控制電路CLC包含：控制功率MOSFET1之閘極電位之高側用驅動電路，及控制功率MOSFET2之閘極電位之低側用驅動電路。控制電路CLC係根據自半導體裝置PKG之外部控制電路CT供給至控制電路CLC之信號等而控制功率MOSFET1、2各者之閘極電位，並控制功率MOSFET1、2各者之動作的電路。 功率MOSFET1之閘極連接於控制電路CLC之高側用驅動電路，功率MOSFET2之閘極連接於控制電路CLC之低側用驅動電路。功率MOSFET1之汲極連接於端子TE1，功率MOSFET1之源極連接於端子TE2，功率MOSFET2之汲極連接於端子TE3，功率MOSFET2之源極連接於端子TE4。即，功率MOSFET1其源極-汲極路徑串聯連接於端子TE1與端子TE2之間，功率MOSFET2其源極-汲極路徑串聯連接於端子TE3與端子TE4之間。於圖4中，符號D1表示功率MOSFET1之汲極，符號S1表示功率MOSFET1之源極，符號D2表示功率MOSFET2之汲極，符號S2表示功率MOSFET2之源極。又，於圖4中，符號D3表示感測MOSFET3之汲極，符號S3表示感測MOSFET3之源極，符號D4表示感測MOSFET4之汲極，符號S4表示感測MOSFET4之源極。控制電路CLC連接於端子TE5，該端子TE5與設置於半導體裝置PKG之外部之上述控制電路CT連接。 端子TE1、TE2、TE3、TE4、TE5其任一者均為半導體裝置PKG之外部連接用端子，由後述之引腳LD形成。其中，端子TE1係電源電位供給用之端子，後述之引腳LD1對應於端子TE1。又，端子TE4係基準電位供給用之端子，後述之引腳LD4對應於端子TE4。另，對電源電位供給用之端子TE1(引腳LD1)供給半導體裝置PKG之外部電源(輸入用電源)之高電位側之電位(電源電位)VIN，對基準電位供給用之端子TE4(引腳LD4)供給較供給至電源電位供給用之端子TE1之電位VIN更低之基準電位，例如接地電位(Ground電位)GND。 又，後述之引腳LD2對應於端子TE2，後述之引腳LD3對應於端子TE3。端子TE2(引腳LD2)與端子TE3(引腳LD3)於半導體裝置PKG之外部電性連接。即，功率MOSFET1之源極與功率MOSFET2之汲極為經由設置於半導體裝置PKG外部之導電路徑(例如設置於安裝半導體裝置PKG之後述之配線基板PB1之導電路徑)而電性連接之狀態。因此，成為於電源電位供給用之端子TE1與基準電位供給用之端子TE4之間串聯連接功率MOSFET1與功率MOSFET2之狀態。功率MOSFET1對應於高側用MOSFET，功率MOSFET2對應於低側用MOSFET。即，功率MOSFET1係高側開關(高電位側開關)用之場效電晶體，功率MOSFET2係低側開關(低電位側開關)用之場效電晶體。功率MOSFET1、2各者可視為開關用之功率電晶體。 惟電性連接端子TE2與端子TE3之導電路徑設置於半導體裝置PKG之外部(例如安裝半導體裝置PKG之後述之配線基板PB1)而非半導體裝置PKG之內部。因此，於將半導體裝置PKG安裝於配線基板等之狀態(構成換流器電路之狀態)，半導體裝置PKG之端子TE2(引腳LD2)與端子TE3(引腳LD3)電性連接。然而，於單獨取出半導體裝置PKG之情形時，於半導體裝置PKG內，半導體裝置PKG之端子TE2(引腳LD2)與端子TE3(引腳LD3)未通過導體相連，而為未電性連接之狀態。因此，功率MOSFET1(之源極)與功率MOSFET2(之汲極)之連接點TE6設置於半導體裝置PKG之外部(例如安裝半導體裝置PKG之後述之配線基板PB1)，該連接點TE6連接於馬達MOT之線圈(負載)CL。 供給至使用半導體裝置PKG之換流器電路INV之直流電力由換流器電路INV轉換為交流電力，供給至負載(此處為馬達MOT之線圈CL)。馬達MOT由自換流器電路INV供給之交流電力驅動。 又，後述之引腳LD5a、LD5b對應於端子TE5。控制電路CLC連接於端子TE5(引腳LD5a、LD5b)，該端子TE5(引腳LD5a、LD5b)與設置於半導體裝置PKG外部之上述控制電路CT連接。因此，半導體裝置PKG內之控制電路CLC通過端子TE5(引腳LD5a、LD5b)、及安裝有半導體裝置PKG之後述之配線基板PB1之配線等，而與設置於半導體裝置PKG外部之上述控制電路CT(參照圖1)連接。圖4中僅顯示1個端子TE5，但實際上，於半導體裝置PKG中，設置有複數個對應於端子TE5之引腳LD5a、LD5b。因此，連接半導體裝置PKG內之控制電路CLC、與半導體裝置PKG外部之上述控制電路CT之導電路徑存在複數條，且通過該等複數條導電路徑，於半導體裝置PKG外部之上述控制電路CT與半導體裝置PKG內之控制電路CLC之間進行信號之交換。半導體裝置PKG內之控制電路CLC由設置於半導體裝置PKG外部之上述控制電路CT控制。 流通於功率MOSFET1之電流由感測MOSFET3檢測(偵測)，且根據流通於感測MOSFET3之電流而控制功率MOSFET1。又，流通於功率MOSFET2之電流由感測MOSFET4檢測(偵測)，且根據流通於感測MOSFET4之電流而控制功率MOSFET2。感測MOSFET3係於半導體晶片CPH內以構成功率MOSFET1與電流鏡電路之方式形成，又，感測MOSFET4係於半導體晶片CPL內以構成功率MOSFET2與電流鏡電路之方式形成。 感測MOSFET3與功率MOSFET1其汲極及閘極為共通。即，感測MOSFET3與功率MOSFET1其汲極彼此電性連接而共通，該共通汲極連接於端子TE1，向感測MOSFET3之汲極及功率MOSFET1之汲極供給相同之電位。又，感測MOSFET3與功率MOSFET1其閘極彼此電性連接而共通，該共通閘極連接於控制電路CLC之高側用驅動電路，自該高側用驅動電路向感測MOSFET3之閘極及功率MOSFET1之閘極輸入相同之閘極信號(閘極電壓)。另一方面，感測MOSFET3之源極不與功率MOSFET1之源極共通，功率MOSFET1之源極連接於端子TE2，相對於此，感測MOSFET3之源極連接於控制電路CLC。 又，感測MOSFET4其汲極及閘極與功率MOSFET2共通。即，感測MOSFET4與功率MOSFET2其汲極彼此電性連接而共通，該共通汲極連接於端子TE3，並向感測MOSFET4及功率MOSFET2之汲極供給相同之電位。又，感測MOSFET4與功率MOSFET2係閘極彼此電性連接而共通，該共通閘極連接於控制電路CLC之低側用驅動電路，並自該低側用驅動電路向感測MOSFET4之閘極及功率MOSFET2之閘極輸入相同之閘極信號(閘極電壓)。另一方面，感測MOSFET4之源極不與功率MOSFET2之源極共通，功率MOSFET2之源極連接於端子TE4，相對於此，感測MOSFET4之源極連接於控制電路CLC。 ＜關於半導體裝置之構造＞ 圖5係本實施形態之半導體裝置PKG之俯視圖，圖6係半導體裝置PKG之仰視圖(後視圖)，圖7～圖9係半導體裝置PKG之俯視透視圖，圖10～圖13係半導體裝置PKG之剖視圖。於圖7顯示自下表面側觀察半導體裝置PKG時之透視密封部MR之俯視透視圖。又，圖8係顯示於圖7中進而透視(省略)導線BW及金屬板MP1、MP2時之半導體裝置PKG之下表面側之俯視透視圖。又，圖9係顯示於圖8中進而透視(省略)半導體晶片CPC、CPH、CPL時之半導體裝置PKG之下表面側之俯視透視圖。於圖6～圖9中，半導體裝置PKG之朝向相同。又，於圖7～圖9中，以虛線顯示密封部MR之外周位置。又，圖5～圖7之A1-A1線位置之半導體裝置PKG之剖面大致對應於圖10，圖5～圖7之A2-A2線位置之半導體裝置PKG之剖面大致對應於圖11，圖5～圖7之A3-A3線位置之半導體裝置PKG之剖面大致對應於圖12，圖5～圖7之A4-A4線位置之半導體裝置PKG之剖面大致對應於圖13。另，各俯視圖所示之符號X表示第1方向，符號Y表示正交於第1方向X(以下稱為X方向)之第2方向(以下稱為Y方向)。即，X方向與Y方向係彼此正交之方向。 於本實施形態中，將形成有控制電路CLC之半導體晶片CPC、形成有高側開關用之場效電晶體即功率MOSFET1之半導體晶片CPH、及形成有低側開關用之場效電晶體即功率MOSFET2之半導體晶片CPL集中(封裝)於1個半導體封裝而成為1個半導體裝置PKG。藉由如此，除了可實現電子裝置(例如上述控制板PB)之小型化、薄型化以外，因可減小配線寄生電感，故能實現高頻率化、高效率化。 圖5～圖13所示之本實施形態之半導體裝置(半導體封裝，電子裝置)PKG係樹脂密封型半導體封裝形態之半導體裝置，此處係SOP(Small Outline Package：小尺寸封裝)形態之半導體裝置。以下，一面參照圖5～圖13一面對半導體裝置PKG之構成進行說明。 圖5～圖13所示之本實施形態之半導體裝置PKG具有：晶片焊墊(晶片搭載部)DPC、DPH、DPL、搭載於該晶片焊墊DPC、DPH、DPL各者之主面上之半導體晶片CPC、CPH、CPL、金屬板MP1、MP2、複數條導線(接合線)BW、複數條引腳LD、及密封該等之密封部(密封體)MR。 作為樹脂密封部(樹脂密封體)之密封部MR包含例如熱硬化性樹脂材料等樹脂材料等，亦可包含填料。例如，可使用包含填料之環氧樹脂等形成密封部MR。除了環氧系樹脂以外，基於謀求低應力化等理由，亦可使用添加有例如酚系硬化劑、矽酮橡膠及填料等之聯苯系熱硬化性樹脂作為密封部MR之材料。 密封部MR具有：主面(上表面)MRa、與主面MRa為相反側之背面(下表面、底面)MRb、與主面MRa及背面MRb交叉之側面MRc1、MRc2、MRc3、MRc4。即，密封部MR之外觀設為由主面MRa、背面MRb及側面MRc1、MRc2、MRc3、MRc4包圍之薄板狀。密封部MR之側面MRc1、MRc2、MRc3、MRc4中，側面MRc1與側面MRc3位於互為相反側，側面MRc2與側面MRc4位於互為相反側，側面MRc1與側面MRc2、MRc4彼此交叉，側面MRc3與側面MRc2、MRc4彼此交叉。側面MRc1、MRc3與X方向大致平行，側面MRc2、MRc4與Y方向大致平行。又，主面MRa及背面MRb各者係與X方向及Y方向兩者平行之面。 又，密封部MR具有俯視時沿著X方向延伸之邊MRd1、沿著X方向延伸且位於與邊MRd1相反側之邊MRd3、沿著Y方向延伸之邊MRd2、沿著Y方向延伸且位於與邊MRd2相反側之邊MRd4。於俯視時，邊MRd2、MRd4各者與邊MRd1、MRd3交叉。於密封部MR中，邊MRd1係對應於側面MRc1之邊，邊MRd2係對應於側面MRc2之邊，邊MRd3係對應於側面MRc3之邊，邊MRd4係對應於側面MRc4之邊。即，密封部MR之各側面MRc1、MRc2、MRc3、MRc4於俯視時可視為密封部MR之各邊MRd1、MRd2、MRd3、MRd4。 密封部MR之平面形狀，即密封部MR之主面MRa及背面MRb之平面形狀為例如矩形狀(長方形狀)。另，構成密封部MR之平面形狀之矩形係具有平行於X方向之邊與平行於Y方向之邊之矩形，但密封部MR之X方向之尺寸大於密封部MR之Y方向之尺寸。即，於俯視時，對應於密封部MR之側面MRc1之邊MRd1及對應於密封部MR之側面MRc3之邊MRd3各者之長度，長於對應於密封部MR之側面MRc2之邊MRd2及對應於密封部MR之側面MRc4之邊MRd4各者的長度。 複數條引腳LD各者之一部分被密封於密封部MR內，另一部分自密封部MR之側面朝密封部MR之外部突出。於以下，將引腳LD中之位於密封部MR內之部分稱為內引腳部，將引腳LD中之位於密封部MR外之部分稱為外引腳部。亦可於引腳LD之外引腳部形成焊料鍍覆層等鍍覆層(未圖示)。藉此，可易於將半導體裝置PKG安裝(焊料安裝)於配線基板等。 另，本實施形態之半導體裝置PKG為各引腳LD之一部分(外引腳部)自密封部MR之側面突出之構造，於以下基於該構造進行說明，但並非限定於該構造者。亦可採用例如各引腳LD幾乎不自密封部MR之側面突出，且各引腳LD之一部分於密封部MR之背面MRb引腳露出之構成(SON(Small Outline Nonleaded Package：小尺寸無鉛封裝)型之構成)等。 複數條引腳LD由配置於密封部MR之側面MRc1側之複數條引腳LD、與配置於密封部MR之側面MRc3側之複數條引腳LD構成。於圖5～圖13之情形時，不於密封部MR之側面MRc2側與密封部MR之側面MRc4側配置引腳LD。 配置於密封部MR之側面MRc1側之複數條引腳LD就其他角度來看，可視為俯視時與密封部MR之邊MRd1交叉之引腳LD。又，配置於密封部MR之側面MRc3側之複數條引腳LD就其他角度來看，可視為俯視時與密封部MR之邊MRd3交叉之引腳LD。 配置於密封部MR之側面MRc1側之複數條引腳LD於俯視時各自朝Y方向延伸，且於X方向上以特定之間隔排列。又，配置於密封部MR之側面MRc3側之複數條引腳LD於俯視時各自朝Y方向延伸，且於X方向上以特定之間隔排列。配置於密封部MR之側面MRc1側之複數條引腳LD之各外引腳部自密封部MR之側面MRc1朝密封部MR外突出。又，配置於密封部MR之側面MRc3側之複數條引腳LD之各外引腳部自密封部MR之側面MRc3朝密封部MR外突出。各引腳LD之外引腳部以外引腳部之端部附近之下表面位於與密封部MR之背面MRb大致同一平面上之方式經彎曲加工。引腳LD之外引腳部作為半導體裝置PKG之外部連接用端子部(外部端子)發揮功能。另，半導體裝置PKG所具有之複數條引腳LD包含後述之引腳LD1、LD2、LD3、LD4、LD5a、LD5b、LD6、LD7、LD8。 晶片焊墊DPC為搭載半導體晶片CPC之晶片搭載部，晶片焊墊DPH為搭載半導體晶片CPH之晶片搭載部，晶片焊墊DPL為搭載半導體晶片CPL之晶片搭載部。晶片焊墊DPC、DPH、DPL各者之平面形狀為例如具有平行於X方向之邊與平行於Y方向之邊之矩形。於圖5～圖13之情形時，於半導體晶片CPC、CPH、CPL各者中，反映出Y方向之尺寸大於X方向之尺寸，且晶片焊墊DPC、DPH、DPL各者之Y方向之尺寸大於X方向之尺寸。因此，半導體晶片CPC、CPH、CPL與晶片焊墊DPC、DPH、DPL各自以Y方向為長邊方向，密封部MR以X方向為長邊方向。 晶片焊墊DPH、晶片焊墊DPC、及晶片焊墊DPL依序於X方向上排列而配置。因此，於晶片焊墊DPH與晶片焊墊DPL之間配置有晶片焊墊DPC，晶片焊墊DPH與晶片焊墊DPC於X方向上相鄰，且晶片焊墊DPC與晶片焊墊DPL於X方向上相鄰。惟晶片焊墊DPH與晶片焊墊DPC彼此不相接，而以特定之間隔離開，且於該等之間介隔有密封部MR之一部分。又，晶片焊墊DPC與晶片焊墊DPL彼此不相接，而以特定之間隔離開，且於該等之間介隔有密封部MR之另一部分。 晶片焊墊DPC、DPH、DPL與複數條引腳LD由導電體構成，且較佳包含銅(Cu)或銅合金等金屬材料。又，晶片焊墊DPC、DPH、DPL與複數條引腳LD較佳由相同之材料(相同之金屬材料)形成，藉此，易於製作將晶片焊墊DPC、DPH、DPL及複數條引腳LD連結之引腳框架，而易於製造使用引腳框架之半導體裝置PKG。 晶片焊墊DPC具有搭載半導體晶片CPC之側之主面DPCa、及與其相反側之背面DPCb。又，晶片焊墊DPH具有搭載半導體晶片CPH之側之主面DPHa、及與其相反側之背面DPHb。又，晶片焊墊DPL具有搭載半導體晶片CPL之側之主面DPLa、及與其相反側之背面DPLb。 各晶片焊墊DPC、DPH、DPL之至少一部分由密封部MR密封，但於本實施形態中，晶片焊墊DPC之背面DPCb、晶片焊墊DPH之背面DPHb、及晶片焊墊DPL之背面DPLb自密封部MR之主面MRa露出。藉此，可將半導體晶片CPC、CPH、CPL動作時產生之熱主要自半導體晶片CPC、CPH、CPL之背面通過晶片焊墊DPC、DPH、DPL放熱至半導體裝置PKG之外部。 另，半導體晶片CPC、CPH、CPL各者具有位於互為相反側之主面即正面(半導體晶片之正面)及背面(半導體晶片之背面)。即，半導體晶片CPC、CPH、CPL各者具有一主面即正面(半導體晶片之正面)、及與其相反側之主面即背面(半導體晶片之背面)。於半導體晶片CPC、CPH、CPL各者中，半導體晶片之正面對應於構成該半導體晶片之最上層保護膜(HGC、HGH、HGL)之正面，半導體晶片之背面對應於構成該半導體晶片之半導體基板之背面。因此，於半導體晶片CPC、CPH、CPL各者中，半導體晶片之正面、與構成該半導體晶片之最上層保護膜(HGC、HGH、HGL)之正面為同一平面。即，半導體晶片CPC具有最上層保護膜(最表層保護膜、保護膜、保護絕緣膜)HGC，於圖11及圖13中，正面CPCa為半導體晶片CPC之正面，但亦為最上層保護膜HGC之正面。又，半導體晶片CPH具有最上層保護膜(最表層保護膜、保護膜、保護絕緣膜)HGH，於圖10及圖13中，正面CPHa為半導體晶片CPH之正面，但亦為最上層保護膜HGH之正面。又，半導體晶片CPL具有最上層保護膜(最表層保護膜、保護膜、保護絕緣膜)HGL，於圖12及圖13中，正面CPLa為半導體晶片CPL之正面，但亦為最上層保護膜HGL之正面。因此，於半導體晶片CPC、CPH、CPL各者中，最上層保護膜(HGC、HGH、HGL)可視為具有(形成)該半導體晶片之正面之保護膜。於半導體晶片CPC、CPH、CPL各者中，最上層保護膜(HGC、HGH、HGL)包含絕緣膜，且形成於該半導體晶片之最上層(最表層)。於半導體晶片CPC、CPH、CPL各者中，最上層保護膜(HGC、HGH、HGL)具有露出接合墊之開口部，接合墊自最上層保護膜(HGC、HGH、HGL)之開口部露出。 又，於晶片焊墊DPC、DPH、DPL、引腳LD及引腳連結部LB2、LB4中，亦可於搭載半導體晶片CPC、CPH、CPL之區域、連接導線BW之區域、及連接金屬板MP1、MP2之區域，形成包含銀(Ag)等之鍍覆層(未圖示)。藉此，可更確實地將半導體晶片CPC、CPH、CPL、金屬板MP1、MP2及導線BW連接於晶片焊墊DPC、DPH、DPL、引腳LD及引腳連結部LB2、LB4。 於晶片焊墊DPH之主面DPHa上，將半導體晶片CPH以其背面朝向晶片焊墊DPH之狀態搭載。半導體晶片CPH經由導電性之接著層BD1而搭載於晶片焊墊DPH之主面DPHa上。於半導體晶片CPH之背面(背面整面)形成有背面電極(電極)BEH，該背面電極BEH經由導電性之接著層BD1而接合且電性連接於晶片焊墊DPH。 又，晶片焊墊DPL之主面DPLa上，將半導體晶片CPL以其背面朝向晶片焊墊DPL之狀態搭載。半導體晶片CPL經由導電性之接著層BD2而搭載於晶片焊墊DPL之主面DPLa上。於半導體晶片CPL之背面(背面整面)形成有背面電極(電極)BEL，且該背面電極BEL經由導電性之接著層BD2而接合且電性連接於晶片焊墊DPL。 又，晶片焊墊DPC之主面DPCa上，將半導體晶片CPC以其背面朝向晶片焊墊DPC之狀態搭載。半導體晶片CPC經由接著層BD3而搭載於晶片焊墊DPC之主面DPCa上，該接著層BD3可為導電性，亦可為絕緣性。 半導體晶片CPC、CPH、CPL各者之平面形狀為例如矩形狀，更特定而言，為具有平行於X方向之邊與平行於Y方向之邊之矩形。晶片焊墊DPH之平面尺寸(平面面積)大於半導體晶片CPH之平面尺寸，晶片焊墊DPL之平面尺寸大於半導體晶片CPL之平面尺寸，晶片焊墊DPC之平面尺寸大於半導體晶片CPC之平面尺寸。因此，於俯視時，半導體晶片CPH內包於晶片焊墊DPH之主面DPHa，半導體晶片CPL內包於晶片焊墊DPL之主面DPLa，半導體晶片CPC內包於晶片焊墊DPC之主面DPCa。半導體晶片CPC、CPH、CPL被密封於密封部MR內，而不自密封部MR露出。 半導體晶片CPH之背面電極BEH與形成於半導體晶片CPH內之上述功率MOSFET1之汲極電性連接，且亦與上述感測MOSFET3之汲極電性連接。即，半導體晶片CPH之背面電極BEH兼作上述功率MOSFET1之汲極電極、與上述感測MOSFET3之汲極電極。又，半導體晶片CPL之背面電極BEL與形成於半導體晶片CPL內之上述功率MOSFET2之汲極電性連接，且亦與上述感測MOSFET4之汲極電性連接。即，半導體晶片CPL之背面電極BEL兼作上述功率MOSFET2之汲極電極、與上述感測MOSFET4之汲極電極。接著層BD1、BD2包含導電性之接合材(接著材)，亦可使用例如銀漿料等漿料型導電性接著材或焊料等。 於半導體晶片CPH之正面(與形成有背面電極BEH之側為相反側之主面)，閘極用之接合墊PDHG、源極用之接合墊PDHS1、PDHS2、及溫度檢測用二極體之陽極用之接合墊PDHA及陰極用之接合墊PDHC自構成半導體晶片CPH之最上層保護膜HGH露出。又，於半導體晶片CPL之正面(與形成有背面電極BEL之側為相反側之主面)，閘極用之接合墊PDLG、源極用之接合墊PDLS1、PDLS2、及溫度檢測用二極體之陽極用之接合墊PDLA及陰極用之接合墊PDLC自構成半導體晶片CPL之最上層保護膜HGL露出。又，於半導體晶片CPC之正面(與背面側為相反側之主面)，複數個接合墊PDC自構成半導體晶片CPC之最上層保護膜HGC露出。另，於以下，將「接合墊」、「接合墊電極」、「焊墊電極」或「電極」簡稱為「焊墊」。 半導體晶片CPC之焊墊PDC通過半導體晶片CPC之內部配線，與形成於半導體晶片CPC內之上述控制電路CLC電性連接。 半導體晶片CPH之閘極用焊墊PDHG與形成於半導體晶片CPH內之上述功率MOSFET1之閘極電極及上述感測MOSFET3之閘極電極電性連接。即，半導體晶片CPH之閘極用焊墊PDHG兼作上述功率MOSFET1之閘極用焊墊、與上述感測MOSFET3之閘極用焊墊。又，半導體晶片CPH之源極用焊墊PDHS1與形成於半導體晶片CPH內之上述功率MOSFET1之源極電性連接，另一方面，半導體晶片CPH之源極用焊墊PDHS2與形成於半導體晶片CPH內之上述感測MOSFET3之源極電性連接。即，半導體晶片CPH之焊墊PDHS1對應於上述功率MOSFET1之源極用焊墊，半導體晶片CPH之焊墊PDHS2對應於上述感測MOSFET3之源極用焊墊。於半導體晶片CPH中，源極用之焊墊PDHS1之平面尺寸(面積)大於其他之焊墊PDHG、PDHS2、PDHA、PDHC各者之平面尺寸。 又，半導體晶片CPL之閘極用焊墊PDLG與形成於半導體晶片CPL內之上述功率MOSFET2之閘極電極及上述感測MOSFET4之閘極電極電性連接。即，半導體晶片CPL之閘極用焊墊PDLG兼作上述功率MOSFET2之閘極用焊墊、與上述感測MOSFET4之閘極用焊墊。又，半導體晶片CPL之源極用焊墊PDLS1與形成於半導體晶片CPL內之上述功率MOSFET2之源極電性連接，另一方面，半導體晶片CPL之源極用焊墊PDLS2與形成於半導體晶片CPL內之上述感測MOSFET4之源極電性連接。即，半導體晶片CPL之焊墊PDLS1對應於上述功率MOSFET2之源極用焊墊，半導體晶片CPL之焊墊PDLS2對應於上述感測MOSFET4之源極用焊墊。於半導體晶片CPL中，源極用之焊墊PDLS1之平面尺寸(面積)大於其他焊墊PDLG、PDLS2、PDLA、PDLC各者之平面尺寸。 另，於構成半導體晶片CPH之半導體基板，形成有構成功率MOSFET1之複數個單位電晶體單元，功率MOSFET1藉由並聯連接該等複數個單位電晶體單元而形成。又，於構成半導體晶片CPL之半導體基板，形成有構成功率MOSFET2之複數個單位電晶體單元，功率MOSFET2藉由並聯連接該等複數個單位電晶體單元而形成。各單位電晶體單元包含例如溝槽式閘極型MISFET。後述之圖29及圖30之電晶體形成區域RG1、RG2對應於形成有功率MOSFET用之複數個單位電晶體單元之區域。 即，形成於構成半導體晶片CPH之半導體基板之正面之功率MOSFET1用之複數個單位電晶體單元之源極區域，與形成於半導體基板上之層面絕緣膜上之構成半導體晶片CPH之共通之源極電極電性連接，且該源極電極自構成半導體晶片CPH之最上層保護膜HGH之開口部露出，藉此形成源極用之焊墊PDHS1。半導體晶片CPH之最上層保護膜HGH以覆蓋源極電極之方式形成於構成半導體晶片CPH之半導體基板上之層間絕緣膜上，但具有露出源極電極之至少一部分之開口部。又，形成於構成半導體晶片CPL之半導體基板之正面之功率MOSFET2用之複數個單位電晶體單元之源極區域，與形成於半導體基板上之層面絕緣膜上之構成半導體晶片CPL之共通之源極電極電性連接，且該源極電極自構成半導體晶片CPL之最上層保護膜HGL之開口部露出，藉此形成源極用之焊墊PDLS1。半導體晶片CPL之最上層保護膜HGL以覆蓋源極電極之方式形成於構成半導體晶片CPL之半導體基板上之層間絕緣膜上，但具有露出源極電極之至少一部分之開口部。又，構成半導體晶片CPH之半導體基板具有作為功率MOSFET1用之複數個單位電晶體單元之共通之汲極區域的功能，且於該半導體基板之背面整面形成有背面電極BEH。又，構成半導體晶片CPL之半導體基板具有作為構成功率MOSFET2用之複數個單位電晶體單元之共通汲極區域的功能，且於該半導體基板之背面整面形成有背面電極BEL。於半導體晶片CPH、CPL各者中，功率MOSFET(1、2)之源極、汲極間之電流於構成該半導體晶片之半導體基板之厚度方向流通。 於半導體晶片CPH不僅形成有上述功率MOSFET1及上述感測MOSFET3，亦形成有溫度檢測用之二極體(對應於後述之圖29及圖30之二極體DA1)，焊墊PDHA電性連接於該溫度檢測用之二極體(DA1)之陽極，焊墊PDHC電性連接於該溫度檢測用之二極體(DA1)之陰極。又，於半導體晶片CPL不僅形成有上述功率MOSFET2及上述感測MOSFET4，亦形成有溫度檢測用之二極體(對應於後述之圖29及圖30之二極體DA2)，焊墊PDLA電性連接於該溫度檢測用之二極體(DA2)之陽極，焊墊PDLC電性連接於該溫度檢測用之二極體(DA2)之陰極。另，溫度檢測用之二極體(DA1、DA2)於上述圖4之電路圖中省略圖示。 於半導體晶片CPH之正面，源極用之焊墊PDHS1以外之焊墊(此處為焊墊PDHG、PDHS2、PDHA、PDHC)沿著與半導體晶片CPC對向之側之邊H1配置(排列)。且，半導體晶片CPH之源極用焊墊PDHS1以外之焊墊PDHG、PDHS2、PDHA、PDHC各自經由導線BW與半導體晶片CPC之焊墊PDC電性連接。即，於焊墊PDHG、PDHS2、PDHA、PDHC各者連接有導線BW之一端，該導線BW之另一端連接於半導體晶片CPC之焊墊PDC。半導體晶片CPH之各焊墊PDHG、PDHS2、PDHA、PDHC經由導線BW而電性連接於半導體晶片CPC之焊墊PDC，進而通過半導體晶片CPC之內部配線而電性連接於半導體晶片CPC內之上述控制電路CLC。 又，於半導體晶片CPL之正面，源極用之焊墊PDLS1以外之焊墊(此處係焊墊PDLG、PDLS2、PDLA、PDLC)沿著與半導體晶片CPC對向之側之邊L1配置(排列)。且，半導體晶片CPL之源極用焊墊PDLS1以外之焊墊PDLG、PDLS2、PDLA、PDLC各自經由導線BW與半導體晶片CPC之焊墊PDC電性連接。即，於焊墊PDLG、PDLS2、PDLA、PDLC各者連接有導線BW之一端，該導線BW之另一端連接於半導體晶片CPC之焊墊PDC。半導體晶片CPL之各焊墊PDLG、PDLS2、PDLA、PDLC經由導線BW而電性連接於半導體晶片CPC之焊墊PDC，進而通過半導體晶片CPC之內部配線而電性連接於半導體晶片CPC內之上述控制電路CLC。 導線(接合線)BW係導電性之連接構件，更特定而言係導電性之導線。由於導線BW包含金屬，故可視為金屬線(金屬細線)。作為導線BW，可較佳使用金(Au)導線、銅(Cu)導線、或鋁(Al)導線等。導線BW被密封於密封部MR內，不自密封部MR露出。於各引腳LD中，導線BW之連接部位為位於密封部MR內之內引腳部。 半導體晶片CPH之源極用焊墊PDHS1(即，上述功率MOSFET1之源極)通過金屬板MP1與引腳連結部(引腳配線部)LB2電性連接。即，金屬板MP1經由導電性之接著層(接合材)BD4而接合於半導體晶片CPH之源極用焊墊PDHS1，且，經由導電性之接著層(接合材)BD5而接合於引腳連結部LB2。 半導體晶片CPL之源極用焊墊PDLS1(即，上述功率MOSFET2之源極)通過金屬板MP2與引腳連結部(引腳配線部)LB4電性連接。即，金屬板MP2經由導電性之接著層(接合材)BD6而接合於半導體晶片CPL之源極用焊墊PDLS1，且，經由導電性之接著層(接合材)BD7而接合於引腳連結部LB4。 電性連接半導體晶片CPH之源極用焊墊PDHS1與引腳LD2不使用導線而使用金屬板MP1，藉此可降低功率MOSFET1之接通電阻。又，電性連接半導體晶片CPL之源極用焊墊PDLS1與引腳LD4不使用導線而使用金屬板MP2，藉此可降低功率MOSFET2之接通電阻。藉此，可降低封裝電阻，可降低導通損失。 接著層BD4、BD5、BD6、BD7包含導電性之接合材(接著材)，可使用例如銀漿料等漿料型導電性接著材或焊料等。又，對於將金屬板MP1、MP2接合(連接)於半導體晶片CPH、CPL之源極用焊墊PDHS1、PDLS1及引腳連結部LB2、LB4，有時不使用導電性之接著層(接合材)BD4、BD5、BD6、BD7，而藉由壓接等直接接合(連接)。 金屬板MP1、MP2為包含導電體之導體板，但較佳由如銅(Cu)、銅(Cu)合金、鋁(Al)或鋁(Al)合金之類的導電性及熱傳遞性高之金屬(金屬材料)形成。各金屬板MP1、MP2之X方向及Y方向之尺寸(寬度)各自大於導線BW之直徑。 半導體晶片CPH、CPL中產生之熱除了自半導體晶片CPH、CPL之背面通過晶片焊墊DPH、DPL發散以外，並自半導體晶片CPH、CPL之正面通過金屬板MP1、MP2發散，藉此，可使半導體晶片CPH、CPL中產生之熱之發散性提高。 半導體晶片CPC之複數個焊墊PDC中未連接於半導體晶片CPH之焊墊且亦未連接於半導體晶片CPL之焊墊之焊墊PDC，各自通過導線BW而與半導體裝置PKG所具有之引腳LD中之引腳LD5a、LD5b電性連接。即，於未連接於半導體晶片CPH之焊墊且亦未連接於半導體晶片CPL之焊墊之焊墊之半導體晶片CPC之焊墊PDC各者連接導線BW之一端，該導線BW之另一端連接於引腳LD5a之內引腳部或引腳LD5b之內引腳部。各引腳LD5a、LD5b可作為半導體裝置PKG內之半導體晶片CPC與半導體裝置PKG外部之上述控制電路CT之間之信號傳送路徑發揮功能。 引腳LD5a、LD5b中，引腳LD5a配置於密封部MR之側面MRc1側，引腳LD5b配置於密封部MR之側面MRc3側。於半導體晶片CPC之正面，沿著密封部MR之側面MRc1側之邊配置(排列)之複數個焊墊PDC與配置於密封部MR之側面MRc1側之複數條引腳LD5a，各自經由導線BW電性連接。又，於半導體晶片CPC之正面，沿著密封部MR之側面MRc3側之邊配置(排列)之複數個焊墊PDC與配置於密封部MR之側面MRc3側之複數條引腳LD5b分別經由導線BW電性連接。各引腳LD5a、LD5b不經由導體與晶片焊墊DPC、DPH、DPL、引腳LD1、LD2、LD3、LD4及引腳連結部LB1、LB2、LB3、LB4之任一者相連，而為孤立之引腳。即，未連接於半導體晶片CPH之焊墊且亦未連接於半導體晶片CPL之焊墊之半導體晶片CPC之焊墊PDC係經由導線BW而連接於孤立之各條引腳LD5a、LD5b。 引腳連結部LB2與晶片焊墊DPH於Y方向上相鄰，且以沿著側面MRc3之方式於密封部MR內朝X方向延伸。又，引腳連結部LB4與晶片焊墊DPL於Y方向上相鄰，且以沿著側面MRc1之方式於密封部MR內朝X方向延伸。惟引腳連結部LB2與晶片焊墊DPH彼此不相接，而以特定之間隔離開，且於該等之間介隔有密封部MR之一部分。又，引腳連結部LB4與晶片焊墊DPL彼此不相接，而以特定之間隔離開，且於該等之間介隔有密封部MR之另一部分。引腳連結部LB2、LB4被密封於密封部MR內，而不自密封部MR露出。 於引腳連結部LB2一體連接(連結)半導體裝置PKG所具有之複數條引腳LD中之複數條引腳LD2。即，引腳連結部LB2與複數條引腳LD2一體形成。複數條引腳LD2彼此於X方向上相鄰，但為複數條引腳LD2之內引腳部彼此藉由於密封部MR內朝X方向延伸之引腳連結部LB2而連結之狀態。因此，引腳連結部LB2可視為連結複數條引腳LD2之內引腳部彼此之連結部。複數條引腳LD2與引腳連結部LB2通過金屬板MP1等而電性連接於形成於半導體晶片CPH內之上述功率MOSFET1之源極。因此，複數條引腳LD2為高側用之上述功率MOSFET1之源極用之引腳，且對應於上述端子TE2。 半導體晶片CPH之源極用焊墊PDHS1為用以輸出流通於功率MOSFET1之電流之焊墊。流通於功率MOSFET1之電流自焊墊PDHS1被輸出至半導體晶片CPH之外部，經過金屬板MP1及引腳連結部LB2自引腳LD2(端子TE2)被輸出至半導體裝置PKG之外部(輸出至上述圖1及圖4之線圈CL)。 又，於引腳連結部LB4一體連接(連結)半導體裝置PKG所具有之複數條引腳LD中之複數條引腳LD4。即，引腳連結部LB4與複數條引腳LD4一體形成。複數條引腳LD4彼此於X方向上相鄰，但為複數條引腳LD4之內引腳部彼此藉由於密封部MR內朝X方向延伸之引腳連結部LB4而連結之狀態。因此，引腳連結部LB4可視為連結複數條引腳LD4之內引腳部彼此之連結部。複數條引腳LD4與引腳連結部LB4通過金屬板MP2等而電性連接於形成於半導體晶片CPL內之上述功率MOSFET2之源極。因此，複數條引腳LD4為低側用之上述功率MOSFET2之源極用之引腳，且對應於上述端子TE4。即，該等複數條引腳LD4成為上述端子TE4，且將上述基準電位(接地電位GND)供給至引腳LD4(端子TE4)。因此，引腳連結部LB4及與其一體連接之複數條引腳LD4可視為接地電位供給用之接地端子部。 藉由將複數條引腳LD2集體連接於引腳連結部LB2，較將複數條引腳LD2分割之情形相比更能使體積增加，因此可降低配線電阻，可降低功率MOSFET1之導通損失。又，藉由將複數條引腳LD4集體連接於引腳連結部LB4，較將複數條引腳LD4分割之情形相比更能使體積增加，因此可降低配線電阻，可降低功率MOSFET2之導通損失。 一體形成之引腳連結部LB2及複數條引腳LD2不經由導體與晶片焊墊DPC、DPH、DPL之任一者相連，又，一體形成之引腳連結部LB4及複數條引腳LD4不經由導體與晶片焊墊DPC、DPH、DPL之任一者相連。 引腳連結部LB2及連結於其之複數條引腳LD2以與晶片焊墊DPH於Y方向上相鄰之方式配置於密封部MR之側面MRc3側，引腳連結部LB4及連結於其之複數條引腳LD4以與晶片焊墊DPL於Y方向上相鄰之方式配置於密封部MR之側面MRc1側。 半導體裝置PKG所具有之複數條引腳LD中，複數條引腳LD1與晶片焊墊DPH一體形成。因此，複數條引腳LD1與晶片焊墊DPH電性連接，經由晶片焊墊DPH及導電性之接著層BD1而電性連接於半導體晶片CPH之背面電極BEH。因此，複數條引腳LD1為高側用之上述功率MOSFET1之汲極用之引腳，且對應於上述端子TE1。即，該等複數條引腳LD1成為上述端子TE1，且將半導體裝置PKG之外部電源(輸入用電源)之高電位側之電位(電源電位)VIN供給至引腳LD1(端子TE1)。因此，複數條引腳LD1可視為電源電位供給用之端子部。 又，半導體裝置PKG所具有之複數條引腳LD中，複數條引腳LD3與晶片焊墊DPL一體形成。因此，複數條引腳LD3與晶片焊墊DPL電性連接，經由晶片焊墊DPL及導電性之接著層BD2而電性連接於半導體晶片CPL之背面電極BEL。因此，複數條引腳LD3為低側用之上述功率MOSFET2之汲極用之引腳，且對應於上述端子TE3。因此，若單獨觀察半導體裝置PKG，則半導體裝置PKG之複數條引腳LD2與複數條引腳LD4未電性連接，但若為了於半導體裝置PKG中形成上述換流器電路INV而將半導體裝置PKG安裝於配線基板等，則通過該配線基板之配線等，將半導體裝置PKG之複數條引腳LD2與複數條引腳LD4電性連接。 複數條引腳LD1以與晶片焊墊DPH於Y方向相鄰之方式配置於密封部MR之側面MRc1側，複數條引腳LD3以與晶片焊墊DPL於Y方向相鄰之方式配置於密封部MR之側面MRc3側。 複數條引腳LD1彼此於X方向上相鄰，但為複數條引腳LD1之內引腳部彼此藉由於密封部MR內朝X方向延伸之引腳連結部LB1而連結之狀態。因此，引腳連結部LB1可視為連結複數條引腳LD1之內引腳部彼此之連結部。引腳連結部LB1經由於Y方向延伸之連結部LB1a而與晶片焊墊DPH一體連接。複數條引腳LD1、引腳連結部LB1、連結部LB1a及晶片焊墊DPH係一體形成。 又，複數條引腳LD3彼此於X方向相鄰，但為複數條引腳LD3之內引腳部彼此藉由於密封部MR內朝X方向延伸之引腳連結部LB3而連結之狀態。因此，引腳連結部LB3可視為連結複數條引腳LD3之內引腳部彼此之連結部。引腳連結部LB3經由朝Y方向延伸之連結部LB3a而與晶片焊墊DPL一體連接。複數條引腳LD3、引腳連結部LB3、連結部LB3a及晶片焊墊DPL係一體形成。 於本實施形態之半導體裝置PKG中，於密封部MR之側面MRc1側配置有對應於上述端子TE1之複數條引腳LD1、及對應於上述端子TE4之複數條引腳LD4，於密封部MR之側面MRc3側配置有對應於上述端子TE2之複數條引腳LD2、及對應於上述端子TE3之複數條引腳LD3。對應於上述端子TE1之複數條引腳LD1、與對應於上述端子TE2之複數條引腳LD2係隔著晶片焊墊DPH(半導體晶片CPH)而位於相反側(Y方向上之相反側)。又，對應於上述端子TE4之複數條引腳LD4、與對應於上述端子TE3之複數條引腳LD3係隔著晶片焊墊DPL(半導體晶片CPL)而位於相反側(Y方向上之相反側)。 因此，包含複數條引腳LD1之引腳群與包含複數條引腳LD4之引腳群配置於密封部MR之相同側面MRc1側，但若自X方向觀察，則包含複數條引腳LD1之引腳群較包含複數條引腳LD4之引腳群位於更靠近密封部MR之側面MRc2之位置。又，包含複數條引腳LD2之引腳群與包含複數條引腳LD3之引腳群配置於密封部MR之相同側面MRc3側，但若自X方向觀察，則包含複數條引腳LD2之引腳群較包含複數條引腳LD3之引腳群位於更靠近密封部MR之側面MRc2之位置。 又，於密封部MR之側面MRc1側，於包含複數條引腳LD1之引腳群與包含複數條引腳LD4之引腳群之間，配置有包含複數條引腳LD5a之引腳群。又，於密封部MR之側面MRc3側，於包含複數條引腳LD2之引腳群與包含複數條引腳LD3之引腳群之間，配置有包含複數條引腳LD5b之引腳群。 因此，於密封部MR之側面MRc1側，於自晶片焊墊DPH朝晶片焊墊DPL之方向，依序排列有包含複數條引腳LD1之引腳群、包含複數條引腳LD5a之引腳群、及包含複數條引腳LD4之引腳群。又，於密封部MR之側面MRc3側中，於自晶片焊墊DPH朝晶片焊墊DPL之方向，依序排列有包含複數條引腳LD2之引腳群、包含複數條引腳LD5b之引腳群、及包含複數條引腳LD3之引腳群。 又，於晶片焊墊DPC一體連結有複數條引腳LD8。該等引腳LD8係於製造半導體裝置PKG時，用於將晶片焊墊DPC支持於後述之引腳框架LF之框架者。因此，引腳LD8不與半導體晶片CPC、CPH、CPL之任一焊墊電性連接，且亦不與半導體晶片CPH、CPL之背面電極BEH、BEL電性連接。因此，引腳LD8不作為半導體裝置PKG內之半導體晶片CPC與半導體裝置PKG外部之上述控制電路CT之間之信號傳送路徑發揮功能，且亦不作為半導體裝置PKG內之半導體晶片CPH、CPL與半導體裝置PKG外部之上述馬達MOT(線圈CL)之間之電流路徑發揮功能。連結於晶片焊墊DPC之引腳LD8分別配置於密封部MR之側面MRc1側與側面MRc3側。 又，於晶片焊墊DPH一體連結有配置於密封部MR之側面MRc3側之引腳LD6。該引腳LD6係於製造半導體裝置PKG時，用於將晶片焊墊DPH支持於後述之引腳框架LF之框架者。又，於晶片焊墊DPL一體連結有配置於密封部MR之側面MRc1側之引腳LD7。該引腳LD7係於製造半導體裝置PKG時，用於將晶片焊墊DPL支持於後述之引腳框架LF之框架者。引腳LD6之數量少於引腳LD1之數量，可為1條，又，引腳LD7之數量少於引腳LD3之數量，可為1條。 又，與晶片焊墊DPH一體連結之懸架引腳TL配置於密封部MR之側面MRc2側，與晶片焊墊DPL一體連結之懸架引腳TL配置於密封部MR之側面MRc4側。該懸架引腳TL係於製造半導體裝置PKG時，用於將晶片焊墊DPH、DPL支持於後述之引腳框架LF之框架者。懸架引腳TL不自密封部MR之側面突出。 由於配置於密封部MR之側面MRc1側之複數條引腳LD1、與配置於密封部MR之側面MRc3側之引腳LD6係與晶片焊墊DPH一體形成，故與搭載於晶片焊墊DPH上之半導體晶片CPH之背面電極BEH電性連接。又，由於配置於密封部MR之側面MRc3側之複數條引腳LD3、與配置於密封部MR之側面MRc1側之引腳LD7係與晶片焊墊DPL一體形成，故與搭載於晶片焊墊DPL上之半導體晶片CPL之背面電極BEL電性連接。然而，引腳LD6、LD7不作為半導體裝置PKG內之半導體晶片CPH、CPL與半導體裝置PKG外部之上述馬達MOT(線圈CL)之間之電流路徑發揮功能，且亦不作為半導體裝置PKG內之半導體晶片CPC與半導體裝置PKG外部之上述控制電路CT之間之信號傳送路徑發揮功能。 即，於半導體裝置PKG中，於功率MOSFET1為接通狀態時，電流自功率MOSFET1之汲極用引腳LD1通過半導體晶片CPH(功率MOSFET1)而向功率MOSFET1之源極用引腳LD2流通。又，於半導體裝置PKG中，於功率MOSFET2為接通狀態時，電流自功率MOSFET2之汲極用引腳LD3通過半導體晶片CPL(功率MOSFET2)而向功率MOSFET2之源極用引腳LD4流通。於將功率MOSFET1設為接通狀態時，作為經由功率MOSFET1流通之電流路徑發揮功能的是引腳LD1而非引腳LD6，又，於將功率MOSFET2設為接通狀態時，作為經由功率MOSFET2流通之電流路徑發揮功能的是引腳LD3而非引腳LD7。 又，於半導體裝置PKG中，電性連接於功率MOSFET1之源極之源極用引腳(此處為引腳LD2)僅配置於密封部MR之側面MRc3側，而未配置於密封部MR之側面MRc1、MRc2、MRc4側。又，於半導體裝置PKG中，電性連接於功率MOSFET2之源極之源極用引腳(此處為引腳LD4)僅配置於密封部MR之側面MRc1側，而未配置於密封部MR之側面MRc2、MRc3、MRc4側。 ＜關於半導體裝置之製造步驟＞ 接著，對上述圖5～圖13所示之半導體裝置PKG之製造步驟(組裝步驟)進行說明。圖14～圖22係本實施形態之半導體裝置PKG之製造步驟中之俯視圖或剖視圖。圖14～圖22中，圖14～圖19係俯視圖，圖20～圖22係剖視圖，但圖20～圖22係與圖19相同之步驟階段之剖視圖。 於製造半導體裝置PKG時，首先，準備引腳框架LF，再者，準備半導體晶片CPC、CPH、CPL。引腳框架LF與半導體晶片CPC、CPH、CPL可先準備任一者，或者，亦可同時準備。 如圖14所示，引腳框架LF一體具有：框架(未圖示)、晶片焊墊DPC、DPH、DPL、複數條引腳LD、引腳連結部LB1、LB2、LB3、LB4、懸架引腳TL。各引腳LD係一端部連結於框架。各晶片焊墊DPC、DPH、DPL經由一部分引腳LD與框架連結。具體而言，晶片焊墊DPC藉由引腳LD8連結於框架，晶片焊墊DPH藉由引腳LD1、LD6及懸架引腳TL連結於框架，晶片焊墊DPL藉由引腳LD3、LD7及懸架引腳TL連結於框架。引腳框架LF包含例如以銅(Cu)為主成分之金屬材料，具體而言，包含銅(Cu)或銅(Cu)合金。圖14中顯示引腳框架LF中自其處製造1個半導體裝置PKG之區域。 另，進行封膠步驟直至形成密封部MR為止，引腳框架LF係以晶片焊墊DPC、DPH、DPL之主面DPCa、DPHa、DPLa朝向上方之狀態進行以下之製造步驟(組裝步驟)。 接著，如圖15所示，進行半導體晶片CPH、CPL之晶片接合步驟，將半導體晶片CPH經由導電性之接合材(晶片接合材)搭載於引腳框架LF之晶片焊墊DPH之主面DPHa上，將半導體晶片CPL經由導電性之接合材(晶片接合材)搭載於晶片焊墊DPL之主面DPLa上。作為導電性之接合材可使用例如銀漿料等。此時，以半導體晶片CPH、CPL之背面側朝向晶片焊墊DPH、DPL之主面DPHa、DPLa側之方式搭載(配置)半導體晶片CPH、CPL。隨後，藉由進行將導電性接合材硬化之處理(熱處理)，形成包含硬化之導電性之接合材之接著層BD1、BD2。藉此，藉由接著層BD1、BD2將半導體晶片CPH、CPL接合並固定於晶片焊墊DPH、DPL。另，圖15中未圖示接著層BD1、BD2，但接著層BD1、BD2顯示於上述圖10、圖12及圖13。隨後，亦可利用電漿進行淨化處理(電漿清洗處理)。藉由該電漿清洗處理，將半導體晶片CPH、CPL之焊墊PDHS1、PDLS1淨化，而易於後續接合金屬板MP1、MP2。 接著，如圖16所示，經由金屬板MP1連接搭載於晶片焊墊DPH上之半導體晶片CPH之源極用焊墊PDHS1、與引腳框架LF之引腳連結部LB2，又，經由金屬板MP2連接搭載於晶片焊墊DPL上之半導體晶片CPL之源極用焊墊PDLS1、與引腳框架LF之引腳連結部LB4。即，將半導體晶片CPH之焊墊PDHS1、與一體連結於引腳連結部LB2之複數條引腳LD2經由金屬板MP1電性連接，又，將半導體晶片CPL之焊墊PDLS1、與一體連結於引腳連結部LB4之複數條引腳LD4經由金屬板MP2電性連接。 金屬板MP1經由導電性之接著層(接合材)BD4接合於半導體晶片CPH之源極用焊墊PDHS1，又，經由導電性之接著層(接合材)BD5接合於引腳連結部LB2。又，金屬板MP2經由導電性之接著層(接合材)BD6接合於半導體晶片CPL之源極用焊墊PDLS1，又，經由導電性之接著層(接合材)BD7接合於引腳連結部LB4。作為接著層BD4、BD5、BD6、BD7可使用例如銀漿料或焊料等。另，圖16中未圖示接著層BD4、BD5、BD6、BD7，但接著層BD4、BD5、BD6、BD7顯示於上述圖10及圖12。 另，此處對於將半導體晶片CPC搭載於晶片焊墊DPC上之前，進行金屬板MP1、MP2之接合步驟之情形進行說明。搭載於晶片焊墊DPC之前進行金屬板MP1、MP2之接合步驟，是為了防止半導體晶片CPC暴露於伴隨金屬板MP1、MP2之接合步驟之熱處理(金屬板MP1、MP2用之接合材(BD4、BD5、BD6、BD7)之硬化步驟等)之故。藉此，可使半導體晶片CPC之可靠性進一步提高。 接著，如圖17所示，進行半導體晶片CPC之晶片接合步驟，將半導體晶片CPC經由接合材(晶片接合材)而搭載於引腳框架LF之晶片焊墊DPC之主面DPCa上。作為接合材可使用例如銀漿料或絕緣性漿料等。此時，以半導體晶片CPC之背面側朝向晶片焊墊DPC之主面DPCa側之方式搭載(配置)半導體晶片CPC。隨後，藉由進行將接合材硬化之處理(熱處理)，形成包含硬化之接合材之接著層BD3。藉此，藉由接著層BD3將半導體晶片CPC接合並固定於晶片焊墊DPC。另，圖17中未圖示接著層BD3，但接著層BD3顯示於上述圖11及圖13。隨後，亦可進行電漿清洗處理。藉由該電漿清洗處理，將半導體晶片CPC、CPH、CPL淨化，而易於接合導線BW。 接著，如圖18所示，進行打線接合連接步驟。即，將半導體晶片CPH之複數個焊墊(PDHG、PDHS2、PDHA、PDHC)與半導體晶片CPC之複數個焊墊(PDC)之間、半導體晶片CPL之複數個焊墊(PDLG、PDLS2、PDLA、PDLC)與半導體晶片CPC之複數個焊墊(PDC)之間、及半導體晶片CPC之複數個焊墊(PDC)與引腳框架LF之複數條引腳(LD5a、LD5b)之間各自經由導線BW電性連接。 亦可將包含不同材料之複數種導線用作導線BW，例如，將半導體晶片CPC之複數個焊墊(PDC)與引腳框架LF之複數條引腳(LD5a、LD5b)之間各自經由包含銅(Cu)之導線BW電性連接。且，將半導體晶片CPH之複數個焊墊(PDHG、PDHS2、PDHA、PDHC)與半導體晶片CPC之複數個焊墊(PDC)之間、及半導體晶片CPL之複數個焊墊(PDLG、PDLS2、PDLA、PDLC)與半導體晶片CPC之複數個焊墊(PDC)之間各自經由包含金(Au)之導線BW電性連接。 接著，利用封膠步驟(樹脂成形步驟)進行樹脂密封，如圖19～圖22所示，藉由密封部MR密封半導體晶片CPC、CPH、CPL及連接於其等之複數條導線BW與金屬板MP1、MP2。藉由該封膠步驟，形成密封半導體晶片CPC、CPH、CPL、晶片焊墊DPC、DPH、DPL、複數條導線BW、金屬板MP1、MP2、引腳連結部LB1、LB2、LB3、LB4及複數條引腳LD之內引腳部之密封部MR。亦如圖20～圖22所示，於封膠步驟中，以晶片焊墊DPC、DPH、DPL之各背面DPCb、DPHb、DPLb自密封部MR之主面MRa露出之方式形成密封部MR。 另，截至該封膠步驟為止之各步驟係以晶片焊墊DPC、DPH、DPL之主面DPCa、DPHa、DPLa朝向上方之狀態進行。因此，於進行封膠步驟而形成密封部MR之階段中，密封部MR之背面MRb朝向上方。然而，於將製造出之半導體裝置PKG安裝於配線基板等時，以密封部MR之背面MRb與配線基板對向之方式將半導體裝置PKG安裝於配線基板。 接著，根據需要於自密封部MR露出之引腳LD之外引腳部形成鍍覆層(未圖示)。隨後，使引腳框架LF之上下(正反)與密封部MR一起翻轉，且於密封部MR之外部，於特定之位置切斷引腳LD而自引腳框架LF之框架分離。 接著，將自密封部MR突出之引腳LD之外引腳部予以彎曲加工(引腳加工、引腳成形)。 如此，製造如上述圖5～圖12所示之半導體裝置PKG。 ＜半導體裝置PKG之安裝例＞ 圖23～圖28係顯示半導體裝置PKG之安裝例之俯視圖(圖23及圖24)或剖視圖(圖25～圖28)。 本實施形態之半導體裝置PKG係構成換流器電路INV之半導體裝置，可藉由1個半導體裝置PKG形成1個換流器電路INV。於控制12相BLDC馬達即上述馬達MOT之情形時，由於需要12個換流器電路INV，故半導體裝置PKG需要12個，且將12個半導體裝置PKG安裝於共通之配線基板(安裝基板、PCB(Printed circuit board：印刷電路板)基板)PB1上。 藉由配線基板PB1、與安裝(搭載)於配線基板PB1上之12個半導體裝置PKG而構成上述控制板PB。即，上述控制板PB對應於將12個半導體裝置PKG安裝(搭載)於配線基板PB1上者。因此，配線基板PB1之平面形狀為控制板PB之平面形狀。由於控制板PB之平面形狀為圓形狀，故配線基板PB1之平面形狀亦為圓形狀。 圖23之情形與圖24之情形之任一者亦為，於圓形狀之配線基板PB1之主面(上表面)PB1a上，將複數個(此處為12個)半導體裝置PKG沿著配線基板PB1之周緣部(邊緣、外周)環狀排列而配置。又，圖23之情形與圖24之情形之任一者亦為，於俯視時，配置於圓形之配線基板PB1上之複數個(12個)半導體裝置PKG各者、與圓形之配線基板PB1之中心之間之距離互為相同。 另，於圖23之情形，配置於配線基板PB1上之12個半導體裝置PKG之各者中，短邊方向(Y方向，即平行於側面MRc2、MRc4之方向)與構成配線基板PB1之平面形狀之圓之半徑方向大致平行。另一方面，於圖24之情形時，配置於配線基板PB1上之12個半導體裝置PKG之各者中，長邊方向(X方向，即平行於側面MRc1、MRc3之方向)與構成配線基板PB1之平面形狀之圓之半徑方向大致平行。 又，於配線基板PB1設置有用以供上述轉向軸SF(參照上述圖2)貫通之孔(貫通孔、開口部)HL。該孔HL於俯視時形成於圓形狀之配線基板PB1之大致中心，且貫通配線基板PB1。孔HL之平面形狀與上述轉向軸SF之剖面形狀(相對於轉向軸SF之軸向大致垂直之剖面形狀)大致一致，為例如大致圓形狀。藉由於配線基板PB1設置孔HL，可使安裝有12個半導體裝置PKG之配線基板PB1(即上述控制板PB)以上述轉向軸SF貫通於配線基板PB1之孔HL之方式配置(參照上述圖2)。 另，此處針對於平面形狀為圓形狀且設置有孔HL之配線基板PB1上安裝複數個(更特定而言為12個)半導體裝置PKG之情形進行說明，但作為其他之實施形態，亦有於平面形狀為圓形狀但無孔HL之配線基板PB1上安裝複數個(更特定而言係12個)半導體裝置PKG之情形。 圖25～圖28係對應於圖23之要部剖視圖、或圖24之要部剖視圖。圖25之剖視圖相當於上述圖10之位置(即，相當於上述圖5～圖7之A1-A1線之位置)的剖視圖，圖26之剖視圖相當於上述圖11之位置(即，相當於上述圖5～圖7之A2-A2線之位置)的剖視圖。又，圖27之剖視圖相當於上述圖12之位置(即，相當於上述圖5～圖7之A3-A3線之位置)的剖視圖，圖28之剖視圖相當於上述圖13之位置(即，相當於上述圖5～圖7之A4-A4線之位置)的剖視圖。 亦如圖25～圖28所示，各半導體裝置PKG以密封部MR之背面MRb對向於配線基板PB1之主面(上表面)PB1a之朝向，搭載於配線基板PB1之主面PB1a上。且，各半導體裝置PKG之複數條引腳LD各自經由焊料等導電性接合材SD而接合並固定於形成於配線基板PB1之主面PB1a之複數個端子(電極)TM。即，各半導體裝置PKG之複數條引腳LD各自經由導電性之接合材SD而與形成於配線基板PB1之主面PB1a之複數個端子TM電性連接。 配線基板PB1所具有之複數個端子TM包含：經由配線基板PB1之配線等被供給上述電位(電源電位)VIN之端子TM1、及經由配線基板PB1之配線等被供給接地電位GND之端子TM4。又，配線基板PB1所具有之複數個端子TE包含：經由配線基板PB1之配線等電性連接於上述控制電路CT之端子TM5、及經由配線基板PB1之配線等電性連接於上述馬達MOT(線圈CL)之端子TM2、TM3。配線基板PB1之各端子TM與配線基板PB1之配線電性連接。又，配線基板PB1之端子TM2與端子TM3經由配線基板PB1之配線等而彼此電性連接。作為配線基板PB1，可使用僅於配線基板之一主面形成有配線層(配線)之配線基板、或於配線基板之位於互為相反側之主面兩者形成配線層(配線)之配線基板、或於配線基板之兩者有主面與配線基板之內部形成有配線層(配線)之配線基板(所謂之多層配線基板)等。 於各半導體裝置PKG中，引腳LD1經由導電性之接合材(焊料)SD接合並電性連接於端子TM1，引腳LD2經由導電性之接合材(焊料)SD接合並電性連接於端子TM2，引腳LD3經由導電性之接合材(焊料)SD接合並電性連接於端子TM3。於各半導體裝置PKG中，引腳LD4經由導電性之接合材(焊料)SD接合而電性連接於端子TM4，引腳LD5a、LD5b經由導電性之接合材(焊料)SD接合並電性連接於端子TM5。 藉此，經由配線基板PB1之配線等自配線基板PB1之端子TM1向半導體裝置PKG之引腳LD1供給上述電位(電源電位)VIN，進而自引腳LD1經由半導體裝置PKG內之晶片焊墊DPH向半導體裝置PKG內之半導體晶片CPH之背面電極BEH供給該電位VIN。又，經由配線基板PB1之配線等自配線基板PB1之端子TM4向半導體裝置PKG之引腳LD4供給接地電位GND，進而自引腳LD4經由半導體裝置PKG內之金屬板MP2向半導體裝置PKG內之半導體晶片CPL之源極用焊墊PDLS1供給該接地電位GND。又，形成於半導體裝置PKG內之半導體晶片CPC內之上述控制電路CLC可通過半導體裝置PKG內之半導體晶片CPC之焊墊PDC、半導體裝置PKG內之導線BW、半導體裝置PKG之引腳LD5a、LD5b、配線基板PB1之端子TM5及配線基板PB1之配線等，與上述控制電路CT進行信號之交換。 又，半導體裝置PKG之引腳LD2與引腳LD3各自經由導電性之接合材(焊料)SD而與端子TM2與端子TM3電性連接，但配線基板PB1之端子TM2與端子TM3經由配線基板PB1之配線等而電性連接。即，配線基板PB1之端子TM2與端子TM3於半導體裝置PKG之外部，經由導體(具體而言為配線基板PB1之配線等)電性連接。因此，於將半導體裝置PKG安裝於配線基板PB1上之狀態，半導體裝置PKG之引腳LD2與引腳LD3經由配線基板PB1之端子TM2、端子TM3及配線彼此電性連接，進而通過配線基板PB1之配線等而電性連接於上述馬達(線圈CL)。 又，於圖25～圖28之情形，於搭載於配線基板PB1上之各半導體裝置PKG之密封部MR之主面MRa上，隔著絕緣性之接著材BD11配置(搭載)有散熱器(殼體)HS。作為絕緣性之接著材BD11，可使用例如具有絕緣性之熱傳遞性潤滑脂等。作為散熱器HS可使用例如風扇型之散熱器等。 於半導體裝置PKG中，晶片焊墊DPC、DPH、DPL之背面DPCb、DPHb、DPLb自密封部MR之主面MRa露出，但該等晶片焊墊DPC、DPH、DPL之背面DPCb、DPHb、DPLb隔著絕緣性之接著材BD11而接合於散熱器HS。即，於半導體裝置PKG之晶片焊墊DPC、DPH、DPL之背面DPCb、DPHb、DPLb與散熱器HS之間介隔有絕緣性之接著材BD11。藉此，可將半導體裝置PKG內之半導體晶片CPC、CPH、CPL中產生之熱通過晶片焊墊DPC、DPH、DPL及接著材BD11(熱傳遞性潤滑脂)而散熱至散熱器HS。 又，將散熱器HS安裝於半導體裝置PKG，藉由使用絕緣性之接著材BD11，可一方面防止半導體裝置PKG之晶片焊墊DPC、DPH、DPL彼此經由接著材BD11及散熱器HS電性連接，一方面將熱容量較大(體積較大)之散熱器HS安裝於半導體裝置PKG。 ＜主要之特徵與效果＞ 本實施形態之半導體裝置PKG具備：包含高側開關用之功率MOSFET1(第1場效電晶體)之半導體晶片CPH(第1半導體晶片)，及包含低側開關用之功率MOSFET2(第2場效電晶體)之半導體晶片CPL(第2半導體晶片)。半導體裝置PKG進而具備包含控制半導體晶片CPH、CPL各者之控制電路CLC之半導體晶片CPC(第3半導體晶片)。半導體裝置PKG進而具備：搭載半導體晶片CPH之晶片焊墊DPH(第1晶片搭載部)、搭載半導體晶片CPL之晶片焊墊DPL(第2晶片搭載部)、及搭載半導體晶片CPC之晶片焊墊DPC(第3晶片搭載部)。 半導體晶片CPH具有正面(第1主面)及與其為相反側之背面(第1背面)，半導體晶片CPL具有正面(第2主面)及與其為相反側之背面(第2背面)，半導體晶片CPC具有正面(第3主面)及與其為相反側之背面(第3背面)。半導體晶片CPH具有：最上層保護膜HGH(第1保護膜)；自最上層保護膜HGH露出，且與功率MOSFET1之源極(第1源極)電性連接之焊墊PDHS1(第1源極電極)；及形成於半導體晶片CPH之背面上，且與功率MOSFET1之汲極(第1汲極)電性連接之背面電極BEH(第1汲極電極)。半導體晶片CPL具有：最上層保護膜HGL(第2保護膜)；自最上層保護膜HGL露出，且與功率MOSFET2之源極(第2源極)電性連接之焊墊PDLS1(第2源極電極)；及形成於半導體晶片CPL之背面上，且與功率MOSFET2之汲極(第2汲極)電性連接之背面電極BEL(第2汲極電極)。 半導體裝置PKG進而具備：電性連接於半導體晶片CPH之背面電極BEH之引腳LD1(第1引腳)，及經由金屬板MP1(第1導電性連接構件)而電性連接於半導體晶片CPH之焊墊PDHS1之引腳LD2(第2引腳)。半導體裝置PKG進而具備：電性連接於半導體晶片CPL之背面電極BEL之引腳LD3(第3引腳)，及經由金屬板MP2(第2導電性連接構件) 而電性連接於半導體晶片CPL之焊墊PDLS1之引腳LD4(第4引腳)。半導體裝置PKG進而具備密封部MR(密封體)，密封部MR係密封半導體晶片CPH、CPL、CPC、金屬板MP1、MP2、晶片焊墊DPH之至少一部分、晶片焊墊DPL之至少一部分、晶片焊墊DPC之至少一部分、引腳LD1之一部分、引腳LD2之一部分、引腳LD3之一部分、及引腳LD4之一部分。於俯視時，密封部MR具有：沿著X方向(第1方向)延伸之邊MRd1(第1邊)，及沿著X方向延伸，且位於與邊MRd1相反側之邊MRd3(第2邊)。 本實施形態之主要特徵之一在於：於俯視時，於密封部MR之邊MRd1與邊MRd3之間，且於半導體晶片CPH與半導體晶片CPL之間，配置有半導體晶片CPC。 本實施形態之主要特徵中之另一者在於：引腳LD1與引腳LD4與密封部MR之邊MRd1交叉，引腳LD2與引腳LD3與密封部MR之邊MRd3交叉。即，引腳LD1與引腳LD4配置於密封部MR之側面MRc1側，引腳LD2與引腳LD3配置於密封部MR之側面MRc3側。另，於半導體裝置PKG中，電流自引腳LD1經由半導體晶片CPH之功率MOSFET1向引腳LD2流通，又，電流自引腳LD3經由半導體晶片CPL之功率MOSFET2向引腳LD4流通。 以下，對採用此種特徵之理由進行說明。 由於半導體晶片CPH、CPL均為形成有開關用場效電晶體(功率電晶體)之半導體晶片，故發熱量較大。因此，半導體晶片CPH、CPL會成為熱源。亦考量與本實施形態不同，於半導體晶片CPH與半導體晶片CPL之間不配置半導體晶片CPC，而以彼此相鄰之方式配置半導體晶片CPH與半導體晶片CPL之情形。於該情形時，例如，對應於將半導體晶片CPH、半導體晶片CPL及半導體晶片CPC於X方向上依序排列之情形、或將半導體晶片CPC與半導體晶片CPH及半導體晶片CPL於X方向上依序排列之情形等。然而，當以彼此相鄰之方式配置發熱量較大之半導體晶片CPH與半導體晶片CPL時，會產生半導體晶片CPH與半導體晶片CPL之熱干擾，而有半導體裝置之可靠性降低之虞。其理由在於：當以彼此相鄰之方式配置發熱量較大之半導體晶片CPH與半導體晶片CPL時，半導體晶片CPL容易受半導體晶片CPH發熱之影響，再者，半導體晶片CPH容易受半導體晶片CPL發熱之影響之故。 因此，於本實施形態之半導體裝置PKG中，於俯視時，於半導體晶片CPH與半導體晶片CPL之間配置半導體晶片CPC。藉由於半導體晶片CPH與半導體晶片CPL之間配置半導體晶片CPC，可擴大半導體晶片CPH與半導體晶片CPL間之距離(間隔)，故可抑制或防止半導體晶片CPH與半導體晶片CPL之熱干擾。即，藉由於半導體晶片CPH與半導體晶片CPL之間配置半導體晶片CPC，則半導體晶片CPL不易受半導體晶片CPH發熱之影響，再者，半導體晶片CPH不易受半導體晶片CPL發熱之影響。因此，可使半導體裝置PKG之可靠性提高。因此，可使半導體裝置PKG之性能提高。 又，於俯視時，於半導體晶片CPH與半導體晶片CPL之間配置半導體晶片CPC，藉此可一面抑制半導體裝置PKG之尺寸，一面擴大半導體晶片CPH與半導體晶片CPL間之距離，因此可兼顧半導體晶片CPH與半導體晶片CPL之熱干擾之抑制、與半導體裝置PKG之小型化。 然而，由於高側開關用之功率MOSFET1、與低側開關用之功率MOSFET2必須串聯連接，故必須電性連接半導體晶片CPH之焊墊PDHS1(功率MOSFET1之源極用焊墊電極)、與半導體晶片CPL之背面電極BEL(功率MOSFET2之汲極用背面電極)。 與本實施形態不同，於半導體晶片CPH與半導體晶片CPL彼此相鄰之情形時，可以金屬板連接搭載半導體晶片CPL之晶片焊墊DPL、與半導體晶片CPH之焊墊PDHS1，並可經由該金屬板，電性連接半導體晶片CPH之焊墊PDHS1與半導體晶片CPL之背面電極BEL。因此，與本實施形態不同，於半導體晶片CPH與半導體晶片CPL彼此相鄰之情形時，於半導體裝置PKG內(即密封部MR內)，易於經由導體而連接半導體晶片CPH之焊墊PDHS1與半導體晶片CPL之背面電極BEL。 然而，於本實施形態中，如上所述，為了防止半導體晶片CPH與半導體晶片CPL之熱干擾，而於半導體晶片CPH與半導體晶片CPL之間配置半導體晶片CPC。於該情形時，由於存在於半導體晶片CPH、CPL間之半導體晶片CPC造成阻礙，故難以以金屬板連接搭載半導體晶片CPL之晶片焊墊DPL與半導體晶片CPH之焊墊PDHS1。因此，如本實施形態般於半導體晶片CPH與半導體晶片CPL之間配置有半導體晶片CPC之情形時，於半導體裝置PKG中(即密封部MR內)，難以經由導體連接半導體晶片CPH之焊墊PDHS1與半導體晶片CPL之背面電極BEL。 因此，於本實施形態中，於半導體裝置PKG設置有(經由金屬板MP1)電性連接於半導體晶片CPH之焊墊PDHS1之引腳LD2(第2引腳)、與電性連接於半導體晶片CPL之背面電極BEL之引腳LD3(第3引腳)。藉此，可將半導體裝置PKG之引腳LD2與引腳LD3於半導體裝置PKG之外部電性連接，由此，能夠將半導體晶片CPH之焊墊PDHS1(功率MOSFET1之源極用焊墊電極)、與半導體晶片CPL之背面電極BEL(功率MOSFET2之汲極用背面電極)電性連接。例如，於將半導體裝置PKG安裝於配線基板PB1上時，可經由該配線基板PB1之配線等而電性連接半導體裝置PKG之引腳LD2與引腳LD3。 因此，於本實施形態中，於半導體裝置PKG設置有：電性連接於半導體晶片CPH之背面電極BEH之引腳LD1、電性連接於半導體晶片CPH之焊墊PDHS1之引腳LD2、電性連接於半導體晶片CPL之背面電極BEL之引腳LD3、及電性連接於半導體晶片CPL之焊墊PDLS1之引腳LD4。藉此，於將半導體裝置PKG安裝於配線基板PB1之狀態下，可將電位(電源電位)NIV供給至引腳LD1，將低於其之基準電位(接地電位GND)供給至引腳LD4，且，可於電位VIN與基準電位(GND)之間串聯連接半導體晶片CPH所包含之功率MOSFET1與半導體晶片CPL所包含之功率MOSFET2。藉此，可使半導體晶片CPH所包含之功率MOSFET1作為高側開關發揮功能，使半導體晶片CPL所包含之功率MOSFET2作為低側開關發揮功能。 然而，於本實施形態中，於半導體裝置PKG不僅設置有該等引腳LD1、LD2、LD3、LD4，且對該等引腳LD1、LD2、LD3、LD4之配置位置加以設想。 即，於本實施形態中，於俯視時，引腳LD1與引腳LD4配置於密封部MR之側面MRc1側，引腳LD2與引腳LD3配置於密封部MR之側面MRc3側。即，於密封部MR之相同側面(此處為側面MRc3)側配置引腳LD2與引腳LD3，於與其相反側之側面(此處為側面MRc1)側配置引腳LD1與引腳LD4。即，於俯視時，引腳LD1與引腳LD4與密封部MR之邊MRd1交叉，引腳LD2與引腳LD3與密封部MR之邊MRd3交叉。 於本實施形態中，藉由於密封部MR之相同側面(此處為側面MRc3)側配置引腳LD2與引腳LD3，而易於將半導體裝置PKG之引腳LD2與引腳LD3於半導體裝置PKG之外部電性連接。即，於將半導體裝置PKG安裝於配線基板PB1上時，易於經由該配線基板PB1之配線等而電性連接半導體裝置PKG之引腳LD2與引腳LD3。 與本實施形態不同，假設將引腳LD1與引腳LD3配置於密封部MR之側面MRc1側，且將引腳LD2與引腳LD4配置於密封部MR之側面MRc3側之情形。於該情形時，必須利用安裝半導體裝置之配線基板PB1之配線，將配置於密封部MR之側面MRc3側之引腳LD2、與配置於密封部MR之側面MRc1側之引腳LD3電性連接。然而，若利用配線基板PB1之配線將配置於密封部MR之互為相反側之側面之引腳彼此電性連接，則難以於配線基板PB1有效率地配置配線，而導致配線設計之限制增大。因此，於配線基板PB1中，不僅是連接引腳LD2與引腳LD3之配線，其他配線亦難以有效率地配置。如此會導致配線基板PB1之配線設計之自由度降低，且亦有招致配線基板PB1之平面尺寸增大之虞。 即，若比較於密封部MR之相同側面(MRc3)側配置引腳LD2與引腳LD3兩者之情形，與於密封部MR之互為相反側之2個側面(MRc1、MRc3)之一者配置引腳LD2、於另一者配置引腳LD3之情形，前者更易於利用安裝半導體裝置PKG之配線基板PB1之配線將引腳LD2與引腳LD3電性連接。 因此，如本實施形態般，藉由於密封部MR之相同側面(此處為側面MRc3)側配置引腳LD2與引腳LD3，於將半導體裝置PKG安裝於配線基板(PB1)上時，易於經由該配線基板(PB1)之配線而電性連接半導體裝置PKG之引腳LD2與引腳LD3。藉此，可於安裝半導體裝置PKG安裝之配線基板(PB1)有效率地配置配線，而減小配線基板(PB1)之配線設計之限制。因此，於供半導體裝置PKG安裝之配線基板(PB1)中，不但易於有效率地配置連接引腳LD2與引腳LD3之配線，亦有效率地配置其以外之配線，而可自由地引繞配線。因此，可提高安裝半導體裝置PKG之配線基板(PB1)之配線設計之自由度。又，可抑制安裝半導體裝置PKG之配線基板(PB1)之平面尺寸(平面面積)。再者，半導體裝置PKG之可用性變佳。另，藉由對半導體裝置PKG加以設想而提高安裝半導體裝置PKG之配線基板(PB1)之配線設計之自由度，連帶關係到將半導體裝置PKG安裝於配線基板(PB1)上之電子裝置(上述控制板PB)之性能提高，故亦可視為該半導體裝置PKG之性能提高。 根據如上理由，本實施形態之半導體裝置PKG中，於俯視時，於半導體晶片CPH與半導體晶片CPL之間配置半導體晶片CPC，將引腳LD2與引腳LD3配置於密封部MR之相同側面(此處為側面MRc3)側，且將引腳LD1與引腳LD4配置於與其為相反側之密封部MR之側面(此處為側面MRc1)側。 另，於本實施形態中，於半導體裝置PKG內，引腳LD2與引腳LD3不通過導體相連，而於半導體裝置PKG之外部將引腳LD2與引腳LD3電性連接。具體而言，經由安裝半導體裝置PKG之配線基板PB1之配線等而電性連接半導體裝置PKG之引腳LD2與引腳LD3。 接著，對本實施形態之進而其他之特徵，於以下進行說明。 本實施形態之半導體裝置PKG中，於俯視時，半導體晶片CPH、半導體晶片CPC、及半導體晶片CPL係於X方向排列。即，於俯視時，於朝X方向延伸之假想之直線上配置有半導體晶片CPH、半導體晶片CPC、及半導體晶片CPL。藉此，由於可有效地抑制半導體裝置PKG(密封部MR)之Y方向之尺寸，故可謀求半導體裝置PKG之小型化。 又，本實施形態之半導體裝置PKG中，於俯視時，引腳LD1與引腳LD2隔著半導體晶片CPH而位於互為相反側，又，引腳LD3與引腳LD4隔著半導體晶片CPL而位於互為相反側。藉此，可有效地配置引腳LD1、LD2、LD3、LD4，而可謀求半導體裝置PKG之小型化。 又，本實施形態之半導體裝置PKG中，引腳LD1一體連結於晶片焊墊DPH，引腳LD3一體連結於晶片焊墊DPL。藉此，可通過晶片焊墊DPH而電性連接引腳LD1、與搭載於晶片焊墊DPH上之半導體晶片CPH之背面電極BEH，又，可通過晶片焊墊DPL而電性連接引腳LD3、與搭載於晶片焊墊DPL上之半導體晶片CPL之背面電極BEL。因此，可以低電阻連接引腳LD1與半導體晶片CPH之背面電極BEH之間、及引腳LD3與半導體晶片CPL之背面電極BEL之間，可降低導通損失。藉此，可使半導體裝置之性能提高。 又，本實施形態之半導體裝置PKG進而具備：一體連結於晶片焊墊DPH，且配置於密封部MR之側面MRc3側之引腳LD6(第5引腳)，及一體連結於晶片焊墊DPL，且配置於密封部MR之側面MRc1側之引腳LD7(第6引腳)。引腳LD6俯視時與密封部MR之邊MRd3交叉，引腳LD7俯視時與密封部MR之邊MRd1交叉。 於該情形時，藉由將引腳LD1、LD6一體連結於晶片焊墊DPH，將引腳LD1配置於密封部MR之側面MRc1側，將引腳LD6配置於密封部MR之側面MRc3側，而於製造半導體裝置PKG時，可將晶片焊墊DPH經由引腳LD1、LD6穩定地支持於引腳框架之框架。又，藉由將引腳LD3、LD7一體連結於晶片焊墊DPL，將引腳LD3配置於密封部MR之側面MRc3側，將引腳LD7配置於密封部MR之側面MRc1側，於製造半導體裝置PKG時，可將晶片焊墊DPL經由引腳LD3、LD7穩定地支持於引腳框架之框架。因此，易於進行使用引腳框架之半導體裝置PKG之製造步驟。 另，一體連結於晶片焊墊DPH之引腳LD1、LD6中，引腳LD1作為經由半導體晶片CPH(功率MOSFET1)而流通之電流路徑發揮功能，但引腳LD6不作為經由半導體晶片CPH(功率MOSFET1)而流通之電流路徑發揮功能。又，一體連結於晶片焊墊DPL之引腳LD3、LD7中，引腳LD3作為經由半導體晶片CPL(功率MOSFET2)流通之電流路徑發揮功能，但引腳LD7不作為經由半導體晶片CPL(功率MOSFET2)流通之電流路徑發揮功能。其理由在於：於本實施形態之半導體裝置PKG中，電流自引腳LD1經由半導體晶片CPH之功率MOSFET1向引腳LD2流通，又，電流自引腳LD3經由半導體晶片CPL之功率MOSFET2向引腳LD4流通之故。因此，一體連結於晶片焊墊DPL之引腳LD3必須經由配線基板PB1之配線電性連接於引腳LD2，但一體連結於晶片焊墊DPL之引腳LD7無須經由配線基板PB1之配線電性連接於引腳LD2。因此，要電性連接半導體晶片CPH之焊墊PDHS1與半導體晶片CPL之背面電極BEL，只要以將半導體裝置PKG安裝於配線基板PB1上之狀態，通過該配線基板PB1之配線電性連接引腳LD2與引腳LD3即可，而無須對半導體裝置PKG之引腳LD6、LD7用之配線加以設想。因此，即使於半導體裝置PKG設置引腳LD6、LD7，亦不會對配線基板PB1之配線設計造成不良影響。 又，本實施形態之半導體裝置PKG中，作為電性連接半導體晶片CPH之焊墊PDHS1與引腳LD2之導電性連接構件，使用金屬板MP1，又，作為電性連接半導體晶片CPL之焊墊PDLS1與引腳LD4之導電性連接構件，使用金屬板MP2。藉此，可降低導通損失，可使半導體裝置之性能提高。 又，本實施形態之半導體裝置PKG具有各複數個：電性連接於半導體晶片CPH之背面電極BEH之引腳LD1、電性連接於半導體晶片CPH之焊墊PDHS1之引腳LD2、電性連接於半導體晶片CPL之背面電極BEL之引腳LD3、電性連接於半導體晶片CPL之焊墊PDLS1之引腳LD4。且，於半導體裝置PKG中，複數條引腳LD1相互連結，且俯視時分別與密封部MR之邊MRd1交叉，複數條引腳LD2相互連結，且俯視時各自與密封部MR之邊MRd3交叉。又，於半導體裝置PKG中，複數條引腳LD3相互連結，且俯視時分別與密封部MR之邊MRd3交叉，複數條引腳LD4相互連結，且俯視時各自與密封部MR之邊MRd1交叉。可藉由使複數條引腳LD1相互連結，使複數條引腳LD2相互連結，使複數條引腳LD3相互連結，使複數條引腳LD4相互連結，而降低導通損失。藉此，可使半導體裝置之性能提高。 又，本實施形態之半導體裝置PKG具有經由複數條導線BW分別電性連接於半導體晶片CPC之複數個焊墊PDC之複數條引腳LD5a、LD5b。於俯視時，複數條引腳LD5a(第7引腳)各者與密封部MR之邊MRd1交叉，複數條引腳LD5b(第8引腳)各者與密封部MR之邊MRd3交叉。即，複數條引腳LD5a配置於密封部MR之側面MRc1側，複數條引腳LD5b配置於密封部MR之側面MRc3側。於側面MRc1(邊MRd1)中，複數條引腳LD5a配置於引腳LD1與引腳LD4之間，於側面MRc3(邊MRd3)，複數條引腳LD5b配置於引腳LD2與引腳LD3之間。藉此，可一面抑制密封部MR之尺寸(尤其是X方向之尺寸)，一面有效地配置電性連接於半導體晶片CPC之焊墊PDC之引腳LD5a、LD5b。因此，可兼顧引腳LD5a、LD5b之總數增加、與半導體裝置PKG之小型化。 又，本實施形態之半導體裝置PKG中，晶片焊墊DPH之背面DPHb、晶片焊墊DPL之背面DPLb及晶片焊墊DPC之背面DPCb自密封部MR之主面MRa露出。藉此，可自於密封部MR之主面MRa露出之晶片焊墊DPH、DPC、DPL向半導體裝置PKG外散熱，且無須將半導體裝置PKG之晶片焊墊DPH、DPC、DPL連接於配線基板PB1之端子。因此，於用以安裝半導體裝置PKG之配線基板PB1中，無須設置用以連接於半導體裝置PKG之晶片焊墊DPH、DPC、DPL的端子，而可於安裝半導體裝置PKG時俯視下與密封部MR重疊的區域，根據需要而自由配置(引繞)配線基板PB1之配線。因此，可進一步提高安裝半導體裝置PKG之配線基板PB1之配線設計之自由度。 另，作為本實施形態之半導體裝置PKG，藉由採用平面形狀為長方形之SOP型封裝構造，與採用平面形狀為大致正方形之QFP(Quad Flat Package)或QFN(Quad Flat Non leaded package：無引腳四邊平面封裝)之情形相比，可更有效率地將複數個(此處為12個)半導體裝置PKG配置於平面形狀為圓形狀之配線基板PB1。藉此，可謀求安裝半導體裝置PKG之配線基板PB1(控制板PB)之小型化。 接著，對經由導線BW而連接半導體晶片CPH、CPC、CPL間、與半導體晶片CPH、CPL之溫度檢測用二極體之配置位置，參照圖29及圖30進行說明。 圖29及圖30係半導體裝置PKG之俯視透視圖，透視顯示半導體裝置PKG內之半導體晶片CPH、CPC、CPL。另，於圖29及圖30中，為了簡化圖式，顯示連接半導體晶片CPH、CPC、CPL與半導體晶片CPH、CPC、CPL間之導線BW，其他則省略圖示。即，於圖29及圖30中，省略晶片焊墊DPH、DPC、DPL及引腳LD之圖示，且對於上述圖7所示之複數條導線中連接半導體晶片CPC之焊墊PDC與引腳LD5a、LD5b間之導線BW亦省略圖示。 首先，參照上述圖7、圖29及圖30，說明將半導體裝置PKG中之半導體晶片CPH、CPC、CPL間經由導線BW進行連接。 於俯視時，半導體晶片CPH具有邊H1、位於與邊H1相反側之邊H3、與邊H1、H3交叉之邊H2、與邊H1、H3交叉且位於與邊H2相反側之邊H4。半導體晶片CPH具有包含該等4條邊H1、H2、H3、H4之矩形狀之平面形狀。半導體晶片CPH之邊H1、H2、H3、H4中，邊H1與半導體晶片CPC對向。 又，於俯視時，半導體晶片CPL具有邊L1、位於與邊L1相反側之邊L3、與邊L1、L3交叉之邊L2、與邊L1、L3交叉且位於與邊L2相反側之邊L4。半導體晶片CPL具有包含該等4條邊L1、L2、L3、L4之矩形狀之平面形狀。半導體晶片CPL之邊L1、L2、L3、L4中，邊L1與半導體晶片CPC對向。 又，於俯視時，半導體晶片CPC具有邊C1、位於與邊C1相反側之邊C3、與邊C1、C3交叉之邊C2、與邊C1、C3交叉且位於與邊C2相反側之邊C4。半導體晶片CPC具有包含該等4條邊C1、C2、C3、C4之矩形狀之平面形狀。半導體晶片CPC之邊C1、C2、C3、C4中，邊C1與半導體晶片CPH對向，邊C3與半導體晶片CPL對向。 於半導體裝置PKG中，半導體晶片CPH之邊H1、H3、半導體晶片CPC之邊C1、C3、及半導體晶片CPL之邊L1、L3於Y方向上大致平行，又，半導體晶片CPH之邊H2、H4、半導體晶片CPC之邊C2、C4、及半導體晶片CPL之邊L2、L4於X方向上大致平行。另，半導體晶片CPH之邊H2、半導體晶片CPC之邊C4、及半導體晶片CPL之邊L4位於密封部MR之側面MRc1側，半導體晶片CPH之邊H4、半導體晶片CPC之邊C2、及半導體晶片CPL之邊L2位於密封部MR之側面MRc3側。 亦如上述圖7所示，半導體晶片CPC所具有之複數個焊墊PDC包含：經由導線BW電性連接於引腳LD5a或引腳LD5b之焊墊PDC，經由導線BW電性連接於半導體晶片CPH之焊墊之焊墊PDC，及經由導線BW電性連接於半導體晶片CPL之焊墊之焊墊PDC。 亦如圖7、圖29及圖30所示，半導體晶片CPH所具有之複數個焊墊中，各自經由導線BW而電性連接於半導體晶片CPC之焊墊PDC之複數個焊墊(此處為焊墊PDHG、PDHS2、PDHA、PDHC)係於半導體晶片CPH之主面上，沿著與半導體晶片CPC對向之邊H1配置。又，半導體晶片CPL所具有之複數個焊墊中，各自經由導線BW而電性連接於半導體晶片CPC之焊墊PDC之複數個焊墊(此處為焊墊PDLG、PDLS2、PDLA、PDLC)係於半導體晶片CPL之主面上，沿著與半導體晶片CPC對向之邊L1配置。又，半導體晶片CPC所具有之複數個焊墊PDC中，各自經由導線BW而電性連接於半導體晶片CPH之焊墊(此處為焊墊PDHG、PDHS2、PDHA、PDHC)之複數個焊墊PDC係於半導體晶片CPC之主面上，沿著與半導體晶片CPH對向之邊C1配置。又，半導體晶片CPC所具有之複數個焊墊PDC中，各自經由導線BW而電性連接於半導體晶片CPL之焊墊(此處為焊墊PDLG、PDLS2、PDLA、PDLC)之複數個焊墊PDC係於半導體晶片CPC之主面上，沿著與半導體晶片CPL對向之邊C3配置。 藉此，易於將半導體晶片CPH之複數個焊墊與半導體晶片CPC之複數個焊墊PDC之間、及半導體晶片CPL之複數個焊墊與半導體晶片CPC之複數個焊墊PDC之間以各條導線BW連接，又，可縮短該導線BW之長度。因此，易於進行半導體裝置PKG之製造步驟中之打線接合連接步驟。又，可藉由能縮短導線BW而降低寄生電感。藉此，可使半導體裝置之性能提高。 接著，參照圖29及圖30，對半導體晶片CPH、CPL內之溫度檢測用二極體DA1、DA2之配置位置進行說明。 如圖29及圖30所示，半導體晶片CPH包含溫度檢測用之二極體DA1，半導體晶片CPL包含溫度檢測用之二極體DA2。二極體DA1、DA2各自包含PN接合二極體。惟於圖29之情形與圖30之情形兩者之間，半導體晶片CPH、CPL之二極體DA1、DA2之配置位置不同。 即，於圖29之情形時，於半導體晶片CPH中，於俯視時，二極體DA1以沿著邊H2之方式配置，又，於半導體晶片CPL中，於俯視時，二極體DA2以沿著邊L2之方式配置。另，半導體晶片CPH之邊H2於半導體晶片CPH中，為與對向於半導體晶片CPC之邊H1交叉之邊，又，半導體晶片CPL之邊L2於半導體晶片CPL中，為與對向於半導體晶片CPC之邊L1交叉之邊。 另一方面，於圖30之情形時，於半導體晶片CPH中，於俯視時，二極體DA1以沿著與半導體晶片CPC對向之邊H1之方式配置，又，於半導體晶片CPL中，於俯視時，二極體DA2以沿著與半導體晶片CPC對向之邊L1之方式配置。 關於二極體DA1、DA2之配置位置，圖29之情形之有利點在於可提高二極體DA1、DA2之溫度檢測之精度。以下對此進行說明。 半導體晶片CPH之二極體DA1係用於檢測半導體晶片CPH之溫度而設置者。為了提高二極體DA1之溫度檢測精度，較為有效的是使半導體晶片CPH之二極體DA1不受半導體晶片CPL發熱之影響，因此，較為有效的是使半導體晶片CPH之二極體DA1之配置位置遠離半導體晶片CPL。又，半導體晶片CPL之二極體DA2係用於檢測半導體晶片CPL之溫度而設置者。為了提高二極體DA2之溫度檢測精度，較為有效的是使半導體晶片CPL之二極體DA2不受半導體晶片CPH發熱之影響，因此，較為有效的是使半導體晶片CPL之二極體DA2之配置位置遠離半導體晶片CPH。 於圖29之情形時，於半導體裝置PKG中，可擴大半導體晶片CPH之二極體DA1與半導體晶片CPL之二極體DA2間之距離(間隔)。就別的角度而言，於圖29之情形時，於半導體裝置PKG中，可擴大半導體晶片CPH之二極體DA1至半導體晶片CPL之距離(間隔)，又，可擴大半導體晶片CPL之二極體DA2至半導體晶片CPH之距離(間隔)。因此，半導體晶片CPH之二極體DA1不易受半導體晶片CPL發熱之影響，又，半導體晶片CPL之二極體DA2不易受半導體晶片CPH發熱之影響，因此，可使二極體DA1、DA2之溫度檢測精度提高。藉此，可使半導體裝置之性能提高。 關於二極體DA1、DA2之配置位置，圖30之情形較為有利之點在於：於半導體晶片CPH、CPL各者中，可擴大形成有功率電晶體MOSFET用之電晶體元件之區域之面積，藉此可降低形成於半導體晶片CPH、CPL各者之功率MOSFET之接通電阻。以下對此進行說明。 於圖29及圖30中，半導體晶片CPH中之以二點鏈線包圍之區域為電晶體形成區域RG1，半導體晶片CPL中之以二點鏈線包圍之區域為電晶體形成區域RG2。此處，電晶體形成區域RG1對應於半導體晶片CPH中形成有功率MOSFET1用之複數個單位電晶體單元(此處為溝槽式閘極型MISFET)的區域(平面區域)。又，電晶體形成區域RG2對應於半導體晶片CPL中形成有功率MOSFET2用之複數個單位電晶體單元(此處為溝槽式閘極型MISFET)的區域(平面區域)。 若比較圖29之情形與圖30之情形，則與於半導體晶片CPH中沿著邊H2配置二極體DA1之圖29之情形相比，沿著邊H1配置二極體DA1之圖30之情形更可擴大電晶體形成區域RG1之Y方向之尺寸。其理由在於：於半導體晶片CPH中，於形成有二極體DA1之區域，無法形成功率MOSFET1用之電晶體元件(溝閘極型MISFET)。因此，若於半導體晶片CPH中沿著邊H2配置二極體DA1，會招致電晶體形成區域RG1之Y方向之尺寸縮小。此點於半導體晶片CPL中亦同，若比較圖29之情形與圖30之情形，則與於半導體晶片CPL中沿著邊L2配置二極體DA2之圖29之情形相比，沿著邊L1配置二極體DA2之圖30之情形更可擴大電晶體形成區域RG2之Y方向之尺寸。 又，若比較圖29之情形與圖30之情形，則半導體晶片CPH之電晶體形成區域RG1之X方向尺寸幾乎不變。其理由在於：於半導體晶片CPH中，沿著邊H1配置有打線接合連接用之焊墊(此處為焊墊PDHG、PDHS2、PDHA、PDHC)，但於該等焊墊(PDHG、PDHS2、PDHA、PDHC)之正下方，未形成功率MOSFET1用之電晶體元件(溝閘極型MISFET)。因此，於半導體晶片CPH中，即使將二極體DA1配置於配置有打線接合連接用之焊墊(PDHG、PDHS2、PDHA、PDHC)之邊H1，亦不會招致電晶體形成區域RG1之X方向尺寸縮小太多。此點於半導體晶片CPL中亦同，若比較圖29之情形與圖30之情形，則半導體晶片CPL之電晶體形成區域RG2之X方向尺寸無太大改變。 因此，若比較圖29之情形及圖30之情形，圖30之情形更可擴大半導體晶片CPH之電晶體形成區域RG1之面積，又，可擴大半導體晶片CPL之電晶體形成區域RG2之面積。藉此，與圖29之情形相比，圖30之情形更可擴大半導體晶片CPH、CPL之電晶體形成區域RG1、RG2之面積，藉此，可降低形成於半導體晶片CPH、CPL之功率MOSFET1、2之接通電阻。藉此，可使半導體裝置之性能提高。 又，本實施形態之半導體裝置PKG具有：形成有高側開關用之功率MOSFET1之半導體晶片CPH，及形成有低側開關用之功率MOSFET2之半導體晶片CPL，但若半導體晶片CPH之構造與半導體晶片CPL之構造彼此相同則更佳。即，更佳為將相同種類(相同構造)之半導體晶片用於半導體晶片CPH與半導體晶片CPL。藉此，可以相同之製造步驟製造半導體晶片CPH與半導體晶片CPL，可抑制半導體裝置PKG之製造成本。 於半導體晶片CPH之構造與半導體晶片CPL之構造彼此相同之情形時，於俯視時，半導體晶片CPL之朝向對應於使半導體晶片CPH旋轉180°之朝向(參照圖29及圖30)。藉此，易於以導線BW連接半導體晶片CPH之焊墊與半導體晶片CPC之焊墊PDC，又，易於以導線BW連接半導體晶片CPL之焊墊與半導體晶片CPC之焊墊PDC。 以上已基於本發明之實施形態具體地說明由本發明者完成之發明，但本發明並非限定於上述實施形態者，於不脫離其主旨之範圍，當得進行各種變更。
1‧‧‧功率MOSFET2‧‧‧功率MOSFET3‧‧‧感測MOSFET4‧‧‧感測MOSFETA1-A1‧‧‧線A2-A2‧‧‧線A3-A3‧‧‧線A4-A4‧‧‧線BD1～BD7‧‧‧接著層BD11‧‧‧接著材BEH‧‧‧背面電極BEL‧‧‧背面電極BW‧‧‧導線CL‧‧‧線圈CLC‧‧‧控制電路CPC‧‧‧半導體晶片CPCa‧‧‧正面CPH‧‧‧半導體晶片CPHa‧‧‧正面CPL‧‧‧半導體晶片CPLa‧‧‧正面CT‧‧‧控制電路C1‧‧‧邊C2‧‧‧邊C3‧‧‧邊C4‧‧‧邊DA1‧‧‧溫度檢測用二極體DA2‧‧‧溫度檢測用二極體DPC‧‧‧晶片焊墊DPCa‧‧‧主面DPCb‧‧‧背面DPH‧‧‧晶片焊墊DPHa‧‧‧主面DPHb‧‧‧背面DPL‧‧‧晶片焊墊DPLa‧‧‧主面DPLb‧‧‧背面D1～D4‧‧‧汲極GND‧‧‧接地電位HGC‧‧‧最上層保護膜HGH‧‧‧最上層保護膜HGL‧‧‧最上層保護膜HL‧‧‧孔HN‧‧‧方向盤HS‧‧‧散熱器H1‧‧‧邊H2‧‧‧邊H3‧‧‧邊H4‧‧‧邊INV‧‧‧換流器電路KP‧‧‧轉向銷LB1～LB4‧‧‧引腳連結部LB1a‧‧‧連結部LB3a‧‧‧連結部LD‧‧‧引腳LD1‧‧‧引腳LD2～LD4‧‧‧引腳LD5a‧‧‧引腳LD5b‧‧‧引腳LD6～LD8‧‧‧引腳LF‧‧‧引腳框架L1‧‧‧邊L2‧‧‧邊L3‧‧‧邊L4‧‧‧邊MOT‧‧‧馬達MP1‧‧‧金屬板MP2‧‧‧金屬板MR‧‧‧密封部MRa‧‧‧主面MRb‧‧‧背面MRc1～MRc4‧‧‧側面MRd1～MRd4‧‧‧邊PB‧‧‧控制板PB1‧‧‧配線基板PB1a‧‧‧主面PDC‧‧‧焊墊PDLA‧‧‧焊墊PDLC‧‧‧焊墊PDLG‧‧‧焊墊PDLS1‧‧‧焊墊PDLS2‧‧‧焊墊PDHA‧‧‧焊墊PDHC‧‧‧焊墊PDHG‧‧‧焊墊PDHS1‧‧‧焊墊PDHS2‧‧‧焊墊PKG‧‧‧半導體裝置RG1‧‧‧電晶體形成區域RG2‧‧‧電晶體形成區域RP‧‧‧齒條與小齒輪機構SD‧‧‧導電性接合材SF‧‧‧轉向軸S1～S4‧‧‧源極TE1～TE6‧‧‧端子TL‧‧‧懸架引腳TM‧‧‧端子TM1～TM5‧‧‧端子TR‧‧‧轉向橫拉杆TY‧‧‧輪胎VIN‧‧‧電位X‧‧‧方向Y‧‧‧方向
圖1係模式性顯示形成於控制12相BLDC(Brushless Direct Current：無刷直流)馬達之控制板之電路的電路圖。 圖2係顯示汽車之齒條與小齒輪型之轉向機構之說明圖。 圖3係顯示控制板與轉向軸一起旋轉之情形之說明圖。 圖4係顯示使用一實施形態之半導體裝置之換流器電路之電路圖。 圖5係一實施形態之半導體裝置之俯視圖。 圖6係一實施形態之半導體裝置之仰視圖。 圖7係一實施形態之半導體裝置之俯視透視圖。 圖8係一實施形態之半導體裝置之俯視透視圖。 圖9係一實施形態之半導體裝置之俯視透視圖。 圖10係一實施形態之半導體裝置之剖視圖。 圖11係一實施形態之半導體裝置之剖視圖。 圖12係一實施形態之半導體裝置之剖視圖。 圖13係一實施形態之半導體裝置之剖視圖。 圖14係一實施形態之半導體裝置之製造步驟中之俯視圖。 圖15係接續圖14之半導體裝置之製造步驟中之俯視圖。 圖16係接續圖15之半導體裝置之製造步驟中之俯視圖。 圖17係接續圖16之半導體裝置之製造步驟中之俯視圖。 圖18係接續圖17之半導體裝置之製造步驟中之俯視圖。 圖19係接續圖18之半導體裝置之製造步驟中之俯視圖。 圖20係與圖19相同之半導體裝置之製造步驟中之剖視圖。 圖21係與圖19相同之半導體裝置之製造步驟中之剖視圖。 圖22係與圖19相同之半導體裝置之製造步驟中之剖視圖。 圖23係顯示一實施形態之半導體裝置之安裝例之俯視圖。 圖24係顯示一實施形態之半導體裝置之安裝例之俯視圖。 圖25係顯示一實施形態之半導體裝置之安裝例之剖視圖。 圖26係顯示一實施形態之半導體裝置之安裝例之剖視圖。 圖27係顯示一實施形態之半導體裝置之安裝例之剖視圖。 圖28係顯示一實施形態之半導體裝置之安裝例之剖視圖。 圖29係一實施形態之半導體裝置之俯視透視圖。 圖30係一實施形態之半導體裝置之俯視透視圖。
A1-A1‧‧‧線
A2-A2‧‧‧線
A3-A3‧‧‧線
A4-A4‧‧‧線
BW‧‧‧導線
CPC‧‧‧半導體晶片
CPH‧‧‧半導體晶片
CPL‧‧‧半導體晶片
DPC‧‧‧晶片焊墊
DPH‧‧‧晶片焊墊
DPL‧‧‧晶片焊墊
LB1~LB4‧‧‧引腳連結部
LD‧‧‧引腳
LD1‧‧‧引腳
LD2~LD4‧‧‧引腳
LD5a‧‧‧引腳
LD5b‧‧‧引腳
LD6~LD8‧‧‧引腳
MP1‧‧‧金屬板
MP2‧‧‧金屬板
MR‧‧‧密封部
PDHG‧‧‧焊墊
PDLG‧‧‧焊墊
PDLS1‧‧‧焊墊
PDHS1‧‧‧焊墊
PKG‧‧‧半導體裝置
TL‧‧‧懸架引腳
X‧‧‧方向
Y‧‧‧方向

Claims (19)

  1. 一種半導體裝置，其具備：第1半導體晶片，其包含高側開關用之第1場效電晶體，且具有第1主面及上述第1主面之相反側之第1背面；此處，上述第1半導體晶片進而具有：第1保護膜，其具有上述第1主面；第1源極電極，其自上述第1保護膜露出，且與上述第1場效電晶體之第1源極電性連接；及第1汲極電極，其形成於上述第1背面上，且與上述第1場效電晶體之第1汲極電性連接；第2半導體晶片，其包含低側開關用之第2場效電晶體，且具有第2主面及上述第2主面之相反側之第2背面；此處，上述第2半導體晶片進而具有：第2保護膜，其具有上述第2主面；第2源極電極，其自上述第2保護膜露出，且與上述第2場效電晶體之第2源極電性連接；及第2汲極電極，其形成於上述第2背面上，且與上述第2場效電晶體之第2汲極電性連接；第3半導體晶片，其包含控制上述第1半導體晶片及上述第2半導體晶片各者之電路，且具有第3主面、及上述第3主面之相反側之第3背面；第1晶片搭載部，其供上述第1半導體晶片搭載，且具有與上述第1半導體晶片之上述第1背面相向之第4主面、及上述第4主面之相反側之第4背面；第2晶片搭載部，其供上述第2半導體晶片搭載，且具有與上述第2半導體晶片之上述第2背面相向之第5主面、及上述第5主面之相反側之第5背面； 第3晶片搭載部，其供上述第3半導體晶片搭載，且具有與上述第3半導體晶片之上述第3背面相向之第6主面、及上述第6主面之相反側之第6背面；第1引腳，其電性連接於上述第1半導體晶片之上述第1汲極電極；第2引腳，其經由第1導電性連接構件而電性連接於上述第1半導體晶片之上述第1源極電極；第3引腳，其電性連接於上述第2半導體晶片之上述第2汲極電極；第4引腳，其經由第2導電性連接構件而電性連接於上述第2半導體晶片之上述第2源極電極；及密封體，其密封上述第1半導體晶片、上述第2半導體晶片、上述第3半導體晶片、上述第1導電性連接構件、上述第2導電性連接構件、上述第1晶片搭載部之至少一部分、上述第2晶片搭載部之至少一部分、上述第3晶片搭載部之至少一部分、上述第1引腳之一部分、上述第2引腳之一部分、上述第3引腳之一部分、及上述第4引腳之一部分；且於俯視時，上述密封體具有沿著第1方向延伸之第1邊、及沿著上述第1方向延伸且位於與上述第1邊為相反側之第2邊，上述第1引腳及上述第4引腳與上述密封體之上述第1邊交叉，上述第2引腳及上述第3引腳與上述密封體之上述第2邊交叉，電流自上述第1引腳經由上述第1半導體晶片之上述第1場效電晶體向上述第2引腳流通，電流自上述第3引腳經由上述第2半導體晶片之上述第2場效電晶體向上述第4引腳流通，於俯視時，於上述第1邊與上述第2邊之間，且上述第1半導體晶片與 上述第2半導體晶片之間，配置有上述第3半導體晶片。
  2. 如請求項1之半導體裝置，其中於俯視時，上述第1半導體晶片、上述第3半導體晶片及上述第2半導體晶片沿著上述第1方向排列。
  3. 如請求項2之半導體裝置，其中於俯視時，上述第1引腳與上述第2引腳隔著上述第1半導體晶片而位於相反側，於俯視時，上述第3引腳與上述第4引腳隔著上述第2半導體晶片而位於相反側。
  4. 如請求項1之半導體裝置，其中上述第1引腳一體連結於上述第1晶片搭載部，上述第3引腳一體連結於上述第2晶片搭載部。
  5. 如請求項4之半導體裝置，其中進而具備：第5引腳，其一體連結於上述第1晶片搭載部，且與上述密封體之上述第2邊交叉，及第6引腳，其一體連結於上述第2晶片搭載部，且與上述密封體之上述第1邊交叉。
  6. 如請求項1之半導體裝置，其中 上述密封體具有第7主面、及上述第7主面之相反側之第7背面，且上述第1晶片搭載部之上述第1背面、上述第2晶片搭載部之上述第2背面及上述第3晶片搭載部之上述第3背面自上述第7主面露出。
  7. 如請求項1之半導體裝置，其中上述第1導電性連接構件及上述第2導電性連接構件各自包含金屬板。
  8. 如請求項7之半導體裝置，其中上述第1半導體晶片之第1汲極電極經由導電性之第1接著層與上述第1晶片搭載部電性連接，上述第2半導體晶片之第2汲極電極經由導電性之第2接著層與上述第2晶片搭載部電性連接。
  9. 如請求項1之半導體裝置，其中上述第3半導體晶片具有：具有上述第3主面之第3保護膜，及自上述第3保護膜露出之複數個第1焊墊電極及複數個第2焊墊電極；且該半導體裝置進而具備：複數條第7引腳，其經由複數條第1導線分別電性連接於上述第3半導體晶片之上述複數個第1焊墊電極；及複數條第8引腳，其經由複數條第2導線分別電性連接於上述第3半導體晶片之上述複數個第2焊墊電極；且於俯視時，上述複數條第7引腳各者與上述密封體之上述第1邊交 叉，上述複數條第8引腳各者與上述密封體之上述第2邊交叉，於上述第1邊，上述複數條第7引腳配置於上述第1引腳與上述第4引腳之間，於上述第2邊，上述複數條第8引腳配置於上述第2引腳與上述第3引腳之間。
  10. 如請求項9之半導體裝置，其中上述第1半導體晶片進而具有自上述第1保護膜露出之複數個第3焊墊電極，上述第2半導體晶片進而具有自上述第2保護膜露出之複數個第4焊墊電極，上述第3半導體晶片進而具有自上述第3保護膜露出之複數個第5焊墊電極及複數個第6焊墊電極，上述第1半導體晶片之上述複數個第3焊墊電極與上述第3半導體晶片之上述複數個第5焊墊電極經由複數條第3導線電性連接，上述第2半導體晶片之上述複數個第4焊墊電極與上述第3半導體晶片之上述複數個第6焊墊電極經由複數條第4導線而電性連接。
  11. 如請求項10之半導體裝置，其中於俯視時，上述第1半導體晶片具有與上述第3半導體晶片對向之第3邊，於俯視時，上述第2半導體晶片具有與上述第3半導體晶片對向之第4邊， 於俯視時，上述第3半導體晶片具有與上述第1半導體晶片對向之第5邊、及與上述第2半導體晶片對向之第6邊，於上述第1半導體晶片之上述第1主面上，上述複數個第3焊墊電極沿著上述第3邊配置，於上述第2半導體晶片之上述第2主面上，上述複數個第4焊墊電極沿著上述第4邊配置，於上述第3半導體晶片之上述第3主面上，上述複數個第5焊墊電極沿著上述第5邊配置，且上述複數個第6焊墊電極沿著上述第6邊配置。
  12. 如請求項11之半導體裝置，其中上述第1半導體晶片進而包含溫度檢測用之第1二極體，上述第2半導體晶片進而包含溫度檢測用之第2二極體，於上述第1半導體晶片中，上述第1二極體以沿著上述第3邊之方式配置，於上述第2半導體晶片中，上述第2二極體以沿著上述第4邊之方式配置。
  13. 如請求項12之半導體裝置，其中上述第1半導體晶片之構造與上述第2半導體晶片之構造互為相同。
  14. 如請求項11之半導體裝置，其中上述第1半導體晶片進而包含溫度檢測用之第1二極體，上述第2半導體晶片進而包含溫度檢測用之第2二極體， 於上述第1半導體晶片中，上述第1二極體以沿著與上述第3邊交叉之第7邊之方式配置，於上述第2半導體晶片中，上述第2二極體以沿著與上述第4邊交叉之第8邊之方式配置。
  15. 如請求項14之半導體裝置，其中上述第1半導體晶片之構造與上述第2半導體晶片之構造互為相同。
  16. 如請求項1之半導體裝置，其中上述第1引腳、上述第2引腳、上述第3引腳、及上述第4引腳分別包含有複數條，且複數條上述第1引腳相互連結，且俯視時各自與上述密封體之上述第1邊交叉，複數條上述第2引腳相互連結，且俯視時各自與上述密封體之上述第2邊交叉，複數條上述第3引腳相互連結，且俯視時各自與上述密封體之上述第2邊交叉，複數條上述第4引腳相互連結，且俯視時各自與上述密封體之上述第1邊交叉。
  17. 如請求項1之半導體裝置，其中上述第1引腳為被供給電源電位之引腳，上述第4引腳為被供給低於上述電源電位之基準電位的引腳。
  18. 如請求項17之半導體裝置，其中於上述半導體裝置內，上述第2引腳與上述第3引腳不通過導體相連，於上述半導體裝置之外部，上述第2引腳與上述第3引腳電性連接。
  19. 如請求項1之半導體裝置，其中上述第1半導體晶片、上述第2半導體晶片及上述第3半導體晶片用於形成換流器(inverter)電路。
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