A7 B7__一 五、發明説明（） 發明領述： 本發明與一種測試装置有關，特别是一種用來承 載晶片，且提供該晶片與測試設備作電性連結之測試装 發明背景： 随著半導體工業進展至超大型積體電路（uLSI)，各 種元件的尺寸也持績缩小，而密集的電路與縮小的元件 往往也造成半導《製程的複雜度及困難度大增。對於猜 密細小的元件，如何對其進行各種測試以保証該元件之 可靠度亦成爲一重要之課題。其中，將晶片（chip)自晶 圓（wafer)取下並包裝成構裝（package)元件的型式，便 須歷經各種不同的測試，以確保最後製作完成的構装元 件不但符合所要求的功能規範，也能具備足夠要求的使 用壽命。此外，對各式各樣晶片的測試方法而言，進行 測試的經濟性與時效性亦受到極大之重視。 經濟部中央標準局系工消費合作社印製 一般而言’在晶片尚未自晶翳分離出來以前，所 經歷的測試皆稱爲晶Si展次測試（w a f e r丨e v e丨t e s t)，其 主要的項目有cp1、cp2及WAT等測試。其中，WAT測試 的主要功能是提供晶圓製造廠在進行晶圓製程監控時， 所進行的抽樣檢驗測試，例如介電層材料測試 (die丨ectric test)、高低電壓埸效電晶體測試（Lvfet 本紙張尺度適用中國國家糅隼（CNS ) A4规格（2丨〇χ297公釐） A7 __—_B7_ 五、發明説明（） & HVFET testing)、PN接面（junction)測試、断路 /導通 (OPEN/S HOT)測試等等，以確保並即時控制晶圓製程之 品質。而CP1主要功用則在進行斷路/導通（open/SHOTJ 測試及部份功能測試（gross test)，至於CP2主要的能 则在進行全功能測試（full function test)。是以對某些可 以作修補的晶片如記憶晶片而言，一般皆可在CP2測試 前，先進行雷射修補（laser repa丨r)的作業，再進行〇ρ2 測試以提高良率。同時，測試的環境也分别在高低溫下（_5 •C /9CTC -1〇5·〇)進行以期先行淘沃一些容易故障之晶片 ，以保証出廠之晶片皆能具有優良品質，且可維持較長 的使用週期。 經濟部中央梯隼局貝工消费合作社印装 其次，在晶片從晶圓分離並完成包裝之製程所經 歷的測試，以記憶元件爲例，一般有FT1、FT2、FT3等 晶片程度測試（chip level test)，其主要的目的除了彌補 晶圓層次測試所無法進行的測試外，亦提供高低溫差異 極大的測試環境對該元件進行測試，以便淘沃有問題的 構装元件，以確保構裝元件之品質且有效控制該元件操 作時之生命週期β同樣地，在FT1(—般而言，包括斷路/ 導通測試及部份功能測試>(open shot & gross test) 及FT2(即全功能測試）（full function test)之間也存在一 預燒（"b-oTri - in)的加速老化過程，用以加速早夭元件的淘 汰，使终的構裝元件能具有一定保證的使用壽命。總 之，晶圓上的晶片在封裝成構裝元件的過程，必須經過 一系列加速老化（precondition)及测試之過程，以確保構 本紙張尺度適用中國國家揉準（CNS ) A4说格（210X297公釐） 經濟部中央標準局貝工消費合作社印^ A7 _________ B7 五、發明説明（） 裝元件本身的可靠度β由此可知，構裝型式的開發與其 測試方法的難易是息息相關且不可分割的。如果—種構 裝型式的開發不能解決測試或造成測試成本太高，就會 面臨市場就爭下被淘汰的命運，除非它們具有市場競爭 者所沒有的特殊功能。 然而’針對那些去除構裝而直接以覆晶凸塊（fMp chip bumps)組裝到基板（substrate)上的晶片而言，除 了 CP1、CP2、WAT等晶圓層次的測試外，很難對其進 行FT1、FT2、FT3等測試。主要原因在於要挾持並進行 測試這些微小且脆弱的晶片，實非現有之測試環境及設 備所能處理，是以必須另行開發測試設備以解決測試問 題。特别是對於承載晶片的載盤（TRAY)、吸附晶片的吸 頭、自動上料下料（LOADING & UNLOADING SYSTEM) 系統、測試承接座（TEST SOCKET)等等的開發，由於沒 有JEDEC的規範而無法統一尺寸，導致由各測試廠製造 出來的規格不具流通性，且造償昂贵。 另外，位於晶片上測試之接觸點，其製造誤差 (tolerance)—般而言大約在20μηι以下，然而傳統測試設 備的製造公差往往都超過25μΐτι以上，也使得測試的誤判 率相對的提升。因爲目前所有量產型的測試機台，幾乎 全部都是先規範測試元件的外觀尺寸及製造公差，然後 再利用測試元件的外型與測試承接座（TEST SOCKET)進 行對準位置（alignment)之動作，使測試元件的外脚與測 本紙張尺度適用中國國家楳準（CNS ) Α4规格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) •裝. 訂 ΜA7 B7__15. Description of the invention () Introduction of the invention: The present invention relates to a test device, especially a test device used to carry a wafer, and to provide the wafer with a test device for electrical connection. Background: With semiconductors Industry has progressed to ultra-large-scale integrated circuits (uLSI), and the size of various components has also continued to shrink, and dense circuits and reduced components have often caused the complexity and difficulty of semiconductors. It is also an important issue for guessing the fine and small components to perform various tests on them to ensure the reliability of the components. Among them, when the chip is removed from the wafer and packaged into a package component type, it must undergo various tests to ensure that the final fabricated component not only meets the required functions Standards can also have sufficient required service life. In addition, for various wafer test methods, the economics and timeliness of testing have also received great attention. Printed by the Central Standards Bureau of the Ministry of Economics and Industry and Consumer Cooperatives. Generally speaking, before the wafer is separated from the wafer, the tests it undergoes are all called wafer Sieve test. The main items are cp1, cp2 and WAT tests. Among them, the main function of the WAT test is to provide sample inspection tests carried out by the wafer manufacturing plant during wafer process monitoring, such as dielectric layer material test (die 丨 ectric test), high and low voltage effect transistor test (Lvfet) This paper size is applicable to China National Standard (CNS) A4 specification (2 丨 〇χ297mm) A7 __—_ B7_ V. Description of the invention () & HVFET testing), PN junction (junction) test, open / conduction (OPEN / S HOT) test and so on to ensure and control the quality of the wafer process in real time. The main function of CP1 is open / SHOTJ test and gross test. As for the main function of CP2, full function test is performed. Some of them can be repaired. For the chips such as memory chips, you can generally perform laser repair before laser CP2 test, and then perform 〇ρ2 test to improve the yield. At the same time, the test environment is also at high and low temperature. (_5 • C / 9CTC -10.5 · 〇) in order to seek out some of the fault-prone wafers in advance to ensure that the wafers from the factory can have excellent quality and can maintain a long service life. Central ladder of the Ministry of Economic Affairs The local shellfish consumer cooperative printed and printed secondly. The test that the wafer undergoes during the process of separating the wafer from the wafer and completing the packaging. Take memory elements as an example. Generally, there are chip level tests such as FT1, FT2, and FT3. In addition to making up for tests that cannot be performed at the wafer level test, the purpose of this test is to provide a test environment with high and low temperature differences to test the component, so as to troubleshoot the problematic component components, To ensure the quality of the component and to effectively control the life cycle of the component during operation. Similarly, at FT1 (in general, including open / continuity test and some functional tests) (open shot & gross test) and FT2 (Ie, full function test), there is also a burn-in (&b; oTri-in) accelerated aging process, which is used to accelerate the elimination of early-aged components, so that the final structural components can have a certain Guaranteed service life. In short, the process of packaging the wafers on the wafer into structural components must undergo a series of accelerated aging (precondition) and testing processes to ensure that the paper size of the structure is applicable to the Chinese National Standard (CNS) A4 said (210X297 mm) printed by the Shellfish Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs ^ A7 _________ B7 V. Description of the invention () The reliability of the component itself β It can be seen that the difficulty of the development of the construction type and its test method is They are closely related and indivisible. If the development of a construction type cannot solve the test or the test cost is too high, it will face the fate of being eliminated in the market unless they have Special features that market competitors do not have. However, for wafers that are directly assembled with fMp chip bumps and removed from the substrate, except for wafer levels such as CP1, CP2, and WAT. It is difficult to test FT1, FT2, FT3, etc. outside of the test. The main reason is to support and test these tiny and fragile chips, which are not handled by the existing test environment and equipment, so it must be developed and tested separately. Equipment to resolve testing issues. Especially for the development of trays (TRAY) for wafers, suction tips for wafers, automatic loading and unloading (LOADING & UNLOADING SYSTEM) systems, test sockets (TEST SOCKET), etc., due to the lack of JEDEC specifications, The inability to unify the dimensions results in the specifications manufactured by the test plants being non-circulating and costly. In addition, the manufacturing tolerances of the contact points tested on the wafer are generally below 20 μηι, but the manufacturing tolerances of traditional testing equipment often exceed 25 μΐτι, which also increases the test's false positive rate. Because almost all of the current production-type test machines, the appearance dimensions and manufacturing tolerances of the test components are first standardized, and then the shape of the test components and the test socket (TEST SOCKET) are used to perform alignment. Action to make the outer leg of the test element and the paper size of the test piece apply the Chinese National Standard (CNS) Α4 specification (210X297 mm) (Please read the precautions on the back before filling this page) • Pack. Order M
U A7 經濟部中央標準局貝工消費合作社印製 ____ B7_______五、發明説明（） 試承接座（TEST SOCKET)的測試接觸點作正確的對準。 然而，在使用這一套方法應用到沒有構装的晶片上時， 除非晶片上測試點的間距（pitch)及接觸面積足以克服測 試元件與測試承接座對位所造成的誤差，或者是藉著在 測試機台加裝視覺系統以進行對位動作，否則誤判率必 然是相當的大。總而言之·，無論該測試晶片之測試點是 否經過重新佈局（redistribution)，不可避免地，皆必須 利用製造裸晶等級的技術去製造測試承接座 (TEST SOCKET)並釔合視覺對位系統進行對位，如此才 減少誤判率並摄聪晶片大小不一造成流通性減小的問 題》而本發明即針對上述的問題，提出一種可以利用現 有測試設備與環境，便可對具有覆晶凸塊的棵晶片進行 測試之方法，使每一個具有覆晶凸塊的晶片皆讦進行FT1 、FT2及預燒法（BURN-IN)等測試。同時，每賴組裝到基 板（SUBSTRATE)上的晶片，經由本發明的方法皆能控制 其品質且提供一定的使用壽命。 發明目的及概诚： 本發明之目的在提供—種測試裝置，用以提供晶 片在進行晶片程度測試時，可直接使用原有之測試設備 進行測試，以有效節省成本。 本發明之另一目的在提供一種測試晶片之方法， 用以對所生產之晶片進行晶片程度之測試。 (請先Μ讀背面之.注意事項再填寫本頁) -裝. 訂U A7 Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs ____ B7_______ V. Description of the invention () The test contact points of the test socket (TEST SOCKET) are correctly aligned. However, when using this method to apply to unstructured wafers, unless the pitch and contact area of the test points on the wafer are sufficient to overcome the error caused by the alignment of the test component and the test socket, or by Install a vision system on the test machine to perform the alignment action, otherwise the false positive rate is bound to be quite large. All in all, no matter whether the test points of the test wafer have been redistributed, it is inevitable that the technology of manufacturing bare die grades must be used to manufacture the test socket (TEST SOCKET) and the alignment of the yttrium vision alignment system In order to reduce the false positive rate and to reduce the liquidity caused by the difference in the size of the photographic chip ", the present invention addresses the above-mentioned problem, and proposes a method that can use existing testing equipment and the environment to The test method of the wafer, so that every wafer with flip-chip bumps is tested by FT1, FT2, and burn-in method (BURN-IN). At the same time, each chip assembled on a substrate can control its quality and provide a certain service life through the method of the present invention. Purpose of the invention and sincerity: The purpose of the present invention is to provide a test device for providing wafers to be tested directly by using original testing equipment when performing wafer level tests, so as to effectively save costs. Another object of the present invention is to provide a method for testing a wafer for testing the degree of wafers on a produced wafer. (Please read the back. Please note before filling out this page)-Pack. Order
本紙張从適^5國家橾準（CNS )八4胁(2l〇^7^T Μ Β7 五、發明説明（） 本發明之再一目的在提供一種測試装置，用以提 供作爲所測試晶片與測試設備之電性連結介面。 一種用以承載晶片之測試裝置包含了複數個内引 脚，用以提供該晶片作電性連结之用。其中該晶片具有 複數個導電性凸塊。此外，一金屬層形成於該内引腳之 表面上，用以固定該晶片於該複數個内引腳上，其中該 金屬層之熔點小於該導電性凸塊之熔點。接著，一黏著 物質貼附於該複數個内引脚之下表面，用以固定該複數 個内引腳。提供一載體裝置，用以連結並承載該複數個 内引腳，且提供該複數個内引腳作為電性連結之用。其 中在該金屬層之上更包含媒介層，作為該複數傭導電性 凸塊與該金屬層間接觸之介面，其中該媒介層之熔點小 於該導電性凸塊之熔點。另外該測試裝置更包括一保護 裝置，用以固定並保護該載體裝置以及位於該載體裝置 上之元件。其中，當上述之載體裝置放置於該保護裝置 内，可將該保護裝置放置於一加熱平台上進行加熱，當 加熱溫度高於該金屬層之熔點時，可使進行測試之該晶 片自該複數個内引腳上脫離。 經濟部中央標準局貝工消費合作社印製 (請讀背^*之注意事項再填寫本瓦) 此外，本發明亦提供一種測試晶片之方法，用以 測試具有導電性凸塊之裸晶片，該方法首先藉著加熱程 序使晶片連結於一導線架上。其中該導線架用以承載該 晶片，且具有複數個内引腳以提供該晶片電性連結至測 本紙張尺度適用中國國家梂準（CNS ) A4说格（210X297公釐） A7 _______B7 五、發明説明（） 試設倕。至於在該複數個内引脚上則形成一沾錫性金屬 層，且該沾鉞性金屬層在加熱程序中會熔解，並使該晶 片上之複數個導電性凸塊連結於該複數個内引脚上。接 著，進行測試程序以淘沃有問題之晶片以控制生產晶片 之品質。最後’藉著加熱程序使位於該内引腳上之沾錫 性金屬熔解以分離該晶片·舆導線架，使測試完之該晶片 自複數個内引脚上脫離。 m式钥單説明 藉由以下詳細之描述結合所附圈示，將可輊易的 了解上述内容及此項發明之諸多優點，其中： 第一圖所顯示為根據本發明提供之導線架其結構之截 面圖。 第二圖所顯示為根據本發明將所測試之晶片連結至該 導線架上其結構之截面圖。 第三圈所顯示為根據本發明提供載體裝置其載面圖與 俯視圖。 第四圖所顯示為根據本發明提供之另一實施例其截面 圈與俯視圖。 第五圖所顯示為根據本發明提供之保護裝置其載面圈 〇 第六圈所顯示為根據本發明將載體裝置玫置於保獲裝 置上之截面圖β 第七圖所顯示為根據本發明將載體裝置放置於保護裝 7 經濟部中央標準局員工消费合作社印装 A7 B7 五、發明説明（） 置上之載面圖。 第八闽所期示為根據本發明加熱該保護裝置使該晶片 自導線架上脫離之裁面圖。 發明詳细説明： 根據本發明所提供之方法，針對具有覆晶凸塊（flip chip bumps)5〇之裸晶片4〇，以暫時固定於導線架 (lead frame) 500的方式進行測試，待測試程序完成後再 將該具有覆晶凸塊50之裸晶片40自導線架500上分離，使 裸晶片40在經由預燒（burn_in)及測試的篩選後，可得到 品質良好之晶片。該導線架500除了具有易於固定及拆除 具有覆晶凸塊50之裸晶片40的特殊設計外，成型後的外 觀尺寸亦能吻合現有之測試承接座（s〇cket)，使預燒 (burn-in)及各種測試皆能利用現有之測試軟硬體加以進 行，以省下额外開發的測試成本與時間。 首先請參照第一圖，該圖所類示爲根據本發明所 形成之導線架5〇〇，用以提供具有覆晶凸塊50之裸晶片4〇 暫時固定於其上，以方便對該晶片40進行測試。其中， 該導線架500包括了内引腳（inner lead)10及外引脚 (outer lead)l 5，且一黏著材料20形成於内引腳1〇之下。 其中’外引腳之區域爲自該導線架平面下凹一深度之區 域。以一較佳實施例而言，可使用膠帶（tape)作爲該黏 著材料20。其中該黏著材料20至少須足以覆蓋整個内引 本紙張尺度適用中國國家橾準（CNS ) A4说格（210X297公釐） ---------L 裝-- (請先’閲讀背命之注意事項再填寫本頁) ,π k 經濟部中央棣準局®;工消費合作社印裝 A7 B7五、發明説明（） 腳10區域，且該黏著材料20之作用在提供具有覆晶凸塊50 之晶片40组裝到内引脚10上時，無論在z方向共平面度 (plaranity)或者在XY方向的位移量皆能限制在一定的誤 差内。此外，一金屬層30形成於該導線架500之表面，其 中該金屬層30至少須覆蓋整個内引腳區域，且其熔點亦 低於位在晶片40上之覆晶凸塊50»接著，一媒介層35形 成於該金屬層30之上，以作爲覆晶凸塊50與内引脚10之 間的橋梁 在一較佳實施例中，上述之導線架500爲一金屬材 質導線架，且形成於導線架500表面之金屬層30可使用沾 錫性之金屬層，且該沾錫性的金屬層30至少須覆蓋整個 内引腳區域，至於其融點則須低於晶片40上的覆晶凸塊50 。一般而言該沾錫性金屬層30的組成，可爲含錫（sn)成 份之銲錫（solder) ◊至於形成於該金屬層30上之媒介廣35 則可使用助辞刻（flux)或錄膏（solder paste)。 接著，請參照第二圖，將晶片40連接於該導線架5〇〇 上。首先將晶片40組裝到内引脚10上使覆晶凸塊5〇與内 引脚10正確對位。如同上述，在該晶片40之覆晶凸塊5〇 與内引腳10接觸之部位，已事先形成媒介層35。其中， 値得注意的是當媒介物35爲助銲剤時，經高溫加熱後導 線架500表面之沾錫性的金屬層30會往覆晶凸塊5〇的表面 衆集，形成如第二圈中箭頭A所示之結構。相對地， 媒介層35爲錫膏（solder paste)時，經高溫加熱後不作導 本纸張又度適用中困國家揉準（CNS ) A4規格（210X297公羞〉 (請也閱讀背·面之注意事項再填寫本頁) 裝· ,π t. A7 B7 五、發明説明（） 線架表面沽錫性之金屬層30會產生熔解現象，所塗佈之 錫膏（solder paste)亦會融解，導致位於覆晶凸塊50四周 融解的錫胥因液態銲錫表面張力之作用往導線架500表面 流動，使最後覆晶凸塊50舆導線架500其内引脚20的連接 部份亦如第二圈中箭頭A所示之結構》至於媒介層35選 用助銲劑或者是錫膏的標準，則端視覆晶凸塊50其球高 之差異程度以及形成於導線架500表面之沾錫性金屬層30 而定，當鍍在導線架表面之沾錫性的金屬層30可以吸收 覆晶凸塊50球高的差異程度時，則媒介物35可選甩助銲 劑。否則，則可選用錫膏。 經濟部中央標準局貞工消费合作社印11 <請b閱讀背，面之注意事項再填寫本頁) 此外，由於本發明之主要目的在要求晶片能暫時 固定於導線架500之内引脚1 〇上，以方便進行測試。是以 在測試程序進行完畢後，最好能輕易的藉由加熱將晶片4〇 由導線架500的内引腳1〇上取下。所以，存在於覆晶凸塊 50與導線架内引脚1〇之間的沾錫性金屬層30，不可過多 以避免在將晶片40自該内引脚10上分離時，殘留在覆晶 凸塊50上的沾錫性的物質過多，而影響晶片4〇實際組裝 時的可靠度。相對的，該沾錫性金屬層30亦不可過少以 避免晶片40在測試時接點發生斷裂甚至晶片發生脱落。 至於形成於導線架500上之沾錫性金屬層30其厚度控制， 在一較佳之具體實施例中，可利用一般構裝廠之錫鉛電 鍍槽，纣該導線架5 00進行電鍍，便能在該導線架之表面 形成電鍍錫鉛（錫：80%/鉛：20%)。値得注意的是所形成之 沾錫性金屬層30可藉著控制其成份比例而調整該沾錫性 本纸張尺度逋用中國國家棣準< CNS > A4规格（210X297公釐） A7 B7 五、發明説明（) 金屬層之熔點，使其低於位在該晶片40上之覆晶凸塊5〇 〇This paper is adapted from 5 national standards (CNS), 8 4 threats (2l0 ^ 7 ^ T Μ B7) V. Description of the invention () Another object of the present invention is to provide a test device for providing the tested wafer and the Electrical connection interface of test equipment. A test device for carrying a chip includes a plurality of internal pins for providing the chip for electrical connection. The chip has a plurality of conductive bumps. In addition, A metal layer is formed on the surface of the inner pin to fix the chip to the plurality of inner pins, wherein the melting point of the metal layer is less than the melting point of the conductive bump. Then, an adhesive substance is attached to The lower surface of the plurality of inner pins is used to fix the plurality of inner pins. A carrier device is provided for connecting and carrying the plurality of inner pins, and the plurality of inner pins are provided as electrical connections. The medium layer further includes a dielectric layer on the metal layer as an interface between the plurality of conductive conductive bumps and the metal layer, wherein the melting point of the dielectric layer is smaller than the melting point of the conductive bump. In addition, the test device is more include A protection device is used to fix and protect the carrier device and components located on the carrier device. When the above-mentioned carrier device is placed in the protection device, the protection device can be placed on a heating platform for heating. When the temperature is higher than the melting point of the metal layer, the wafer under test can be detached from the plurality of inner pins. Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the notes on the back ^ * before filling in this In addition, the present invention also provides a method for testing a wafer for testing a bare wafer having conductive bumps. The method firstly connects the wafer to a lead frame by a heating process. The lead frame is used to carry the Chip, and has a plurality of internal pins to provide the chip electrical connection to the test paper size applicable to China National Standards (CNS) A4 grid (210X297 mm) A7 _______B7 5. Description of the invention () Trial setup. As for A tin-wet metal layer is formed on the plurality of inner pins, and the tin-wet metal layer is melted during the heating process, and the plurality of inner pins are melted. Electrical bumps are connected to the plurality of inner pins. Then, a test procedure is carried out to control the quality of the produced wafers by diluting the defective wafers. Finally, the soldering properties on the inner pins are made by the heating process. The metal is melted to separate the wafer and the lead frame, so that the wafer can be separated from the plurality of inner pins after the test. The m-type key sheet description can be easily understood through the following detailed description combined with the attached circle. The content and many advantages of this invention are as follows: The first picture shows a cross-sectional view of the structure of the lead frame provided according to the present invention. The second picture shows the wafer to be tested connected to the lead frame according to the present invention. A cross-sectional view of the structure. The third circle is a cross-sectional view and a top view of a carrier device provided according to the present invention. The fourth circle is a cross-sectional circle and a top view of another embodiment according to the present invention. The fifth figure shows the protective device provided by the present invention. The sixth circle shows the cross-sectional view of the carrier device placed on the retaining device according to the invention. The seventh figure shows the device according to the invention. The carrier device is placed in a protective package. 7 A7 B7 printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs. 5. Description of the invention. The eighth embodiment is a sectional view of heating the protection device according to the present invention to release the wafer from the lead frame. Detailed description of the invention: According to the method provided by the present invention, a bare chip 40 with flip chip bumps 50 is tested in a manner of being temporarily fixed to a lead frame 500, to be tested After the procedure is completed, the bare wafer 40 having the flip-chip bumps 50 is separated from the lead frame 500, so that the bare wafer 40 can be obtained by burn-in and test screening to obtain a wafer of good quality. In addition to the special design of the lead frame 500 which is easy to fix and remove the bare wafer 40 with flip-chip bumps 50, the appearance size after molding can also fit the existing test sockets, so that the burn- In) and various tests can be performed using existing test software and hardware to save additional development test costs and time. First, please refer to the first figure, which is shown as a lead frame 500 formed in accordance with the present invention to provide a bare wafer 40 with a flip-chip bump 50 temporarily fixed on it to facilitate the wafer. 40 for testing. The lead frame 500 includes an inner lead 10 and an outer lead 15, and an adhesive material 20 is formed below the inner lead 10. The region of the 'outer pin' is a region recessed to a depth from the plane of the lead frame. In a preferred embodiment, a tape can be used as the adhesive material 20. The adhesive material 20 must be at least enough to cover the entire internal citation. The paper size is applicable to China National Standards (CNS) A4 grid (210X297 mm) --------- L Pack-(Please read the back first Please fill out this page before ordering), π k Central Bureau of Standards, Ministry of Economic Affairs®; Industrial and Consumer Cooperatives printed A7 B7 V. Description of the invention () Foot 10 area, and the role of this adhesive material 20 is to provide When the wafer 40 of the block 50 is assembled on the inner lead 10, both the plaranity in the z direction and the displacement in the XY direction can be limited to a certain error. In addition, a metal layer 30 is formed on the surface of the lead frame 500. The metal layer 30 must cover at least the entire inner pin area, and its melting point is lower than the flip-chip bump 50 located on the wafer 40. Then, a The dielectric layer 35 is formed on the metal layer 30 to serve as a bridge between the flip-chip bump 50 and the inner pin 10. In a preferred embodiment, the above-mentioned lead frame 500 is a metal material lead frame and is formed. The metal layer 30 on the surface of the lead frame 500 can be a tin-wet metal layer, and the tin-wet metal layer 30 must cover at least the entire inner pin area, and its melting point must be lower than the flip-chip on the chip 40 Bump 50. Generally speaking, the composition of the tin-wettable metal layer 30 can be a solder containing tin (sn). As for the medium 35 formed on the metal layer 30, flux or recording paste can be used. (Solder paste). Next, referring to the second figure, the chip 40 is connected to the lead frame 500. First, the wafer 40 is assembled on the inner pin 10 so that the flip-chip bump 50 and the inner pin 10 are correctly aligned. As described above, the dielectric layer 35 has been formed in advance at the portion where the flip-chip bump 50 of the wafer 40 is in contact with the inner lead 10. Among them, it should be noted that when the medium 35 is a soldering flux, the tin-containing metal layer 30 on the surface of the lead frame 500 after being heated at a high temperature will be concentrated on the surface of the flip-chip bump 50, forming a second surface as shown in FIG. The structure shown by the arrow A in the circle. In contrast, when the medium layer 35 is a solder paste, the paper is not used as a guide after heating at high temperature, and it is suitable for medium and poor countries (CNS) A4 specification (210X297 public shame) (please also read Note: Please fill in this page again.) Installation, π t. A7 B7 V. Description of the invention () The tin-sold metal layer 30 on the surface of the wire frame will melt, and the applied solder paste will also melt. As a result, the tin tin melted around the flip chip bump 50 flows to the surface of the lead frame 500 due to the surface tension of the liquid solder, so that the last flip chip bump 50 and the connecting portion of the lead 20 in the lead frame 500 are also the second The structure shown by the arrow A in the circle "As for the standard of using the flux or solder paste for the dielectric layer 35, the degree of difference in ball height of the flip-chip bump 50 and the tin-wet metal layer formed on the surface of the lead frame 500 30. When the tin-plated metal layer 30 plated on the surface of the lead frame can absorb the difference in height of 50 bumps of the flip-chip bumps, the flux 35 may be used as a soldering flux. Otherwise, solder paste may be used. Printed by Zhengong Consumer Cooperative, Central Standards Bureau, Ministry of Economic Affairs 11 < Back, then fill the surface Notes page) Moreover, since the primary object of the present invention in the claims of the wafer can be temporarily fixed to the lead frame 500 within a square pin to facilitate testing. Therefore, after the test procedure is completed, it is best to easily remove the wafer 40 from the inner lead 10 of the lead frame 500 by heating. Therefore, the tin-containing metal layer 30 existing between the flip-chip bump 50 and the lead 10 in the lead frame should not be excessive to avoid remaining on the flip-chip bump when the wafer 40 is separated from the inner lead 10. There is too much tin-sticking substance on the block 50, which affects the reliability of the wafer 40 when it is actually assembled. In contrast, the tin-wettable metal layer 30 should not be too small to prevent the contacts of the wafer 40 from breaking or even the wafers falling off during the test. As for the thickness control of the tin-adhesive metal layer 30 formed on the lead frame 500, in a preferred embodiment, a tin-lead plating tank of a general assembly factory can be used, and the lead frame 500 can be electroplated. Electroplated tin-lead (tin: 80% / lead: 20%) was formed on the surface of the lead frame. It should be noted that the tin-wettable metal layer 30 formed can be adjusted by controlling the proportion of the tin-wetness. The paper size is in accordance with China's national standard < CNS > A4 (210X297mm) A7 B7 V. Description of the invention () The melting point of the metal layer is lower than the flip-chip bump 500 located on the wafer 40.
接著請參照第三圖，在完成上述固定晶片40於該 導線架500上之程序後’纣該導線架5〇〇進行切割分離之 程序’將第一圖中之外引脚15區域移除。然後，再將該 導線架500放置於載髖装置80之上，其中該載體装置80具 有凸出部份70，其中，該凸出部份70是設計用來滿足電 路測試装置之對位要求，亦即其需符合JEDEC之要求， 並可放入符合JEDEC之測試承接座中，是以該凸出部份7〇 的一項功能是幫助導線架與測試承接座作對位，該凸出 部份70爲選擇性元件’且任何具有相同功能的元件皆可 取代之，例如該對準元件70可設計爲任何形狀以滿足其 他形狀之測試裝置。是以藉著該凸出部份能夠使該載禮 装置80¾合現有自動化測試的軟硬體進行測試。在一具 體實施例中，該載體装置80之外觀尺寸的設計，可完全 使用tsop(II) 44-PIN測試的設備，其中包括承載的TRAY 經濟部中央榡準局貝工消费合作社印装 盤、全自動化吸嘴吸附的上料下料系統、批次測試承接 座（HIGH FIX SOCKET;即一次可進行32-64個元件測試的 承接座）等等，而不必额外投資改良測試流程中的任何硬 體設備。如此一來，測試具有覆晶凸塊50之晶片，便可 完全利用現有的測試環境及資源，以有效節省測試時間 及成本，並提高測試良率。 另外，參照第四圖，該圈所顯示爲根據本發明所 提供之另一實施例。其中針對那些具有更多輸入/輸出 本紙張尺度逍用中國國家樣準（CNS ) A4规格（210X297公釐〉Next, referring to the third figure, after completing the above procedure of fixing the wafer 40 on the lead frame 500, 'the lead frame 500 performs the cutting and separating process', the area of the pin 15 outside the first figure is removed. Then, the lead frame 500 is placed on the hip-carrying device 80, wherein the carrier device 80 has a protruding portion 70, wherein the protruding portion 70 is designed to meet the alignment requirements of the circuit testing device. That is, it must meet the requirements of JEDEC and can be placed in a test socket that complies with JEDEC. One of the functions of the protruding part 70 is to help the lead frame be aligned with the test socket. The protruding part 70 is a selective element 'and any element having the same function can be replaced. For example, the alignment element 70 can be designed into any shape to satisfy other shapes of testing devices. The test can be performed by using the protruding part to enable the gift-carrying device 802 to fit the existing automated testing hardware and software. In a specific embodiment, the external dimensions of the carrier device 80 are designed to fully use the tsop (II) 44-PIN test equipment, including the printed trays of the Tray Central Cooperative Bureau of the Ministry of Economic Affairs, the Bayong Consumer Cooperative, Fully automatic suction nozzle loading and unloading system, batch test socket (HIGH FIX SOCKET; that is, socket that can test 32-64 components at a time), etc., without having to invest extra to improve any hardware in the test process Body equipment. In this way, when testing wafers with flip-chip bumps 50, the existing test environment and resources can be fully utilized to effectively save test time and cost and improve test yield. In addition, referring to the fourth figure, this circle shows another embodiment provided according to the present invention. Which for those who have more input / output, this paper size uses the Chinese National Standard (CNS) A4 specification (210X297 mm>