JP2003297868A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the connection of a semiconductor chip having a bump electrode and a mounting board. <P>SOLUTION: A passivation film 21 and a polyimide resin film 22 for which a pad area PAD on top layer wiring M composed of Al formed above a semiconductor substrate 1 is opened are formed. A resist film R having an opening OA smaller than the pad area PAD is formed at the upper part of the polyimide resin film 22 including the PAD area PAD and an Ni film B1 whose film thickness is ≥3 μm is formed by electroless plating inside the opening OA. Further, an Au film B2 is formed by electroless plating, then the resist film R is removed, heat treatment is performed, and thus the bump electrode composed of the Ni film B1 and the Au film B2 is formed. In such a manner, since the bump electrode is formed thin and high, connection reliability at connecting the mounting board or the like via the bump electrode is improved. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly, to a semiconductor device having a bump electrode and a technique effectively applied to a manufacturing method thereof.

[0002]

2. Description of the Related Art Wire bonding (wi) for electrically connecting a bonding pad portion on the surface of an IC (Integrated Circuit) chip and a package lead with a gold wire or the like.
Wireless bonding has been put into practical use as a package that can be made smaller and thinner than rebonding).

In this wireless bonding, when an IC chip is mounted on a printed board or the like, a bonding wire such as a gold wire is not used, and the chip is bonded (bonding).
This is a mounting mode in which the protrusions (bumps) formed on the pad portion are connected.

Among them, CSP (chip size package) is a general term for packages that are the same size as or slightly larger than the size of a semiconductor chip, and 1) facilitates a large number of pins, and 2) allows a wide space between bump electrodes. And so on.

[0005] For example, "UBM bump formation by electroless plating, Kenzo Hatada" Electronic material May 1999, P38
-43 describes a semiconductor device in which a metal such as Ni and a metal of Au on the entire surface of the Al terminal of a semiconductor element are formed to form bumps, and solder is placed on the bumps. There is.

[0006] For example, “Bump forming technology by electric field plating, Motoaki Ishigami et al.” Electronic material May 1999, P
51-55 describe a semiconductor device using Au bumps.

[0007]

As described above, "UBM bump formation by electroless plating, Kenzo Hatada" Electronic material May 38, 1999, P38-43, the surface of the Al terminal of the semiconductor element, such as Ni Metal and Au on the whole surface
There is described a semiconductor device having a bump structure in which bumps made of the above metal are formed and solder is placed on the bumps.

The use of Ni or the like for this bump prevents Sn (tin) in the solder from reaching the Al interface due to melting or diffusion during high-temperature processing such as reflow and preventing the solder from peeling off at the Al interface. That is the main purpose.

The bump of Ni or the like in the above-mentioned document is formed larger than the Al opening (opening) (see, for example, the electric field plating method of FIG. 3 and FIG. 4). The reason for this is presumed to be the following three points. (1) To increase the connection reliability, to widen the connection area. (2) To prevent the solder from diffusing due to reflow or the like and contacting the underlying Al, misalignment in the formation of bumps such as Ni. This is considered to be because (3) the reliability of the solder connection portion is increased and a large solder can be placed in order to increase the solder connection height.

However, in this structure, the bump of Ni or the like is widened, and when the solder is mounted on the upper portion of the bump, the solder may further spread on the upper portion to form a spherical shape that covers the side wall of Ni or the like. Therefore, the gap between the bumps or the solder is narrowed, and defects such as a short circuit increase. Therefore, it is difficult to deal with a product having a narrow pitch.

Further, as described above, “Bump forming technology by electric field plating, Motoaki Ishigami et al.” Electronic material 1999
May 51, P51-55, a semiconductor device using Au bumps is described.

Au on the semiconductor device (semiconductor chip) side
The bumps are generally connected by, for example, pressure bonding or the like, facing the Au bumps on the mounting substrate side. The space between the semiconductor device and the mounting substrate is sealed with resin or the like.

In this document, Au on the semiconductor device side is used.
Although the shape of the bump is not touched, the forming method is the wire bump method, the Au bump by the plating process,
The entire surface of the Ni bump is covered with Au to form a bump. The wire bump method is a method in which a wire bump is formed on a pad of a terminal of a semiconductor device and is further connected to a terminal on a substrate through an anisotropic conductive film.

However, in this method, since the semiconductor device and the substrate are connected by the contact between the Au bump and the metal of the substrate terminal, the connection reliability is low. This is because the substrate, the anisotropic conductive film, and the semiconductor device are deformed due to the temperature change, so that the contact portion is disengaged and the Au bump is plastically deformed so that the contact cannot be achieved. this is,
The same applies to the method using Au bumps or the like.

An object of the present invention is to improve the reliability of the connection between a semiconductor device (semiconductor chip) having bump electrodes and a mounting substrate. Another object is to improve the characteristics of the semiconductor device and also improve the yield.

In particular, it is to improve the reliability of a semiconductor device having a terminal on a specific surface such as a flip chip or a CSP.

The above objects and novel features of the present invention will be apparent from the description of the present specification and the accompanying drawings.

[0018]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

(1) In the semiconductor device of the present invention, the wiring formed above the semiconductor chip and the wiring formed on the wiring,
A semiconductor device having an insulating film having an opening on the wiring and a bump electrode formed on the opening,
The bump electrode formation region is smaller than the exposed region of the wiring exposed from the opening.

This bump electrode is provided with a first metal film having a nickel (Ni), copper (Cu), titanium (Ti) or zinc (Zn) film, and gold (Au) on the first metal film.
And a second metal film having a palladium (Pd), silver (Ag), rhodium (Rh), or platinum (Pt) film. The bump electrodes may be covered with flux.

The height of the bump electrode may be 3 μm or more from the surface of the insulating film.

Further, the bump electrode may be composed of a metal film and a ball-shaped conductive portion above the metal film. This metal film is made of, for example, nickel (Ni), copper (C
u), a titanium (Ti) or zinc (Zn) film, and a gold (Au), palladium (Pd), silver (Ag), rhodium (Rh) or platinum (Pt) film on the first film. And a second film having a film. Further, the ball-shaped conductive portion may be, for example, a solder ball.

The bump electrodes of the semiconductor chip are
A sealing resin may be formed between the semiconductor chip and the mounting substrate, which is connected to the wiring formed on the mounting substrate.

(2) The semiconductor device manufacturing method of the present invention is
(A) a step of forming wiring above the semiconductor substrate,
(B) a step of forming an insulating film on the wiring, and (c)
Exposing the pad region of the wiring by selectively removing the insulating film on the wiring; and (d) a mask having an opening smaller than the pad region on the insulating film on the pad region. The method includes a step of forming a film and (e) a step of forming a bump electrode in the opening.

In the step (e), for example, a first metal film having a nickel (Ni), copper (Cu), titanium (Ti) or zinc (Zn) film is formed in the opening, and then, There is a step of forming a second metal film having a gold (Au), palladium (Pd), silver (Ag), rhodium (Rh) or platinum (Pt) film on the first metal film. The first metal film and the second metal film can be formed by a plating method. Further, when the electric field plating method is used, a step of previously forming a power feeding layer on the entire surface of the semiconductor substrate including the pad region is required.

The height of the bump electrode may be 3 μm or more from the surface of the insulating film.

Further, the step (e) includes, for example, a step of forming a metal film in the opening and a step of forming a ball-shaped conductive portion above the metal film. This metal film is, for example, a first film having a nickel (Ni), copper (Cu), titanium (Ti) or zinc (Zn) film, and gold (Au), palladium (P) on the first film.
d), silver (Ag), rhodium (Rh) or platinum (P
t) a second film having a film, and a second film having a film. Further, the ball-shaped conductive portion may be, for example, a solder ball.

In addition, after the step (e), a step of adhering the semiconductor chip onto the mounting substrate, in which the bump electrodes and the wiring on the mounting substrate face each other, is provided. Good. Further, the space between the semiconductor chip and the mounting substrate may be sealed with resin.

[0029]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.

(First Embodiment) A semiconductor device according to an embodiment of the present invention will be described according to its manufacturing method.

As shown in FIG. 1, a semiconductor substrate 1 on which an insulating film 11 made of a silicon oxide film and an uppermost layer wiring M are formed is prepared. In addition, in the insulating film 11, MISF
ET (Metal Insulator Semiconductor Field Effect T
Although a semiconductor element such as a ransistor), a plurality of wirings, elements and wirings or plugs for connecting the wirings, and the like are formed, their illustration is omitted. In addition, in the semiconductor substrate 1,
Although element isolation made of a silicon oxide film or the like is appropriately formed, its illustration is omitted.

The uppermost layer wiring M is, for example, the insulating film 11
It is formed by depositing an Al (aluminum) film as a conductive film thereon by, for example, a sputtering method and etching it into a desired shape. Here, the Al film is a film containing Al as a main component, and also includes an alloy film with another metal. A TiN film or the like may be formed above and below the Al film.

Then, as shown in FIG. 2, the uppermost layer wiring M
A silicon nitride film and a silicon oxide film as a protective film are sequentially deposited thereon by, for example, a CVD method to form a passivation film 21 composed of a laminated film of these films. The passivation film 21 may be composed of a single layer. Next, the passivation film 21 is removed by dry etching to expose the pad region PAD of the uppermost layer wiring M.

Next, a polyimide resin film 22 having an opening is formed on the passivation film 21.
To form this polyimide resin film 22, first, a photosensitive polyimide resin film is spin-coated and heat treatment (prebaking) is performed. Next, the polyimide resin film is exposed and developed to open on the pad region PAD, and then heat treatment (post-baking) is performed to cure (cure) the polyimide resin film. Note that the passivation film 21 may be dry-etched after the polyimide resin film 22 is opened.

Here, the pad region PAD is a part of the uppermost layer wiring M and is not covered with the passivation film 21 or the polyimide resin film 22 formed on the uppermost layer wiring M. The pad area PAD is, for example, 80
It is μm square.

Then, as shown in FIG.
A resist film (mask film) R having an opening OA is formed on the pad region PAD on the upper part of the polyimide resin film 22 including AD by photolithography.
The film thickness of the resist film R is, for example, about 5.5 μm. The opening (opening region) is 60 μm square.

Here, the opening (opening area) OA of the resist film R is made smaller than the pad area PAD.

Next, the pad area PAD (Al film surface)
After cleaning, the pad area PAD is activated using, for example, a palladium chloride solution in order to facilitate deposition of a plating film. Then, the semiconductor substrate 1 is immersed in a plating solution for Ni (nickel) to form a Ni film B1 in the opening OA. The plating of the Ni film B1 is so-called electroless plating. The film thickness of the Ni film B1 is, for example, about 5 μm from the surface of the polyimide resin film 22 (FIG. 4).
This is because the bump electrode needs to protrude more than the insulating film such as the polyimide resin film 22 that covers the outside of the pad region, and thus the surface of this film is used as a reference for the height of the Ni film B1 ( Hereinafter, the same applies to the height of B1 such as the Ni film).

Next, the semiconductor substrate 1 is immersed in a plating solution for Au (gold) to form an Au film B2 on the Ni film B1. The film thickness of the Au film B2 is, for example, 0.05 μm.
The degree is (Fig. 5). The plating of the Au film B2 is so-called electroless plating. The Au film B2 is a Ni film B
It is formed to prevent surface oxidation of the No. 1 and the like.

After that, the resist film R is removed and a heat treatment is performed, whereby the Ni film B1 and the Au film B above it are formed.
A bump (projection) electrode B of 2 is formed (FIG. 6).

As a result, the bump electrode B is formed on the pad area PAD. The formation area of the bump electrode B is
It is smaller than the pad area PAD. Here, the bump electrode B
The formation region of is a region defined by the maximum outer circumference of the bump electrode B.

Thereafter, the semiconductor substrate 1 in a wafer state is cut along the scribe lines existing between the chip regions,
A plurality of substantially rectangular chips are formed (diced).

Thereafter, the wiring and the bump electrode are adhered so that the wiring and the bump electrode are matched on a tape or a mounting substrate on which the wiring is printed,
It is sealed with resin as necessary, but these are not shown. Note that such an implementation mode will be described in detail in Embodiment 8.

According to this embodiment, the following (A)-
The effect of (E) is obtained.

(A) First, the formation area of the bump electrode B is
Since it is smaller than the pad area PAD, the following effects can be obtained.

1) The tip shape of the bump electrode can be uniformly flattened, and stable contact can be obtained with the mounting substrate or the like.

As described with reference to FIG. 2, the periphery of the pad area PAD is usually covered with an insulating film (passivation film 21 and polyimide resin film 22 in this embodiment) which defines the pad area. ing. In such a case, when a bump electrode made of the Ni film B1 or the like having a bottom surface wider than the pad region PAD is formed, the bottom surface of the Ni film or the like will hang on the insulating film. As a result, the shape is also reflected on the surface of the plating film forming the bump electrode such as the Ni film B1 and the Au film B2 thereabove, and the surface of the bump electrode becomes low on the pad region and high on the insulating film. Will end up. When the bump electrode having such a shape is pressed against the wiring (terminal) on the mounting substrate, the effective contact area is small and the connection reliability is deteriorated.

On the other hand, in the present embodiment, since the bump electrode is formed in the opening of the resist film having the opening smaller than the pad area PAD, the flatness of the bump electrode surface can be ensured. As a result, the adhesiveness between the bump electrode and the mounting substrate or the like can be improved, and the connection reliability can be improved.

The present effect can be obtained even when the formation area of the bump electrode B is the same as the pad area PAD.

2) It is possible to reduce the occurrence of peeling and voids (holes) at the interface between the bump electrode and the insulating film (in this embodiment, the passivation film 21 and the polyimide resin film 22).

That is, when a bump electrode made of the Ni film B1 or the like having a bottom surface wider than the pad area PAD is formed, the portion protruding from the pad area will hang over the insulating film. The adhesion between the metal such as the Ni film B1 and the resin or the inorganic insulating film is low. As a result, a gap is formed in this portion. This gap causes generation of voids and peeling. For example, bump electrodes and wiring (terminals) on the mounting board
After bonding and, the encapsulating resin is injected between them and cured to fix the space between the semiconductor chip (bump electrode) and the mounting substrate. In particular, in such a case, the molten resin is hard to enter into the gap portion and becomes a void. In addition, many sealing resins have moisture permeability, and depending on the environment of use, moisture or the like is absorbed, and the resin may accumulate in the voids and cause corrosion.

On the other hand, in the present embodiment, the formation area of the bump electrode B is made smaller than the pad area PAD, so that the bump electrode and the insulating film (in the case of the present embodiment, the passivation film 21 and It is possible to avoid contact with the polyimide resin film 22). As a result, it is possible to prevent peeling and voids (holes) that may occur at these interfaces. Therefore, the reliability of the semiconductor device can be improved.

It should be noted that the adhesiveness between the bump electrode and the insulating film can be improved by forming a conductive film having a high adhesiveness with the insulating film in advance under the bump electrode made of the Ni film B1 or the like. However, in this case, the number of manufacturing steps is increased.

When the bump electrode B is formed in the same area as the pad area PAD, the effect 1) can be obtained but the effect 2) cannot be obtained.
It is more preferable to make the formation area of the bump electrode B smaller than the pad area PAD.

3) The area where the bump electrodes are formed can be made small, and it becomes possible to deal with a semiconductor device having a fine pitch.

That is, in the present embodiment, since the bump electrode is formed in the opening of the resist film having the opening smaller than the pad area PAD, it is possible to form the fine bump electrode, and the fine pitch can be formed. Can easily be connected to.

4) Since the formation area of the bump electrode is made small (the bump electrode is made thin), the mounting allowable range is widened.

If the bump electrodes are thin, when the semiconductor chip is mounted with the bump electrodes and the wirings (terminals) of the mounting substrate aligned, the tolerance of the mounting position deviation becomes wide. That is, the maximum permissible deviation amount with respect to the normal mounting position on the mounting board is the end of the bump electrode and the mounting board side corresponding to the bump electrode adjacent to this bump electrode when the mounting board and the semiconductor chip are stacked. It is the shortest distance among the distances to the ends of the terminals. Therefore, if the semiconductor chip and the mounting substrate have the same terminal pitch, the thinner the bump electrode is, the larger the maximum allowable shift amount is. Further, if the bump electrodes are thin, the mounting substrate terminals are correspondingly small, and the pitch can be narrowed, so that the maximum allowable shift amount can be further increased.

As described above, according to this embodiment, even if the amount of displacement of the mounting position of the semiconductor chip is large, normal connection can be secured and mounting becomes easy. In addition, it becomes difficult to short-circuit even in the connection at a fine pitch.

5) Since the bump electrodes are thin and high, the life after mounting can be extended.

That is, by miniaturizing the bump electrode (reducing the width of the bump electrode and increasing the height relative to the width), the connection reliability when the semiconductor chip is pressure-bonded to a mounting board or the like is improved. To do. This is because if a bump electrode having a narrow (thin) width is used with respect to the height, even if a load due to heat, pressure, or the like is generated, the bump electrode is more likely to be deformed than the thick bump electrode and can be easily followed. It is thought to be because.

(B) Further, in this embodiment, N
The bump electrode was formed using the i film and the Au film, but Cu (copper), Ti (titanium), or Zn was used instead of the Ni film.
A material containing (zinc) as a main component may be used.

1) These materials (Ni, Cu, Ti, Z)
In n), deformation due to heat or the like can be easily dealt with, and connection with a mounting board or the like can be achieved with high accuracy.

That is, after the space between the mounting substrate and the mounting substrate is solidified with resin,
For example, when kept at a low temperature, the resin shrinks. For example, when the bump electrode is made of only a soft metal such as Au (gold) or Sn (tin) instead of the above material, Au
Etc. also contract and plastically deform, but it is difficult for these metals to return to their original shape. As a result, the connection reliability is reduced. On the other hand, when a hard metal such as W (tungsten) or Cr (chrome) is used, it is difficult to deform and it is difficult to absorb thermal strain, and as a result, the pad area and the terminal surface of the mounting board are not easily absorbed. At the interface, peeling easily occurs and the connection reliability decreases.

Therefore, within the range examined by the present inventors,
As a bump electrode material, Ni, Cu, Ti or Zn
It was possible to improve the connection reliability by using a material containing as a main component.

2) Further, these materials are base metals and have high adhesiveness between the semiconductor chip and the sealing resin filling the space between the mounting substrate and the mounting substrate. As a result, high reliability of connection can be achieved.

(C) Further, the Ni film is set to about 3 μm, and the like. 1) The height of the bump electrode is set to 3 μm or more, so that the connection between the mounting substrate and the semiconductor chip (bump electrode) can be improved. it can. 2) Further, by making the bottom area of the bump electrode small and further increasing the height to 3 μm or more, the bump electrode can be easily deformed due to thermal strain and the like, and the connection reliability can be improved.

(D) Further, since the Au film or the like is formed on the upper surface of the Ni film or the like forming the bump electrode, it is possible to 1) prevent the Ni film surface from being oxidized or contaminated. As a result, good electrical contact between the terminals of the mounting board and the bump electrodes can be achieved. Instead of the Au film, Pd (palladium), Ag (silver), Rh (rhodium) or Pt.
(Platinum) or the like can also be used. 2) Further, since the Au film or the like is formed only on the surface of the bump electrode, that is, the Au film or the like is not formed on the side wall of the Ni film, a sealing resin between the semiconductor chip and the mounting substrate is not formed. It is possible to improve the adhesion. This is because the adhesion between the noble metal surface such as Au and the sealing resin is generally low.
It is intended to increase the exposure of the Ni film or the like having high adhesiveness to improve the adhesiveness with the sealing resin. As a result, the connection reliability can be improved.

(E) Further, as described above, Au is used as a film formed on the upper surface of the Ni film or the like which constitutes the bump electrode.
Besides the film, a Pd, Ag, Rh or Pt film can be used. These materials (Au, Pd, Ag, Rh, P
In t), film formation by plating or the like is easy, and since it has low resistance, contact resistance can be reduced and good connection can be achieved in connection with terminals and the like of the mounting substrate.

The results of testing (evaluating) one aspect of the semiconductor device of this embodiment will be described below.

(Evaluation 1) The target product is an SRAM (Static
Random Access Memory). That is, in the insulating film 11 shown in FIG. 6, MISFETs forming SRAMs, elements for driving the MISFETs, and wirings (not shown) connecting these are formed. The outer shape of the chip is about 8 mm × 15 mm, and the number of pins is 119 pins (all are not shown). As shown in FIGS. 7 and 8, the pad areas PAD are formed in a line in the long side direction at the center of the chip. FIG. 7 is a top view of the semiconductor chip 1, and FIG.
FIG. 8 is a sectional view taken along line AA of FIG. 7. The average pitch between the pads is about 0.12 mm. The average pitch between the pads means the distance between the central portions of the pads.

Further, as shown in FIGS. 7 and 8, four dummy pads DPAD are formed at the corners of the chip, one dummy pad DPAD in total. This dummy pad DPAD
A bump electrode is also formed on the top. The dummy bump electrode plays a role of supporting the semiconductor chip so as to be mounted in parallel with the mounting substrate when connected to the mounting substrate or the like.

Pad area PAD and dummy pad DP
The shape (outer shape) of AD is 80 μm square, and the opening is 70 μm square. The insulating film around it is a silicon-based insulating film.

This SRAM (semiconductor chip) was mounted on a substrate for characteristic evaluation (hereinafter referred to as "evaluation substrate"), and various connection reliability was evaluated. FIG. 9 shows a top view (plan view) of the evaluation substrate.

A microcomputer chip (not shown) is mounted on this evaluation board, and the quality of the connection can be determined from the quality of the operation of the SRAM.

As shown in FIG. 9, the evaluation substrate T1 has SRAM mounting areas SA1 to SA4 in the central portion thereof, and a test corresponding to the bump electrodes (pad areas) of the SRAM is provided in the central portion of each mounting area. The terminal T3 is formed. Each test terminal T3 is composed of a contact area of 80 μm square and a wiring portion extending from the contact area to the outside.

For example, the wiring portion is made of Cu, and the contact region has a laminated structure (a film thickness of about 5 μm) of a Ni plating film and an Au plating film above it. In addition, SRAM
The wiring on the outside of the mounting areas SA1 to SA4 is covered with a resist film (not shown), but the SRAM mounting area is not covered with the resist film, and the contact area and a part of the wiring portion are It is exposed. In an actual mounting form, the SRAM and the mounting substrate are fixed with a sealing resin, and the contact area and the wiring portion are covered with the sealing resin.

Twenty of these evaluation substrates were prepared and S
Four RAMs are mounted. In the mounting method, the connection region of the evaluation substrate and the bump electrode of the SRAM are opposed to each other, a liquid adhesive is placed between them, and the temperature is raised to 180 ° C. while applying pressure to the evaluation substrate and the SRAM to bond them. On this occasion,
The bump electrode and the contact region of the evaluation substrate come into close contact with each other, and the adhesive between them is pushed out to the periphery. The remaining adhesive spreads around the semiconductor chip.

After confirming the initial characteristics of the SRAM using these evaluation substrates, 10 of the 20 evaluation substrates are
After the high temperature storage test at 125 ° C for 500 hours, the remaining 10
Each of the evaluation substrates was subjected to a temperature cycle test of -55 ° C and 125 ° C for 1000 cycles. As a result, it was confirmed that no abnormal operation occurred in any of the samples.

(Evaluation 2) DRAM (Dynamic Random Acc
The same evaluation was performed for ess Memory). In this case, the outer shape of the chip is 15 mm × 8 mm,
58 terminals are formed at a pitch of 0.22 mm. The pad has a width of 0.14 mm on the Al surface and 0.1 at the opening.
It has a width of 0 mm.

The thickness of the resist film is 5.5 μm and the width of the opening is about 0.095 mm. Ni film 5 in the opening
The film was formed by electroplating to a thickness of approximately μm, and a Pd film having a thickness of approximately 0.5 μm was further deposited thereon by electroless plating.

After the initial characteristics of the DRAM were confirmed by using the evaluation substrates mounted with these as in Evaluation 1, 25 of the 50 evaluation substrates were subjected to a high temperature storage test at 125 ° C. for 500 hours. The remaining 25 evaluation substrates were subjected to a temperature cycle test of −55 ° C. and 125 ° C. for 1000 cycles. As a result, it was confirmed that no abnormal operation occurred in any of the samples.

(Second Embodiment) In the first embodiment, the bump electrode B is directly formed on the uppermost layer wiring M made of an Al film.
However, the pad area PAD on the uppermost layer wiring may be routed by using rewiring, and the bump electrode may be formed on the pad area PAD. The steps up to the pad area PAD forming step on the uppermost layer wiring M are the same as those in the first embodiment described with reference to FIGS. 1 and 2, and therefore description thereof will be omitted.

That is, as shown in FIG. 10, the uppermost layer wiring M
A polyimide resin film 22 and a passivation film 21 are formed on the top. These films have openings and the uppermost layer wiring M is exposed. Here, the exposed region of the uppermost layer wiring M is referred to as a first pad portion PAD1.

Next, a seed layer (power feeding layer) 45 is formed on the polyimide resin film 22 including the first pad portion PAD1.
To form. The seed layer 45 is made of, for example, a laminated film of a Cr (chrome) film and a Cu (copper) film. For example, a Cr film is deposited on the polyimide resin film 22 by a sputtering method, and then the Cr film is formed. It is formed by depositing a Cu film on the upper portion by a sputtering method.

Next, a resist film R2 having a long groove 47 extending from an upper portion of the first pad portion PAD1 to a second pad portion PAD2 forming region described later is formed on the seed layer 45 by using a photolithography technique. .

Next, C is formed inside the long groove 47 by electrolytic plating.
The u film 49a is formed. To form the Cu film 49a,
The substrate 1 is dipped in a Cu plating solution to fix the seed layer 45 to the negative (-) electrode, and the Cu film 4 is formed on the surface of the seed layer 45 at the bottom of the long groove 47 not covered with the resist film R2.
9a is deposited.

Further, thereafter, a Ni (nickel) film 49b is formed on the Cu film 49a inside the long groove 47 by the electroplating method. To form the Ni film 49b, the substrate 1 is made of Ni.
The seed layer 45 with a minus (-)
Long groove 47 fixed to the electrode and not covered with the resist film R
A Ni film 49b is deposited on the surface of the Cu film 49a at the bottom of the.

Then, after removing the resist film R2, C
The unnecessary seed layer 45 is removed by wet etching using the u film 49a and the Ni film 49b as a mask. As a result, the rewiring 49 composed of the seed layer 45, the laminated film of the Cu film 49a and the Ni film 49b is formed.

This rewiring, for example, when arranging the bump electrodes at a wider interval than the first pad portion PAD1 over the entire surface of the chip area, the first pad portion PAD1 and the bump electrodes (second pad portion PAD2 described later) are arranged. Play a role in connecting.

Next, the second pad portion PAD on the rewiring 49
A polyimide resin film 51 having openings 2 is formed. As the polyimide resin film 51, a photosensitive polyimide resin film is spin-coated and heat treatment (prebaking) is performed. Next, the polyimide resin film is exposed and developed to develop the second pad portion PAD2.
After opening (diameter 0.25 mm), heat treatment (post-baking) is performed to cure (cure) the polyimide resin film.

Here, the surface of the rewiring 49 (Ni film 49b) is exposed from the opening (second pad portion PAD2) of the polyimide resin film 51.

Next, as shown in FIG. 12, the bump electrode B is formed on the Ni film 49b exposed in the opening (second pad portion PAD2) of the polyimide resin film 51. A seed layer (power feeding layer) 55 is formed on the polyimide resin film 51 including the pad portion PAD2. The seed layer 55 is made of, for example, a laminated film of a Cr (chrome) film and a Cu (copper) film. For example, a Cr film is deposited on the polyimide resin film 51 by a sputtering method, and then the Cr film is formed. Cu on top by sputtering
It is formed by depositing a film.

Next, the second pad area PA is formed on the seed layer (power feeding layer) 55 by photolithography.
A resist film R3 (having a film thickness of about 11 μm) having an opening (OA, diameter 0.23 mm) is formed on D2. Here, the opening (opening region) OA of the resist film R3 is changed to the second
It is made smaller than the pad area PAD2.

Next, a Ni (nickel) film B1 is formed on the seed layer 55 in the opening OA by electroplating to a thickness of about 8 μm. To form the Ni film B1, the substrate 1 is dipped in a plating solution for Ni to fix the seed layer 55 to the minus (−) electrode, and the opening O not covered with the resist film R3 is formed.
The Ni film B1 is deposited on the surface of the seed layer 55 at the bottom of A. Next, the semiconductor substrate 1 is immersed in a plating solution for Au (gold) to fix the seed layer 55 to the negative (-) electrode, and the Ni of the opening OA not covered with the resist film R3.
An Au film B2 of about 1 μm is deposited on the film B1.

After that, the resist film R3 is removed, the unnecessary seed layer 55 is removed by wet etching using the Ni film B1 and the Au film B2 as a mask, and heat treatment is performed to remove the Ni film B1 and the upper portion thereof. A bump (projection) electrode B made of the Au film B2 is formed (FIG. 13).
That is, the bump electrode B is formed on the second pad area PAD2. The formation area of the bump electrode B is smaller than the second pad area PAD2.

Thereafter, as in the first embodiment, the semiconductor substrate 1 in a wafer state is cut along the scribe lines existing between the chip regions to form a plurality of substantially rectangular chips (dicing).

After that, the wiring and the bump electrodes are attached to the tape or the mounting substrate on which the wiring is printed so that the wiring and the bump electrodes are aligned with each other.
It is sealed with resin as necessary, but these are not shown.

As described above, according to the present embodiment, since the formation area of the bump electrode B is made smaller than the second pad area PAD2, the structure similar to that of the first embodiment is obtained.
The effects (A) to (E) described in the first embodiment can be obtained. Further, by using the rewiring, the pitch of the bump electrodes can be made wider than that of the first pad region.

The results of testing (evaluating) one aspect of the semiconductor device of this embodiment will be described below.

(Evaluation 1) The target product is a microcomputer.
That is, in the insulating film 11 shown in FIG. 13, elements and wirings (not shown) that form a microcomputer are formed. Figure 1
4 is a top view of this microcomputer (semiconductor chip), FIG.
FIG. 15 is a B1-B1 sectional view of FIG. 14;

The outer shape of the chip is about 10 mm square. For example, a first pad area (not shown) is formed around the chip, and the pad area is routed by the above-mentioned rewiring and area-arrayed inside the chip. Area-padded second pad area PAD2
The diameter of the opening is 0.25 mm, and the bump electrode B is formed on the upper portion thereof. Pin arrangement is 16 rows x 1
In 6 rows, the number of pins is 256, and the average pitch between pads is about 0.5 mm. A semiconductor chip having such a pin arrangement is often used for CSP.

This microcomputer (semiconductor chip) was mounted on an evaluation board (not shown) and various connection reliability was evaluated. This evaluation substrate is an organic substrate and has one microcomputer mounting area. In the mounting area, test terminals (diameter 0.25 mm, corresponding to bump electrodes of the microcomputer,
0.5 mm pitch, 256 pieces) are formed. Similar to the first embodiment (see FIG. 9), this terminal is pulled out to the outside and a part thereof is exposed.

Fifty evaluation boards are prepared, and one microcomputer is mounted on each of the evaluation boards. The mounting method is the same as in the first embodiment.

After confirming the initial characteristics of the microcomputer using these evaluation boards, 25 of the 50 evaluation boards were
The high temperature storage test at 125 ° C for 500 hours was performed for the remaining 25 hours.
Each of the evaluation substrates was subjected to a temperature cycle test of −55 ° C. and 125 ° C. for 1000 cycles. As a result, it was confirmed that no abnormal operation occurred in any of the samples.

(Evaluation 2) In Evaluation 1, the resist film R3 has a film thickness of 11 μm and the Ni film has a film thickness of 8 μm. However, the resist film R3 has a film thickness of 8 μm and the Ni film has a film thickness of 1.
The same evaluation was performed when the thickness was 5 μm, 3 μm or 5 μm. The thickness of the Au film on the Ni film is
All were 1 μm.

After confirming the initial characteristics of the microcomputer using the evaluation boards equipped with these, 25 out of 50 evaluation boards were subjected to a high temperature storage test at 125 ° C. for 500 hours. There was no malfunction in the film thickness. However, the remaining 25 evaluation substrates were subjected to a temperature cycle test of -55 ° C and 125 ° C, respectively.
After 0 cycles, the Ni film thickness was 1.5 μm.
It was confirmed that the resistance increasing defect was found in 4 out of 25 evaluation substrates having the above-mentioned ones mounted thereon. However, the Ni film thickness is 3
It was confirmed that no abnormal operation occurred with respect to the evaluation substrates mounted with μm and 5 μm.

(Evaluation 3) In this evaluation, the same evaluation was performed for the resist film R3 having a film thickness of 16 μm, the Ni film having a film thickness of 13 μm, and the Au film having a film thickness of 1 μm.

After confirming the initial characteristics of the microcomputer using 50 evaluation substrates, 25 of the 50 evaluation substrates are set to 1
A high temperature storage test was performed at 25 ° C. for 500 hours, and the remaining 25 evaluation substrates were subjected to temperature cycle tests of −55 ° C. and 125 ° C. for 1000 cycles. As a result, it was confirmed that no abnormal operation occurred in any of the samples.

(Third Embodiment) In the above-mentioned embodiment, the bump electrode B is composed of the Ni film B1 and the Au film B2, but a solder ball HB may be further formed on the bump electrode B.

The steps up to the step of forming the laminated film of the Ni film B1 and the Au film B2 are the same as those in the above-described embodiment described with reference to FIGS. 1 to 6 and 10 to 13. , The description is omitted. In this embodiment, the thickness of the Ni film B1 is about 5 μm and the thickness of the Au film B2 is about 0.05 μm. At this time, the semiconductor substrate is in a wafer state. That is, the solder balls HB are formed in a wafer state (before dicing). Although the process of forming the solder ball HB on the bump electrode B shown in FIG. 6 will be described here, the solder ball HB can be similarly formed on the bump electrode B shown in FIG. it can.

For example, as shown in FIG. 16, a glass substrate 61 having a solder paste 63 formed thereon is prepared. The solder paste 63 can be formed, for example, by printing on the glass substrate 61 using a metal mask. The printing position of the solder paste corresponds to the bump electrode B when the bump electrode B on the semiconductor chip shown in FIG. 6 is mounted face down on the glass substrate 61. For example, with a pitch of 0.5 mm, 1
It is arranged in 6 rows × 16 columns.

Then, as shown in FIG. 17, the solder paste 63 on the glass substrate 61 and the Au film B2 are aligned, and the semiconductor wafer (1) is mounted. At this time, Au
The film B2 and the solder paste 63 are in contact with each other.

Then, with the back surface of the semiconductor wafer facing upward, the semiconductor wafer was carried into a reflow furnace and subjected to heat treatment. As a result, the solder paste 63 becomes a ball shape and adheres to the Ni film B1 (FIG. 18). The Au film B2 melts inside the solder ball HB.

Next, the glass substrate 61 is separated from the semiconductor wafer, and the glass substrate 61 and the semiconductor wafer are washed (FIG. 19). At this time, the flux contained in the solder paste and exposed on the surface of the solder ball HB during heat treatment is removed. Solder ball height is 0.2mm
It is a degree.

As described above, according to the present embodiment, the Ni film and the Au film (hereinafter, these laminated films are referred to as the first bump electrodes) are formed as in the first and second embodiments.
The various effects described in the first embodiment can be obtained.

That is, (A) First, since the formation area of the bump electrode B is made smaller than the pad area PAD, 2) the bump electrode and the insulating film (of the present embodiment) described in detail in the first embodiment. In this case, peeling at the interface with the passivation film 21 and the polyimide resin film 22) and the occurrence of voids (holes) can be reduced. 3) The bump electrode formation region can be made small and its pitch can be made fine. 4) The bump electrode formation area is small (the bump electrode is thin), so the mounting allowable range is wide. 5) The bump electrode is thin and high, resulting in a long life after mounting. It is possible to obtain effects such as being able to lengthen.

Also, as in the first embodiment, (B) Ni
Cu (copper), Ti (titanium) or Zn instead of the film
A material containing (zinc) as a main component can be used, and 1)
By using these materials (Ni, Cu, Ti, Zu), the connection with the mounting board or the like can be achieved accurately. 2) Further, by using these materials, the adhesiveness between the semiconductor chip and the sealing resin filling the space between the semiconductor chip and the mounting substrate can be improved, and as a result, high reliability of connection can be achieved.

Furthermore, 3) these materials have a high barrier property against solder, and Sn or the like in the solder may reach the interface with Al (uppermost layer wiring) even if the solder ball on the upper part is reflowed. Can be prevented.

Further, (C) the Ni film has a thickness of about 3 μm, and 1) the height of the bump electrode is 3 μm or more, so that the connection between the mounting substrate and the semiconductor chip (bump electrode) can be improved. it can. 2) Further, by making the bottom area of the bump electrode small and further increasing the height to 3 μm or more, the bump electrode can be easily deformed due to thermal strain and the like, and the connection reliability can be improved.

Furthermore, 3) when connecting to the mounting substrate via solder balls, the connection reliability can be ensured by ensuring the solder barrier property of the first bump electrodes (Ni film or the like). That is, when the solder balls are connected to the upper surface of the first bump electrodes (Ni film or the like) by reflowing the solder, and this semiconductor chip is mounted on the mounting substrate with solder, the reflow process may be performed depending on the case. The Sn in the solder ball can thermally diffuse in the first bump electrode even when the semiconductor chip is repaired and re-reflow mounting is performed, or even under the actual use environment of the mounting substrate. However, by setting the height of the first bump electrode to 3 μm or more, it is possible to prevent Sn from reaching the underlying pad such as Al (uppermost layer wiring) on the lower surface of the first bump electrode. As a result, the connection reliability can be improved.

Further, in the present embodiment, since the Au film is formed on the surface of the Ni film, the first bump electrode (Ni
Solder balls can be accurately formed on the upper part of a film or the like). That is, not only on the surface of the Ni film but also on the side wall thereof, Au is formed.
When the film is formed, solder balls are formed so as to cover the side walls, and it becomes impossible to secure the height of the first bump electrodes and the solder balls above them. However, in the present embodiment, since the Au film is formed on the surface of the Ni film, the solder balls can be formed with high accuracy, and the heights of the first bump electrode and the solder balls above it can be secured. can do.

For example, when the Au film or the like is formed on the upper surface of Ni or the like, if the adhesion between the resist film for plating and the bump of Ni or the like is not good, the A or even the upper surface of the bump of Ni or the like is
The u film adheres. In such a case, when the solder bump is formed, the solder ball is attached so as to cover the upper surface thereof. However, if the solder is not attached over the height of 2 μm or more of Ni or the like, there is a problem due to thermal diffusion of the solder during heating such as reflow. I'm sure it's not.

Further, (D) since the Au film or the like is formed on the upper surface of the Ni film or the like forming the bump electrode, it is possible to 1) prevent the Ni film surface from being oxidized or contaminated. As a result, good electrical contact between the terminals of the mounting board and the bump electrodes can be achieved. Instead of the Au film, Pd (palladium), Ag (silver), Rh (rhodium) or Pt.
(Platinum) or the like can also be used.

2) In the present embodiment, N
Since the Au film was formed on the surface of the i film, the side surface of the Ni film,
It is possible to prevent the solder from spreading wet to at least the lower portion of the side surface (Al side). Further, the solder ball formed on the upper surface of the first bump electrode or the solder mounted on the mounting substrate connects only on the upper surface of the first bump electrode.
Therefore, the height of the solder balls can be increased for a certain amount of solder, and the connection reliability after mounting can be increased.

Also, 3) the solder ball is first mounted after mounting.
When the solder adheres to the lower part of the side surface of the bump electrode, the solder will propagate along the side surface of the first bump electrode A depending on the temperature environment thereafter.
Thermal diffusion to the l interface. As a result, the first bump electrode is A
It becomes easy to peel from the l-pad. However, in the present embodiment, these phenomena can be prevented by the solder ball covering only the upper surface of the first bump electrode or only the upper surface and the upper side surface.

4) Only on the upper surface of the first bump electrode,
When the solder gets wet, the outer shapes (maximum outer circumference) of the first bump electrodes and the solder balls become smaller than when the solder gets wet to the side surfaces of the first bump electrodes. Therefore,
At the time of mounting, it is possible to reduce the rate of occurrence of a short circuit with an adjacent bump electrode or the like. As a result, even in the case of a fine pitch, the connection becomes easy.

5) When the resin is filled between the semiconductor chip and the mounting substrate, the generation of voids in the resin is reduced, and as a result, the connection reliability is improved. This is because when the side surface of the Ni film is covered with the Au film or the like, the solder also wets the side surface, and a solder ball is formed so as to cover the side surface. As a result, the gap with the underlying Al film or insulating film becomes very narrow. In particular, when soldering with flux or the like, the flux in the gap is difficult to remove even by washing, and the flux remains. Further, even if the flux is removed by cleaning, it is difficult to fill the sealing resin in the narrow gap and a void is formed. Thus, due to the residual flux and the generation of voids, the connection reliability is reduced. However, in the present embodiment, the side surface of the first bump electrode such as the Ni film, at least,
Since no coating such as Au film is formed on the upper side surface,
A narrow gap or the like does not occur under the first bump electrode, and the connection reliability can be kept high.

6) The adhesion between the side surface of the first bump electrode and the resin is secured, and the connection reliability is improved. Upon customer mounting, it is often attempted to fill a resin between a semiconductor chip and a mounting board to improve connection reliability against thermal stress and the like. In this case, it is necessary that the resin has high adhesion to the mounting substrate and the semiconductor chip. In this case, if the noble metal surface such as the Au film remains on the side surface of the first bump electrode, the adhesion with the epoxy resin, which is a general sealing resin, is poor and it is difficult to adhere. Therefore, if the side surface of the first bump electrode is made of a Ni film, a Cu film, or the like, surface oxidation is promoted by heating during mounting and the like, and good adhesion between the side surface of the first bump electrode and the resin can be secured. . As a result, the connection reliability is improved.

Further, (E) in the present embodiment,
Since the Au film or the like is formed on the upper surface of the Ni film or the like forming the bump electrode, the following effects are obtained. As mentioned above, A
Instead of the u film, Pd (palladium), Ag (silver), R
It is also possible to use h (rhodium) or Pt (platinum).

That is, these metals can be easily formed by plating or the like, and a low resistance connection can be obtained in the electrical connection with the solder balls.

A flux may be formed instead of these metals. For example, by forming a Ni film and then forming a flux film on the Ni film, oxidation of the upper surface of the first bump electrode such as the Ni film can be prevented, and the solder oxide film can be removed by the flux. A low resistance connection can be obtained in the electrical connection between the and the first bump electrode.

Further, (F) in the present embodiment,
Since the solder balls (second bump electrodes) are formed on the first bump electrodes, the following effects are obtained.

For example, when connecting a semiconductor chip to a mounting substrate via a solder ball, solder is formed on the mounting substrate side by a printing method, bump electrodes of the semiconductor chip are made to face it, and reflowing is performed for connection. There is a way to do it. However, as the terminal pitch of the semiconductor chip becomes finer, it becomes difficult to supply solder with a fine pitch onto the mounting substrate by the printing method. Conversely, it is necessary to prepare a fine-pitch print mask and a high-precision printing machine. In such a case, if solder balls are formed on the semiconductor chip side, it is not necessary to print solder on the mounting substrate side. For example, it is possible to simply print the flux on the top surface of the mounting board, or to soak the solder balls of the semiconductor chip in the flux, mount it directly on the mounting board, and then reflow it. become.

The results of testing (evaluating) one aspect of the semiconductor device of this embodiment will be described below.

(Evaluation 1) The target product is a solder ball (98.5Sn-1Ag-0.5C) on the Ni film (height 5 μm) shown in FIGS. 14 and 15 of the second embodiment.
u) is the formed microcomputer. 20 is a top view of this microcomputer (semiconductor chip), and FIG. 21 is C of FIG.
FIG. The outer shape of the chip is about 10 mm square.

This microcomputer (semiconductor chip) was mounted on an evaluation board (not shown), and various connection reliability was evaluated. This evaluation substrate is an organic substrate and has one microcomputer mounting area. In the mounting area, test terminals (diameter 0.25 mm, corresponding to bump electrodes of the microcomputer,
0.5 mm pitch, 256 pieces) are formed. Similar to the first embodiment (see FIG. 9), this terminal is pulled out to the outside and a part thereof is exposed.

Fifty evaluation substrates are prepared, and one microcomputer is mounted on each of the evaluation substrates. The mounting method will be described below. Non-cleaning flux is previously formed on the terminals of the evaluation substrate by a printing method. This terminal and the terminal of the microcomputer to be evaluated are aligned and mounted so as to face each other. After that, reflow at about 240 ℃,
Resin is filled between the evaluation board and the microcomputer, and the temperature is 150 ° C.
To cure.

After confirming the initial characteristics of the microcomputer using these evaluation boards, 25 of the 50 evaluation boards were
The high temperature storage test at 125 ° C for 500 hours was performed for the remaining 25 hours.
Each of the evaluation substrates was subjected to a temperature cycle test of −55 ° C. and 125 ° C. for 1000 cycles. As a result, it was confirmed that no abnormal operation occurred in any of the samples.

(Evaluation 2) In Evaluation 1, the thickness of the Ni film was set to 5
However, the same evaluation was performed when the thickness of the Ni film was 3 μm.

After confirming the initial characteristics of the microcomputer using the evaluation boards on which these are mounted, 2 out of 50 evaluation boards are used.
Five of them were subjected to a high temperature storage test at 125 ° C. for 500 hours, and the remaining 25 evaluation substrates were subjected to a temperature cycle test of −55 ° C. and 125 ° C. for 1000 cycles. As a result, it was confirmed that no abnormal operation occurred in any of the samples.

(Embodiment 4) In Embodiment 1, electroless plating is used to form the Ni film and the A film forming the bump electrode.
Although the u film is formed, these may be formed by using the electroplating method. It should be noted that the method of forming the bump electrode using the electric field plating method is the same as that in the second embodiment with reference to FIGS.
Since it is the same as the method described with reference to FIG. 3, detailed description thereof will be omitted.

According to this embodiment, the effects (A) to (E) can be obtained as in the first embodiment.

The results of testing (evaluating) one aspect of the semiconductor device of this embodiment will be described below.

(Evaluation 1) The target product is an ASIC (Applic
ation specific IC). That is, in the insulating film on the semiconductor substrate, elements and wirings (not shown) that form the ASIC are formed. 22 is a top view of this ASIC (semiconductor chip), and FIG. 23 is a sectional view taken along line DD of FIG.

The outer shape of the chip is about 5 mm square,
The number of terminals is 196 and the minimum is 0.08 on the periphery of the chip.
The terminals are lined up at mm pitch. The shape (outer shape) of the pad PAD is 50 μm width (short side), and its opening is 4
The width is 5 μm (short side).

The seed layer is a Ti film having a thickness of about 0.05 μm, and the thickness of the resist film on the seed layer after baking is 7 μm.
The opening was 40 μm square. A Ti film was deposited in this opening by electroplating to a thickness of about 5 μm, and an Au film was further deposited thereon to a thickness of about 1 μm to form bump electrodes B. Therefore, a 40 μm square Ti film of 5 μm and 1
The bump electrode B having an Au film of μm is formed.

This microcomputer (semiconductor chip) was mounted on an evaluation board (not shown), and various connection reliability was evaluated. This evaluation substrate has one ASIC mounting area, and test terminals (50 μm square) corresponding to the bump electrodes of the ASIC are formed in the mounting area. Similar to the first embodiment (see FIG. 9), this terminal is pulled out to the outside and a part thereof is exposed. Fifty evaluation substrates are prepared, and one ASIC is mounted on each. The mounting method is the same as in the first embodiment.

After confirming the initial characteristics of the ASIC using these evaluation substrates, 25 of the 50 evaluation substrates were
The high temperature storage test at 125 ° C for 500 hours was performed for the remaining 25 hours.
Each of the evaluation substrates was subjected to a temperature cycle test of −55 ° C. and 125 ° C. for 1000 cycles. As a result, it was confirmed that no abnormal operation occurred in any of the samples.

(Evaluation 2) In Evaluation 1, the Ti film was formed by electroplating to a thickness of about 5 μm.
It is formed by electrolytic plating with a thickness of about μm, and further on top of it,
The evaluation was performed on a film having an Au film with a thickness of about 1 μm and a film having a Pt film (1 μm) formed on a Cu film (5 μm).

Using the evaluation board on which these are mounted, the AS
After checking the initial characteristics of the IC, 2 out of 50 evaluation boards
Five of them were subjected to a high temperature storage test at 125 ° C. for 500 hours, and the remaining 25 evaluation substrates were subjected to a temperature cycle test of −55 ° C. and 125 ° C. for 1000 cycles. As a result, it was confirmed that no abnormal operation occurred in any of the samples.

(Embodiment 5) Evaluations were made on the ASIC bump electrodes on which solder balls were mounted and the bumps on which flux was formed as described in the fourth embodiment. The method of forming the solder ball is
Since the third embodiment has been described with reference to FIGS. 16 to 19, detailed description thereof will be omitted.

(Evaluation) The target product is the one shown in FIG.
2 and the ASIC shown in FIG. 23 (chip outline: approximately 5 mm
The number of terminals is 196).

Two ASIC wafers were obtained, and a Ti film was formed as a seed layer on the circuit surface. A resist film having an opening of 40 μm square is formed on top of it. The resist film thickness after baking is about 12 μm. A Ni film is deposited in this opening by electroplating to a thickness of about 10 μm. After removing the resist film, the Ti film is etched.

These two wafers were mounted on a sheet containing an alkaline processing liquid, and the oxide film at the tip of the Ni film was removed. Next, one wafer is mounted on a glass substrate on which 63Sn-37Pb solder paste is printed, and the solder paste is attached to the surface of each terminal of the wafer. This is passed through the reflow furnace and 63Sn is put on the terminals.
Shape a -37Pb solder bump. On the other hand, after removing the oxide film on the surface of the Ni film, another wafer is mounted on a glass substrate on which the liquid flux is printed, and the flux is attached to the surface of each terminal. By drying this,
Form a flux coating on the terminals. Further, these two wafers are diced into semiconductor chips.

These two types of ASIC semiconductor devices were mounted on an evaluation board and various connection reliability evaluations were carried out.
As the evaluation substrate, the same substrate as used in the fourth embodiment was used. 63Sn is pre-installed on the terminal of the evaluation board.
-37Pb solder paste was printed, and the semiconductor chip was mounted face down on it. This was passed through a reflow furnace having a maximum temperature of about 230 ° C. to connect the semiconductor chip and the evaluation substrate. Then, the flux in the solder was removed by washing, resin was injected between the evaluation substrate and the semiconductor chip, and this was baked at 180 ° C.

Using the evaluation board on which these are mounted, the AS
After checking the initial characteristics of the IC, 2 out of 50 evaluation boards
Five of them were subjected to a high temperature storage test at 125 ° C. for 500 hours, and the remaining 25 evaluation substrates were subjected to a temperature cycle test of −55 ° C. and 125 ° C. for 1000 cycles. As a result, it was confirmed that no abnormal operation occurred in any of the samples (the upper part has solder balls and flux).

(Embodiment 6) The bump electrodes of the ASIC described in Embodiment 5 are laid out by rewiring to form an area arrangement (14 columns × 14 rows, 0.3 mm pitch), and solder balls are formed. Good. The rewiring and the solder ball forming method are the same as those in the second embodiment.
10 and FIG. 11 and FIG. 16 to FIG. 1 of the third embodiment.
Since the description has been made with reference to FIG. 9, detailed description thereof will be omitted.

(Evaluation 1) The target product is an ASIC (chip outer shape: about 5 m) shown in FIGS. 22 and 23 of the fourth embodiment.
Although it is m square and the number of terminals is 196), the terminals are arranged in an area by rewiring. Figure 24 shows this ASIC
FIG. 25 is a top view of the (semiconductor chip), and FIG.
FIG.

The rewiring material is a laminated film of Cr / Cu / Cr, and the insulating layer above it is a polyimide resin film.
The rewiring layer has two layers, and the terminals of the area array are composed of a Cr film and a Cu film above the Cr film. The periphery of this terminal is covered with a polyimide resin film, and the diameter of the terminal opening is 0.15 mm.

C is used as a seed layer on the polyimide resin film.
An r film is formed, and a resist film having an opening with a diameter of 0.11 mm is formed on the r film. Resist film thickness is 8μ
m. The Ti film is electroplated up to about 5 μm from the upper surface of the peripheral polyimide resin film, and further the Au film is electroplated on the upper part thereof by about 1 μm. After that, the resist film is removed, the Cr film is etched, and then a solder ball is formed on the Ni film. This solder ball is performed using the glass plate on which the solder paste is printed, as described in the second embodiment. The height of the solder balls was about 0.1 mm.

This ASIC (semiconductor chip) was mounted on an evaluation board (not shown), and various connection reliability was evaluated. The evaluation substrate is an organic substrate, and
There is one SIC mounting area, and the mounting area has a test terminal (0.15 mm diameter) corresponding to the bump electrode of the ASIC.
Are formed. Similar to the first embodiment (see FIG. 9), this terminal is pulled out to the outside and a part thereof is exposed.

Fifty evaluation substrates were prepared and A
One SIC is installed. The mounting method will be described below. An uncleaned solder paste is previously formed on the terminals of the evaluation board by a printing method. This terminal and the terminal of the microcomputer to be evaluated are aligned and mounted so as to face each other. After that, reflow is performed at about 240 ° C., and resin is filled between the evaluation substrate and the microcomputer, and 1
Cure at 50 ° C.

Using the evaluation board on which these are mounted, the AS
After checking the initial characteristics of the IC, 2 out of 50 evaluation boards
Five of them were subjected to a high temperature storage test at 125 ° C. for 500 hours, and the remaining 25 evaluation substrates were subjected to a temperature cycle test of −55 ° C. and 125 ° C. for 1000 cycles. As a result, it was confirmed that no abnormal operation occurred in any of the samples.

(Evaluation 2) In Evaluation 1, Ti of about 5 μm
A film was formed, and the case where this was used as the Zn film was evaluated. The Zn film is formed by the electroplating method in the same manner as in Evaluation 1, and is about 5 μm from the upper surface of the polyimide resin film.

After the initial characteristics of the ASIC were confirmed using the evaluation boards on which these were mounted, as in Evaluation 1, 25 of the 50 evaluation boards were subjected to a high temperature storage test at 125 ° C. for 500 hours. The remaining 25 evaluation substrates were subjected to a temperature cycle test of −55 ° C. and 125 ° C. for 1000 cycles. As a result, it was confirmed that no abnormal operation occurred in any of the samples.

(Embodiment 7) Further, a solder ball HB is formed on the bump electrode formed along one side of the chip.
May be formed. Evaluations were made on such items.

The evaluation target is a flash memory having an outer shape of about 16 mm × 8 mm, that is, a flash memory is formed on a semiconductor substrate. FIG. 26 is a top view of this memory (semiconductor chip), and FIG. 27 is a sectional view taken along line FF of FIG. Fifty terminals (HB) are formed on one side of the long side of this chip at a pitch of 0.3 mm. Dummy terminals (DHB) are formed on the other long side corners. The terminal pad is made of Al and has a width of 0.19 mm, and the opening is made of silicon nitride (SiN) and has a width of 0.15 mm. Since the method of forming the solder ball HB has been described in the third embodiment with reference to FIGS. 16 to 19, detailed description thereof will be omitted.

A resist film having an opening is formed on the uppermost wiring (Al). The film thickness is about 5.5 μm,
The diameter of the opening is about 0.11 mm. It should be noted that openings are similarly made on the pads for the dummy terminals. A Ni film with a thickness of about 5 μm is formed in the opening, and about 0.05 μm is formed on the Ni film.
Then, an Au film of m is formed and bump electrodes B are formed. After that, a solder ball HB is formed on the Ni film by using a glass plate on which a solder paste is printed. The height of the solder ball HB was about 0.1 mm.

This semiconductor chip was mounted on an evaluation board and various connection reliability evaluations were carried out. The evaluation substrate is an organic substrate and has one flash memory mounting area, and the mounting area is provided with test terminals (diameter 0.18 mm) corresponding to the bump electrodes of the memory.
Similar to the first embodiment (see FIG. 9), this terminal is pulled out to the outside and a part thereof is exposed.
The mounting method is the same as in the third embodiment and the like.

After confirming the initial characteristics of these substrate-mounted samples, the 25 substrates were subjected to a high temperature storage test at 125 ° C. for 500 times.
The other 25 substrates were subjected to a temperature cycle test of −55 ° C. and 125 ° C. for 1000 cycles. As a result, it was confirmed that no abnormal operation occurred in any of the samples.

(Embodiment 8) In this embodiment, a mounting form of the semiconductor chip described in Embodiments 1 to 7 will be described. Below is the BGA (ball grid arra
y), tape mounting, MCM (multi chip module), MC
The case of mounting a semiconductor chip on an M card, a memory board, etc. will be described below together with the specific evaluation results.

(Evaluation 1) An evaluation was carried out in the case where an Ag film was used in place of the Pd film of Evaluation 2 of the first embodiment and a BGA shape was formed. The film thickness of the Ag film is about 0.05 μm. 28 is a sectional view of this BGA (semiconductor device), FIG. 29 is a back view (plan view) of the BGA, and FIG.
For example, it corresponds to the GG cross section of FIG.

As shown in FIGS. 28 and 29, the semiconductor chip mounted on a mounting board having area array terminals was evaluated. Such a device is
Called GA. 30 and 31 show the bonding state between the semiconductor chip and the mounting substrate.

On the mounting board JK, a terminal (T8) having a width of 0.13 mm is formed at a position corresponding to the DRAM terminal. This terminal is made of Sn having a thickness of 1 μm. This S
n can be formed by plating. This terminal and the BGA terminal portion (T9 portion, FIG. 28) on the back surface of the mounting board are
It is connected by Cu wiring extending through the substrate surface and the inner layer. As shown in FIG. 29, the BGA terminal portions are arranged in 4 rows × 15 columns, the terminal opening diameter is 0.5 mm, the long side direction has a 1.0 mm pitch, and the short side direction has a minimum 1.27 mm pitch. Is. The BGA terminal portion on the back surface of the mounting substrate is also plated with Sn having a thickness of about 1 μm. This board is a multi-series board in which the same circuit is formed in 5 series.

100 boards of this substrate were prepared, and DRA
One M semiconductor chip 1 was mounted. The mounting method will be described below. The terminal (T8) of the mounting substrate JK and the terminal (B) of the DRAM are opposed to each other (FIG. 30), and the temperature is raised to 240 ° C. while applying pressure to the substrate and the DRAM to bond the terminals (FIG. 31). In addition, M8 is a Cu wiring and R8 is a resist film. After that, an adhesive resin is filled between the DRAM and the mounting board and cured at 180 ° C., and then a non-cleaning flux is printed on the terminals on the back surface of the mounting board, and Sn-Ag- with a diameter of about 0.7 μm is printed there. A Cu-based solder ball is mounted and reflowed at a maximum temperature of 240 ° C. to form a solder ball (BGA terminal T9) on the back surface of the mounting substrate (FIGS. 28 and 29).

After that, the five mounting boards are separated into DRAM units, and the BGA is almost completed. As a result of disassembling this BGA and inspecting the inside, it was confirmed that Sn on the surface of the mounting substrate was melted like solder and connected to a semiconductor chip (DRAM) terminal.

Fifty BGAs were taken out and mounted on a substrate for evaluation having printed wiring by reflow to evaluate the characteristics and reliability of BGA. After confirming the initial characteristics of the BGA, 25 of the 50 evaluation substrates were tested at 125 ° C.
A high temperature storage test of 0 hours was performed, and the remaining 25 evaluation substrates were subjected to a temperature cycle test of -55 ° C and 125 ° C at 1000 times.
Went cycle. As a result, it was confirmed that no abnormal operation occurred in any of the samples.

(Evaluation 2) An evaluation was carried out for the case where the DRAM was mounted on a mounting substrate composed of a tape circuit. Figure 32
FIG. 3 is a sectional view of the device.

As shown in FIG. 32, wiring M81 is printed on the back surface of the mounting board JK made of a polyimide tape,
On the back surface thereof, for example, 4 rows × 1 on which the solder balls HB described above with reference to FIGS. 28 and 29 can be mounted.
Five rows of pads are formed. The periphery of this pad and the printed wiring are covered with a resist film R81.

On the surface of the mounting board, terminals and wirings T81 extending from the terminals are formed at positions corresponding to the terminals of the DRAM. No resist film is formed on the surface of this mounting substrate.

The DRAM terminal (T81) has a width of 0.
Cu film with a height of 095 mm and a height of 5 μm and A above it
The u-film (film thickness: 0.05 μm) is used, and the DRAM is mounted face down on the mounting board JK. In addition, A
The u film and the Cu film can be formed by electroplating. The mounting method will be described below. The terminal T81 of the mounting board JK and the terminal (B) of the DRAM (1) are made to face each other, and a sheet-shaped adhesive film is placed therebetween, and the board and the DRA.
While pressurizing M, the temperature is raised to 180 ° C. and they are bonded one by one.

From these samples, 50 pieces were taken out,
After confirming the initial characteristics, 25 BGAs were subjected to a high temperature storage test at 125 ° C for 500 hours, and another 25 BGAs were -55 ° C.
And a temperature cycle test of 125 ° C. was performed for 1000 cycles. As a result, it was confirmed that no abnormal operation occurred in any of the samples.

(Evaluation 3) The DRAM used in the evaluation 1 of the first embodiment, the microcomputer used in the evaluation 1 of the second embodiment, and other components (C1 to C5) such as capacitors are mounted on the mounting board JK. The MCM mounted on the board was evaluated.

FIG. 33 is a top view of the MCM, and FIG. 34 is FIG.
The HH sectional drawing of is shown. As shown in FIG. 33, the outer shape of the MCM is about 30 mm × 30 mm, and its thickness is about 2.5 mm. On the surface of the mounting board, a microcomputer or DR
AM etc. (C1 to C5) are mounted and 1m on the back side
It has 512 pins (HB) in which the central 8 rows × 8 columns out of 24 rows × 24 columns at m pitch are omitted.

On the surface of the mounting board JK, terminals are formed at positions corresponding to the terminals of the microcomputer and the DRAM, and terminals are also formed at positions corresponding to the terminals of the capacitor and the like. Each terminal is provided on the front surface of the mounting board and the BG on the back surface of the mounting board JK through the Cu wiring routed inside the mounting board.
It is connected to the A terminal (HB) to form a circuit. BG
The A terminal has an opening diameter of about 0.6 mm, a Ni film is formed on the terminal and the terminal on the surface of the mounting substrate, and an Au film is further formed on the Ni film. These films can be formed by a plating method.

First, a component such as a capacitor is mounted on a mounting board on which a solder paste is printed, and adhered by reflow. Next, the microcomputer and the DRAM were mounted on the mounting board in this order. The mounting method is the same as the evaluation 1 of the first embodiment and the evaluation 1 of the second embodiment. That is, the terminals of the mounting board and the terminals of the microcomputer and the DRAM are opposed to each other, and a liquid adhesive material is placed between them, and the mounting board and the microcomputer and the DRAM are heated to 180 ° C. while being pressure-bonded to each other.

Next, non-cleaning flux is printed on the terminals on the back surface of the mounting board, and solder balls HB having a diameter of about 0.7 mm are formed thereon by reflow.

50 from the plurality of MCMs formed in this way
Individual pieces are taken out and mounted on a board for evaluation printed with wiring by reflow to confirm the initial characteristics. After that, 25 boards are subjected to a high temperature storage test at 125 ° C. for 500 hours, and another 25 boards are 55 ℃ and 125 ℃ temperature cycle test 1
000 cycles were carried out. As a result, it was confirmed that no abnormal operation occurred in any of the samples.

(Evaluation 4) In this evaluation, the MCM card was evaluated. FIG. 35 is a top view of the MCM card,
FIG. 36 is a sectional view taken along line I-I of FIG. 35. As shown in FIG. 35, the outer shape of the MCM card is about 74 mm × 48 mm, and the thickness thereof is about 2.5 mm. Each of the DRAM used in the evaluation 1 of the first embodiment, the microcomputer used in the evaluation 1 of the second embodiment, the ASIC used in the evaluation 1 of the fourth embodiment, etc., is provided on the surface of the mounting board. It is mounted (C1 to C8, etc.), and 12 flash memories used in the seventh embodiment are mounted. In addition, parts such as capacitors are also mounted.

On the front surface and the back surface of the card substrate CK, terminals are formed at positions corresponding to the terminals of each chip such as a microcomputer and DRAM, and terminals are also formed at positions corresponding to the terminals of a capacitor and the like. . The terminals of each chip are connected by Cu wiring routed to the front surface, the back surface of the card substrate and the inside thereof as necessary to form a circuit. A Ni film is formed on the contact plug T83 of the card and the terminal for mounting the component, and an Au film is further formed on the Ni film. These films can be formed by a plating method.

First, a component such as a capacitor is mounted on a card substrate CK on which a solder paste is printed, and adhered by reflow. Next, the microcomputer, the DRAM, etc. are mounted in this order on the card substrate CK. Next, the remaining chips such as the flash memory are mounted on the back surface of the card substrate on which the solder paste is printed, and adhered by reflow. After that, resin MR is applied between the surface of the card substrate and the semiconductor chip.
Was filled with the resin MR, and the resin MR was filled between the back surface of the card substrate and the semiconductor chip, and the whole substrate was baked at 180 ° C. In this way, the MCM card is almost completed.

Fifty MCM cards thus formed were taken out and mounted on a board for evaluation printed with wiring by reflow to confirm the initial characteristics. After that, 25 boards were heated at a high temperature of 125 ° C. The standing test was performed for 500 hours, and the other 25 substrates were subjected to a temperature cycle test of −55 ° C. and 125 ° C. for 1000 cycles. As a result, it was confirmed that no abnormal operation occurred in any of the samples.

(Evaluation 5) Evaluation was carried out for the case where the DRAM of Evaluation 2 was mounted on a memory board (outer shape: 130 mm × 25 mm). A total of 16 DRAMs are mounted, 8 on each of the front and back surfaces.

On this memory board, there are a total of 16 DRAM mounting positions, and terminals each having a width of 0.13 mm are formed at positions corresponding to the DRAM terminals. Similar to the evaluation board of FIG. 9, this terminal is pulled out to the outside, and a part thereof is exposed. The mounting method of the DRAM is similar to that of the evaluation 1 and the like. 100 such memory boards were prepared.

Similar to the evaluation 1, these are set in the memory board 10.
After checking out the initial characteristics of the DRAM by extracting 20 out of 0 sheets, 10 sheets were subjected to a high temperature storage test at 125 ° C. for 500 hours, and the remaining 10 sheets were subjected to a temperature cycle test at −55 ° C. and 125 ° C. Was carried out for 1000 cycles. As a result, it was confirmed that no abnormal operation occurred in any of the samples.

As described above, according to this embodiment, since the bump electrodes of the semiconductor chip have the shapes described in the first to seventh embodiments, the reliability of connection with the mounting substrate can be improved. it can. Further, the characteristics of the semiconductor device (MCM card or the like) can be improved, and the yield can be improved.

The inventions made by the present inventors are as follows.
Although the specific description has been given based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and it is needless to say that the present invention can be changed without departing from the scope of the invention.

In particular, in the first embodiment and the like, the bump electrode B is formed after the passivation film 21, the polyimide resin film 22 and the like are formed on the uppermost wiring M.
When such a surface of the semiconductor chip is covered with the sealing resin, the bump electrodes B of the respective embodiments are formed on the uppermost layer wiring M, and then the uppermost layer wiring M is covered or insulated with the sealing resin. May be.

[0200]

The effects obtained by the typical ones of the inventions disclosed in this application will be briefly described as follows.
It is as follows.

Wiring formed above the semiconductor chip,
The wiring in which a region for forming a bump electrode of a semiconductor device, which has an insulating film formed on the wiring and has an opening on the wiring and a bump electrode formed on the opening, is exposed from the opening. Since the bump electrodes are smaller than the exposed area, the bump electrodes can be connected easily even at a narrow pitch, and the connection reliability can be improved.

Further, it is possible to improve the connection reliability of the terminals when mounting the semiconductor chip on the mounting substrate or the like.
In addition, it is possible to reduce short circuits and open defects during mounting. In addition, the manufacturing yield of semiconductor devices can be improved. Further, the semiconductor device can be manufactured at low cost. In addition, miniaturization of the semiconductor device can be dealt with. Further, the shorter wiring can improve the operation speed of the semiconductor device. Further, since the bump electrodes are fine, the bump electrode material can be reduced.

[Brief description of drawings]

FIG. 1 is a main-portion cross-sectional view of a substrate showing a manufacturing step of a semiconductor device which is Embodiment 1 of the present invention.

FIG. 2 is a main-portion cross-sectional view of the substrate, showing the manufacturing process of the semiconductor device which is Embodiment 1 of the present invention;

FIG. 3 is a main-portion cross-sectional view of the substrate showing the manufacturing process of the semiconductor device which is Embodiment 1 of the present invention.

FIG. 4 is a main-portion cross-sectional view of the substrate, showing the manufacturing process of the semiconductor device which is Embodiment 1 of the present invention;

FIG. 5 is a main-portion cross-sectional view of the substrate, showing the manufacturing process of the semiconductor device which is Embodiment 1 of the present invention;

FIG. 6 is a main-portion cross-sectional view of the substrate, showing the manufacturing process of the semiconductor device which is Embodiment 1 of the present invention;

FIG. 7 is a main-portion plan view (top view) of a substrate showing an example of the semiconductor device according to the first embodiment of the present invention;

FIG. 8 is a cross-sectional view of essential parts of a substrate showing an example of the semiconductor device according to the first embodiment of the present invention.

FIG. 9 is a plan view (top view) of a main part of a substrate for evaluating the semiconductor device according to the first embodiment of the present invention.

FIG. 10 is a main-portion cross-sectional view of the substrate showing the manufacturing process of the semiconductor device which is Embodiment 2 of the present invention.

FIG. 11 is a main-portion cross-sectional view of the substrate showing the manufacturing process of the semiconductor device which is Embodiment 2 of the present invention.

FIG. 12 is a main-portion cross-sectional view of the substrate showing the manufacturing process of the semiconductor device which is Embodiment 2 of the present invention.

FIG. 13 is a main-portion cross-sectional view of the substrate showing the manufacturing process of the semiconductor device which is Embodiment 2 of the present invention.

FIG. 14 is a plan view (top view) of a main part of a substrate showing an example of a semiconductor device according to a second embodiment of the present invention.

FIG. 15 is a main-portion cross-sectional view of a substrate illustrating an example of a semiconductor device which is Embodiment 2 of the present invention.

FIG. 16 is a main-portion cross-sectional view of the substrate, showing the manufacturing process of the semiconductor device which is Embodiment 3 of the present invention.

FIG. 17 is a main-portion cross-sectional view of the substrate showing the manufacturing process of the semiconductor device which is Embodiment 3 of the present invention.

FIG. 18 is a main-portion cross-sectional view of the substrate showing the manufacturing process of the semiconductor device which is Embodiment 3 of the present invention.

FIG. 19 is a main-portion cross-sectional view of the substrate showing the manufacturing process of the semiconductor device which is Embodiment 3 of the present invention.

FIG. 20 is a main-portion plan view (top view) of a substrate showing an example of a semiconductor device which is Embodiment 3 of the present invention;

FIG. 21 is a main-portion cross-sectional view of a substrate illustrating an example of a semiconductor device which is Embodiment 3 of the present invention.

FIG. 22 is a plan view (top view) of a main portion of a substrate showing an example of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 23 is a main-portion cross-sectional view of a substrate illustrating an example of a semiconductor device in Embodiment 4 of the present invention.

FIG. 24 is a plan view (top view) of a main portion of a substrate showing an example of a semiconductor device according to a sixth embodiment of the present invention.

FIG. 25 is a main-portion cross-sectional view of a substrate showing an example of a semiconductor device in Embodiment 6 of the present invention.

FIG. 26 is a plan view (top view) of a main portion of a substrate showing an example of a semiconductor device according to a seventh embodiment of the present invention.

FIG. 27 is a fragmentary cross-sectional view of a substrate showing an example of a semiconductor device according to a seventh embodiment of the present invention.

FIG. 28 is a cross-sectional view of essential parts of a device showing an example of a mounting form of a semiconductor device (semiconductor chip) according to an embodiment of the present invention.

FIG. 29 is a main-portion plan view (back view) of a device showing an example of a mounting form of a semiconductor device (semiconductor chip) according to an embodiment of the present invention;

FIG. 30 is a cross-sectional view of essential parts of a device showing an example of a mounting form of a semiconductor device (semiconductor chip) according to an embodiment of the present invention.

FIG. 31 is a cross-sectional view of essential parts of a device showing an example of a mounting form of a semiconductor device (semiconductor chip) according to an embodiment of the present invention.

FIG. 32 is a main-portion cross-sectional view of a semiconductor device (semiconductor chip) which is an embodiment of the present invention and shows an example of how the semiconductor device is mounted;

FIG. 33 is a main-portion plan view (top view) of a device showing an example of a mounting mode of a semiconductor device (semiconductor chip) according to an embodiment of the present invention;

FIG. 34 is a cross-sectional view of essential parts of a device showing an example of a mounting form of a semiconductor device (semiconductor chip) according to an embodiment of the present invention.

FIG. 35 is a main-portion plan view (top view) of a device showing an example of a mounting form of a semiconductor device (semiconductor chip) according to an embodiment of the present invention;

FIG. 36 is a main-portion cross-sectional view of an example of a mounting mode of a semiconductor device (semiconductor chip) according to an embodiment of the present invention.

[Explanation of symbols]

1 Semiconductor substrate (semiconductor wafer, semiconductor chip) 11 Insulating film 21 passivation film 22 Polyimide resin film 45 seed layer 47 long groove 49 Rewiring 49a Cu film 49b Ni film 51 Polyimide resin film 55 Seed layer 61 glass substrate 63 Solder paste B bump electrode B1 Ni film B2 Au film C1 to C10 semiconductor chips CK card board DPAD dummy pad HB solder ball JK mounting board M Top layer wiring M8 Cu wiring M81 wiring MR resin OA opening PAD pad area PAD1 first pad section PAD2 second pad section R resist film R2 resist film R3 resist film R8 resist film R81 resist film SA1 to SA4 SRAM mounting area T1 evaluation board T3 test terminal T81 wiring (terminal) T83 plug T9 BGA terminal

Claims (5)

[Claims] 1. A semiconductor device having a wiring formed above a semiconductor chip, an insulating film formed on the wiring and having an opening on the wiring, and a bump electrode formed on the opening. The semiconductor device is characterized in that a formation region of the bump electrode is smaller than an exposed region of the wiring exposed from the opening. 2. A semiconductor device having a wiring formed above a semiconductor chip, an insulating film formed on the wiring and having an opening on the wiring, and a bump electrode formed on the opening. The bump electrode formation region is smaller than the exposed region of the wiring exposed from the opening, and the bump electrode is formed of nickel (Ni), copper (Cu), titanium (Ti), or zinc (Zn). A first metal film having a film, and gold (Au), palladium (P) on the first metal film.
d), silver (Ag), rhodium (Rh) or platinum (P
t) A second metal film having a film, and a semiconductor device. 3. A semiconductor device having a wiring formed above a semiconductor chip, an insulating film formed on the wiring and having an opening on the wiring, and a bump electrode formed on the opening. The bump electrode formation region is smaller than an exposed region of the wiring exposed from the opening, and the bump electrode has a height of 3 μm from the surface of the insulating film.
A semiconductor device having the above. 4. A semiconductor device having a wiring formed above a semiconductor chip, an insulating film formed on the wiring and having an opening on the wiring, and a bump electrode formed on the opening. The bump electrode formation region is smaller than an exposed region of the wiring exposed from the opening, and the bump electrode is formed of a metal film and a ball-shaped conductive portion above the metal film. A semiconductor device characterized by: 5. (a) a step of forming a wiring above the semiconductor substrate; (b) a step of forming an insulating film on the wiring; and (c) a selective removal of the insulating film on the wiring. Thereby exposing the pad region of the wiring, (d) forming a mask film having an opening smaller than the pad region on the pad region on the insulating film, and (e) A step of forming a bump electrode in the opening,
A method of manufacturing a semiconductor device, comprising: