TWI729301B - 功率半導體集成式封裝用陶瓷模組及其製備方法 - Google Patents

功率半導體集成式封裝用陶瓷模組及其製備方法 Download PDF

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TWI729301B
TWI729301B TW107123343A TW107123343A TWI729301B TW I729301 B TWI729301 B TW I729301B TW 107123343 A TW107123343 A TW 107123343A TW 107123343 A TW107123343 A TW 107123343A TW I729301 B TWI729301 B TW I729301B
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layer
ceramic substrate
heat dissipation
electrode pad
metal dam
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TW201909346A (zh
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吳朝暉
康為
郭曉泉
章軍
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大陸商西安柏芯創達電子科技有限公司
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Abstract

本發明公開一種功率半導體集成式封裝用陶瓷模組及其製備方法，所述陶瓷模組包括一個陶瓷基板和一個一體式金屬圍壩層，藉由在所述陶瓷基板上表面設置所述一體式金屬圍壩，與一個固晶區圍構成一個凹形腔室，可實現半導體晶片的氣密性封裝；藉由在所述陶瓷基板的下表面設置一個散熱層，可把半導體晶片產生的熱量快速向外部傳導；又本產品生產工藝簡單，產品一致性高。

Description

功率半導體集成式封裝用陶瓷模組及其製備方法
本發明涉及功率半導體封裝領域技術，尤其是指一種功率半導體集成式封裝用陶瓷模組及其製備方法。
在積體電路、電力電子應用中，用於光電轉換、功率變換的半導體功率器件已經廣泛應用於諸如大功率發光二極體、雷射器、電機控制、風力發電和UPS等各種領域。近年來，為應對電力電子系統對空間和重量的要求，功率半導體模組小型化已成為發展趨勢。
在功率半導體模組封裝過程中，為解決單一晶片功率小、集成度低和功能不夠完善的問題，需要把多個高集成度、高性能、高可靠性的晶片通過串並聯方式封裝在一個模組內，從而實現多晶片的集成式封裝。
多晶片集成式封裝會導致流經模組的電流密度增加，晶片功耗也會增加，故而需要提高模組的導熱性能。此外，隨著工作電壓的提高，也需要提高模組的絕緣性能，因此，需要選擇低電阻率的佈線導體材料，低介電常數、高導熱率的絕緣材料作為封裝載體，陶瓷模組剛好契合了這個發展要求。
在功率半導體封裝中，陶瓷模組(或稱陶瓷基座)是半導體晶片及其它微電子器件重要的承載基板，主要起形成密封腔室、機械支撐保護、電 互連(絕緣)、導熱散熱、輔助出光等作用。現階段應用於功率半導體封裝的陶瓷模組有HTCC/LTCC及DBC陶瓷基板等。
HTCC又稱為高溫共燒多層陶瓷，LTCC又稱為低溫共燒多層陶瓷，此技術均採用厚膜印刷技術完成線路製作，因此線路表面較為粗糙(Ra約為1~3um)，對位不精準；而且多層陶瓷疊壓、高溫燒結等工藝使得陶瓷模組尺寸不精確，曲翹高；此外，該工藝採用的陶瓷材料配方複雜、導熱率低，且需要專用成型模具，製造週期長，成本高。DBC陶瓷基板又稱直接鍵合陶瓷基板，此技術採用高溫鍵合的方式將銅箔燒結在陶瓷上下表面，再依據線路設計，以蝕刻方式製備線路。該工藝使得DBC陶瓷基板無法在其表面獲得凹形密封腔室，故而無法實現真空氣密封裝，且無法製備垂直導通孔以實現上下線路的互連，因此多晶片的串並聯佈線比較困難。上述問題，已嚴重制約了這類陶瓷基板在功率半導體封裝中的應用。
有鑑於此，本發明針對現有技術存在之缺失，其第一目的是提供一種功率半導體集成式封裝用陶瓷模組，其能有效解決現有之陶瓷基板尺寸不精準、曲翹高、散熱差、無凹形密封腔室及不方便進行多晶片集成的問題。
於是，本發明一種功率半導體集成式封裝用陶瓷模組包含一個陶瓷基板、一個一體式金屬圍壩層、一個導電線路層、一個絕緣層、一個散熱層、一個正極焊盤、一個負極焊盤、多個固晶區，及一個垂直導通孔。
所述導電線路層、所述絕緣層和所述散熱層分別設置於所述陶瓷基板的下表面，所述絕緣層完全覆蓋住所述導電線路層，所述散熱層位於非所述導電線路層的區域上並與所述導電線路層間隔分開，所述散熱層的厚度不小於所述導電線路層及所述絕緣層的總厚度，所述正極焊盤、所述負極焊盤及所述等固晶區分別設置於所述陶瓷基板的上表面，每一固晶區上均具有一個連接 層和一個固晶層，所述連接層和所述固晶層彼此間隔分開，所述垂直導通孔設置於所述陶瓷基板，且電連接所述固晶區與所述導電線路層之間以及所述導電線路層與所述正極焊盤、所述負極焊盤之間，所述一體式金屬圍壩層設置於所述陶瓷基板的上表面上，所述一體式金屬圍壩層環繞於所述固晶區的周圍並與所述固晶區間隔分開，所述一體式金屬圍壩層的厚度大於所述固晶區的厚度，所述一體式金屬圍壩層部分區域加厚，獲得一台階面及一台階層，該台階層設置在該一體式金屬圍壩層的上方且覆蓋該一體式金屬圍壩層的部分區域，該一體式金屬圍壩層上方未被該台階層覆蓋的區域為該台階面。
進一步，所述陶瓷基板選自於氧化鋁陶瓷、氮化鋁陶瓷、氮化矽陶瓷或碳化矽陶瓷。
進一步，所述導電線路層和所述散熱層均為電鍍銅材質，所述散熱層的厚度大於所述導電線路層的厚度。
進一步，所述一體式金屬圍壩層為電鍍銅材質。
進一步，所述正極焊盤、所述負極焊盤分別位於所述陶瓷基板上表面周邊，且與所述一體式金屬圍壩層間隔分開。。
進一步，所述垂直導通孔採用外部金屬填充技術或者電鍍銅填充技術。
本發明之第二目的是提供一種功率半導體集成式封裝用陶瓷模組的製備方法，包含以下步驟：(A)取一陶瓷基板，在所述陶瓷基板上開一貫穿孔；(B)對所述陶瓷基板的上下表面進行金屬化；(C)對上下表面金屬化的所述陶瓷基板進行貼乾膜、曝光、顯影和電鍍，從而形成一個正極焊盤、一個負極焊盤、一個連接層、一個固晶層、一個一體式金屬圍壩底層、一個導電線路層、一個散熱底層，及一個垂直導通孔；(D)在所述陶瓷基板的上下表面再次進行貼乾膜、曝光、顯影和電鍍，使所述一體式金屬圍壩底層及所述散熱底層各自被 電鍍加厚，獲得一個一體式金屬圍壩層及一個散熱層；(E)對所述陶瓷基板進行退膜、蝕刻；及(F)在所述陶瓷基板的下表面塗上絕緣材質，形成一個絕緣層。
進一步，所述功率半導體集成式封裝用陶瓷模組的製備方法在步驟(F)之後還包含一步驟(G)，在所述正極焊盤、所述負極焊盤、所述連接層、所述固晶層、所述一體式金屬圍壩層及所述散熱層的表面上鍍金或銀。
本發明之第三目的是提供一種功率半導體集成式封裝用陶瓷模組的製備方法，包含以下步驟：(A)取一陶瓷基板，在所述陶瓷基板上開一貫穿孔；(B)對所述陶瓷基板的上下表面進行金屬化；(C)對上下表面金屬化的所述陶瓷基板進行貼乾膜、曝光、顯影和電鍍，從而形成一個正極焊盤、一個負極焊盤、一個連接層、一個固晶層、一個一體式金屬圍壩底層、一個導電線路層、一個散熱底層，及一個垂直導通孔；(D)在所述陶瓷基板的上下表面再次進行貼乾膜、曝光、顯影和電鍍，使所述一體式金屬圍壩底層及所述散熱底層各自被電鍍加厚，獲得一個一體式金屬圍壩層及一個散熱層；(E)在所述陶瓷基板的上表面再次進行貼乾膜、曝光、顯影和電鍍，使所述一體式金屬圍壩層部分區域被電鍍加厚，獲得一個限位用台階面及一個台階層；(F)對所述陶瓷基板進行退膜、蝕刻；及(G)在所述陶瓷基板的下表面塗上絕緣材質，形成一個絕緣層。
進一步，所述功率半導體集成式封裝用陶瓷模組的製備方法在步驟(G)之後還包含一步驟(H)，在所述正極焊盤、所述負極焊盤、所述連接層、所述固晶層、所述一體式金屬圍壩層及所述散熱層的表面上鍍金或銀。
根據上述技術特徵可達成以下功效：
1.藉由在所述陶瓷基板上表面設置所述一體式金屬圍壩，與所述固晶區圍構成一凹形腔室，可實現半導體晶片的氣密性封裝。
2.藉由在所述陶瓷基板的下表面設置所述散熱層，可把半導體晶片產生的熱量快速向外部傳導，提高散熱性能。
3.藉由設置所述導電線路層及所述垂直導通孔，可在所述陶瓷基板的下表面實現多晶片的串並聯連接。
(10):陶瓷基板
(20):一體式金屬圍壩層
(201):一體式金屬圍壩底層
(202):台階面
(203):台階層
(21):凹形腔室
(301):散熱底層
(31):導電線路層
(32):絕緣層
(33):散熱層
(34):正極焊盤
(35):負極焊盤
(36):垂直導通孔
(40):固晶區
(41):連接層
(42):固晶層
[第一圖]是一立體示意圖，說明本發明係本發明功率半導體集成式封裝用陶瓷模組的一實施例。
[第二圖]是一仰視圖，說明該實施例的底部結構。
[第三圖]是一局部剖視圖，說明該實施例的結構。
綜合上述技術特徵，本發明功率半導體集成式封裝用陶瓷模組及其製備方法的主要功效將可於下述實施例清楚呈現。
請參閱第一圖至第三圖，其顯示出了本發明功率半導體集成式封裝用陶瓷模組之實施例的具體結構，包含一個陶瓷基板10以及一個一體式金屬圍壩層20。
所述陶瓷基板10的下表面設置有一個導電線路層31、一個絕緣層32和一個散熱層33，所述絕緣層32完全覆蓋住所述導電線路層31，所述散熱層33位於非所述導電線路層31的區域上並與所述導電線路層31間隔分開，所述散熱層33的厚度不小於所述導電線路層31及所述絕緣層32的總厚度；在本實施例中，所述導電線路層31和散熱層33均為電鍍銅材質，所述散熱層33的厚度大於所述導電線路層31的厚度，所述絕緣層32為白色或者綠色油墨材質，所述絕緣層32的厚度小於所述散熱層33的厚度。
所述陶瓷基板10的上表面設置有一個正極焊盤34、一個負極焊盤35和多個固晶區40，每一固晶區40上均具有一個連接層41和一個固晶層42，所述連接層41和所述固晶層42彼此間隔分開；在本實施例中，所述正極焊盤34、 所述負極焊盤35分別位於所述陶瓷基板10上表面周邊，且與所述一體式金屬圍壩層20間隔分開，所述多個固晶區40呈陣列式排布。
所述陶瓷基板10設置有一個垂直導通孔36，所述垂直導通孔36電連接於所述固晶區40與所述導電線路層31之間以及所述導電線路層31與所述正極焊盤34、所述負極焊盤35之間，即所述連接層41和所述固晶層42透過對應的所述垂直導通孔36而分別與所述導電線路層31導通連接，所述正極焊盤34和所述負極焊盤35透過對應的所述垂直導通孔36而分別與所述導電線路層31導通連接，從而形成串並聯線路結構。在本實施例中，所述垂直導通孔36採用外部金屬填充技術或者電鍍銅填充技術，並且，所述陶瓷基板10選自於氧化鋁(Al2O3)陶瓷、氮化鋁(AlN)陶瓷、氮化矽(Si3N4)陶瓷、或碳化矽(SiC)陶瓷，其中，氧化鋁陶瓷價格便宜，氮化鋁陶瓷散熱效果好，氮化矽陶瓷強度高，碳化矽陶瓷價格適中，散熱效果良好，不以為限。
所述一體式金屬圍壩層20設置於所述陶瓷基板10的上表面上，所述一體式金屬圍壩層20環繞於所述的單個或者所述的多個固晶區40的周圍，並與所述固晶區40間隔分開，所述一體式金屬圍壩層20的厚度大於所述固晶區40的厚度。在本實施例中，所述一體式金屬圍壩層20為電鍍銅材質，以及所述一體式金屬圍壩層20上具有多個凹形腔室21，所述多個凹形腔室21亦呈陣列式排布，前述多個固晶區40分別位於對應的所述凹形腔室21中，並且所述凹形腔室21的周緣下沉形成一個台階面202。
本發明還公開了一種功率半導體集成式封裝用陶瓷模組的製備方法，包括有以下步驟：
(1)取一陶瓷基板10，在所述陶瓷基板10上開一貫穿孔。
(2)對所述陶瓷基板10的上下表面進行金屬化。
(3)對上下表面金屬化的所述陶瓷基板10進行貼乾膜、曝光、顯影和電鍍，從而形成一個正極焊盤34、一個負極焊盤35、一個連接層41、一個固晶層42、一個一體式金屬圍壩底層201，一個導電線路層31、一個散熱底層301、一個垂直導通孔36。
(4)在所述陶瓷基板10的上下表面再次進行貼乾膜、曝光、顯影和電鍍，使所述一體式金屬圍壩底層201及所述散熱底層301各自被電鍍加厚，獲得一個一體式金屬圍壩層20及一個散熱層33。
(5)對所述陶瓷模組進行退膜、蝕刻。
(6)在所述陶瓷基板10的下表面塗上絕緣材質，形成一個絕緣層32。
(7)在陶瓷模組之各金屬層的表面上鍍金或銀(圖中未示)，即對所述正極焊盤34、所述負極焊盤35、所述連接層41、所述固晶層42、所述一體式金屬圍壩層20及所述散熱層33的表面進行鍍金或銀。
本發明還公開了另一種功率半導體集成式封裝用陶瓷模組的製備方法，包括有以下步驟：
(1)取一陶瓷基板10，在所述陶瓷基板10上開一貫穿孔。
(2)對所述陶瓷基板10的上下表面進行金屬化。
(3)對上下表面金屬化的所述陶瓷基板10進行貼乾膜、曝光、顯影和電鍍，從而形成一個正極焊盤34、一個負極焊盤35、一個連接層41、一個固晶層42、一個一體式金屬圍壩底層201，一個導電線路層31、一個散熱底層301、一個垂直導通孔36。
(4)在所述陶瓷基板10的上下表面再次進行貼乾膜、曝光、顯影和電鍍，使所述一體式金屬圍壩底層201及所述散熱底層301各自被電鍍加厚，獲得一個一體式金屬圍壩層20及一個散熱層33。
(5)在所述陶瓷基板10的上表面再次進行貼乾膜、曝光、顯影和電鍍，使所述一體式金屬圍壩層20部分區域被電鍍加厚，獲得限位用的一個台階面202及一個台階層203，其中，該台階層203設置在所述一體式金屬圍壩層20的上方且覆蓋所述一體式金屬圍壩層20的部分區域，所述一體式金屬圍壩層20上方未被該台階層203覆蓋的區域為該台階面202。
(6)對所述陶瓷模組進行退膜、蝕刻。
(7)在所述陶瓷基板10的下表面塗上絕緣材質，形成一個絕緣層32。
(8)在陶瓷模組之各金屬層的表面上鍍金或銀(圖中未示)，即對所述正極焊盤34、所述負極焊盤35、所述連接層41、所述固晶層42、所述一體式金屬圍壩層20及所述散熱層33的表面進行鍍金或銀。
綜上所述，藉由在所述陶瓷基板10上表面設置所述一體式金屬圍壩20，與固晶區40圍構成所述凹形腔室21，可實現半導體晶片的氣密性封裝；藉由在所述陶瓷基板10的下表面設置所述散熱層33，可把半導體晶片產生的熱量快速向外部傳導，提高散熱性能；藉由設置所述導電線路層31及所述垂直導通孔36，可在所述陶瓷基板10的下表面實現多晶片的串並聯連接。本發明可以實現功率半導體的多晶片集成式封裝，具有熱電分離良好、氣密性高、熱阻低、結構緊湊等優點，且生產工藝簡單，產品一致性高。
綜合上述實施例之說明，當可充分瞭解本發明之操作、使用及本發明產生之功效，惟以上所述實施例僅係為本發明之較佳實施例，當不能以此限定本發明實施之範圍，即依本發明申請專利範圍及發明說明內容所作簡單的等效變化與修飾，皆屬本發明涵蓋之範圍內。
(10):陶瓷基板
(20):一體式金屬圍壩層
(201):一體式金屬圍壩底層
(202):台階面
(203):台階層
(21):凹形腔室
(301):散熱底層
(31):導電線路層
(32):絕緣層
(33):散熱層
(34):正極焊盤
(36):垂直導通孔
(40):固晶區
(41):連接層
(42):固晶層

Claims (10)

  1. 一種功率半導體集成式封裝用陶瓷模組，包含一個陶瓷基板、一個一體式金屬圍壩層、一個導電線路層、一個絕緣層、一個散熱層、一個正極焊盤、一個負極焊盤、多個固晶區，及一個垂直導通孔，所述導電線路層、所述絕緣層和所述散熱層分別設置於所述陶瓷基板的下表面，所述絕緣層完全覆蓋住所述導電線路層，所述散熱層位於非所述導電線路層的區域上並與所述導電線路層間隔分開，所述散熱層的厚度不小於所述導電線路層及所述絕緣層的總厚度，所述正極焊盤、所述負極焊盤及所述固晶區分別設置於所述陶瓷基板的上表面，每一固晶區上均具有一個連接層和一個固晶層，所述連接層和所述固晶層彼此間隔分開，所述垂直導通孔設置於所述陶瓷基板，且電連接所述固晶區與所述導電線路層之間以及所述導電線路層與所述正極焊盤、所述負極焊盤之間，所述一體式金屬圍壩層設置於所述陶瓷基板的上表面上，所述一體式金屬圍壩層環繞於所述固晶區的周圍並與所述固晶區間隔分開，所述一體式金屬圍壩層的厚度大於所述固晶區的厚度，所述一體式金屬圍壩層部分區域加厚，獲得一台階面及一台階層，該台階層設置在該一體式金屬圍壩層的上方且覆蓋該一體式金屬圍壩層的部分區域，該一體式金屬圍壩層上方未被該台階層覆蓋的區域為該台階面。
  2. 如請求項1所述之功率半導體集成式封裝用陶瓷模組，其中，所述陶瓷基板選自於氧化鋁陶瓷、氮化鋁陶瓷、氮化矽陶瓷、或碳化矽陶瓷。
  3. 如請求項1所述之功率半導體集成式封裝用陶瓷模組，其中，所述導電線路層和所述散熱層均為電鍍銅材質，所述散熱層的厚度大於所述導電線路層的厚度。
  4. 如請求項1所述之功率半導體集成式封裝用陶瓷模組，其中，所述一體式金屬圍壩層為電鍍銅材質。
  5. 如請求項1所述之功率半導體集成式封裝用陶瓷模組，其中，所述正極焊盤、所述負極焊盤分別位於所述陶瓷基板上表面周邊，且與所述一體式金屬圍壩層間隔分開。
  6. 如請求項1所述之功率半導體集成式封裝用陶瓷模組，其中，所述垂直導通孔採用外部金屬填充技術或者電鍍銅填充技術。
  7. 一種如請求項1所述的一種功率半導體集成式封裝用陶瓷模組的製備方法，包含以下步驟：(A)取一陶瓷基板，在所述陶瓷基板上開一貫穿孔；(B)對所述陶瓷基板的上下表面進行金屬化；(C)對上下表面金屬化的所述陶瓷基板進行貼乾膜、曝光、顯影和電鍍，從而形成一個正極焊盤、一個負極焊盤、一個連接層、一個固晶層、一個一體式金屬圍壩底層、一個導電線路層、一個散熱底層，及一個垂直導通孔；(D)在所述陶瓷基板的上下表面再次進行貼乾膜、曝光、顯影和電鍍，使所述一體式金屬圍壩底層及所述散熱底層各自被電鍍加厚，獲得一個一體式金屬圍壩層及一個散熱層；(E)對所述陶瓷基板進行退膜、蝕刻；及(F)在所述陶瓷基板的下表面塗上絕緣材質，形成一個絕緣層。
  8. 如請求項7所述之功率半導體集成式封裝用陶瓷模組的製備方法，在步驟(F)之後還包含一步驟(G)，在所述正極焊盤、所述負極焊盤、所述連接層、所述固晶層、所述一體式金屬圍壩層及所述散熱層的表面上鍍金或銀。
  9. 一種如請求項1所述的一種功率半導體集成式封裝用陶瓷模組的製備方法，包含以下步驟：(A)取一陶瓷基板，在所述陶瓷基板上開一貫穿孔；(B)對所述陶瓷基板的上下表面進行金屬化；(C)對上下表面金屬化的所述陶瓷基板進行貼乾膜、曝光、顯影和電鍍，從而形成一個正極焊盤、一個負極焊盤、一個連接層、一個固晶層、一個一體式金屬圍壩底層、一個導電線路層、一個散熱底層，及一個垂直導通孔；(D)在所述陶瓷基板的上下表面再次進行貼乾膜、曝光、顯影和電鍍，使所述一體式金屬圍壩底層及所述散熱底層各自被電鍍加厚，獲得一個一體式金屬圍壩層及一個散熱層；(E)在所述陶瓷基板的上表面再次進行貼乾膜、曝光、顯影和電鍍，使所述一體式金屬圍壩層部分區域被電鍍加厚，獲得一個限位用台階面及一個台階層；(F)對所述陶瓷基板進行退膜、蝕刻；及(G)在所述陶瓷基板的下表面塗上絕緣材質，形成一個絕緣層。
  10. 如請求項9所述之功率半導體集成式封裝用陶瓷模組的製備方法，在步驟(G)之後還包含一步驟(H)，在所述正極焊盤、所述負極焊盤、所述連接層、所述固晶層、所述一體式金屬圍壩層及所述散熱層的表面上鍍金或銀。
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